Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes providing a substrate having a buffer layer, a channel layer, and a barrier layer sequentially formed thereon; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a dielectric layer on the second etch stop layer; forming an etch protection layer on the dielectric layer; performing a first etch process to etch through the etch protection layer and partially through the dielectric layer to form a recess in the dielectric layer; performing a second etch process to etch the dielectric layer under the recess to form an opening, wherein the etch protection layer protects the dielectric layer underneath from etching during the second etch process; and performing a removal process to remove the etch protection layer remaining on the dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices, and more particularly, to a semiconductor device having a doped compound semiconductor and a method of forming the same. BACKGROUND

[0002] GaN-based semiconductor materials have many excellent material properties, such as high thermal resistance, wide band-gap, and high electron saturation velocity. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) elements, high-frequency elements, such as high electron mobility transistors (HEMTs) having a heterojunction structure.

[0003] High electron mobility transistors can be affected by processes, such as etching processes, during processing, resulting in poor electrical performance or uniformity. Although existing high electron mobility transistors are generally satisfactory, they are not entirely satisfactory in all respects. SUMMARY

[0004] Embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a substrate, the substrate having a buffer layer, a channel layer, and a barrier layer sequentially formed thereon; forming a doped compound semiconductor layer on part of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a dielectric layer on the second etch stop layer, the dielectric layer covering part of the doped compound semiconductor layer and part of the barrier layer exposed by the doped compound semiconductor layer; forming an etch protection layer on the dielectric layer; performing a first etching process to etch through the etch protection layer and part of the dielectric layer to form a recess in the dielectric layer; performing a second etching process to etch the dielectric layer under the recess to form an opening, the opening exposing part of the second etch stop layer, the etch protection layer protecting the dielectric layer under the etch protection layer from etching during the second etching process; performing a removal process to remove the etch protection layer remaining on the dielectric layer; and forming a gate metal layer to fill the opening.

[0005] Embodiments of the present application provide a semiconductor device, comprising: a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier layer on the channel layer; a doped compound semiconductor layer on part of the barrier layer; a first etch stop layer on the doped compound semiconductor layer; a second etch stop layer on the first etch stop layer; a dielectric layer on the second etch stop layer, the dielectric layer covering part of the doped compound semiconductor layer and part of the barrier layer exposed by the doped compound semiconductor layer; and

[0006] a gate metal layer on the second etch stop layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the present application will be described below in detail with reference to the accompanying drawings. It should be noted that various features are not drawn to scale and are only intended to illustrate the example. In fact, the size of the elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present application.

[0008] Figures 1-8 is a schematic diagram illustrating a process cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0009] Figures 9-10 is a schematic diagram illustrating a process cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0010] Figure 11 is a schematic diagram illustrating a process cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0011] SYMBOL DESCRIPTION

[0012] 10, 20: semiconductor device

[0013] 100: substrate

[0014] 102: buffer layer

[0015] 104: channel layer

[0016] 106: barrier layer

[0017] 108: doped compound semiconductor layer

[0018] 110: dielectric layer

[0019] 111: first etch stop layer

[0020] 112: second etch stop layer

[0021] 113: third etch stop layer

[0022] 114: etch protection layer

[0023] 116R: recess

[0024] 116O: opening

[0025] 118: gate metal layer

[0026] 120: opening

[0027] 124 / 126: source / drain structure DETAILED DESCRIPTION

[0028] The following detailed description is presented in terms of a number of embodiments or examples, for illustrative purposes. Descriptions of specific examples, configurations, and embodiments are presented herein to illustrate various aspects of the present embodiments. Of course, these are merely examples and are not intended to limit the present embodiments. For example, when a first element is referred to as being formed "on" a second element, this can include embodiments where the first and second elements are in direct contact, and where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, the present embodiments can have repeated use of reference characters in the descriptions for clarity and ease of understanding. The repeated descriptions of "one embodiment" or "an embodiment" do not necessarily refer to the same embodiment, although they can.

[0029] In addition, in some embodiments of the present invention, the term "connected" and / or "coupled" and / or "interconnected" used in the description can mean that two or more elements are either in direct contact, or that additional elements can be found between the two elements making up the "connection" or "coupling" or "interconnection". As such, the term "connected" and / or "coupled" and / or "interconnected" can also include instances in which the two structures are movable relative to each other, or in which the two structures are fixed relative to each other.

[0030] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0031] The terms "about", "approximately", "substantially" as used herein generally mean within ±20% of a given value, preferably within ±10%, more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. For example, the term "about 5 nm" can encompass a range of sizes from 4.5 nm to 5.5 nm. Numerical values given herein are approximate values, i.e., the given numerical value can also implicitly include the meaning of "about", "approximately", "substantially" in the absence of the specific recitation of "about", "approximately", "substantially".

[0032] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. The semiconductor device of the embodiments of the invention may have additional components added. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0033] This invention provides a method for forming a semiconductor device, in which an etching protection layer is formed on a dielectric layer to reduce damage to the device caused by the etching process and further prevent short circuits. Furthermore, the semiconductor device provided in this invention has an etch stop layer, which, in addition to stopping etching and protecting other components, allows for adjustment of the etch stop layer's configuration according to different design requirements.

[0034] Figures 1-8 This is a schematic cross-sectional view of a semiconductor device illustrating certain embodiments of the present invention. (Refer to...) Figure 1 A substrate 100 is provided, and a buffer layer 102, a channel layer 104, and a barrier layer 106 are sequentially formed on the substrate 100. The substrate 100 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, including silicon-germanium alloy, gallium arsenide-phosphide alloy, aluminum-indium arsenide alloy, aluminum-indium arsenide alloy, indium-indium arsenide alloy, indium-indium arsenide alloy, and / or indium-indium arsenide alloy, or combinations of the foregoing materials.

[0035] In some embodiments, substrate 100 may be a semiconductor-on-insulator (SGOI) substrate, such as silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI). In other embodiments, substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina (Al2O3) substrate (or sapphire substrate), a glass substrate, or other similar substrates. In some embodiments, substrate 100 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may contain a ceramic material, and the ceramic material may contain a metallic inorganic material. For example, the ceramic substrate may contain silicon carbide, aluminum nitride, a sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

[0036] The lattice or coefficient of thermal expansion of the substrate 100 may be different from that of the upper component (such as the channel layer 104). Therefore, strain may occur at or near the interface between the substrate 100 and the upper component, and defects such as cracks or warping are likely to form. As Figure 1 shown, a buffer layer 102 can be formed on the substrate 100 to mitigate the strain of the component (such as the channel layer 104) formed above the buffer layer 102 and prevent defects from forming in the upper component. The material of the buffer layer 102 can include: AlN, GaN, AlxGa 1-x N (where 0 < x < 1), the foregoing combinations, or other similar materials, and can be formed by an epitaxial growth process, such as: metalorganic chemical vapor deposition, hydride vapor epitaxy, molecular beam epitaxy, the foregoing combinations, or similar methods. In some embodiments, the buffer layer 102 can be a multi-layer structure (not shown). For example, the buffer layer 102 can include a superlattice buffer layer and / or a graded buffer layer, where the superlattice buffer layer is disposed on the substrate 100 and the graded buffer layer is disposed on the superlattice buffer layer, which can effectively prevent dislocations in the substrate 100 from entering the upper component and further improve the crystallization quality of other films and / or layers above.

[0037] In some embodiments, a seed layer (not shown) can be optionally formed between the substrate 100 and the buffer layer 102. In these embodiments, the seed layer can alleviate the lattice difference between the substrate 100 and the film and / or layer grown above to improve the crystallization quality. The material of the seed layer can include: AlN, Al2O3, AlGaN, SiC, Al, the foregoing combinations, or similar materials. The seed layer with a single-layer or multi-layer structure can be formed by a suitable process, such as: chemical vapor deposition, atomic layer deposition, physical vapor deposition, other processes, or the foregoing combinations. In some embodiments, the material of the buffer layer 102 depends on the material of the seed layer and the gases introduced in the epitaxial process.

[0038] The channel layer 104 is formed on the buffer layer 102. In some embodiments, the material of the channel layer 104 includes a binary III-V compound semiconductor material, such as a Group III nitride. For example, the material of the channel layer 104 can be gallium nitride. In some embodiments, the channel layer 104 can be doped with an n-type dopant or a p-type dopant. The channel layer 104 can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or the like. In some embodiments, the breakdown voltage of the high electron mobility transistor is mainly dependent on the thickness of the gallium nitride channel layer. For example, an increase of 1 pm in the thickness of the gallium nitride channel layer can increase the breakdown voltage of the high electron mobility transistor by about 100 V. During the epitaxial growth process to form the gallium nitride layer, a substrate with high thermal conductivity and high mechanical strength is needed to deposit the gallium nitride material on the substrate, otherwise the substrate can be bent or even broken. Compared to a silicon substrate, an aluminum nitride substrate has higher thermal conductivity and mechanical strength, and thus a thicker gallium nitride layer can be formed on the aluminum nitride substrate.

[0039] A barrier layer 106 is formed on the channel layer 104. The material of the barrier layer 106 can include a ternary III-V compound semiconductor, such as a group III nitride. For example, the material of the barrier layer 106 can be AlGaN, AlInN, or a combination thereof. In other embodiments, the barrier layer 106 can also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. In some embodiments, the barrier layer 106 can be doped, such as with an n-type dopant or a p-type dopant. The barrier layer 106 can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, a combination thereof, or the like. According to some embodiments of the present application, the material of the channel layer 104 is different from the material of the barrier layer 106, and the interface between them is a heterojunction structure. Due to the lattice mismatch between the channel layer 104 and the barrier layer 106, a stress can be generated to cause a piezoelectric polarization effect, and the bond between the group III metal (e.g., Al, Ga, or In) and nitrogen is more ionic, resulting in a spontaneous polarization. Due to the difference in energy gap between the channel layer 104 and the barrier layer 106, as well as the piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed at the heterointerface between the channel layer 104 and the barrier layer 106. Some semiconductor devices according to embodiments of the present application are high electron mobility transistors (HEMTs) that utilize the two-dimensional electron gas (2DEG) as the conduction carrier.

[0040] A doped compound semiconductor layer 108 is formed on the barrier layer 106. According to some embodiments of the present application, the material of the doped compound semiconductor layer 108 includes a doped compound semiconductor material, such as GaN doped with a p-type dopant or an n-type dopant. The steps of forming the doped compound semiconductor layer 108 can include depositing a layer of doped compound semiconductor material on the barrier layer 106 by an epitaxial growth process, forming a patterned mask layer on the layer of doped compound semiconductor material, performing an etching process on the layer of doped compound semiconductor material to remove portions of the layer of doped compound semiconductor material not covered by the patterned mask layer, and removing the patterned mask. The patterned mask layer can be a hard mask or a photoresist. In some embodiments, the doped compound semiconductor layer can be deposited in-situ with the seed layer (optional), the buffer layer 102, the channel layer 104, and the barrier layer 106 in the same deposition chamber. The doped compound semiconductor layer 108 can have a rectangular cross-section as shown in FIG. 1C. In other embodiments, the doped compound semiconductor layer 108 can have other shaped cross-sections, such as a trapezoidal cross-section. Figure 1 ​

[0041] Referring to Figure 1 A first etch stop layer 111 is formed on the doped compound semiconductor layer 108. The material of the first etch stop layer 111 can include a nitride, such as silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, gallium nitride, aluminum nitride, a metal nitride, a metal silicon nitride, or a combination thereof. The metal nitride can include, for example, titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, tantalum silicon nitride, aluminum titanium nitride, or other suitable material, or a combination thereof. The step of forming the first etch stop layer 111 can include depositing a layer of etch stop material and patterning the same. The deposition process can include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) such as sputtering or evaporation, other suitable process, or a combination thereof. In some embodiments, the first etch stop layer 111 can protect the underlying doped compound semiconductor layer 108 during subsequent processing, reducing or avoiding the doped compound semiconductor layer 108 from being affected by the etchant (e.g., plasma) or ambient gases used in the etching process, which can result in poor electrical uniformity. The thickness of the first etch stop layer 111 can be about 100 A to 1000 A, such as 300 A. A second etch stop layer 112 is formed on the first etch stop layer 111, as shown in FIG. 1C. The second etch stop layer 112 can act as an etch stop layer during subsequent etching processes and protect the first etch stop layer 111 from being damaged by the etchant, which can affect the threshold voltage of the device. The material of the second etch stop layer 112 is different from the first etch stop layer 111. For example, the material of the second etch stop layer 112 can include doped or undoped silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxide, silicon carbon oxynitride, metal silicide, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric material (dielectric constant less than 4), other suitable material, or a combination thereof. Figure 1

[0042] ​A deposition process can be used to deposit and pattern a layer of etch stop material to form the second etch stop layer 112, which can have a thickness of about 2 nm to about 50 nm, such as about 10 to 20 nm. The deposition process can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition (PECVD), electroplating, other suitable processes, or combinations thereof. In some embodiments, the first and second etch stop layers 111, 112 can protect the doped compound semiconductor layer 108 from the effects of etching processes and reduce or avoid poor electrical performance of the doped compound semiconductor layer 108.

[0043] In a particular embodiment, the first etch stop layer 111 includes titanium nitride and the second etch stop layer 112 includes doped or undoped polysilicon. The first etch stop layer 111 including titanium nitride can form a Schottky barrier with the doped compound semiconductor layer 108, which can increase the threshold voltage. In this embodiment, in addition to protecting the doped compound semiconductor layer 108 from subsequent processing, the second etch stop layer 112 can be doped or undoped polysilicon depending on the application and design requirements of the product. In this embodiment, the first and second etch stop layers 111, 112 have substantially the same width as the doped compound semiconductor layer 108. In an embodiment, the first and second etch stop layers 111, 112 can have a different width than the doped compound semiconductor layer 108.

[0044] As Figure 1As shown, a dielectric layer 110 is formed on the second etch stop layer 112, and the dielectric layer 110 covers a portion of the doped compound semiconductor layer 108 and the barrier layer 106 exposed by the doped compound semiconductor layer 108. The dielectric layer 110 can include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. The aforementioned low-k dielectric materials can include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The dielectric layer 110 can be formed using deposition processes, such as spin coating, chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, other suitable processes, or combinations thereof.

[0045] Referring to Figure 2 An etch protection layer 114 is formed on the dielectric layer 110. The etch protection layer 114 includes materials such as silicon nitride, titanium nitride, other suitable materials, or combinations thereof, and can be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition (e.g., sputtering or evaporation), other suitable processes, or combinations thereof. In other embodiments, the etch protection layer 114 can be a photoresist material. The etch protection layer 114 can have a thickness of about 100 A to about 1000 A, such as 300 A. In some embodiments, the etch protection layer 114 can protect the underlying dielectric layer 110 during subsequent etching processes to avoid defects in the dielectric layer 110 and to ensure the open rate for subsequent formation of the openings 116O.

[0046] Referring to Figure 3In some embodiments, the first etching process is a dry etching process, wherein the etchant used includes a plasma composed of argon (Ar) or fluorine (F) gas. In other embodiments, the material of the etch protection layer 114 includes an organic material, such as photoresist, spin on glass (SOG), resin, polyimide. In one embodiment, the material of the etch protection layer 114 includes an inorganic material, such as silicon oxide, titanium nitride, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric material (dielectric constant less than 4), silicon, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, and / or other suitable dielectric material.

[0047] In some embodiments, the material of the dielectric layer 110 includes silicon oxide, and the first etching process is a wet etching process, wherein the etchant used includes hydrofluoric acid (HF) or buffered oxide etch (BOE). In other embodiments, the material of the dielectric layer 110 includes silicon nitride, and the first etching process is a dry etching process, wherein the etchant used includes a plasma composed of argon (Ar) or fluorine (F) gas.

[0048] Referring to Figure 4A second etching process is performed to remove the dielectric layer 110 under the notch 116R to expose the second etching stop layer 112 and form an opening 116O. According to some embodiments of the present application, when the material of the dielectric layer 110 includes silicon oxide, the second etching process is preferably a wet etching process, in which the etchant used includes a buffered oxide etchant (BOE). During the second etching process, the etching protection layer 114 can protect the underlying dielectric layer 110 from etching to avoid defects in the dielectric layer 110 and to avoid the expansion of defects (if any) in the dielectric layer 110. The second etching stop layer 112 can protect the doped compound semiconductor layer 108 during the etching process.

[0049] In the aforementioned deposition process of the dielectric layer 110, since the dielectric layer 110 is conformally deposited on the second etching stop layer 112, the corners of the dielectric layer 110 generated due to the topography can cause defects, such as holes, in the dielectric layer 110. In the prior art, the etching process can also cause defects in the dielectric layer, or the etchant can enter the holes of the dielectric layer and expand the holes, which can cause the gate metal to fill into the holes of the dielectric layer during the subsequent filling of the gate metal, resulting in device short (e.g., gate-drain short). The method for forming a semiconductor device according to embodiments of the present application includes forming an etching protection layer 114 over the dielectric layer 110 to protect the dielectric layer 110 during the etching process to prevent the etching process from forming defects in the dielectric layer 110 or expanding the holes of the dielectric layer, thereby avoiding device short.

[0050] Referring to Figure 5 A removal process is performed to remove the remaining etching protection layer 114 on the dielectric layer 110. During the removal process, the second etching stop layer 112 can protect the underlying first etching stop layer 111 and doped compound semiconductor layer 108. For example, when the etching protection layer 114 and the first etching stop layer 111 include the same material, and the second etching stop layer 112 and the first etching stop layer 111 are different, the second etching stop layer 112 can protect the first etching stop layer 111 from etching during the removal process. In some embodiments, when the material of the etching protection layer 114 includes silicon nitride or titanium nitride, the removal process includes a wet etching process, in which the etchant used includes an acid, such as hydrochloric acid or sulfuric acid, in combination with hydrogen peroxide, but the present application is not limited thereto.

[0051] Referring to Figure 6A gate metal layer 118 is formed to fill the openings 116O. The material of the gate metal layer 118 can include: a metal, a metal nitride, a metal oxide, a metal alloy, other suitable conductive material, a combination thereof, or a multi-layer structure thereof. For example, the metal can include: Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, or other similar materials; the metal nitride can include: MoN, WN, TiN, TaN, TaSiN, TaCN, TiAlN, or other similar materials. In other embodiments, the conductive material of the gate metal layer 118 can include: NiSi, CoSi, TaC, TiAl, or other similar materials. The material layers can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering or evaporation), and then patterned to form the gate metal layer 118.

[0052] Referring to Figure 7 and Figure 8 The source / drain structures 124 / 126 can be formed on both sides of the doped compound semiconductor layer 108 after the removal process. In some embodiments, the source / drain structures 124 / 126 are formed by performing a patterning process to form a pair (or more) of openings 120 through the dielectric layer 110 and the barrier layer 106 and extending into the channel layer 104, depositing a conductive material layer in the openings 120, and patterning the conductive material layer to form the source / drain structures 124 / 126. The conductive material layer can include the material of the gate metal layer 118, a combination thereof, or a multi-layer structure thereof. In other embodiments, the material of the source / drain structures 124 / 126 can include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, a metal oxide, a metal alloy, other suitable conductive material, a combination thereof, or a multi-layer structure thereof. In some embodiments, the source / drain structures 124 / 126 can include the same or similar material as the gate metal layer 118 and can be formed by the same process or by a different process.

[0053] In another embodiment, another dielectric layer (not shown) is formed on the gate metal layer 118, and the source / drain structures 124 / 126 are formed on the other dielectric layer. The openings 120 are formed through the other dielectric layer, the dielectric layer 110, and the barrier layer 106 and extend into the channel layer 104, and the source / drain structures 124 / 126 fill the openings 120. In this embodiment, the gate metal layer 118 and the source / drain structures 124 / 126 are formed in different steps.

[0054] In other embodiments, the source / drain structures 124 / 126 can be formed on both sides of the doped compound semiconductor layer 108 after forming the dielectric layer 110 on the second etch stop layer 112 and before performing the removal process. For example, referring to Figure 9 The source / drain structures 124 / 126 can be formed after forming the dielectric layer 110 on the second etch stop layer 112 and before forming the etch protection layer 114 on the dielectric layer 110. The method of forming the source / drain structures 124 / 126 includes performing a patterning process to form a pair (or more) of openings through the dielectric layer 110 and the barrier layer 106 and extending into the channel layer 104, depositing a layer of conductive material in the openings, and patterning the layer of conductive material to form the source / drain structures 124 / 126. The material of the layer of conductive material is the same as or similar to the material of the source / drain structures 124 / 126 described above. In one embodiment, another dielectric layer can be formed on the dielectric layer 110. Then, as shown in Figure 10 the etch protection layer 114 is formed on the dielectric layer 110 and the source / drain structures 124 / 126, or the etch protection layer 114 is formed on the other dielectric layer and the source / drain structures 124 / 126. Subsequently, a process similar to that shown in Figures 3 to 6 may be performed to form the semiconductor device 10 as shown in Figure 8 In these embodiments, the etch protection layer 114 also has the effect of the aforementioned protection of the dielectric layer 110 from shorting the device.

[0055] Referring to Figure 11 , compared to the semiconductor device 10 shown in Figure 8 , the semiconductor device 20 further includes a third etch stop layer 113 between the doped compound semiconductor layer 108 and the first etch stop layer 111. In some embodiments, the material of the third etch stop layer 113 can be the same as or similar to the material of the second etch stop layer 112. The third etch stop layer 113 can be formed by a method similar to the formation of the first etch stop layer 111 or the second etch stop layer 112 described above. The thickness of the third etch stop layer 113 can be about 2 nm to about 50 nm, such as about 10 to 20 nm. In some embodiments of the present application, the first etch stop layer 111 includes titanium nitride and the second etch stop layer 112 and the third etch stop layer 113 include doped or undoped silicon, which can be single crystal, poly-crystal, or amorphous. In these embodiments, in addition to some of the advantages of the first etch stop layer 111 and the second etch stop layer 112 described above, the third etch stop layer 113 can be doped or undoped poly-crystal silicon, depending on the desired threshold voltage. In further embodiments, the doping concentration of the third etch stop layer 113 can be varied to adjust the threshold voltage.

[0056] In some embodiments of the p-doped doped compound semiconductor layer 108, due to the low activation rate of the dopant after doping, the non-activated dopant can generate many charged defects in the doped compound semiconductor layer 108, which can affect the performance of the semiconductor device. In these embodiments, in addition to the effects described above and the protection of the underlying doped compound semiconductor layer 108 from the adverse effects of subsequent processes, the undoped silicon in the third etch stop layer 113 can further compensate for the non-activated dopant, further improve the characteristics of the semiconductor device, and enable the semiconductor device to provide a higher saturation current. In addition, compared to the p-doped doped compound semiconductor layer 108, the undoped silicon in the third etch stop layer 113 is an n-type semiconductor material, so the undoped silicon in the third etch stop layer 113 can form an NP junction with the p-doped doped compound semiconductor layer 108. This NP junction is reverse biased when the semiconductor device is in the on-state, which can reduce the gate leakage current of the semiconductor device and also increase the breakdown voltage of the gate.

[0057] The method for forming a semiconductor device provided by the embodiments of the present application includes forming an etch protection layer on a dielectric layer to protect the dielectric layer during an etching process, prevent defects from being formed in the dielectric layer or the aperture of the dielectric layer from being expanded during the etching process, avoid the metal filled in the aperture of the dielectric layer in subsequent processes from causing the device to short circuit, and thus improve the electrical properties of the device. The semiconductor device provided by the embodiments of the present application can avoid device damage in the process, for example, the impact of the etchant on the components can be reduced in the etching process, and the configuration of the device can also be adjusted according to the desired threshold voltage. In some embodiments, the characteristics of the elements of the semiconductor device can be further improved and a higher saturation current can be obtained.

[0058] The features of the above-described embodiments are summarized in order to enable those skilled in the art to better understand the various aspects of the present application. Those skilled in the art will understand that they can easily design or modify other processes and structures based on the present application to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not deviate from the spirit and scope of the present application, and that various changes, substitutions, and replacements can be made herein without deviating from the spirit and scope of the present application.

Claims

1. A method for forming a semiconductor device, characterized by, comprising: providing a substrate having a buffer layer, a channel layer, and a barrier layer formed thereon in sequence; forming a doped compound semiconductor layer on part of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a dielectric layer on the second etch stop layer, wherein the dielectric layer covers part of the doped compound semiconductor layer and the barrier layer exposed by the doped compound semiconductor layer; forming an etch protection layer on the dielectric layer; performing a first etching process to etch through the etch protection layer and part of the dielectric layer to form a recess in the dielectric layer; performing a second etching process to etch the dielectric layer under the recess to form an opening exposing part of the second etch stop layer, wherein the etch protection layer protects the dielectric layer underneath from etching during the second etching process; performing a removal process to remove the etch protection layer remaining on the dielectric layer; and forming a gate metal layer to fill the opening. Further comprising: forming a third etch stop layer on the doped compound semiconductor layer before forming the first etch stop layer.

2. The method for forming a semiconductor device according to Claim 1, wherein The material of the etch protection layer comprises: an organic material, an inorganic material, a low dielectric constant dielectric material, or a combination thereof.

3. The method for forming a semiconductor device according to Claim 1, wherein The material of the etch protection layer comprises: photoresist, spin-on glass, polyimide, silicon oxide, silicon oxynitride, tetraethoxysilane oxide, phosphosilicate glass, borophosphosilicate glass, silicon, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, silicon nitride, titanium nitride, or a combination thereof.

4. The method for forming a semiconductor device according to Claim 3, wherein Further comprising: forming a source / drain structure on both sides of the doped compound semiconductor layer after forming the dielectric layer on the second etch stop layer and before performing the removal process.

5. The method for forming a semiconductor device according to Claim 1, wherein The first etching process is a dry etching process and the second etching process is a wet etching process.

6. The method for forming a semiconductor device according to Claim 1, wherein The first etching process is a first wet etching process and the second etching process is a second wet etching process.

7. The method for forming a semiconductor device according to Claim 1, wherein Further comprising: forming a source / drain structure on both sides of the doped compound semiconductor layer after the removal process.

8. The method for forming a semiconductor device according to Claim 1, wherein comprising:

9. A semiconductor device, characterized by comprising: a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier layer on the channel layer; a doped compound semiconductor layer on part of the barrier layer; a first etch stop layer on the doped compound semiconductor layer; a second etch stop layer on the first etch stop layer; a dielectric layer on the second etch stop layer, wherein the dielectric layer covers part of the doped compound semiconductor layer and the barrier layer exposed by the doped compound semiconductor layer; and a gate metal layer on part of the second etch stop layer. Further comprising a third etch stop layer between the doped compound semiconductor layer and the first etch stop layer. The material of the third etch stop layer comprises doped or undoped silicon.

10. The semiconductor device according to claim 9, wherein The material of the first etch stop layer comprises: nitride.

11. The semiconductor device according to claim 10, wherein ​ 12. The semiconductor device according to claim 9, wherein ​ 13. The semiconductor device according to claim 12, wherein The material of the first etch stop layer includes silicon nitride, titanium nitride, silicon oxynitride, silicon carbon nitride, gallium nitride, aluminum nitride, molybdenum nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, aluminum titanium nitride, or a combination thereof.

14. The semiconductor device according to claim 9, wherein The material of the second etch stop layer includes a low dielectric constant dielectric material.

15. The semiconductor device according to claim 14, wherein The material of the second etch stop layer includes doped or undoped silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxide, silicon carbon oxynitride, metal silicide, tetraethoxysilane oxide, phosphorus silicon glass, boron phosphorus silicate glass, or a combination thereof.

16. The semiconductor device according to claim 9, wherein A source / drain structure is further included on both sides of the doped compound semiconductor layer, and the source / drain structure penetrates the dielectric layer and the barrier layer and extends into the channel layer.

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