A silicon carbide mosfet device and method of manufacturing the same
By forming a field oxide layer under the polycrystalline gate region A in silicon carbide MOSFET devices to block JFET implantation, the problem of insufficient device breakdown voltage is solved, yield is improved and production costs are reduced.
Patent Information
- Application Number
- CN202210155406.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-21
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2042-02-21
AI Technical Summary
Existing silicon carbide MOSFET devices are prone to a decrease in drain-source breakdown voltage under reverse voltage, and their production cost is relatively high.
A field oxide layer is formed below the polycrystalline gate region A as a barrier layer to avoid JFET implantation. JFET implantation is only performed below the polycrystalline gate region B, and the gate structure is formed by process adjustment.
This improved the device's withstand voltage and yield while reducing production costs.
Smart Images
Figure CN114496801B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon carbide MOSFET device technology, and particularly to a silicon carbide MOSFET device and its manufacturing method. Background Technology
[0002] Silicon carbide (SiC) materials possess excellent physical and electrical properties. With its wide bandgap (7 ohms), high thermal conductivity, large saturation drift velocity, and high critical breakdown electric field, it has become an ideal semiconductor material for fabricating high-power, high-frequency, high-voltage, high-temperature resistant, and radiation-resistant devices, showing broad application prospects in both military and civilian fields. Silicon carbide metal-oxide-semiconductor transistors (MOSFETs) offer advantages such as fast switching speed and low on-resistance. Furthermore, they can achieve high breakdown voltage levels with relatively small drift layer thicknesses, reducing the size of power switching modules and lowering energy consumption, making them significantly advantageous in power switching, converter, and other application areas.
[0003] In the fabrication process of conventional silicon carbide planar MOSFETs, junction field-effect transistors (JFETs) are implanted throughout the entire cell region. Their doping type is the same as the epitaxial layer, N-type, and their concentration is greater than that of the N-type epitaxial layer. (Reference) Figure 1 and Figure 2 , Figure 1 This is a top view of the existing silicon carbide MOSFET layout. Figure 2 It corresponds Figure 1 The electric field distribution diagram of the structure under reverse breakdown voltage. Due to the limitations of the MOSFET itself, the JFET length L1 of the polycrystalline gate region A (denoted as A) is greater than the JFET length L2 of the polycrystalline gate region B (denoted as B). Therefore, when the MOSFET is subjected to reverse voltage, the JFET region of the polycrystalline gate region A is longer than that of the polycrystalline gate region B, and the depletion regions 14 of the P-body regions 12 at both ends are less likely to merge together, which easily leads to a decrease in drain-source breakdown voltage (BVds).
[0004] In conclusion, there is a genuine need for a novel MOSFET drain layout design to address these issues, thereby improving MOSFET yield and reducing production costs. Summary of the Invention
[0005] In view of the above problems, the object of the present invention is to provide a silicon carbide MOSFET device and a method for manufacturing the same, wherein a field oxide layer is formed below the polycrystalline gate region A, and no JFET implantation occurs below the field oxide layer due to the blocking effect during JFET implantation. Furthermore, the present invention can be used in device structures such as hexagonal or square cells.
[0006] To achieve the above objectives, embodiments of this application provide a method for manufacturing a silicon carbide MOSFET device. The MOSFET device includes a source, a drain, and a gate. The method includes: forming a substrate of a first doped type on the drain; forming a drift region of the first doped type on the substrate, wherein a polycrystalline gate region A and a polycrystalline gate region B are defined on the drift region; forming a plurality of body regions of a second doped type on the drift region, wherein the second doped type has the opposite polarity to the first doped type; depositing / growing a field oxide layer, wherein the field oxide layer is used to shield the polycrystalline gate region A; JFET implantation, such that: no JFET implantation is performed on the drift region adjacent to the polycrystalline gate region A, while JFET implantation is performed on the drift region adjacent to the polycrystalline gate region B; removing the field oxide layer; and forming a gate at the location where the field oxide layer is removed.
[0007] In addition to the above-described manufacturing method, the present invention also provides a silicon carbide MOSFET device, including a drain, a first-doped substrate, a first-doped drift region, a plurality of second-doped base regions, a source, and a gate, wherein the second doping type is opposite in polarity to the first doping type, wherein an A polycrystalline gate region and a B polycrystalline gate region are defined on the drift region, and the A polycrystalline gate region and the B polycrystalline gate region are generated by: depositing / growing a field oxide layer, wherein the A polycrystalline gate region is shielded by the field oxide layer; and JFET implantation, such that: the drift region adjacent to the A polycrystalline gate region has no JFET implantation, while the drift region adjacent to the B polycrystalline gate region has JFET implantation.
[0008] Optionally, the step of forming a gate at the location where the field oxide layer is removed includes: active source etching, gate layer growth, polysilicon deposition, polysilicon etching; source CT and gate CT etching, P+ implantation; metal deposition and etching; and passivation / polyimide deposition and etching.
[0009] Optionally, the length of the A polycrystalline gate region in the diagonal direction is greater than the length of the B polycrystalline gate region.
[0010] Optionally, in some embodiments of this application, the field oxide layer is in the shape of a non-geometric polygon.
[0011] Optionally, in some embodiments of this application, the field oxide layer is circular in shape.
[0012] Optionally, in some embodiments of this application, the field oxide layer is rectangular in shape.
[0013] In summary, this invention, without altering the process steps or adding any process flow, only uses the JFET implanted field oxide layer as a shield, and does not perform JFET implantation below the field oxide layer in the first polysilicon region of the A polysilicon gate region. In other words, a field oxide layer is grown below the first polysilicon region, and because the field oxide layer acts as a barrier during JFET implantation, no JFET implantation occurs below the field oxide layer. Therefore, when the MOSFET device withstands reverse voltage, the JFET region below the first polysilicon region is more easily depleted, without affecting the device's withstand voltage.
[0014] This application effectively solves the problems of the prior art through the above-mentioned novel solution without increasing costs too much, and improves the yield of MOSFETs and reduces production costs in a cost-effective manner. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a top view of the drain layout of a conventional silicon carbide MOSFET.
[0017] Figure 2 It corresponds Figure 1 Electric field distribution diagram of the structure under reverse withstand voltage.
[0018] Figure 3 This is a schematic diagram of a silicon carbide MOSFET device according to an embodiment of the present invention.
[0019] Figure 4 For the corresponding Figure 3 A schematic diagram of the B-type polycrystalline gate region.
[0020] Figures 5A to 5C They are respectively the corresponding Figure 3 A schematic diagram of the fabrication process of the A-type polycrystalline gate region.
[0021] Figures 6 to 8 These are top views of the drain layout of silicon carbide MOSFETs in different embodiments of the present invention.
[0022] Figure 9 This is a flowchart of a method for manufacturing a silicon carbide MOSFET device according to an embodiment of the present invention. Detailed Implementation
[0023] The disclosure is specifically described by the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “described” mean that such a statement includes “a or at least one” of the stated components or ingredients. Furthermore, as used in this disclosure, the singular article also includes a statement of a plurality of components or ingredients unless it is clearly apparent from the specific context that a plurality is excluded. Moreover, when applied in this description and all the following claims, unless explicitly stated otherwise, “in which” means both “in which” and “therein”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the art, in the content of this disclosure, and in the specific context. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not, of course, limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.
[0024] The terms “approximately,” “about,” or “nearly” as used herein should generally mean that a given value or error range is within 20%, preferably within 10%. Furthermore, the quantities provided herein may be approximate, and therefore mean that unless otherwise stated, they may be expressed using the terms “approximately,” “about,” or “nearly.” When a quantity, concentration, or other numerical value or parameter has a specified range, preferred range, or lists upper and lower ideal values, it should be considered as specifically disclosing all ranges consisting of any pairs of upper and lower limits or ideal values, regardless of whether such ranges are separately disclosed. For example, if a range of length X cm to Y cm is disclosed, it should be considered as disclosing a length of H cm, where H can be any real number between X and Y.
[0025] Furthermore, "electrical coupling" or "electrical connection" herein includes any direct and indirect means of electrical connection. For example, if a first device is described as electrically coupled to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. Additionally, in descriptions concerning the transmission or provision of electrical signals, those skilled in the art will understand that attenuation or other non-ideal variations may occur during the transmission of electrical signals; however, unless otherwise specified, the source and receiver of the transmitted or provided electrical signal should be considered substantially the same signal. For example, if an electrical signal S is transmitted (or provided) from terminal A of an electronic circuit to terminal B of the same electronic circuit, a voltage drop may occur across the source and drain of a transistor switch and / or possible stray capacitance; however, unless the purpose of this design is to intentionally utilize attenuation or other non-ideal variations during transmission to achieve certain specific technical effects, the electrical signal S at terminals A and B of the electronic circuit should be considered substantially the same signal.
[0026] It is understood that terms such as “comprising,” “having,” and “containing,” as used herein, are open-ended terms, meaning including but not limited to. Furthermore, no embodiment or claim of this application is required to achieve all the purposes, advantages, or features disclosed herein. In addition, the abstract and headings are merely for assisting in patent document searching and are not intended to limit the claims of the invention.
[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings, while "inner" and "outer" refer to the outline of the device.
[0028] Please refer to the figures in the accompanying drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments illustrated in this application and should not be construed as limiting other specific embodiments not detailed herein.
[0029] The present invention will now be described in detail from various aspects in conjunction with preferred embodiments.
[0030] refer to Figure 3 , Figure 3This is a schematic diagram of a silicon carbide MOSFET device 100 according to an embodiment of the present invention. The silicon carbide MOSFET device 100 includes: a drain 1, an N+ substrate 2, an N-type drift region 3, a P-type base region 4, an N+ source region 5, a source 8, an isolation dielectric 9, and a gate. The substrate 2 may be a silicon carbide substrate. A channel 11 is formed between the gate 10 and the N-type drift region 3, and a JFET region 6 is formed in the N-type drift region 3. Please note that the polarity of the components in this embodiment is only one implementation method, and the present invention is not limited thereto. For example, in other variations, a P-type component can be replaced by an N-type component, and an N-type component can be replaced by a P-type component.
[0031] Next, please refer to Figure 4 and Figures 5A to 5C , Figure 4 For the corresponding Figure 3 A schematic diagram of the B polysilicon gate region (labeled B), and Figures 5A to 5C They are respectively the corresponding Figure 3 A schematic diagram of the fabrication process for the polysilicon gate region A (labeled A). Figure 4 In this process, the JFET region is first formed by implanting a JFET, and then the B polysilicon gate region is formed. Figure 5A The process involves first covering the field oxide layer (FOX) before implanting the JFET; therefore, there is no JFET region directly beneath the field oxide layer (FOX). Then, as... Figure 5B As shown, the field oxide layer FOX is removed. Finally, the A polycrystalline gate region is formed above the JFET region. Thus, there is no FET region at the center below the A polycrystalline gate region, but a JFET region is still formed below the A polycrystalline gate region adjacent to the body region. This avoids the situation in the prior art where the length of the JFET region diagonally opposite the A polycrystalline gate region is greater than the length of the B polycrystalline gate region JFET.
[0032] In other words, this embodiment modifies only the JFET implantation shielding without changing the process steps or adding process flow, eliminating JFET implantation below the field oxide FOX layer in the polysilicon gate region A. That is, a field oxide FOX layer is grown below the polysilicon gate region A, but because the field oxide FOX layer blocks JFET implantation, no JFET implantation occurs below the FOX. By forming the field oxide FOX layer before JFET implantation in the JFET region, an implantation shielding effect is achieved, preventing JFET layer implantation below the field oxide FOX layer, while JFET implantation occurs in other locations. Therefore, when the MOS is subjected to reverse breakdown voltage, the JFET region below the polysilicon gate region A is more easily depleted, without affecting the device's breakdown voltage. It should be noted that although this embodiment uses a field oxide layer for shielding, the invention is not limited to this; other materials that provide similar physical or chemical properties can also be used.
[0033] In detail, the steps for forming the gate after removing the field oxide layer include: active source etching, gate layer growth, polysilicon deposition, polysilicon etching; source CT and gate CT etching, P+ implantation; metal deposition and etching; and passivation / polyimide deposition and etching.
[0034] It should be noted that, although the silicon carbide MOSFET device 100 as a whole... Figure 3 As described above, this invention does not limit the overall architecture of silicon carbide MOSFET devices. As long as the drain adopts the shielding architecture shown in Figure 5, it falls within the scope of this invention.
[0035] It is important to note that the field oxide layer (FOX), acting as an implantation barrier, is a casualty of the fabrication process. It is removed after the JFET implantation is complete and does not remain until the end. Therefore, in Figure 5C The final structure will not contain the field oxide (FOX) region. The shape of the field oxide (FOX) can be square, circular, irregular, etc., which will be described in detail below.
[0036] Please see Figures 6 to 8 These are top views of the drain layout of silicon carbide MOSFETs in different embodiments of the present invention. Optionally, in some embodiments of this application, the shape of the field oxide layer used for shielding purposes may be... Figure 6 The non-geometric pattern shown is a polygon; in other embodiments, the field oxide layer may be circular, such as... Figure 7 As shown; and, in some other embodiments, the field oxide layer may be rectangular, such as... Figure 8 As shown above. Figures 6 to 8 This is only a preferred embodiment of the present invention. In practice, the present invention may also employ other types of geometric or non-geometric patterns.
[0037] Please refer to Figure 9 , Figure 9 This is a flowchart of a method for manufacturing a silicon carbide MOSFET device according to an embodiment of the present invention. Please note that these steps do not necessarily need to be followed if substantially the same result can be obtained. Figure 9 The execution will proceed in the order shown. Figure 9 The method shown can be adopted by the silicon carbide MOSFET device 100 shown in Figure 3, and can be simply summarized as follows:
[0038] Step 804: Form a substrate of the first doped type on the drain electrode;
[0039] Step 806: Form a drift region of the first doping type on the substrate, wherein a polycrystalline gate region A (Poly A) and a polycrystalline gate region B (Poly B) are defined on the drift region, wherein the length of the polycrystalline gate region A in the diagonal direction is greater than the length of the polycrystalline gate region B;
[0040] Step 808: Form multiple second-doped bulk regions on the drift region;
[0041] Step 810: Deposit / grow field oxide layer, wherein the field oxide layer is used to shield the polycrystalline gate region A;
[0042] Step 812: JFET injection, such that: there is no JFET injection in the drift region adjacent to polysilicon gate region A, while there is JFET injection in the drift region adjacent to polysilicon gate region B;
[0043] Step 814: After JFET implantation is complete, remove the field oxide layer;
[0044] Step 816: Form a gate at the location where the field oxide layer is removed. Detailed steps may include: active source etching, gate layer growth, polysilicon deposition, polysilicon etching; source CT and gate CT etching, P+ implantation; metal deposition and etching; and passivation / polyimide deposition and etching.
[0045] Step 818: End.
[0046] Since those skilled in the craft should be able to easily understand the details of each step in Figure 8 after reading the above paragraphs, further descriptions will be omitted here for the sake of brevity.
[0047] In summary, this invention modifies the JFET implantation shielding without changing the process steps or adding any process flow, eliminating JFET implantation below the field oxide layer in the A polysilicon gate region. In other words, a field oxide layer is formed below the A polysilicon gate region, and because the field oxide layer blocks JFET implantation, no JFET implantation occurs below it. Therefore, when the MOS is subjected to reverse voltage, the JFET region below the A polysilicon gate region is more easily depleted, without affecting the device's breakdown voltage.
[0048] In summary, this application effectively solves the problems of the prior art through the above-mentioned novel solution without increasing costs too much, and improves the yield of MOSFETs and reduces production costs in a cost-effective manner.
[0049] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The embodiments described above are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort, except for designs consistent with the solutions of the embodiments of this application mentioned in this application, are within the scope of protection of this application.
[0050] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
[0051] Although the present application has disclosed the preferred embodiments above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a silicon carbide MOSFET device, the MOSFET device comprising a source, a drain, and a gate, characterized in that, include: A substrate of the first doped type is formed on the drain electrode; A drift region of a first doping type is formed on the substrate, wherein a polycrystalline gate region A and a polycrystalline gate region B are defined on the drift region, and the length of the polycrystalline gate region A in the diagonal direction is greater than the length of the polycrystalline gate region B. Multiple body regions of a second doping type are formed on the drift region, wherein the second doping type has the opposite polarity to the first doping type. JFET implantation involves first implanting a JFET to form a JFET region, then forming a B polysilicon gate region. A field oxide layer is formed first, followed by JFET implantation so that there is no JFET region directly below the field oxide layer. Finally, an A polysilicon gate region is formed above the JFET region, such that: there is no JFET region at the center below the A polysilicon gate region, but a JFET region is formed below the A polysilicon gate region adjacent to the body region, and JFET implantation occurs in the drift region adjacent to the B polysilicon gate region. Remove the field oxide layer; And a gate is formed at the location where the field oxide layer is removed.
2. The manufacturing method according to claim 1, characterized in that, The field oxide layer has a non-geometric polygonal shape.
3. The manufacturing method according to claim 1, characterized in that, The field oxide layer is circular in shape.
4. The manufacturing method according to claim 1, characterized in that, The field oxide layer is rectangular in shape.
5. A silicon carbide MOSFET device, comprising a drain, a first-doped substrate, a first-doped drift region, a plurality of second-doped base regions, a source, and a gate, wherein the second doping type has the opposite polarity to the first doping type, characterized in that: The drift region is defined with a polycrystalline gate region A and a polycrystalline gate region B. The length of the polycrystalline gate region A in the diagonal direction is greater than the length of the polycrystalline gate region B. The polycrystalline gate region A and the polycrystalline gate region B are generated in the following manner: first, a JFET is implanted to form a JFET region, and then the polycrystalline gate region B is formed. A field oxide layer is formed first, and then a JFET is implanted so that there is no JFET region directly below the field oxide layer. Finally, the polycrystalline gate region A is formed above the JFET region, such that: there is no JFET region at the center below the polycrystalline gate region A, and a JFET region is formed below the polycrystalline gate region A near the body region, while a JFET is implanted in the drift region adjacent to the polycrystalline gate region B.
6. The silicon carbide MOSFET device according to claim 5, characterized in that, The field oxide layer has a non-geometric polygonal shape.
7. The silicon carbide MOSFET device according to claim 5, characterized in that, The field oxide layer is circular in shape.
8. The silicon carbide MOSFET device according to claim 5, characterized in that, The field oxide layer is rectangular in shape.
Citation Information
Patent Citations
VDMOS device and manufacturing method thereof
CN113937167A
Power semiconductor device
CN206685391U