Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: using a first selective chemical vapor deposition process to form a first plug material layer in the first opening, and forming a second plug material layer in the second opening, wherein the top surface of the first plug material layer is higher than the top surface of the second plug material layer; performing a passivation treatment on the first plug material layer and the second plug material layer; after the passivation treatment, using a second selective chemical vapor deposition process to form a third plug material layer on the surface of the first plug material layer in the first opening, so that the third plug material layer fills the first opening, and forming a fourth plug material layer on the surface of the second plug material layer in the second opening, so that the fourth plug material layer fills the second opening, and the rate of forming the third plug material layer is lower than the rate of forming the fourth plug material layer. The method is conducive to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved. As the size requirements of components become smaller and smaller, the size of the corresponding conductive structure is also getting smaller and smaller.

[0003] The method for forming the conductive structure is as follows: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer has a first opening; forming a first plug in the first opening; after forming the first plug, forming a second dielectric layer on the surface of the first plug and the surface of the first dielectric layer; forming a second opening in the second dielectric layer; after forming the second opening, forming a second plug in the second opening. The first plug and the second plug constitute a conductive structure. In order to reduce the resistance of the conductive structure with an increasingly reduced size, the conductive structure is formed by using a material with a relatively low resistivity.

[0004] However, the performance of semiconductor devices formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a first conductive layer and a second conductive layer separated from each other; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first opening and a second opening, wherein the first opening exposes the first conductive layer, and the second opening exposes the second conductive layer; using a first selective chemical vapor deposition process to form a first plug material layer in the first opening, and a second plug material layer in the second opening, wherein the top surface of the first plug material layer is higher than the top surface of the second plug material layer; performing a passivation treatment on the first plug material layer and the second plug material layer; after the passivation treatment, using a second selective chemical vapor deposition process to form a third plug material layer on the surface of the first plug material layer in the first opening, such that the third plug material layer fills up the first opening, and forming a fourth plug material layer on the surface of the second plug material layer in the second opening, such that the fourth plug material layer fills up the second opening, and the rate of forming the third plug material layer is lower than the rate of forming the fourth plug material layer.

[0007] Optionally, it also includes: after forming the first plug material layer and the second plug material layer and before the passivation treatment, performing a first ion implantation on the first dielectric layer exposed by the first opening and the second opening to reduce the width of the first opening above the surface of the first plug material layer and to reduce the width of the second opening above the second plug material layer.

[0008] Optionally, the passivation treatment method includes: using a remote plasma process to introduce a passivation gas; parameters of the remote plasma process include: an angle between the incident direction of the passivation gas and the normal to the substrate surface, and the angle is greater than 0 degrees.

[0009] Optionally, the passivation gas includes: a nitrogen-containing gas, and the nitrogen-containing gas includes nitrogen, ammonia, nitric oxide or nitrous oxide.

[0010] Optionally, the parameters of the first ion implantation process include: implanting a first ion whose relative atomic mass is greater than a relative atomic mass of an element in the first dielectric layer, an implantation energy ranging from 1 keV to 100 keV, a dose ranging from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and a cycle number ranging from 1 to 1000.

[0011] Optionally, the material of the first dielectric layer contains silicon and oxygen, and the relative atomic mass of the first ions is greater than the relative atomic mass of silicon.

[0012] Optionally, the first ions include germanium ions or tin ions.

[0013] Optionally, the first plug material layer and the second plug material layer are made of the same material; the first plug material layer and the second plug material layer include metals, including copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0014] Optionally, the parameters of the first selective chemical vapor deposition process include: the gas introduced includes WF 6 and H 2 , the WF 6 The flow rate range is 0 ml / min to 1000 ml / min, the H 2 The flow rate range is 0 ml / min to 10000 ml / min and the pressure is 0 torr to 100 torr.

[0015] Optionally, the method further includes: performing a cleaning process after the passivation process and before the second selective chemical vapor deposition process.

[0016] Optionally, the cleaning method includes: introducing a reducing gas to allow the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.

[0017] Optionally, the third plug material layer and the fourth plug material layer are made of the same material; the material of the third plug material layer and the fourth plug material layer includes: metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0018] Optionally, the second selective chemical vapor deposition process parameters include: the gas introduced includes WF 6 and H 2 , the WF 6 The flow rate range is 0 ml / min to 1000 ml / min, the H 2 The flow rate range is 0 ml / min to 10000 ml / min and the pressure is 0 torr to 100 torr.

[0019] Optionally, it also includes: forming an adhesion layer on the surfaces of the first dielectric layer, the third plug material layer and the fourth plug material layer; forming a fifth plug material layer on the surface of the adhesion layer; planarizing the fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer until they are flush with or lower than the surface of the second plug material layer, forming a first plug in the first opening, and forming a second plug in the second opening.

[0020] Optionally, the method further includes: after forming the third plug material layer and the fourth plug material layer and before forming the adhesion layer, performing a second ion implantation on the first dielectric layer to reduce gaps between the first plug material layer, the second plug material layer, the third plug material layer, and the fourth plug material layer and the first dielectric layer.

[0021] Optionally, the process parameters of the second ion implantation include: implanting a second ion, and the relative atomic mass of the second ion is greater than the relative atomic mass of an element in the first dielectric layer material, the implantation energy ranges from 1 keV to 100 keV, the dose ranges from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and the number of cycles is 1 to 1000.

[0022] Optionally, the material of the first dielectric layer contains silicon and oxygen, and the relative atomic mass of the second ions is greater than the relative atomic mass of silicon.

[0023] Optionally, the second ions include germanium ions or tin ions.

[0024] Optionally, the base includes: a substrate and a second dielectric layer located on a surface of the substrate, the first conductive layer and the second conductive layer are located in the second dielectric layer, and the second dielectric layer exposes the first conductive layer and the second conductive layer.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming the first plug material layer and the second plug material layer, the first plug material layer and the second plug material layer are passivated, and the passivation treatment can reduce the rate of forming a film layer by the second selective chemical vapor deposition process. Since the top surface of the first plug material layer located in the first opening is higher than the top surface of the second plug material layer located in the second opening, the passivation treatment causes a passivation effect on the first plug material layer to a greater extent than the passivation effect on the second plug material layer, so that the rate of forming the third plug material layer is less than the rate of the fourth plug material layer, thereby reducing the difference in the rate of forming the film layer in the first opening and the second opening by the first selective chemical vapor deposition process, so that the overall thickness of the first plug material layer and the third plug material layer formed in the first opening is close to the overall thickness of the second plug material layer and the fourth plug material layer formed in the second opening, thereby improving the morphology uniformity of the film layer formed in the first opening and the film layer formed in the second opening, which is conducive to improving the performance of the formed semiconductor structure.

[0027] Furthermore, before the passivation treatment is performed, the method further includes: performing a first ion implantation on the first dielectric layer exposed by the first opening and the second opening, wherein the implanted first ions can replace the atomic positions in the crystal lattice of the material of the first dielectric layer, and the relative atomic mass of the first ions is greater than the relative atomic mass of an element in the first dielectric layer, so that the film layer after the first ion implantation treatment expands, thereby reducing the width of the first opening above the surface of the first plug material layer and the width of the second opening above the surface of the second plug material layer. In addition, the top surface of the first plug material layer is higher than the top surface of the second plug material layer, the height of the first opening exposed by the first plug material layer is less than the height of the second opening exposed by the second plug material layer, and the height of the first opening width reduced by the first ion implantation is less than the height of the second opening width reduced, thereby facilitating the passivation effect of the passivation treatment on the first plug material layer and the second plug material layer, increasing the difference in the subsequent film layer formation rate in the first opening and the second opening, thereby facilitating the improvement of the morphology uniformity of the film layer formed in the first opening and the film layer formed in the second opening, and facilitating the improvement of the performance of the formed semiconductor structure.

[0028] Furthermore, after forming the third plug material layer and the second plug layer, the method further includes: performing a second ion implantation on the first dielectric layer. Since the implanted second ions can replace the atomic positions in the crystal lattice of the first dielectric layer material, and the relative atomic mass of the second ions is greater than the relative atomic mass of an element in the first dielectric layer, the film layer after the second ion implantation process expands, thereby reducing the gaps between the first plug material layer, the second plug material layer, the third plug material layer, and the fourth plug material layer and the first dielectric layer, which is beneficial to reducing the loss of the first conductive layer and the second conductive layer caused by the grinding solution used in the subsequent planarization process, thereby improving the performance of the formed semiconductor structure.

[0029] Furthermore, through the cleaning treatment, the introduced reducing gas reacts with impurities on the surfaces of the first plug material layer and the second plug material layer, thereby removing surface impurities and improving the surface smoothness of the first plug material layer and the second plug material layer, thereby improving the quality of the film layer subsequently formed by the second selective chemical vapor deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 4 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0031] Figures 5 to 14 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0032] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0033] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 4 The present invention is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure.

[0034] Please refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a first conductive layer 111 and a second conductive layer 112 separated from each other, and a dielectric layer 120 is provided on the substrate 100, wherein the dielectric layer 120 has a first opening 121 and a second opening 122, and the first opening 121 exposes the first conductive layer 111, and the second opening 122 exposes the second conductive layer 112.

[0035] Please refer to Figure 2, a first selective chemical vapor deposition process is used to form a first plug material layer 131 in the first opening 121 , and a second plug material layer 132 in the second opening 122 , and the first plug material layer 131 fills the first opening 121 .

[0036] Please refer to Figure 3 , a second selective chemical vapor deposition process is used to form a third plug material layer 141 on the surface of the first plug material layer 131 , and a fourth plug material layer 142 is formed on the surface of the second plug material layer 132 , and the fourth plug material layer 142 fills the second opening 122 .

[0037] Please refer to Figure 4 , forming an adhesion layer (not shown in the figure) on the surface of the dielectric layer 120, the third plug material layer 141 and the fourth plug material layer 142; forming a fifth plug material layer (not shown in the figure) on the surface of the adhesion layer; and planarizing the third plug material layer 141, the fourth plug material layer 142, the adhesion layer, and the fifth plug material layer until the surface of the dielectric layer 120 is exposed.

[0038] In the above method, since the selective chemical vapor deposition process can grow layer by layer on the exposed surfaces of the first conductive layer 111 and the second conductive layer 112 without growing on the surface of the dielectric layer 120, the formed film layer has better quality and density, is not prone to holes, and does not need to form an adhesion layer in advance, which is beneficial to reducing contact resistance.

[0039] However, due to the different amounts of residual by-products in the first opening 121 and the second opening 122, the rate consistency of the first plug material layer 131 and the second plug material layer 132 formed by the selective chemical vapor deposition process is poor, so that while the first plug material layer 131 in the first opening 121 fills the first opening 121, the film layer in the second opening 122 does not fill the second opening 122, and the first plug material layer 131 with a faster growth rate is prone to premature closure at the top of the second opening 122, resulting in the generation of a void a in the second opening 122, which makes the contact resistance of the conductive structure in the second opening 122 larger.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: performing a passivation treatment on the first plug material layer and the second plug material layer, wherein the passivation treatment can reduce the rate of subsequent formation of a film layer using a second selective chemical vapor deposition process, so that the overall thickness of the first plug material layer and the third plug material layer formed in the first opening is close to the overall thickness of the second plug material layer and the fourth plug material layer formed in the second opening, thereby improving the uniformity of the morphology of the film layer formed in the first opening and the film layer formed in the second opening, which is beneficial to improving the performance of the formed semiconductor structure.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 5 to 14 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0043] Please refer to Figure 5 , providing a substrate 200, wherein the substrate 200 has a first conductive layer 211 and a second conductive layer 212 separated from each other.

[0044] In this embodiment, the base 200 includes: a substrate (not shown in the figure) and a second dielectric layer (not shown in the figure) located on the surface of the substrate, the first conductive layer 211 and the second conductive layer 212 are located in the second dielectric layer, and the second dielectric layer exposes the first conductive layer 211 and the second conductive layer 212.

[0045] The material of the first conductive layer 211 includes metal, including copper, tungsten, aluminum, titanium, titanium nitride or tantalum; the material of the second conductive layer 212 includes metal, including copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

[0046] In this embodiment, the first conductive layer 211 and the second conductive layer 212 are made of the same material, namely, cobalt.

[0047] The material of the substrate includes: silicon, germanium, germanium silicon, silicon on insulator or germanium on insulator. In this embodiment, the material of the substrate is silicon.

[0048] The material of the second dielectric layer is an insulating material, including one or more of silicon oxide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon oxynitride. In this embodiment, the material of the second dielectric layer is silicon oxide.

[0049] Please refer to Figure 6A first dielectric layer 220 is formed on the substrate 200 . The first dielectric layer 220 has a first opening 221 and a second opening 222 . The first opening 221 exposes the first conductive layer 211 , and the second opening 222 exposes the second conductive layer 212 .

[0050] The material of the first dielectric layer 220 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, and silicon nitride oxide. In this embodiment, the material of the first dielectric layer 220 is silicon oxide.

[0051] It should be noted that, in the present embodiment, the first opening 221 is also located in the first conductive layer 211, and the width of the first opening 221 located in the first conductive layer 211 is greater than the width of the first dielectric layer 220, that is, the first opening 221 has a protruding portion, and the protruding portion can play a certain blocking role on the grinding solution used in the planarization process during the subsequent process of filling the first opening 221 with material and performing a planarization process, thereby reducing the etching damage to the first conductive layer 211 at the bottom of the first opening 221 caused by the grinding solution, which is beneficial to improving the performance of the formed semiconductor structure.

[0052] Similarly, in the present embodiment, the second opening 222 is also located in the second conductive layer 212, and the width of the second opening 222 located in the second conductive layer 212 is greater than the width of the second opening 222 located in the first dielectric layer 220. Similarly, the second opening 222 has a protruding portion, and the protruding portion can play a certain blocking role on the grinding solution used in the planarization process during the subsequent process of filling the second opening 222 with material and performing a planarization process, thereby reducing the etching damage caused by the grinding solution to the second conductive layer 212 at the bottom of the second opening 222, which is beneficial to improving the performance of the formed semiconductor structure.

[0053] Please refer to Figure 7 , a first selective chemical vapor deposition process is used to form a first plug material layer 231 in the first opening 221 and a second plug material layer 232 in the second opening 222 , and a top surface of the first plug material layer 221 is higher than a top surface of the second plug material layer 232 .

[0054] The first plug material layer 231 provides material for subsequently forming a first plug in the first opening 221 ; the second plug material layer 232 provides material for subsequently forming a second plug in the second opening 222 .

[0055] The first plug material layer 231 and the second plug material layer 232 are made of the same material; the materials of the first plug material layer 231 and the second plug material layer 232 include: metal, the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum. In this embodiment, the materials of the first plug material layer 231 and the second plug material layer 232 are both tungsten.

[0056] The parameters of the first selective chemical vapor deposition process include: the gas introduced includes WF 6 and H 2 , the WF 6 The flow rate range is 0 ml / min to 1000 ml / min, the H 2 The flow rate range is 0 ml / min to 10000 ml / min and the pressure is 0 torr to 100 torr.

[0057] The first selective chemical vapor deposition process is used to form the first plug material layer 231 and the second plug material layer 232 with good film quality and density, and is not prone to generating holes. An adhesion layer does not need to be formed, which is beneficial to reducing contact resistance.

[0058] It should be noted that the first dielectric layer 220 includes a to-be-implanted region A, and the to-be-implanted region A will be implanted with first ions in a subsequent first ion implantation process.

[0059] Please refer to Figure 8 , a first ion implantation is performed on the first dielectric layer 220 exposed by the first opening 221 and the second opening 222 to reduce the width of the first opening 221 above the surface of the first plug material layer 231 and to reduce the width of the second opening 222 above the second plug material layer 232.

[0060] It should be noted that the first dielectric layer 220 includes a region A to be implanted, and the first ion implantation causes the region A to be implanted to form an implantation region B, and the width of the implantation region B is greater than the width of the region A to be implanted.

[0061] The width refers to a dimension in a direction perpendicular to the sidewall of the first opening 221 or the second opening 222 .

[0062] The parameters of the first ion implantation process include: implanting a first ion whose relative atomic mass is greater than the relative atomic mass of an element in the first dielectric layer, an implantation energy ranging from 1 keV to 100 keV, a dose ranging from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and a cycle number ranging from 1 to 1000.

[0063] Since the injected first ions can replace the atomic positions in the lattice of the first dielectric layer 220 material, and the relative atomic mass of the first ions is greater than the relative atomic mass of an element in the first dielectric layer 220, the film layer expands after the first ion implantation treatment, that is, the size of the area A to be implanted of the first dielectric layer 220 increases after the first ions are implanted, thereby reducing the width of the first opening 221 above the surface of the first plug material layer 231 and the width of the second opening 222 above the surface of the second plug material layer 232, that is, the width of the implantation area B is greater than the width of the area A to be implanted. Furthermore, the top surface of the first plug material layer 231 is higher than the top surface of the second plug material layer 232, and the height of the first opening 221 above the surface of the first plug material layer 231 is less than the height of the second opening 222 above the surface of the second plug material layer. The height by which the width of the first opening 221 is reduced by the first ion implantation is less than the height by which the width of the second opening 222 is reduced, thereby facilitating the passivation effect of subsequent passivation treatment on the first plug material layer 231 and the second plug material layer 232, and increasing the difference in the subsequent film layer formation rate in the first opening 221 and the second opening 222, thereby facilitating the improvement of the uniformity of the morphology of the film layer formed in the first opening 221 and the second opening 222, and thereby facilitating the improvement of the performance of the formed semiconductor structure.

[0064] The dosage range of the first ion implantation process is 1E10 atoms per square centimeter to 1E12 atoms per square centimeter. The first ion implantation process has a higher dosage range, which is beneficial to fully expand the implantation area of ​​the first dielectric layer 220, so that the first opening 221 exposed by the first plug material layer 231 is reduced to a greater extent, and the second opening 222 exposed by the second plug material layer 232 is reduced to a greater extent, thereby improving the morphology uniformity of the film layer formed in the first opening 221 and the film layer formed in the second opening 222.

[0065] In this embodiment, the material of the first dielectric layer 220 contains silicon and oxygen, and the relative atomic mass of the first ion is greater than the relative atomic mass of silicon. The first ion is germanium ion. In other embodiments, the first ion may also be tin ion.

[0066] Please refer to Fig. 9 After the first ion implantation, the first plug material layer 231 and the second plug material layer 232 are passivated.

[0067] The passivation treatment method includes: using a remote plasma process to introduce a passivation gas; the parameters of the remote plasma process include: an angle between the incident direction of the passivation gas and the normal line of the substrate surface, and the angle is greater than 0 degrees.

[0068] The passivation gas includes: a nitrogen-containing gas, and the nitrogen-containing gas includes nitrogen, ammonia, nitric oxide or nitrous oxide. In this embodiment, the passivation gas is nitrogen.

[0069] By performing a passivation treatment on the first plug material layer 231 and the second plug material layer 232, the passivation treatment can reduce the rate of forming a film layer using the second selective chemical vapor deposition process in the subsequent process. Since the top surface of the first plug material layer 231 located in the first opening 221 is higher than the top surface of the second plug material layer 232 located in the second opening 222, the passivation treatment causes a greater degree of passivation on the first plug material layer 231 than on the second plug material layer 232, so that the rate of forming the third plug material layer in the subsequent process is lower than the rate of forming the fourth plug material layer.

[0070] In other embodiments, the first ion implantation process may not be performed, and after the first plug material layer and the second plug material layer are formed, the first plug material layer and the second plug material layer are passivated.

[0071] Please refer to Fig.10 After the passivation treatment, a cleaning treatment is performed.

[0072] The cleaning method includes: introducing a reducing gas to allow the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.

[0073] The reducing gas includes hydrogen.

[0074] Through the cleaning treatment, the introduced reducing gas reacts with impurities on the surface of the first plug material layer 231 and the second plug material layer 232, thereby removing the surface impurities and improving the surface smoothness of the first plug material layer 231 and the second plug material layer 232, thereby improving the quality of the film layer subsequently formed by the second selective chemical vapor deposition process.

[0075] In other embodiments, the cleaning process may not be performed after the passivation process.

[0076] Please refer to Fig.11 , using a second selective chemical vapor deposition process, a third plug material layer 241 is formed on the surface of the first plug material layer 231 in the first opening 221, so that the third plug material layer 241 fills the first opening 221, and a fourth plug material layer 242 is formed on the surface of the second plug material layer 232 in the second opening 222, so that the fourth plug material layer 242 fills the second opening 222, and the rate of forming the third plug material layer 241 is lower than the rate of forming the fourth plug material layer 242.

[0077] The third plug material layer 241 provides material for subsequently forming a first plug in the first opening 221 ; and the fourth plug material layer 242 provides material for subsequently forming a second plug in the second opening 222 .

[0078] The second selective chemical vapor deposition process parameters include: the gas introduced includes WF 6 and H 2 , the WF 6 The flow rate range is 0 ml / min to 1000 ml / min, the H 2 The flow rate range is 0 ml / min to 10000 ml / min and the pressure is 0 torr to 100 torr.

[0079] The third plug material layer 241 and the fourth plug material layer 242 are made of the same material; the materials of the third plug material layer 241 and the fourth plug material layer 242 include: metal, the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum. In this embodiment, the material of the third plug material layer 241 and the fourth plug material layer 242 is tungsten.

[0080] The first selective chemical vapor deposition process is used to form the first plug material layer 231 and the second plug material layer 232 with good film quality and density, and is not prone to generating holes. An adhesion layer does not need to be formed, which is beneficial to reducing contact resistance. Since the passivation treatment can reduce the rate of forming the film layer by the selective chemical vapor deposition process, and the degree of passivation caused to the first plug material layer 231 is greater than the degree of passivation caused to the second plug material layer 232, the rate of forming the third plug material layer 241 by the second selective chemical vapor deposition process is lower than the rate of forming the fourth plug material layer 242, thereby reducing the difference in the rate of forming the film layer in the first opening 221 and the second opening 222 by the first selective chemical vapor deposition process, so that the overall thickness of the first plug material layer 231 and the third plug material layer 241 formed in the first opening 221 is close to the overall thickness of the second plug material layer 232 and the fourth plug material layer 242 formed in the second opening 222, thereby improving the morphology uniformity of the film layer formed in the first opening 221 and the film layer formed in the second opening 222, which is beneficial to improving the performance of the formed semiconductor structure.

[0081] Please refer to Fig.12 After forming the third plug material layer 241 and the fourth plug material layer 242 , a second ion implantation is performed on the first dielectric layer 220 to reduce the gaps between the first plug material layer 231 , the second plug material layer 232 , the third plug material layer 241 , and the fourth plug material layer 242 and the first dielectric layer 220 .

[0082] The process parameters of the second ion implantation include: implanting the second ion, and the relative atomic mass of the second ion is greater than the relative atomic mass of an element in the first dielectric layer material, the implantation energy ranges from 1 keV to 100 keV, the dose ranges from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and the number of cycles is 1 to 1000.

[0083] Since the injected second ions can replace the atomic positions in the lattice of the material of the first dielectric layer 220, and the relative atomic mass of the second ions is greater than the relative atomic mass of an element in the first dielectric layer 220, the film layer expands after the second ion implantation treatment, thereby reducing the gaps between the first plug material layer 231, the second plug material layer 232, the third plug material layer 241 and the fourth plug material layer 242 and the first dielectric layer 220, which is beneficial to reducing the loss of the grinding solution used in the subsequent planarization process on the first conductive layer 211 and the second conductive layer 212, thereby improving the performance of the formed semiconductor structure.

[0084] By adopting the second ion implantation in the higher implantation energy range, the region of the implanted first dielectric layer 220 can be made deep enough, so that the gap of the entire depth between the film layer in the first opening 221 and the first dielectric layer 220 can be reduced, and the gap of the entire depth between the film layer in the second opening 222 and the first dielectric layer 220 can be reduced, thereby ensuring that the loss of the first conductive layer 211 and the second conductive layer 212 caused by the grinding solution used in the subsequent planarization process is effectively reduced, thereby improving the performance of the formed semiconductor structure.

[0085] In this embodiment, the material of the first dielectric layer 220 contains silicon and oxygen, and the relative atomic mass of the second ions is greater than the relative atomic mass of silicon. The second ions are germanium ions.

[0086] In other embodiments, the second ions may also be tin ions.

[0087] In other embodiments, the second ion implantation may not be performed.

[0088] Please refer to Fig.13 After the second ion implantation, an adhesion layer 251 is formed on the surfaces of the first dielectric layer 220 , the third plug material layer 241 , and the fourth plug material layer 242 ; and a fifth plug material layer 252 is formed on the surface of the adhesion layer 251 .

[0089] The adhesion layer 251 has a function of being formed on the surface of the first dielectric layer 220 , so that the subsequent fifth plug material layer 252 can be well adhered to the adhesion layer 251 , thereby enabling the fifth plug material layer 252 to be well formed on the first dielectric layer 220 .

[0090] The material of the adhesion layer 251 includes titanium nitride or tantalum nitride.

[0091] By forming the fifth plug material layer 252 , the entire surface of the fifth plug material layer 252 is relatively flat, which is beneficial for a subsequent planarization process.

[0092] The material of the fifth plug material layer 252 includes: metal, and the metal includes copper, tungsten, aluminum, titanium, titanium nitride or tantalum. In this embodiment, the material of the fifth plug material layer 252 is tungsten.

[0093] Please refer to Fig.14 , planarize the fifth plug material layer 252 , the adhesion layer 251 , the third plug material layer 241 and the fourth plug material layer 242 until they are flush with or lower than the surface of the second plug material layer 232 , and form a first plug 261 in the first opening 221 , and form a second plug 262 in the second opening 222 .

[0094] In this embodiment, the planarization process is performed until the second plug material layer 232 ( Figure 7 as shown in ).

[0095] The planarization process includes: a chemical mechanical polishing process.

[0096] A grinding liquid is used in the chemical mechanical grinding process.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first conductive layer and a second conductive layer separated from each other; Forming a first dielectric layer on the substrate, wherein the first dielectric layer has a first opening and a second opening, wherein the first opening exposes the first conductive layer, and the second opening exposes the second conductive layer; Using a first selective chemical vapor deposition process, forming a first plug material layer in the first opening, forming a second plug material layer in the second opening, and a top surface of the first plug material layer is higher than a top surface of the second plug material layer; performing a passivation process on the first plug material layer and the second plug material layer; After the passivation treatment, a second selective chemical vapor deposition process is used to form a third plug material layer on the surface of the first plug material layer in the first opening, so that the third plug material layer fills the first opening, and a fourth plug material layer is formed on the surface of the second plug material layer in the second opening, so that the fourth plug material layer fills the second opening, and the rate of forming the third plug material layer is lower than the rate of forming the fourth plug material layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first plug material layer and the second plug material layer and before the passivation treatment, the first dielectric layer exposed by the first opening and the second opening is subjected to a first ion implantation to reduce the width of the first opening above the surface of the first plug material layer and reduce the width of the second opening above the second plug material layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The passivation treatment method includes: using a remote plasma process to introduce a passivation gas; the parameters of the remote plasma process include: an angle between the incident direction of the passivation gas and the normal line of the substrate surface, and the angle is greater than 0 degrees.

4. The method for forming a semiconductor structure according to claim 3, wherein: The passivation gas includes: a nitrogen-containing gas, and the nitrogen-containing gas includes nitrogen, ammonia, nitric oxide or nitrous oxide.

5. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the first ion implantation process include: implanting a first ion whose relative atomic mass is greater than the relative atomic mass of an element in the first dielectric layer, an implantation energy ranging from 1 keV to 100 keV, a dose ranging from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and a cycle number ranging from 1 to 1000.

6. The method for forming a semiconductor structure according to claim 5, wherein: The material of the first dielectric layer contains silicon and oxygen, and the relative atomic mass of the first ions is greater than the relative atomic mass of silicon.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first ions include germanium ions or tin ions.

8. The method for forming a semiconductor structure according to claim 1, wherein: The first plug material layer and the second plug material layer are made of the same material; the first plug material layer and the second plug material layer include metals, including copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

9. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the first selective chemical vapor deposition process include: the gases introduced include WF6 and H2, the flow range of WF6 is 0 ml / min to 1000 ml / min, the flow range of H2 is 0 ml / min to 10000 ml / min, and the pressure is 0 torr to 100 torr.

10. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After the passivation process, a cleaning process is performed before the second selective chemical vapor deposition process.

11. The method for forming a semiconductor structure according to claim 10, wherein: The cleaning method includes: introducing a reducing gas to allow the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.

12. The method for forming a semiconductor structure according to claim 1, wherein: The third plug material layer and the fourth plug material layer are made of the same material; the third plug material layer and the fourth plug material layer include metals, including copper, tungsten, aluminum, titanium, titanium nitride or tantalum.

13. The method for forming a semiconductor structure according to claim 1, wherein: The second selective chemical vapor deposition process parameters include: the introduced gases include WF6 and H2, the flow range of WF6 is 0 ml / min to 1000 ml / min, the flow range of H2 is 0 ml / min to 10000 ml / min, and the pressure is 0 torr to 100 torr.

14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming an adhesion layer on the surfaces of the first dielectric layer, the third plug material layer and the fourth plug material layer; forming a fifth plug material layer on the surface of the adhesion layer; The fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer are planarized until they are flush with or lower than a surface of the second plug material layer, a first plug is formed in the first opening, and a second plug is formed in the second opening.

15. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: After forming the third plug material layer and the fourth plug material layer and before forming the adhesion layer, the first dielectric layer is subjected to second ion implantation to reduce gaps between the first plug material layer, the second plug material layer, the third plug material layer and the fourth plug material layer and the first dielectric layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The process parameters of the second ion implantation include: implanting the second ion, and the relative atomic mass of the second ion is greater than the relative atomic mass of an element in the first dielectric layer material, the implantation energy ranges from 1 keV to 100 keV, the dose ranges from 1E10 atoms per square centimeter to 1E100 atoms per square centimeter, and the number of cycles is 1 to 1000.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the first dielectric layer contains silicon and oxygen, and the relative atomic mass of the second ions is greater than the relative atomic mass of silicon.

18. The method for forming a semiconductor structure according to claim 17, wherein: The second ions include germanium ions or tin ions.

19. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises: a substrate and a second dielectric layer located on the surface of the substrate, the first conductive layer and the second conductive layer are located in the second dielectric layer, and the second dielectric layer exposes the first conductive layer and the second conductive layer.

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