A method for integrating a Schottky diode in a trench-type double-layer gate structure

Abstract

The invention provides a method for integrating a Schottky diode in a trench-type double-layer gate structure, which comprises the following steps: forming an SBD region, a cell region, and a first trench region and a second trench region; forming a first dielectric layer and depositing polysilicon; performing photolithography and back etching on the polysilicon, and removing the polysilicon in the SBD region, the cell region, and the upper section of the second trench region; depositing a high-density plasma oxide film, and removing the high-density plasma oxide film in the SBD region, the cell region, and the upper section of the second trench region, and forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region, and the second trench region; removing the first gate oxide layer in the SBD region; forming a second gate oxide layer in the SBD region; forming a second polysilicon layer in the SBD region, the cell region, and the second trench region; forming a first implantation region and a second implantation region in the region between the cell region and the first trench region and the region between the first trench region and the second trench region; and forming a contact hole and filling it with metal.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for integrating a Schottky diode in a trench-type double-layer gate structure. Background Art

[0002] The Schottky diode is named after its inventor, Dr. Schottky. SBD is the abbreviation of Schottky Barrier Diode (SBD). SBD is not made using the principle of PN junction formed by the contact between P-type semiconductor and N-type semiconductor, but is made using the principle of metal-semiconductor junction formed by the contact between metal and semiconductor. Therefore, SBD is also called metal-semiconductor (contact) diode or surface barrier diode, which is a hot carrier diode.

[0003] The Schottky diode is a metal-semiconductor device made by using the rectifying characteristics of the potential barrier formed on the contact surface of the metal A as the positive electrode and the N-type semiconductor B as the negative electrode. Because there are a large number of electrons in the N-type semiconductor and only a very small number of free electrons in the metal, the electrons diffuse from the high-concentration B to the low-concentration A. Obviously, there are no holes in the metal A, and there is no diffusion movement of holes from A to B. As the electrons continue to diffuse from B to A, the electron concentration on the surface of B gradually decreases, and the surface electrical neutrality is destroyed, so a potential barrier is formed, and its electric field direction is from B to A. However, under the action of the electric field, the electrons in A will also drift from A to B, thereby weakening the electric field formed by the diffusion movement. When a space charge region of a certain width is established, the electron drift movement caused by the electric field and the electron diffusion movement caused by different concentrations reach a relative balance, and a Schottky barrier is formed.

[0004] SBD has the advantages of high switching frequency, low switching loss and low forward voltage, and is particularly suitable for high-frequency applications, but its reverse bias voltage is low and reverse leakage current is relatively large. The development of high-voltage SBD above 100V has always been a research topic and a hot topic of concern. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for integrating a Schottky diode in a trench double-layer gate structure, so as to solve the problems of low reverse bias voltage and large reverse leakage current of the Schottky diode in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for integrating a Schottky diode in a trench double-layer gate structure, which at least comprises:

[0007] Step 1: forming a plurality of grooves on the substrate, wherein the plurality of grooves are respectively an SBD region, a cell region, and a first groove region and a second groove region;

[0008] Step 2: forming a first dielectric layer on the sidewalls and bottoms of the plurality of trenches;

[0009] Step 3, depositing polysilicon to fill the plurality of trenches;

[0010] Step 4: performing photolithography and back etching on the polysilicon in the plurality of trenches, wherein the polysilicon in the SBD region, the cell region and the middle and upper portion of the second trench region is removed by etching, and the remaining polysilicon in the SBD region, the cell region and the second trench region forms a first polysilicon layer; and all the polysilicon in the first trench region is retained;

[0011] Step 5: depositing a high-density plasma oxide film to fill the SBD region, the cell region and the middle and upper portion of the second trench region, and the high-density plasma oxide film covers the upper surfaces of the plurality of trenches on the substrate;

[0012] Step 6, grinding the high-density plasma oxide film on the upper surface of the substrate until the high-density plasma oxide film is higher than 3000 angstroms above the plurality of grooves;

[0013] Step 7: performing photolithography and back etching on the high-density plasma oxide film to remove the high-density plasma oxide film in the SBD region, the cell region and the upper portion of the second trench region, and the high-density plasma oxide film of a remaining portion of the height in the SBD region, the cell region and the second trench region covers the first polysilicon layer;

[0014] Step eight, forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region and the second trench region;

[0015] Step nine, removing the first gate oxide layer in the SBD region by photolithography and etching;

[0016] Step 10, forming a second gate oxide layer on the exposed surface in the SBD region;

[0017] Step 11: depositing polysilicon in the SBD region, the cell region and the second trench region to form a second polysilicon layer;

[0018] Step 12, performing ion implantation in the region between the cell region and the first trench region and the region between the first and second trench regions to form body regions respectively, wherein the body region is a first implantation region;

[0019] Step 13, performing ion implantation in the body region to form a second implantation region;

[0020] Step 14: Covering the upper surfaces of the plurality of grooves with a second dielectric layer;

[0021] Step 15, forming contact holes in the region between the SBD region and the cell region, in the first implantation region between the cell region and the first trench region, on the polysilicon in the first trench region, and on the second polysilicon layer in the second trench region;

[0022] Step 16: Covering the metal layer to fill the contact hole, and etching the metal layer to disconnect the metal layer on the first and second trench contact holes.

[0023] Preferably, in step one, the plurality of grooves are formed on the substrate by wet etching.

[0024] Preferably, in step 2, the first dielectric layer is formed on the sidewalls and bottoms of the plurality of trenches by deposition.

[0025] Preferably, the method for photolithography and back etching of the polysilicon in the multiple grooves in step four is: covering the multiple grooves with photoresist, photolithography opening the SBD area, the cell area and the second groove area, and then etching away the polysilicon in the upper part of the SBD area, the cell area and the second groove area, retaining all the polysilicon in the first groove area.

[0026] Preferably, in step six, the method of grinding the high-density plasma oxide film on the upper surface of the substrate is chemical mechanical grinding.

[0027] Preferably, the method of photolithography and back etching the high-density plasma oxide film in step seven is: covering the upper surfaces of the multiple grooves with photoresist, photolithography opens the SBD area, the cell area and the second groove area, and then wet-etching the high-density plasma oxide film in the SBD area, the cell area and the second groove area.

[0028] Preferably, the first gate oxide layer formed in step eight covers the bottom and sidewalls of the SBD region, the cell region and the upper section of the second trench region, and has a thickness of 250 to 1000 angstroms.

[0029] Preferably, the method of photolithography and etching to remove the first gate oxide layer in the SBD area in step nine is: covering the multiple grooves with photoresist, photolithography to open the cell area, the first and second groove areas, and then wet etching to remove the first gate oxide layer in the SBD area.

[0030] Preferably, the photoresist is removed before forming the second gate oxide layer in step ten, and the thickness of the formed second gate oxide layer is 50 to 250 angstroms.

[0031] Preferably, the method for forming the body region in step twelve is: covering the multiple grooves with photoresist, then photolithographically opening the area between the cell area and the first groove area, and the area between the first and second groove areas, and implanting to form the body region.

[0032] Preferably, the method for forming the contact hole in step fifteen is: after etching the second dielectric layer, sequentially etching the area between the SBD area and the cell area, the first injection area between the cell area and the first trench area, the polysilicon in the first trench area, and the second polysilicon layer in the second trench area to form the contact hole.

[0033] As described above, the method of integrating a Schottky diode in a trench double-layer gate structure of the present invention has the following beneficial effects: the present invention does not perform body region injection and Source injection in a part of the cell region, and performs the same type of injection as the body region at the bottom as the Source contact hole in the cell region, so that the Schottky diode is integrated inside the cell region. By adding a gate lithography, the gate oxide thickness of the trench double-layer gate MOS tube and the Schottky diode in the cell region can be distinguished, so as to achieve the adjustment and control of the threshold voltage of the Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram showing the structure of multiple grooves formed on a substrate in the present invention;

[0035] Figure 2 It is a schematic structural diagram showing a first dielectric layer formed on the sidewalls and bottoms of a plurality of trenches in the present invention;

[0036] Figure 3 It is a schematic diagram of the structure after polysilicon is deposited in a plurality of trenches in the present invention;

[0037] Figure 4 It is a schematic diagram of the structure after etching away the polysilicon in the SBD region, the cell region and the middle and upper section of the second trench region in the present invention;

[0038] Figure 5 It is a schematic diagram of the structure after high-density plasma oxide film is deposited in the present invention;

[0039] Figure 6 It is a schematic diagram showing the structure after the high-density plasma oxide film on the upper surface of the substrate is ground in the present invention;

[0040] Figure 7 It is a schematic diagram of the structure after the high-density plasma oxide film in the SBD region, the cell region and the upper portion of the second trench region is removed in the present invention;

[0041] Figure 8It is a schematic diagram showing the structure of forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region and the second trench region in the present invention;

[0042] Fig. 9 It is a schematic diagram of the structure after the first gate oxide layer in the SBD region is removed by photolithography and etching in the present invention;

[0043] Fig.10 It is a schematic diagram of the structure after the second gate oxide layer is formed on the surface exposed in the SBD region in the present invention;

[0044] Fig.11 It is a schematic diagram of the structure after forming a second polysilicon layer in the SBD region, the cell region and the second trench region in the present invention;

[0045] Fig.12 It is a schematic diagram of the structure after the first injection region is formed in the present invention;

[0046] Fig.13 It is a schematic diagram of the structure after ion implantation is performed in the body region to form a second implantation region in the present invention;

[0047] Fig.14 It is a schematic diagram showing a structure in which a second dielectric layer is covered on the upper surface of a plurality of grooves in the present invention;

[0048] Fig.15 It is a schematic diagram of the structure after the contact hole is formed in the present invention;

[0049] Fig.16 It is a schematic diagram of the structure after the metal layer is formed in the present invention. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] See also Figures 1 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] The present invention provides a method for integrating a Schottky diode in a trench-type double-layer gate structure, which at least comprises the following steps:

[0053] Step 1: forming a plurality of grooves on the substrate, wherein the plurality of grooves are respectively an SBD region, a cell region, and a first groove region and a second groove region; Figure 1 As shown, Figure 1 The schematic diagram of the structure of multiple grooves formed on the substrate in the present invention is shown. In step 1, multiple grooves are formed on the substrate, and the multiple grooves are respectively SBD area 01, cell area 02, first groove area 03, and second groove area 04.

[0054] Furthermore, in the present invention, in step 1 of this embodiment, the plurality of grooves are formed on the substrate by wet etching.

[0055] Step 2: forming a first dielectric layer on the sidewalls and bottoms of the plurality of trenches; Figure 2 As shown, Figure 2 The structure schematic diagram of forming the first dielectric layer on the sidewalls and bottom of multiple trenches in the present invention is shown. In step 2, the first dielectric layer 05 is formed on the bottom and sidewalls of the SBD region 01 , the cell region 02 , and the first trench region 03 and the second trench region 04 .

[0056] According to the present invention, in step 2 of this embodiment, the first dielectric layer is formed on the sidewalls and bottoms of the plurality of trenches by deposition.

[0057] Step 3: depositing polysilicon to fill the plurality of trenches; Figure 3 As shown, Figure 3 The structure diagram after polysilicon is deposited in multiple trenches in the present invention is shown. In step three, polysilicon 06 is deposited to fill the SBD region 01 , the cell region 02 , the first trench region 03 , and the second trench region 04 .

[0058] Step 4: performing photolithography and back etching on the polysilicon in the plurality of trenches, wherein the polysilicon in the SBD region, the cell region and the middle and upper portion of the second trench region is removed by etching, and the remaining polysilicon in the SBD region, the cell region and the second trench region forms a first polysilicon layer; and all the polysilicon in the first trench region is retained; Figure 4 As shown, Figure 4 The schematic diagram of the structure after etching away the polysilicon in the SBD area, the cell area, and the middle and upper part of the second trench area in the present invention is shown. In step 4, the polysilicon in the plurality of trenches is photolithographically and back-etched, wherein the polysilicon in the SBD area 01, the cell area 02, and the middle and upper part of the second trench area 04 is etched away, and the remaining polysilicon in the SBD area, the cell area, and the second trench area forms a first polysilicon layer 07; and all the polysilicon in the first trench area 02 is retained.

[0059] The present invention further provides that in step four of this embodiment, the method for photolithography and back etching of the polysilicon in the multiple grooves is: covering the multiple grooves with photoresist, photolithography opens the SBD area, the cell area and the second groove area, and then etching away the polysilicon in the upper and middle sections of the SBD area, the cell area and the second groove area, retaining all the polysilicon in the first groove area.

[0060] Step 5: depositing a high-density plasma oxide film to fill the SBD region, the cell region and the upper portion of the second trench region, and the high-density plasma oxide film covers the upper surfaces of the plurality of trenches on the substrate; Figure 5 As shown, Figure 5 It is a schematic diagram of the structure after the high-density plasma oxide film is deposited in the present invention. In step five, a high-density plasma oxide film 08 is deposited to fill the SBD area, the cell area and the upper part of the second trench area, and the high-density plasma oxide film covers the upper surfaces of the multiple trenches on the substrate.

[0061] Step 6: grinding the high-density plasma oxide film on the upper surface of the substrate until the high-density plasma oxide film is higher than 3000 angstroms above the plurality of grooves; Figure 6 As shown, Figure 6 The structure diagram after grinding the high density plasma oxide film on the upper surface of the substrate in the present invention is shown. In step six, the high density plasma oxide film 08 on the upper surface of the substrate is ground until the high density plasma oxide film 08 is higher than 3000 angstroms above the plurality of grooves.

[0062] According to the present invention, in step six of this embodiment, the method for grinding the high-density plasma oxide film on the upper surface of the substrate is chemical mechanical grinding.

[0063] Step 7: performing photolithography and back etching on the high-density plasma oxide film to remove the high-density plasma oxide film in the SBD region, the cell region and the upper portion of the second trench region, and the high-density plasma oxide film of a remaining portion of the height in the SBD region, the cell region and the second trench region covers the first polysilicon layer; Figure 7 As shown, Figure 7 It is a schematic diagram of the structure after the high-density plasma oxide film in the SBD region, the cell region and the upper portion of the second trench region is removed in the present invention. In step seven, the high-density plasma oxide film is photolithographically and back-etched to remove the high-density plasma oxide film in the SBD region 01, the cell region 02 and the upper portion of the second trench region 04. The remaining portion of the high-density plasma oxide film in the SBD region, the cell region and the second trench region covers the first polysilicon layer.

[0064] The present invention further comprises the following steps: in step seven of the present embodiment, the method for photolithography and back etching of the high-density plasma oxide film is as follows: covering the upper surfaces of the plurality of grooves with photoresist, photolithography opens the SBD region, the cell region and the second groove region, and then wet-etching the high-density plasma oxide film in the SBD region, the cell region and the second groove region.

[0065] Step eight, forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region and the second trench region; Figure 8 As shown, Figure 8 It is a schematic structural diagram of forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region and the second trench region in the present invention. The step eight forms a first gate oxide layer 09 on the exposed surfaces of the SBD region 01, the cell region 02 and the second trench region 04.

[0066] In the present invention, further, the first gate oxide layer formed in step eight of this embodiment covers the bottom and sidewalls of the SBD region, the cell region and the upper section of the second trench region, and has a thickness of 250 to 1000 angstroms.

[0067] Step nine: photolithography and etching to remove the first gate oxide layer in the SBD region; Fig. 9 As shown, Fig. 9 The structure diagram after the first gate oxide layer in the SBD region is removed by photolithography and etching in the present invention is shown. The step nine is to remove the first gate oxide layer in the SBD region 01 by photolithography and etching.

[0068] The present invention further comprises the method of removing the first gate oxide layer in the SBD region by photolithography and etching in step nine of this embodiment: covering the multiple grooves with photoresist, photolithographically opening the cell region, the first and second groove regions, and then wet etching to remove the first gate oxide layer in the SBD region.

[0069] Step 10: forming a second gate oxide layer on the exposed surface of the SBD region; Fig.10 As shown, Fig.10 The schematic diagram of the structure after the second gate oxide layer is formed on the surface exposed in the SBD region in the present invention is shown. The step ten forms the second gate oxide layer 11 on the surface exposed in the SBD region 01.

[0070] In the present invention, further, in step 10 of this embodiment, the photoresist is removed before forming the second gate oxide layer, and the thickness of the formed second gate oxide layer is 50 to 250 angstroms.

[0071] Step 11: depositing polysilicon in the SBD region, the cell region and the second trench region to form a second polysilicon layer; Fig.11 As shown, Fig.11 It is a schematic diagram of the structure after forming the second polysilicon layer in the SBD area, the cell area and the second trench area in the present invention. In step eleven, polysilicon is deposited in the SBD area 01, the cell area 02 and the second trench area 04 to form a second polysilicon layer 12.

[0072] Step 12, ion implantation is performed in the region between the cell region and the first trench region and the region between the first and second trench regions to form body regions respectively, wherein the body region is a first implantation region; Fig.12 As shown, Fig.12 It is a schematic diagram of the structure after the first injection region is formed in the present invention. In step twelve, ion implantation is performed in the region between the cell region 02 and the first groove region 03 and the region between the first and second groove regions to form body regions 13 respectively. The body region is the first injection region.

[0073] The present invention further provides that the method for forming the body region in step twelve of this embodiment is: covering the plurality of grooves with photoresist, then photolithographically opening the region between the cell region and the first groove region, and the region between the first and second groove regions, and implanting to form the body region.

[0074] Step 13: performing ion implantation in the body region to form a second implantation region; Fig.13 As shown, Fig.13 It is a schematic diagram of the structure after ion implantation is performed in the body region to form the second implantation region in the present invention. In step thirteen, ion implantation is performed in the body region 13 to form the second implantation region 14 .

[0075] Step 14: Covering the upper surfaces of the plurality of grooves with a second dielectric layer; Fig.14 As shown, Fig.14 It is a schematic structural diagram of covering the upper surfaces of the plurality of grooves with the second dielectric layer in the present invention. The step fourteen covers the upper surfaces of the plurality of grooves with the second dielectric layer 15 .

[0076] Step 15, forming contact holes in the region between the SBD region and the cell region, in the first implantation region between the cell region and the first trench region, on the polysilicon in the first trench region, and on the second polysilicon layer in the second trench region; Fig.15 As shown, Fig.15It is a schematic diagram of the structure after the contact holes are formed in the present invention. In step fifteen, contact holes 16 are respectively formed in the area between the SBD area and the cell area, in the first injection area between the cell area and the first trench area, on the polysilicon in the first trench area, and on the second polysilicon layer in the second trench area.

[0077] The present invention further provides that the method for forming the contact hole in step fifteen of this embodiment is: after etching the second dielectric layer, the area between the SBD area and the cell area, the first injection area between the cell area and the first trench area, the polysilicon in the first trench area, and the second polysilicon layer in the second trench area are sequentially etched to form the contact hole.

[0078] Step 16: Covering the metal layer to fill the contact hole, and etching the metal layer to disconnect the metal layer on the first and second trench contact holes. Fig.16 As shown, Fig.16 The structure diagram after the metal layer is formed in the present invention is shown. The sixteenth step is to cover the metal layer 17 to fill the contact hole, and etch the metal layer 17 to disconnect the metal layer 17 on the first and second trench contact holes.

[0079] In summary, the present invention does not perform body region injection and Source injection in part of the cell region. Like the Source contact hole in the cell region, the bottom is injected with the same type as the body region, so that the Schottky diode is integrated inside the cell region. By adding a gate lithography, the gate oxide thickness of the trench double-layer gate MOS tube and the Schottky diode in the cell region can be distinguished, and the threshold voltage of the Schottky diode can be adjusted and controlled. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for integrating a Schottky diode in a trench-type double-layer gate structure, characterized in that: At least: Step 1: forming a plurality of grooves on the substrate, wherein the plurality of grooves are respectively an SBD region, a cell region, and a first groove region and a second groove region; Step 2: forming a first dielectric layer on the sidewalls and bottoms of the plurality of trenches; Step 3, depositing polysilicon to fill the plurality of trenches; Step 4: performing photolithography and back etching on the polysilicon in the plurality of trenches, wherein the polysilicon in the SBD region, the cell region and the middle and upper portion of the second trench region is removed by etching, and the remaining polysilicon in the SBD region, the cell region and the second trench region forms a first polysilicon layer; and all the polysilicon in the first trench region is retained; Step 5: depositing a high-density plasma oxide film to fill the SBD region, the cell region and the middle and upper portion of the second trench region, and the high-density plasma oxide film covers the upper surfaces of the plurality of trenches on the substrate; Step 6, grinding the high-density plasma oxide film on the upper surface of the substrate until the high-density plasma oxide film is higher than 3000 angstroms above the plurality of grooves; Step 7: performing photolithography and back etching on the high-density plasma oxide film to remove the high-density plasma oxide film in the SBD region, the cell region and the upper portion of the second trench region, and the high-density plasma oxide film of a remaining portion of the height in the SBD region, the cell region and the second trench region covers the first polysilicon layer; Step eight, forming a first gate oxide layer on the exposed surfaces of the SBD region, the cell region and the second trench region; Step nine, removing the first gate oxide layer in the SBD region by photolithography and etching; Step 10, forming a second gate oxide layer on the exposed surface in the SBD region; Step 11: depositing polysilicon in the SBD region, the cell region and the second trench region to form a second polysilicon layer; Step 12, performing ion implantation in the region between the cell region and the first trench region and the region between the first and second trench regions to form body regions respectively, wherein the body region is a first implantation region; Step 13, performing ion implantation in the body region to form a second implantation region; Step 14: Covering the upper surfaces of the plurality of grooves with a second dielectric layer; Step 15, forming contact holes in the region between the SBD region and the cell region, in the first implantation region between the cell region and the first trench region, on the polysilicon in the first trench region, and on the second polysilicon layer in the second trench region; Step 16: Covering the metal layer to fill the contact hole, and etching the metal layer to disconnect the metal layer on the first and second trench contact holes.

2. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: In step one, the plurality of grooves are formed on the substrate by wet etching.

3. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: In step 2, the first dielectric layer is formed on the sidewalls and bottoms of the plurality of trenches by deposition.

4. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The method for photolithography and back etching of the polysilicon in the multiple grooves in step four is: covering the multiple grooves with photoresist, photolithography opens the SBD area, the cell area and the second groove area, and then etches away the polysilicon in the upper part of the SBD area, the cell area and the second groove area, retaining all the polysilicon in the first groove area.

5. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: In step six, the method for grinding the high-density plasma oxide film on the upper surface of the substrate is chemical mechanical grinding.

6. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The method of photolithography and back etching the high-density plasma oxide film in step seven is: covering the upper surfaces of the multiple grooves with photoresist, photolithography opens the SBD area, the cell area and the second groove area, and then wet-etching the high-density plasma oxide film in the SBD area, the cell area and the second groove area.

7. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The first gate oxide layer formed in step eight covers the bottom and sidewalls of the SBD region, the cell region and the upper section of the second trench region, and has a thickness of 250 to 1000 angstroms.

8. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The method of removing the first gate oxide layer in the SBD area by photolithography and etching in step nine is: covering the multiple grooves with photoresist, opening the cell area, the first and second groove areas by photolithography, and then removing the first gate oxide layer in the SBD area by wet etching.

9. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 8, characterized in that: In step 10, the photoresist is removed before forming the second gate oxide layer, and the thickness of the formed second gate oxide layer is 50-250 angstroms.

10. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The method for forming the body region in step twelve is: covering the plurality of grooves with photoresist, then photolithographically opening the region between the cell region and the first groove region, and the region between the first and second groove regions, and implanting to form the body region.

11. The method for integrating a Schottky diode in a trench double-layer gate structure according to claim 1, characterized in that: The method for forming the contact hole in step fifteen is: after etching the second dielectric layer, sequentially etching the area between the SBD area and the cell area, the first injection area between the cell area and the first trench area, the polysilicon in the first trench area, and the second polysilicon layer in the second trench area to form the contact hole.

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