Silicon carbide semiconductor device, power conversion device, and method for manufacturing silicon carbide semiconductor device

Abstract

The present invention aims to suppress the variation of threshold voltage and the generation of cracks in a barrier metal in a silicon carbide semiconductor device. The silicon carbide semiconductor device (101) comprises: a silicon carbide substrate (11); a semiconductor layer (12) formed on the silicon carbide substrate (11); a gate electrode (18) facing the semiconductor layer (12) via a gate insulating film (26); an interlayer insulating film (19) covering the gate electrode (18); a barrier metal formed on the interlayer insulating film (19); and a top surface electrode covering the barrier metal, wherein the barrier metal has a two-layer structure consisting of a barrier metal (21) and a barrier metal (22), wherein the barrier metal (21) on the interlayer insulating film (19) side is made of the same metal as the barrier metal (22) and has a smaller thickness than the barrier metal (22).

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device. Background Art

[0002] Currently, silicon carbide semiconductor devices employ barrier metals to prevent diffusion of metal materials from electrodes (e.g., Patent Document 1). To minimize variations in threshold voltage, the thickness of a single barrier metal layer is preferably as thick as possible (e.g., Patent Document 2, paragraph 0021), with the thickness of the single barrier metal layer preferably being greater than or equal to 100 nm.

[0003] However, there is a problem: the thicker the barrier metal layer, the more likely cracks will form in the barrier metal or interlayer insulating film during post-processing or electrical screening due to the internal stress of the barrier metal. Furthermore, cracks can create areas that are no longer protected by the barrier metal, causing fluctuations in the threshold voltage.

[0004] Furthermore, in Embodiment 5 of Patent Document 2, it is described that the barrier metal has a two-layer structure consisting of a TiSi layer and a Ti layer. However, if the barrier metal has a two-layer structure consisting of different materials, there is a problem that thermal stress caused by the difference in thermal expansion coefficient may be applied between the first and second layers, causing cracks.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-182032

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2012-129503 Summary of the Invention

[0007] An object of the present invention is to suppress variations in threshold voltage and to prevent the generation of cracks in a barrier metal in a silicon carbide semiconductor device.

[0008] The silicon carbide semiconductor device of the present invention comprises: a silicon carbide substrate; a semiconductor layer formed on the silicon carbide substrate; a gate electrode opposite to the semiconductor layer via a gate insulating film; an interlayer insulating film covering the gate electrode; a barrier metal formed on the interlayer insulating film; and an upper surface electrode covering the barrier metal, wherein the barrier metal has a two-layer structure consisting of a first barrier metal and a second barrier metal, and the barrier metal on the interlayer insulating film side, i.e., the first barrier metal, is composed of the same metal as the second barrier metal and has a smaller thickness than the second barrier metal.

[0009] Effects of the Invention

[0010] According to the technology of the present invention, in a silicon carbide semiconductor device, it is possible to suppress variations in threshold voltage and to suppress the generation of cracks in a barrier metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a top view of the silicon carbide semiconductor device according to the first embodiment.

[0012] Figure 2 This is a cross-sectional view of a cell region of the silicon carbide semiconductor device according to the first embodiment.

[0013] Figure 3 This is a cross-sectional view of the gate pad region of the silicon carbide semiconductor device according to the first embodiment.

[0014] Figure 4 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0015] Figure 5 sectional views showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0016] Figure 6 sectional views showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0017] Figure 7 sectional views showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0018] Figure 8 sectional views showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0019] Figure 9 is a cross-sectional view of a silicon carbide semiconductor device according to a comparative example.

[0020] Figure 10 This is a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment.

[0021] Figure 11 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device according to the second embodiment.

[0022] Figure 12 This is a cross-sectional view of a silicon carbide semiconductor device according to a third embodiment.

[0023] Figure 13 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device according to the third embodiment.

[0024] Figure 14 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device according to the fourth embodiment.

[0025] Figure 15It is a block diagram showing the structure of the power conversion system of Embodiment 5. Detailed Embodiment

[0026] In this specification, the first conductivity type of the semiconductor is set to n-type, and the second conductivity type is set to p-type. However, the first conductivity type may also be set to p-type, and the second conductivity type may be set to n-type. Additionally, , , ,

[0033] ,

[0032] ,

[0035] ,

[0034] marks such as n-type and n-type indicate that the n-type impurity concentration increases in the order of the description. That is, compared with n-type, the n-type has a higher impurity concentration. For - marks such as p-type and p-type, this relationship of impurity concentration also applies to the p-type impurity concentration.

[0027] <A. Embodiment 1>

[0028] <A-1. Structure>

[0029] <A-1-1. Planar Structure><A-1-1. Planar Structure>

[0030] Figure 1 It is a top view of the silicon carbide semiconductor device 101 of Embodiment 1. As Figure 1 shown, the silicon carbide semiconductor device 101 is configured to have a cell region 1, an end region 2, and a pad region 3. In addition, Figure 1 the shown top view is applicable not only to the silicon carbide semiconductor device 101 of Embodiment 1 but also to semiconductor devices of other embodiments and semiconductor devices of comparative examples described later.

[0031] In the following description, the silicon carbide semiconductor device 101 is described as a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0032] The cell region 1 is a region where a semiconductor element structure is formed and operates as a semiconductor element. When the silicon carbide semiconductor device 101 is a MOSFET, a MOSFET structure is formed in the cell region 1 and operates as a MOSFET.

[0033] The end region 2 is provided to surround the cell region 1 and the pad region 3 and is responsible for maintaining the breakdown voltage of the silicon carbide semiconductor device 101.

[0034] The pad region 3 is a region where a control pad 4 for controlling the silicon carbide semiconductor device 101 is provided and is adjacent to the cell region 1. In addition, the cell region 1 and the pad region 3 together are also referred to as the element region.

[0035] ​​The control pad 4 is, for example, a current sensing pad 4a or a gate pad 4b. The current sensing pad 4a is a control pad for detecting the current flowing through the cell region 1. The current sensing pad 4a is electrically connected to a part of the cell region 1, so that when a current flows through the cell region 1, a current of one fraction to one ten-thousandth of the current flowing through the entire cell region 1 flows through the current sensing pad 4a. The current sensing pad 4a may be provided in multiple numbers as shown in Figure 1 , or may be provided with only one. The current sensing pad 4a is also referred to as a sensing cell region. On the other hand, the gate pad 4b is connected to the gate electrode of the cell region 1 to control the current flowing through the cell region 1. The region where the gate pad 4b is formed is also referred to as the gate pad region.

[0036] <A-1-2. Cross-sectional structure>

[0037] Figure 2 and Figure 3 are cross-sectional views of the silicon carbide semiconductor device 101. Figure 2 is Figure 1 a cross-sectional view of the cell region 1 at the line A-A. In addition, Figure 1 the cross-sectional view of the current sensing pad 4a at the line B-B of Figure 2 is also the same as that shown in Figure 3 is Figure 1 a cross-sectional view of the gate pad region at the line C-C of

[0038] As shown in Figure 2 , the silicon carbide semiconductor device 101 is configured to include a silicon carbide substrate 11, a semiconductor layer 12, a gate insulating film 26, a gate electrode 18, barrier metals 21, 22, a source electrode 23, and a drain electrode 24 in the cell region 1.

[0039] The silicon carbide substrate 11 is of n - type and has a first substrate main surface S111 and a second substrate main surface S112 opposite to the first substrate main surface S111.

[0040] The semiconductor layer 12 is provided on the first substrate main surface S111 of the silicon carbide substrate 11 and has a first semiconductor layer main surface S121 and a second semiconductor layer main surface S122 opposite to the first semiconductor layer main surface S121. The second semiconductor layer main surface S122 contacts the first substrate main surface S111 of the silicon carbide substrate 11. The semiconductor layer 12 has an n - type epitaxial layer 14, multiple p-type well regions 15, multiple n-type source regions 16, and multiple p+-type contact regions 17.

[0041] The epitaxial layer 14 is provided on the first substrate main surface S111 of the silicon carbide substrate 1 with a first substrate main surface S111.

[0042] The plurality of well regions 15 are selectively formed in the surface layer of the epitaxial layer 14 on the first semiconductor layer principal surface S121 side.

[0043] Each source region 16 is selectively formed in the surface layer of each well region 15 on the first semiconductor layer principal surface S121 side.

[0044] Each contact region 17 is selectively formed in the surface layer of each well region 15 on the first semiconductor layer main surface S121 side, adjacent to each source region 16. Alternatively, the contact region 17 may not exist in the silicon carbide semiconductor device 101.

[0045] The surface layer of the well region 15 functions as a channel region, being sandwiched between the source region 16 and the epitaxial layer 14. A gate insulating film 26 is formed on the channel region.

[0046] The gate electrode 18 is formed on the gate insulating film 26. The gate electrode 18 faces the channel region of the well region 15 with the gate insulating film 26 interposed therebetween.

[0047] The interlayer insulating film 19 is formed so as to cover the gate electrode 18. The interlayer insulating film 19 is a thermally oxidized film. Contact holes 19h are formed in the interlayer insulating film 19 to expose the source region 16 and the contact region 17.

[0048] A barrier metal 21 is formed in the contact hole 19h and on the interlayer insulating film 19. The barrier metal 21 is in contact with the source region 16 and the contact region 17 in the contact hole 19h.

[0049] A barrier metal 22 is formed on the barrier metal 21. That is, the silicon carbide semiconductor device 101 has two barrier metal layers: a lower barrier metal 21 and an upper barrier metal 22. The barrier metal 21 is also referred to as a first barrier metal, and the barrier metal 22 is also referred to as a second barrier metal. The barrier metals 21 and 22 are made of the same metal material. With respect to the barrier metal 21, in order to suppress variations in the threshold voltage and to suppress cracks, the thickness is preferably less than or equal to 100 nm. With respect to the barrier metal 22, in order to suppress variations in the threshold voltage and to suppress cracks, the thickness is preferably greater than that of the barrier metal 21 and less than or equal to 100 nm. The total thickness of the barrier metals 21 and 22 is greater than or equal to 100 nm and less than or equal to 200 nm.

[0050] The source electrode 23 is formed on the barrier metal 22 and is in contact with the source region 16 and the contact region 17 via the barrier metals 21 and 22. The source electrode 23 is an example of an upper surface electrode.

[0051] The drain electrode 24 is formed on the second main surface S112 of the silicon carbide substrate 11. The drain electrode 24 is an example of a bottom surface electrode.

[0052] On the other hand, in the gate pad region, as Figure 3 shown, a field oxide film 27 is formed on the upper surface of the well region 15, and the gate electrode 18 extends over the field oxide film 27. Further, in the gate pad region, the interlayer insulating film 19 is removed to expose the gate electrode 18. On the upper surface of the exposed gate electrode 18, the above-described barrier metals 21 and 22 are formed, and a gate pad 4b is formed thereon. In addition, the source electrode 23 and the gate pad 4b are formed by the same process, but are electrically separated by patterning together with the barrier metals 21 and 22.

[0053] <A-2. Manufacturing process>

[0054] Figure 4 is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 101. Further, Figures 5 to 8 is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device 101. Hereinafter, according to Figure 4 the flowchart of Figures 5 to 8 the manufacturing process of the silicon carbide semiconductor device 101 will be described with reference to Figures 5 to 8 In correspondence with the cross-sectional view along the Figure 1 line A-A or B-B of

[0055] First, a silicon carbide substrate 11 is prepared (step S101).

[0056] Next, epitaxial growth is performed on the first main surface S111 of the silicon carbide substrate 11 to form an epitaxial layer 14 (step S102). Here, the concentrations of the n-type impurities contained in the silicon carbide substrate 11 and the epitaxial layer 14 are appropriately selected according to the breakdown voltage of the semiconductor device to be manufactured. Thus, the structure shown in Figure 5 is obtained.

[0057] Next, ions of p-type impurities and n-type impurities are implanted from the upper surface of the epitaxial layer 14, and the implanted ions are diffused in the epitaxial layer 14 by heat treatment or the like, whereby well regions 15, source regions 16, and contact regions 17 are formed in the unit region 1 and the current sense pad 4a (step S1o3).

[0058] Specifically, a masking process is performed on the upper surface of epitaxial layer 14. Masking involves applying a resist and using photolithography to create openings in designated areas of the resist. P-type impurities such as boron (B) are implanted into epitaxial layer 14 through the resist openings. Heat treatment diffuses the p-type impurities, forming multiple well regions 15. Multiple well regions 15 are selectively formed on the upper surface of epitaxial layer 14.

[0059] The depths and p-type impurity concentrations of the multiple well regions 15 can be the same. In this case, since only a single ion implantation is required to form the multiple well regions 15, the productivity of the silicon carbide semiconductor device 101 is improved. Furthermore, since the depths of the multiple well regions 15 are the same, electric field concentration can be mitigated, thereby suppressing a decrease in withstand voltage. Furthermore, the depths and p-type impurity concentrations of the multiple well regions 15 can be varied by performing multiple ion implantations.

[0060] Next, a mask is applied to the upper surfaces of epitaxial layer 14 and well region 15, and n-type impurities are implanted into well region 15 through the openings in the resist. The implanted n-type impurities are, for example, arsenic (As) or phosphorus (P). Then, a heat treatment is performed to diffuse the n-type impurities within well region 15, thereby forming source region 16. Source region 16 is selectively formed in the surface layer of well region 15.

[0061] After that, a mask is applied to the upper surface of the epitaxial layer 14, and p-type impurities such as boron are implanted into the well region 15 through the opening of the resist. Then, the p-type impurities are diffused by heat treatment, thereby forming a p+ type contact region 17. The contact region 17 is selectively formed on the surface of the well region 15 adjacent to the source region 16. In this way, a semiconductor layer 12 including the epitaxial layer 14, the well region 15, the source region 16, and the contact region 17 is formed, and a semiconductor layer 12 including the epitaxial layer 14, the well region 15, the source region 16, and the contact region 17 is obtained. Figure 6 The structure shown.

[0062] Next, a gate insulating film 26, a gate electrode 18, and an interlayer insulating film 19 are formed on the cell region 1 and the current sensing pad 4a (step S104). Specifically, the wafer is first heated in an oxygen-containing atmosphere to form a gate insulating film 26 made of SiO2 on the upper surface of the semiconductor layer 12. Polycrystalline silicon doped with n-type or p-type impurities is then deposited on the gate insulating film 26 by CVD (Chemical Vapor Deposition) or other methods to form the gate electrode 18.

[0063] Then, an interlayer insulating film 19 is formed on the gate electrode 18. The interlayer insulating film 19 is made of, for example, SiO2 or TEOS (Tetraethyl Orthosilicate). Then, a mask is applied to the upper surface of the interlayer insulating film 19, and a portion of the interlayer insulating film 19 is etched through the opening of the resist, thereby forming a gate electrode 18. Figure 7 As shown, a contact hole 19h is formed in the interlayer insulating film 19. The contact hole 19h is formed above the well region 15 and the contact region 17.

[0064] Next, in the cell region 1, a barrier metal 21 is formed in the contact hole 19h of the interlayer insulating film 19 and on the interlayer insulating film 19 (step S105). The barrier metal 21 is formed by forming a titanium (Ti) film using PVD (Physical Vapor Deposition) or CVD.

[0065] After forming the barrier metal 21, titanium (Ti) is continuously formed by PVD (Physical Vapor Deposition) or CVD without exposing the wafer to the atmosphere. In this way, a barrier metal 22 is formed on the barrier metal 21 in the cell region 1 (step S106). Here, the barrier metal 22 is formed thicker than the barrier metal 21. In this way, Figure 8 The structure shown.

[0066] Next, the source electrode 23 is formed on the barrier metal 22 (step S107). The source electrode 23 is formed, for example, by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 22 by PVD such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be further formed on the aluminum silicon alloy by chemical plating or electroplating, and the aluminum silicon alloy and the nickel alloy can be combined to form the source electrode 23. According to the plating process, a thick metal film can be easily formed as the source electrode 23. Therefore, the heat capacity of the source electrode 23 is increased and the heat resistance is improved. The formation of the nickel alloy by the above-mentioned plating process can also be implemented after the formation of the drain electrode 24 described later.

[0067] Next, a drain electrode 24 is formed on the second substrate main surface S112 of the silicon carbide substrate 11. The drain electrode 24 is formed across the unit region 1 and the terminal region 2. The drain electrode 24 is formed, for example, by depositing aluminum silicon alloy or titanium by PVD such as sputtering or evaporation. In addition, the drain electrode 24 can also be formed by stacking multiple metals such as aluminum silicon alloy, titanium, nickel or gold. In addition, a metal film can be further formed on the metal film formed by PVD by chemical plating or electroplating, and the metal film formed by PVD and the metal film formed by plating treatment can be combined to form the drain electrode 24. Thus, Figure 2The structure shown.

[0068] Multiple silicon carbide semiconductor devices 101 are fabricated in a matrix on a single n-type wafer. Thus, one wafer is cut into individual silicon carbide semiconductor devices 101 by laser cutting or blade cutting, thereby completing the silicon carbide semiconductor devices 101.

[0069] <A-3. Variation>

[0070] Above, the metal materials of the barrier metals 21 and 22 were described as Ti. However, as long as the metal materials of the barrier metals 21 and 22 are the same, it is not limited to Ti, and the same effect can be obtained even with TiN or TiSi. When the metal materials of the barrier metals 21 and 22 are TiN, the barrier metal 21 is formed by heat treatment in an N2 environment after depositing titanium (Ti) by PVD (Physical Vapor Deposition) or CVD. The annealing temperature is 500 - 1100 °C, and the time is about 1 hour. A natural oxide film can also be formed on the TiN. Thereafter, the barrier metal 22 is formed in the same manner as the barrier metal 21.

[0071] <A-4. Effect>

[0072] Figure 9 It is a cross-sectional view of a silicon carbide semiconductor device 100 of a comparative example having a single-layer barrier metal 20. For the silicon carbide semiconductor device 100, by increasing the thickness of the barrier metal 20, the variation of the threshold voltage can be suppressed. However, there is a problem that the thicker the barrier metal 20, the more likely cracks are to occur in the barrier metal 20 or the interlayer insulating film 19 due to the influence of the internal stress of the barrier metal 20. As the cause of the cracks generated in the barrier metal 20, there is heat generated during a processing step of cutting out a chip from a semiconductor wafer such as dicing cut, or heat stress generated by current application during a screening test with poor electrical characteristics. Moreover, if cracks occur, unprotected parts that cannot be protected by the barrier metal 20 are locally generated, so that variations in the threshold voltage occur.

[0073] In contrast, the silicon carbide semiconductor device 101 of the first embodiment includes two barrier metal layers 21 and 22. Furthermore, the lower barrier metal 21 is thinner than the upper barrier metal 22. Specifically, the silicon carbide semiconductor device 101 is divided into a cell region 1 and a sensing cell region adjacent to the cell region 1 when viewed from above. The silicon carbide semiconductor device 101 includes: a silicon carbide substrate 11; a semiconductor layer 12 formed on the silicon carbide substrate 11; a gate electrode 18 facing the semiconductor layer 12 via a gate insulating film 26; an interlayer insulating film 19 covering the gate electrode 18; a barrier metal formed on the interlayer insulating film 19; and a top surface electrode covering the barrier metal. The barrier metal layer has a two-layer structure consisting of the barrier metal 21 and the barrier metal 22. The barrier metal 21 on the interlayer insulating film 19 side is made of the same metal as the barrier metal 22 and is thinner than the barrier metal 22.

[0074] In the manufacturing method of the silicon carbide semiconductor device 101 of embodiment 1, a silicon carbide substrate 11 is prepared, a semiconductor layer 12 is formed on the silicon carbide substrate 11, a gate electrode 18 is formed opposite to the semiconductor layer 12 via a gate insulating film 26, an interlayer insulating film 19 is formed to cover the gate electrode 18, a barrier metal 21 is formed on the interlayer insulating film 19, a barrier metal 22 composed of the same metal as the barrier metal 21 and thicker than the barrier metal 21 is formed on the barrier metal 21, and an upper surface electrode covering the barrier metal 22 is formed.

[0075] Therefore, even if cracks are generated in the upper barrier metal 22, the possibility of cracks being generated in the thin lower barrier metal 21 is lower than that in the upper barrier metal 22. Therefore, even if cracks are generated in the upper barrier metal 22, the cracks are suppressed by the lower barrier metal 21, and the propagation of the cracks into the interlayer insulating film 19 is suppressed, thereby suppressing the fluctuation of the threshold voltage.

[0076] Furthermore, because the barrier metals 21 and 22 are made of the same metal material, the interatomic bonding between the barrier metals 21 and 22 is stronger than if they were made of different materials. Therefore, even if the first barrier metal 21 is thin, its strong bond with the second barrier metal 22 further suppresses hydrogen ion intrusion into the gate insulating film 26, which can cause threshold voltage fluctuations. Furthermore, if the barrier metals 21 and 22 are made of different metal materials, the thermal expansion coefficients differ between the barrier metals 21 and 22, generating thermal stress due to this difference in thermal expansion coefficients. However, by making the barrier metals 21 and 22 of the same metal material, this thermal stress is suppressed.

[0077] As described above, according to the silicon carbide semiconductor device 101 , variations in threshold voltage and the generation of cracks can be suppressed, thereby improving productivity.

[0078] <B. Embodiment 2>

[0079] <B-1. Structure>

[0080] Figure 10 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device 102 of Embodiment 2. Figure 9 It is along Figure 1 The cross-sectional view taken along the line A-A. The silicon carbide semiconductor device 102 has an oxide film 25 between the lower barrier metal 21 and the upper barrier metal 22 in addition to the structure of the silicon carbide semiconductor device 101 of Embodiment 1. The thickness of the oxide film 25 is extremely small, about around.

[0081] <B-2. Manufacturing Process>

[0082] Figure 11 It is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 102 of Embodiment 2. The manufacturing process of the silicon carbide semiconductor device 102 of Embodiment 2 will be described.

[0083] The processes (steps S101 to step S105) until the formation of the lower barrier metal 21 are the same as those in Embodiment 1.

[0084] After the formation of the lower barrier metal 21, the wafer is taken out, and an oxide film 25 with a thickness of about is formed by naturally oxidizing the surface of the barrier metal 21 made of Ti (step S105A).

[0085] The subsequent steps S106 and step S107 are the same as those in Embodiment 1.

[0086] <B-3. Effects>

[0087] The silicon carbide semiconductor device 102 has an oxide film 25 between the barrier metal 21 and the barrier metal 22 in addition to the structure of the silicon carbide semiconductor device 101 of Embodiment 1. In the manufacturing method of the silicon carbide semiconductor device 102, the oxide film 25 is formed on the barrier metal 21, and the barrier metal 22 is formed on the barrier metal 21隔着氧化膜25. The oxide film 25 prevents cracks generated in the upper barrier metal 22 from reaching the lower barrier metal 21, and suppresses the intrusion of hydrogen ions, which are the cause of threshold voltage variation, into the gate insulating film 26. Therefore, according to the silicon carbide semiconductor device 102 of Embodiment 2, compared with the silicon carbide semiconductor device 101 of Embodiment 1, the variation of the threshold voltage can be further suppressed.

[0088] <C. Embodiment 3>

[0089] <C-1. Structure>

[0090] Figure 12 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device 103 of Embodiment 3. Figure 12 This is a cross-sectional view along Figure 1 line A-A. For the silicon carbide semiconductor device 101 of Embodiment 1, the lower barrier metal 21 and the upper barrier metal 22 are formed over the entire region of the interlayer insulating film 19. In contrast, the silicon carbide semiconductor device 103 of Embodiment 3 is characterized in that the lower barrier metal 21 is not formed over a part of the region of the interlayer insulating film 19, but the upper barrier metal 22 is formed, thereby creating a step in the upper barrier metal 22.

[0091] <C-2. Manufacturing Process>

[0092] Figure 13 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 103 of Embodiment 3. The manufacturing process of the silicon carbide semiconductor device 103 of Embodiment 3 will be described.

[0093] The processes up to the formation of the lower barrier metal 21 (Steps S101 to Step S105) are the same as those of Embodiment 1. After the lower barrier metal 21 is formed, the barrier metal 21 over a part of the region of the interlayer insulating film 19 is removed (Step S105B).

[0094] The removal of the barrier metal 21 is performed, for example, by the following method. That is, through a photolithography process, a resist pattern is formed over the barrier metal 21, and the barrier metal 21 is locally etched. After that, the resist is removed to complete the patterning of the barrier metal 21.

[0095] The subsequent Steps S106 and Step S107 are the same as those of Embodiment 1.

[0096] In addition, similar to Embodiment 2, for the silicon carbide semiconductor device 103 of Embodiment 3, an oxide film 25 may also be formed between the barrier metals 21 and 22. In this case, Step S105A described in Embodiment 2 is performed between Step S105B and Step S106.

[0097] In Figure 12 a structure is shown in which the lower barrier metal 21 is not formed over a part of the region of the interlayer insulating film 19, but instead of the lower barrier metal 21, the upper barrier metal 22 may not be formed over a part of the region of the interlayer insulating film 19. In this case, the above Step S105B is not performed, and after proceeding to form the upper barrier metal 22 in the same manner as in Embodiment 1, photolithography processing is performed on the barrier metal 22, and the barrier metal 22 is locally etched.

[0098] Above, the removal of a part of the barrier metal 21 by photolithography processing has been described. However, when foreign matter adheres to the underlying barrier metal 21 during the manufacturing process, a water washing process may also be performed after forming the barrier metal 21 and before forming the barrier metal 22. Since the foreign matter and the barrier metal 21 formed thereon are peeled off from the interlayer insulating film 19 by the water washing process, a part of the barrier metal 21 can be removed without using photolithography processing.

[0099] <C-3. Effect>

[0100] Regarding the silicon carbide semiconductor device 103 of Embodiment 3, there is a part where the barrier metal 21 is not formed between the interlayer insulating film 19 and the source electrode 23. At the part where the barrier metal 21 is not formed, the surface of the barrier metal 22 has a step. Thus, by having a step on the surface of the barrier metal 22, stress can be relaxed, and the generation of cracks after heat treatment of the barrier metal 22 can be suppressed.

[0101] <D. Embodiment 4>

[0102] <D-1. Structure>

[0103] The top view of the silicon carbide semiconductor device 104 of Embodiment 4 is as Figure 1 shown. Regarding the silicon carbide semiconductor device 104 of Embodiment 4, in the sense unit region, that is, the current sense pad 4a, two layers of barrier metals 21 and 22 similar to those in the unit region 1 are also provided.

[0104] <D-2. Manufacturing Process>

[0105] Figure 14 is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 104 of Embodiment 4. The manufacturing process of the silicon carbide semiconductor device 104 of Embodiment 4 will be described. [[ID=2,7]]

[0106] The processes from forming the upper barrier metal 22 of the unit region 1 to (steps S101 to step S106) are the same as those in Embodiment 1. After forming the upper barrier metal 22 of the unit region 1, in the sense unit region, a lower barrier metal 21 is also formed on and within the contact hole 19h above the interlayer insulating film 19 in the same manner as in the unit region 1 (step S106A). Next, an upper barrier metal 22 is formed on the barrier metal 21 in the sense unit region (step S106B). The subsequent step S107 is the same as that in Embodiment 1.

[0107] <D-3. Effect>

[0108] If the threshold voltage is different between the cell region 1 and the sense cell region, accurate current detection cannot be performed in the sense cell region, and thus appropriate overcurrent protection cannot be achieved. However, in the case of the silicon carbide semiconductor device 104 of Embodiment 4, the two-layer barrier metals 21 and 22 made of the same metal are also provided in the sense cell region. That is, in the case of the silicon carbide semiconductor device 104 of Embodiment 4, the barrier metals 21 and 22 are formed between the interlayer insulating film 19 and the source electrode 23 in the sense cell region. As a result, the threshold voltage can be made consistent between the sense cell region and the cell region 1, and accurate current detection can be performed.

[0109] The film thickness and material of the barrier metals 21 and 22 may also be different between the sense cell region and the cell region 1. However, if the film thickness and material of the barrier metals 21 and 22 are the same between the sense cell region and the cell region 1, the barrier metals of the sense cell region and the cell region 1 can be formed simultaneously, and thus the productivity is improved.

[0110] In addition, in the above embodiments, a MOSFET is described as an example of the semiconductor device. However, it is not limited to a MOSFET. Even for other semiconductor devices, as long as they have an element structure on the silicon carbide layer, the structure of the above embodiments can be applied, and the same effects can be obtained.

[0111] Several embodiments of the present invention have been described, but these embodiments are only presented as examples. Various omissions, substitutions, and changes can be made without departing from the gist thereof. In addition, the embodiments can be combined.

[0112] <E. Embodiment 5>

[0113] In this embodiment, the silicon carbide semiconductor devices 101-104 of the above embodiments are applied to a power conversion device. The application of the silicon carbide semiconductor devices 101-104 is not limited to a specific power conversion device. However, below, as Embodiment 5, the case where the silicon carbide semiconductor devices 101-104 are applied to a three-phase inverter will be described.

[0114] Figure 15 It is a block diagram showing the structure of a power conversion system in which the power conversion device according to this embodiment is applied.

[0115] Figure 15The illustrated power conversion system consists of a power supply 150, a power conversion device 200, and a load 300. Power supply 150 is a DC power supply that supplies DC power to power conversion device 200. Power supply 150 can be composed of various power sources, such as a DC system, a solar cell, a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, power supply 150 can be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0116] The power conversion device 200 is a three-phase inverter connected between the power source 150 and the load 300, which converts the DC power supplied from the power source 150 into AC power and supplies the AC power to the load 300. Figure 15 As shown, the power conversion device 200 has: a main conversion circuit 201, which converts DC power into AC power and outputs it; a drive circuit 202, which outputs a drive signal for driving each switching element of the main conversion circuit 201; and a control circuit 203, which outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0117] Load 300 is a three-phase motor driven by the AC power supplied from power conversion device 200. Load 300 is not limited to a specific application and may be a motor mounted on various electrical devices, for example, a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0118] The following describes the details of the power conversion device 200. The main conversion circuit 201 has a switching element and a freewheeling diode (not shown), and converts the DC power supplied from the power supply 150 into AC power by turning the switching element on and off, and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 is diverse, but the main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in reverse parallel to each switching element. Each switching element of the main conversion circuit 201 applies the silicon carbide semiconductor device 101-104 of any of the above-mentioned embodiments 1-4. The 6 switching elements are connected in series two by two to form an upper and lower bridge arm, and each upper and lower bridge arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the output terminal of each upper and lower bridge arm, that is, the three output terminals of the main conversion circuit 201, is connected to the load 300.

[0119] The drive circuit 202 generates a drive signal for driving the switching elements of the main conversion circuit 201 and supplies it to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, the drive signal for turning the switching element on and the drive signal for turning the switching element off are output to the control electrodes of each switching element. To maintain the switching element in the on state, the drive signal is a voltage signal greater than or equal to the threshold voltage of the switching element (an on signal); to maintain the switching element in the off state, the drive signal is a voltage signal less than or equal to the threshold voltage of the switching element (an off signal).

[0120] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on-time) at which each switching element of the main conversion circuit 201 should be turned on is calculated based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on-time of the switching elements according to the voltage to be output. Furthermore, a control instruction (control signal) is output to the drive circuit 202 in such a manner that an on signal is output to the switching element to be turned on, and an off signal is output to the switching element to be turned off, at each moment. In accordance with the control signal, the drive circuit 202 outputs the on signal or off signal as a drive signal to the control electrode of each switching element.

[0121] In the power conversion device according to this embodiment, since the silicon carbide semiconductor devices 101 to 104 according to any of Embodiments 1 to 4 are used as switching elements of the main conversion circuit 201 , reliability can be improved.

[0122] In this embodiment, the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 are described as being applied to a two-level, three-phase inverter. However, the applications of the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 are not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. When supplying power to a single-phase load, the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 can also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 can also be applied to a DC / DC converter or an AC / DC converter.

[0123] In addition, the power conversion device using the silicon carbide semiconductor devices 101-104 of embodiments 1-4 is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0124] Description of the label

[0125] 1 Unit region, 2 Terminal region, 3 Pad region, 4 Control pad, 4a Current sensing pad, 4b Gate pad, 11 Silicon carbide substrate, 12 Semiconductor layer, 14 Epitaxial layer, 15 Well region, 16 Source region, 17 Contact region, 18 Gate electrode, 19 Interlayer insulating film, 19h Contact hole, 20, 21, 22 Barrier metal, 23 Source electrode, 24 Drain electrode, 25 Oxide film, 26 Gate oxide film, 27 Field insulating film, 100, 101, 102, 103, 104 Semiconductor device, 150 Power supply, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load

Claims

1. A silicon carbide semiconductor device comprising: Silicon carbide substrate; a semiconductor layer formed on the silicon carbide substrate; a gate electrode facing the semiconductor layer via a gate insulating film; an interlayer insulating film covering the gate electrode; a contact hole formed in the interlayer insulating film to expose the semiconductor layer; a barrier metal formed in the contact hole and on the interlayer insulating film; as well as an upper surface electrode covering the barrier metal, The barrier metal has a two-layer structure consisting of a first barrier metal and a second barrier metal. The barrier metal on the interlayer insulating film side, that is, the first barrier metal, is made of the same metal as the second barrier metal and has a smaller thickness than the second barrier metal. There is a portion between the interlayer insulating film and the upper surface electrode where the second barrier metal is not formed but the first barrier metal is formed. A portion where the second barrier metal is not formed but the first barrier metal is formed exists between the semiconductor layer and the upper surface electrode at the contact hole.

2. The silicon carbide semiconductor device according to claim 1, wherein The total thickness of the first barrier metal and the thickness of the second barrier metal is greater than or equal to 100 nm and less than or equal to 200 nm.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein: An oxide film is further provided between the first barrier metal and the second barrier metal.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein The first barrier metal and the second barrier metal are made of Ti or TiN.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein The barrier metal is formed between the interlayer insulating film and the upper surface electrode in the sensing unit region.

6. A power conversion device comprising: A main conversion circuit comprising the silicon carbide semiconductor device according to any one of claims 1 to 5, the main conversion circuit converting input power and outputting the converted power; a driving circuit configured to output a driving signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; as well as A control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

7. A method for manufacturing a silicon carbide semiconductor device, wherein: Prepare silicon carbide substrate, forming a semiconductor layer on the silicon carbide substrate, forming a gate electrode facing the semiconductor layer via a gate insulating film, forming an interlayer insulating film covering the gate electrode, forming a contact hole in the interlayer insulating film to expose the semiconductor layer; forming a first barrier metal in the contact hole and on the interlayer insulating film, forming a second barrier metal on the first barrier metal, the second barrier metal being made of the same metal as the first barrier metal and being thicker than the first barrier metal; forming an upper surface electrode covering the second barrier metal, There is a portion between the interlayer insulating film and the upper surface electrode where the second barrier metal is not formed but the first barrier metal is formed. A portion where the second barrier metal is not formed but the first barrier metal is formed exists between the semiconductor layer and the upper surface electrode at the contact hole.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein: The total thickness of the first barrier metal and the second barrier metal is greater than or equal to 100 nm and less than or equal to 200 nm.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7 or 8, wherein: forming an oxide film on the first barrier metal; The second barrier metal is formed by forming the second barrier metal on the first barrier metal via the oxide film.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 7 or 8, wherein: The first barrier metal and the second barrier metal are made of Ti or TiN.

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