Failure-resistant electronic packages

Abstract

The present disclosure relates to fault-tolerant electronic packages. Specifically, a chip package includes a chip having a first temperature sensor. The first temperature sensor is configured to measure a first temperature of the chip in a local area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a local area around the second temperature sensor. The chip carrier further includes a local heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on a comparison of the first temperature and the second temperature, so that the detected difference is adjusted in the local area around the first temperature sensor.

Description

Technical Field

[0001] The present disclosure relates to failure-tolerant electronic packages. Background Art

[0002] Electronic packages (also referred to herein as chip packages) are typically made of subcomponents such as chips, stacks, interconnects, lids, etc. These subcomponents are often made of different materials with different coefficients of thermal expansion (CTE). During operation of the electronic package, the chip dissipates heat, causing different temperatures in the package subcomponents. The different temperatures and different CTEs of the materials can lead to differential expansion in the package components, resulting in warping and stresses. These stresses can be highest near the corners of the chip. Repeated cycling of temperatures can lead to component fatigue failure. The interconnects between the chip and the chip carrier are particularly susceptible to fatigue failure. Summary of the Invention

[0003] Aspects of the present disclosure may include a method for reducing temperature-induced stress in a chip package, an electronic device, and a chip package. An example of the chip package includes a chip having a first temperature sensor located in a back-end process level of the chip. The first temperature sensor is configured to measure a first temperature of the chip in a local area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor in the chip. The second temperature sensor is configured to measure a second temperature of the chip carrier in a local area around the second temperature sensor. The chip carrier further includes a local heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on a comparison of the first temperature and the second temperature, so that the detected difference is adjusted in the local area around the first temperature sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Understanding that the drawings depict only example embodiments and are therefore not to be considered limiting in scope, example embodiments will be described with additional specificity and detail through use of the accompanying drawings, in which:

[0005] Figure 1A is a high-level block diagram of a cross-sectional view of one example embodiment of an enhanced chip package.

[0006] Figure 1B yes Figure 1A A high-level block diagram of a top view of an example embodiment of an enhanced chip package in FIG.

[0007] Figure 2 is a high-level block diagram of a cross-sectional view of another example embodiment of an enhanced chip package.

[0008] Figure 3 is a high-level block diagram of an example electronic device.

[0009] Figure 4 is a circuit diagram of one embodiment of a temperature sensor.

[0010] Figure 5 is a flow chart depicting one embodiment of an example method for reducing temperature-induced stress in a chip package.

[0011] According to common practice, the various features described are not drawn to scale but are drawn to emphasize specific features relevant to the example embodiments. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific illustrative embodiments. However, it should be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the drawings and the specification should not be construed as limiting the order in which the various steps may be performed. Therefore, the following detailed description should not be considered limiting.

[0013] Figure 1A is a high-level block diagram of a cross-sectional view of one example embodiment of an enhanced chip package 100 . Figure 1B is a high-level block diagram of a top view of an example embodiment of an enhanced chip package 100. It should be understood that the enhanced chip package 100 is a simplified depiction and that enhanced chip packages according to embodiments described herein may include Figure 1A and Figure 1B Other components not shown in FIG. For example, Figure 2 A more detailed cross-sectional view of an enhanced chip package 200 is depicted.

[0014] The enhanced chip package 100 includes a chip 102 physically attached to a chip carrier 104 via an interconnect 106 (also referred to herein as an interconnect or interconnect). As known to those skilled in the art, the interconnect 106 is implemented as a controlled collapse chip connection (also referred to as a C4 connection) using a plurality of solder balls. Figure 1A or Figure 1B Although not shown, it should be understood that chip 102 includes a plurality of electronic circuits, such as resistors, transistors, capacitors, inductors, and / or diodes. As known to those skilled in the art, the electronic circuits may include analog and / or digital circuits. During operation, current flows through the plurality of electronic circuits, which may cause temperature changes in chip 102 at locations in chip 102 where the current flows.

[0015] In some embodiments, chip 102 is composed of a first material having a first coefficient of thermal expansion (CTE), and chip carrier 104 is composed of a second material having a second CTE different from the first CTE. For example, in some such embodiments, chip 102 is composed of a silicon material having a CTE of approximately 2.6 parts per million (ppm) per degree Celsius (C), and chip carrier 104 is composed of one or more organic laminate materials having a composite CTE of approximately 13-17 ppm / C. In other embodiments, chip carrier 104 may be composed of a material having a CTE closer to that of chip 102. For example, in some embodiments, chip carrier 104 may be composed of a ceramic material having a CTE of approximately 3 ppm / C.

[0016] As discussed above, temperature variations may occur in chip 102 and chip carrier 104 during assembly and / or operation of chip 102. The temperature variations may not be uniform throughout enhanced chip package 100. For example, the temperature in chip carrier 104 may be different from the temperature of chip 102. Additionally, different portions of chip 102 and / or chip carrier 104 may be at different temperatures than other portions of chip 102 and / or chip carrier 104, respectively. For example, as more current flows through certain portions of chip 102 than other portions, the temperature of chip 102 will vary based on the location of the current. Additionally, due to the current flowing through chip 102, the temperature of chip 102 may be different from the temperature of chip carrier 104.

[0017] In conventional chip packages, these temperature variations induce stresses on components of the conventional chip package, for example due to CTE mismatches between these components. As the temperature of the package components cyclically increases and decreases, the stresses generated in the package components may also cyclically increase or decrease, which may lead to fatigue failure of the package components. The interconnect 106 between the chip 102 and the chip carrier 104 (which may be made of solder material) is particularly susceptible to fatigue failure.

[0018] Conventional techniques for attempting to minimize package interconnect stress may include attempting to minimize component CTE mismatch through material selection, locally reinforcing the substrate or chip carrier, and / or using epoxy underfill materials around the interconnects to reduce shear stress at chip corners.

[0019] Unlike conventional techniques, embodiments of the enhanced chip package 100 reduce stress in the interconnect 106 by responding to and adjusting for temperature variations in components of the chip package 100. Specifically, one or more chip temperature sensors 108 and one or more chip heater elements 110 are included in the chip 102. Additionally, one or more carrier temperature sensors 112 and one or more carrier heater elements 114 are included in the chip carrier 104. The one or more carrier temperature sensors 112 are vertically aligned with the corresponding one or more chip temperature sensors 108. By vertically aligning the carrier temperature sensors 112 with the corresponding chip temperature sensors 108, localized temperature variations on the interconnect 106 can be measured at specific locations in the enhanced chip package 100.

[0020] For example, in Figure 1A and Figure 1B In the illustrated embodiment, chip temperature sensor 108 is located at a corner of chip 102. Thus, carrier temperature sensor 112 is located in chip carrier 104 at a location corresponding to the corner of chip 102, so that carrier temperature sensor 112 is vertically aligned with chip temperature sensor 108. In this way, these sensors can be located at interconnect locations that are expected to experience more stress. For example, the corners of chip 102 are often subject to more stress than the center of chip 102. However, it should be understood that the embodiments described herein are not limited to placing sensors 108 / 112 at the corners of chip 102. For example, in other embodiments, sensors 108 / 112 can be located at locations corresponding to the edges of chip 102.

[0021] In addition, Figure 1A and 1B In the embodiment of FIG. 1 , these chip heater elements 110 are also located in the corners of the chip 102. Similarly, in this embodiment, the carrier heater elements 114 are also vertically aligned with the chip heater elements 110 and located at positions corresponding to the corners of the chip 102. However, it should be understood that in some embodiments, the chip heater elements 110 are omitted and only the chip temperature sensors 108 are included in the chip 102. In some such embodiments, the carrier heater elements 114 are positioned adjacent to corresponding carrier temperature sensors 112 that are vertically aligned with the chip temperature sensors 108. Additionally, the carrier 104 in this example includes a central core 116, a front-side layer or top (also referred to as an FC layer) 118, and a bottom-side layer or bottom (also referred to as a BC layer) 120. In this example, the carrier temperature sensors 112 and the carrier heater elements 114 are located in the FC layer 118 closer to the chip 102, and the chip temperature sensors 108 are embedded in a layer in the back-end of the line (BEOL) of the chip.

[0022] The chip temperature sensors 108 are configured to measure the temperature of the chip 102 at corresponding locations of the chip temperature sensors 108, for example, during assembly and / or operation of the chip 102. Similarly, the carrier temperature sensors 112 are configured to measure the temperature of the chip carrier 104 at corresponding locations of the carrier temperature sensors 112, for example, during assembly and / or operation of the chip 102.

[0023] Thus, enhanced chip package 100 is configured to enable measurement of a local value of a temperature difference between chip 102 and chip carrier 104. As used herein, the terms local or local refer to a sub-portion of chip 102 and a corresponding area of ​​chip carrier 104 in an area around temperature sensors 108 / 112, wherein the sub-portion is smaller than the entire chip 102 or chip carrier 104.

[0024] Furthermore, the enhanced chip package 100 is configured to reduce stress on the interconnects 106 of the enhanced chip package 100 by selectively activating a plurality of localized heater elements 110 / 114 to adjust the local temperature of the chip 102 and / or chip carrier 104. For example, if a given pair of vertically aligned temperature sensors 108 / 112 identifies that the temperature difference between a subsection of the chip 102 in the localized region and the temperature of a corresponding section of the chip carrier 104 is outside a predetermined range, the heater elements 114 and / or heater elements 110 in the localized region can be activated to adjust the temperature of the chip carrier 104 and / or chip 102 until the measured temperature difference is brought within the predetermined range. Once the temperature difference is within the predetermined range, the heater elements 114 and / or heater elements 110 can be deactivated or turned off. In some embodiments, it is desirable to minimize the temperature difference. Thus, in such embodiments, the predetermined range can be approximately zero. In other embodiments, it may be necessary to increase the localized temperature difference in order to reduce stress on the interconnects. In some such embodiments, the predetermined range may be a range around a non-zero value or may be a range excluding values ​​around zero. The specific range used will vary based on the implementation details of the enhanced chip package.

[0025] In this way, a control loop is used to reduce the stress imposed on the interconnect 106. It should be understood that by using multiple localized and vertically aligned temperature sensors 108 / 112 and heater elements 110 / 114, the enhanced chip package can reduce both stress caused by vertical temperature variations and stress caused by horizontal temperature variations. In other words, the enhanced chip package 100 can identify both temperature variations that occur vertically (e.g., between the chip 102 and the chip carrier 104) and horizontal temperature variations (e.g., between different portions of the chip 102 and / or different portions of the chip carrier 104).

[0026] In some embodiments, for example, when the CTE of the chip 102 closely matches the CTE of the chip carrier 104, the enhanced chip package 100 is configured to adjust the measured temperature difference. In other embodiments, for example, when the CTE of the chip 102 does not closely match the CTE of the chip carrier 104, the enhanced chip package 100 is configured to modify the measured temperature to adjust for the difference between the measured temperature and the corresponding product of the corresponding CTE values.

[0027] Comparison of temperature values, modification of temperature values, and control of heater elements 110 / 114 can be accomplished using analog and / or digital electronic circuitry coupled to the temperature sensors 108 / 112 and the heater elements 110 / 114. For example, transistors can be interconnected to form logic gates, such as, but not limited to, AND gates, OR gates, XOR gates, and the like. The logic gates can perform the aforementioned functions, such as comparing the outputs of the temperature sensors 108 / 112 and activating / deactivating the heater elements 110 / 114 by controlling the current to the heater elements 110 / 114 based on the comparison of the outputs of the temperature sensors 108 / 112. Thus, as described above, the enhanced chip package 100 is configured to dynamically reduce temperature-induced stresses on components of the enhanced chip package 100 by using localized, vertically aligned temperature sensors 108 / 112 and corresponding heater elements 110 / 114.

[0028] In addition, it should be understood that Figure 1A and Figure 1B The embodiments are provided by way of example, and different embodiments may be implemented differently. For example, in some embodiments, heater element 110 in chip 102 is omitted because the current on chip 102 flows through the circuits on chip 102, as chip 102 typically has a higher temperature than chip carrier 104 during operation. Furthermore, it should be understood that Figure 1A and Figure 1B The relative sizes of the components of the enhanced chip package 100 depicted in FIG. 1 are provided for illustrative purposes only and should not be construed as limiting. In particular, it should be understood that components of various sizes may be used. For example, in some embodiments, the chip 102 is approximately 25 mm x 29 mm, and the chip carrier 104 is approximately 68.5 mm x 68.5 mm. However, it should be understood that in other embodiments, other sizes of the chip 102 and chip carrier 104 may be used.

[0029] Furthermore, in some embodiments, heater elements 110 / 114 are 0.5 mm x 0.5 mm. In other embodiments, larger or smaller sizes of heater elements 110 / 114 are used, such as, but not limited to, 1 mm x 1 mm or 20 μm x 20 μm. Heater elements 110 / 114 can be implemented as resistors that generate heat when current is applied to them. In such embodiments, the required resistance of heater elements 110 / 114 will vary based on various factors, such as the size of heater elements 110 / 114, the voltage level used, the amount of power to be dissipated, etc. For example, in one embodiment using a voltage of 1.2 V and a heater element of 0.5 mm x 0.5 mm, the heater element is selected to have a resistance of approximately 50-100 ohms. In another embodiment using a voltage of 1.2 V and a heater element of 1 mm x 1 mm, the heater element is selected to have a resistance of approximately 30-60 ohms. Thus, the size and resistivity of heater elements 110 / 114 will vary based on the specific implementation.

[0030] As discussed above, Figure 1A and 1B The enhanced chip package 100 is a high-level block diagram for explanation purposes and may include other components. Figure 2 An example enhanced chip package 200 depicting additional components is shown in . Although the enhanced chip package 200 includes more components than the enhanced chip package 100, it should be understood that the enhanced chip package 200 is also simplified for purposes of illustration and explanation, and additional elements may be included and / or omitted in implementations of the embodiments described herein.

[0031] Enhanced chip package 200 includes a chip 202, a chip carrier 204, and interconnects 206, which are similar to the chip 102, chip carrier 104, and interconnects 106 discussed above. Additionally, enhanced chip package 200 includes one or more chip temperature sensors 208, one or more chip heater elements 210, one or more carrier temperature sensors 212 vertically aligned with the one or more chip temperature sensors 208, and one or more carrier heater elements 214, which are similar to the chip temperature sensors 108, chip heater elements 110, carrier temperature sensors 112, and carrier heater elements 114 described above.

[0032] also, Figure 2The enhanced chip package 200 shown in FIG includes a lid 216 that covers the chip 202 and is connected to the chip carrier 204. Specifically, the lid 216 is separated from the chip 202 via a thermal interface material (TIM) 218 ​​and is connected to the chip carrier 204 via a sealant 220, as known to those skilled in the art. The specific materials used for the TIM 218 and the sealant 220 will vary based on the implementation of the chip package 200, as known to those skilled in the art. In addition, Figure 2 An underfill material 222 is depicted around the interconnect 206. Suitable materials for the underfill material 222 and uses of the underfill material 222 are known to those skilled in the art.

[0033] in addition, Figure 2 The example shown in FIG2 depicts an enhanced chip package 200 coupled to a printed circuit board (PCB) 224 via a solder ball grid array (BGA) 226. Coupling a chip package to a PCB via a solder BGA is known to those skilled in the art and will not be described in detail herein. Figure 2 The example of the chip package 200 also includes a PCB cutout 228 that provides space for additional backside components (such as capacitor 230) coupled to the bottom side level of the chip carrier 204. Thus, the enhanced chip package 200 can be integrated into one or more components of an electronic device. Other examples of chip package to PCB interconnects are land grid arrays (LGAs) or pin grid arrays (PGAs).

[0034] Such components may include, but are not limited to, multi-core processors, application-specific integrated circuits (ASICs), and memory modules, such as dynamic random access memory (DRAM) chips. For example, Figure 3 is a high-level block diagram illustrating one embodiment of an electronic device 301 utilizing an enhanced chip package. The electronic device 301 may be implemented as any suitable electronic device, such as, but not limited to, a personal computer, a server, a mobile device, a tablet computer, etc. By utilizing one or more enhanced chip packages, the operating life of the components of the electronic device may be increased due to the ability of these enhanced chip packages to reduce temperature-induced stresses (such as corner stress), which in turn reduces cyclic fatigue failures of interconnects, as discussed above.

[0035] like Figure 3As depicted in the example of FIG3 , the electronic device 301 includes a PCB 324 to which a processor package 331 and a memory module 332 are coupled. The processor package 331 is implemented using an enhanced chip package (such as the enhanced chip package 100 discussed above). Similarly, the memory module 332 is implemented using an enhanced chip package (such as the enhanced chip package 100). The PCB 324 also includes a plurality of connectors 334 that are configured to connect to one or more additional components, such as a power supply 336 and one or more input / output devices 338. In some embodiments, the power supply 336 is configured to provide the power required to supply current to heater elements and temperature sensors (such as heater elements 110 / 114 and temperature sensors 108 / 112) to reduce temperature-induced stress.

[0036] Figure 4 is a circuit diagram depicting one embodiment of a temperature sensor 405 that can be used to implement the temperature sensors 108 / 112 discussed above. The temperature sensor 405 is an on-chip temperature sensor diode (OCTS) based on a pn junction. As described above, in some embodiments, the power supply 336 can provide the supply voltage VDD. As known to those skilled in the art, if the ratio of the currents I1 and I2 in the diode is constant, the differential output voltage VEE is proportional to the temperature. Those skilled in the art are familiar with OCTS, and further details of the operation of OCTS 405 are not described herein. It should be understood that Figure 4 The OCTS 405 depicted in FIG. 4 is provided by way of example only, and other temperature sensors may be used in other embodiments, such as, but not limited to, metal wire resistive temperature devices (RTDs) and / or thermistors.

[0037] Figure 5 1 is a flow chart depicting one embodiment of a method 500 for reducing temperature-induced stress in an interconnect of a chip package, such as the enhanced chip package 100. At 502, a local temperature sensor is used to measure the local temperature of a portion of a chip. In some embodiments, the temperature sensor may be located at a corner of the chip. In other embodiments, the temperature sensor may be located along the edge of the chip. Furthermore, in some embodiments, multiple temperature sensors are included, such as at each corner of the chip, as discussed above. Furthermore, in some embodiments, one or more temperature sensors are embedded in a layer in the back end of the line (BEOL) of the chip.

[0038] At 504, a local temperature of a portion of the chip carrier is measured using a local temperature sensor located in the chip carrier. The temperature sensor in the chip carrier is vertically aligned with the temperature sensor in the chip, as described above. Thus, for example, the temperature sensor in the chip carrier can be located at a position corresponding to a corner of the chip or along an edge of the chip. Furthermore, in some embodiments, as discussed above, the temperature sensor in the chip carrier is embedded in a front-side layer of the chip carrier. The measured temperature values ​​from the multiple temperature sensors can be combined in a suitable mathematical algorithm, for example, all the measured values ​​can be averaged.

[0039] At 506, the measured local temperature of the chip is compared to the measured local temperature of the chip carrier. For example, in some embodiments, a difference in the measured temperatures can be calculated. At 508, a determination is made as to whether the difference based on the comparison of the measured local temperature of the chip and the measured local temperature of the chip carrier is within a predetermined range, as described above. In some embodiments, the difference can be a difference in the measured temperatures. In other embodiments, the difference can be a difference in the product of the respective CTEs and the measured temperatures. Furthermore, in some embodiments, the range can be set to zero so that any detected difference will be outside of the range.

[0040] If the difference at 508 is within the range, then at 510, if the local heater element was previously activated, the local heater element is deactivated. Method 500 then returns to 502 to continue measuring the local temperature of the chip and chip carrier. If the difference at 508 is not within the predetermined range, then at 512, the local heater element is activated based on the comparison, as described above. For example, if the comparison determines that the chip carrier is cooler than the chip, the local heater element in the chip carrier may be activated to bring the measured difference within the predetermined range. As described above, the heater element can be activated by providing current to the heater element. Similarly, the heater element can be deactivated by removing current from the heater element. Method 500 then returns to 502 to continue measuring the local temperature of the chip and chip carrier.

[0041] It should be understood that Figure 5 The order of the actions described in 500 may be implemented differently. For example, the measurement of the local temperature at 502 may occur simultaneously with the measurement of the local temperature at 504. Furthermore, it should be understood that in some embodiments, method 500 may be implemented using analog and / or digital circuitry implemented in a chip. Additionally, in other embodiments, method 500 may be implemented in firmware embedded in the chip, where the measured values ​​are provided to circuitry configured to process instructions for operating on the measured temperature values.

[0042] Furthermore, it should be understood that method 500 can be performed independently for each of multiple pairs of vertically aligned temperature sensors. For example, an enhanced chip package can include multiple temperature sensors in the chip and multiple corresponding temperature sensors in the chip carrier. Thus, method 500 can be performed for each pair of vertically aligned temperature sensors to provide local temperature adjustment to reduce local temperature-induced stress. Thus, the embodiments described herein can reduce temperature-induced stress through the novel use of vertically aligned local temperature sensors and heater elements, which can improve the operating life of electronic components by reducing the failure of interconnects in the electronic components due to temperature-induced stress.

[0043] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown.It is manifestly intended that the present invention be limited only by the claims and the equivalents thereof.

Claims

1. A chip package, comprising: a chip having a plurality of first temperature sensors located at a back-end-of-the-line (BOL) level of the chip, each of the plurality of first temperature sensors being configured to measure a first temperature of the chip in a local area around the first temperature sensor, wherein the local area corresponds to a sub-portion of the chip, the sub-portion being smaller than the entire chip; and a chip carrier coupled to the chip via a plurality of solder connections, wherein the chip carrier includes a plurality of second temperature sensors, wherein each of the plurality of second temperature sensors is vertically aligned with a corresponding first temperature sensor of the plurality of first temperature sensors in the chip, each of the plurality of second temperature sensors being configured to measure a second temperature of the chip carrier in a second localized area around the second temperature sensor, wherein the second localized area corresponds to a subportion of the chip carrier, the subportion being smaller than the entire chip carrier; wherein the chip carrier further includes a plurality of localized heater elements, wherein each of the plurality of localized heater elements is located proximate a corresponding one of the plurality of second temperature sensors and is configured to generate heat in response to a detected difference based on a comparison of the first temperature measured by the corresponding first temperature sensor with the second temperature measured by the corresponding second temperature sensor, such that the detected difference is adjusted in the second localized area around the corresponding second temperature sensor, wherein each of the plurality of localized heater elements is independently controlled to reduce stress caused by vertical temperature variation and stress caused by horizontal temperature variation. 2 . The chip package according to claim 1 , wherein the detected difference is a temperature difference between the first temperature and the second temperature. 3 . The chip package according to claim 1 , wherein the detected difference is a difference between a first product of a first coefficient of thermal expansion (CTE) of the chip and the first temperature and a second product of a second CTE of the chip carrier and the second temperature. 4 . The chip package of claim 3 , wherein the chip comprises a silicon material having a CTE of 2.6 parts per million per degree Celsius (° C.), and the chip carrier comprises one or more organic laminate materials having a composite CTE of 15 ppm / ° C.

5. The chip package of claim 1 , wherein the chip further comprises a plurality of second localized heater elements, each of the plurality of second localized heater elements being located adjacent to a corresponding first temperature sensor among the plurality of first temperature sensors and configured to generate heat in response to the detected difference based on a comparison of the first temperature measured by the corresponding first temperature sensor with the second temperature measured by the corresponding second temperature sensor, such that the detected difference is adjusted in the local area around the corresponding first temperature sensor. 6 . The chip package according to claim 1 , wherein each of the plurality of first temperature sensors is an on-chip temperature sensor diode (OCTS) and each of the plurality of second temperature sensors is an OCTS. 7 . The chip package of claim 1 , wherein each of the plurality of local heater elements is a resistor configured to generate heat in response to a current applied thereto.

8. An electronic device comprising: printed circuit boards; as well as An enhanced chip package is coupled to the printed circuit board via a ball grid array, wherein the enhanced chip package comprises: a chip having a plurality of first temperature sensors located at a back-end-of-the-line (BOL) level of the chip, each of the plurality of first temperature sensors being configured to measure a first temperature of the chip in a local area around the first temperature sensor, wherein the local area corresponds to a sub-portion of the chip, the sub-portion being smaller than the entire chip; and a chip carrier coupled to the chip via a plurality of solder connections, wherein the chip carrier includes a plurality of second temperature sensors, wherein each of the plurality of second temperature sensors is vertically aligned with a corresponding first temperature sensor of the plurality of first temperature sensors in the chip, each of the plurality of second temperature sensors being configured to measure a second temperature of the chip carrier in a second localized area around the second temperature sensor, wherein the second localized area corresponds to a subportion of the chip carrier, the subportion being smaller than the entire chip carrier; wherein the chip carrier further includes a plurality of localized heater elements, wherein each of the plurality of localized heater elements is located proximate a corresponding one of the plurality of second temperature sensors and is configured to generate heat in response to a detected difference based on a comparison of the first temperature measured by the corresponding first temperature sensor with the second temperature measured by the corresponding second temperature sensor, such that the detected difference is adjusted in the second localized area around the corresponding second temperature sensor, wherein each of the plurality of localized heater elements is independently controlled to reduce stress caused by vertical temperature variation and stress caused by horizontal temperature variation. 9 . The electronic device of claim 8 , wherein the detected difference is a temperature difference between the first temperature and the second temperature. 10 . The electronic device of claim 8 , wherein the detected difference is a difference between a first product of a first coefficient of thermal expansion (CTE) of the chip and the first temperature and a second product of a second CTE of the chip carrier and the second temperature.

11. The electronic device of claim 10, wherein the chip comprises a silicon material having a CTE of 2.6 parts per million per degree Celsius (ppm), and the chip carrier comprises one or more organic laminate materials having a composite CTE of 15 ppm / °C.

12. The electronic device of claim 8 , wherein the chip further comprises a plurality of second localized heater elements, each of the plurality of second localized heater elements being located adjacent to a corresponding first temperature sensor among the plurality of first temperature sensors and configured to generate heat in response to the detected difference based on a comparison of the first temperature measured by the corresponding first temperature sensor with the second temperature measured by the corresponding second temperature sensor, thereby adjusting the detected difference in the localized area around the corresponding first temperature sensor. 13 . The electronic device of claim 8 , wherein each of the plurality of first temperature sensors is an on-chip temperature sensor diode (OCTS), and each of the plurality of second temperature sensors is an OCTS. 14 . The electronic device of claim 8 , wherein each of the plurality of local heater elements is a resistor configured to generate heat in response to an electric current applied thereto.

15. A method for reducing temperature-induced stress in a chip package, the method comprising: measuring a first local temperature of a sub-portion of a chip in the chip package using a plurality of first local temperature sensors embedded in a back-end-of-line process level of the chip, the sub-portion being smaller than the entire chip; measuring a second local temperature of a subsection of the chip carrier coupled to the chip using a plurality of second local temperature sensors embedded in a front-side level of the chip carrier, the subsection being smaller than the entire chip carrier, wherein each of the plurality of second local temperature sensors is vertically aligned with a corresponding one of the plurality of first local temperature sensors; comparing the first local temperature of the chip measured by a first local temperature sensor of the plurality of first local temperature sensors with the second local temperature of the chip carrier measured by a corresponding second local temperature sensor of the plurality of second local temperature sensors; determining that a difference based on the comparison is not within a predetermined range; as well as In response to determining that the difference is not within the predetermined range, independently activating one of a plurality of heater elements in one of the chip or the chip carrier to generate heat so that the difference is adjusted to be within the predetermined range to reduce stress caused by vertical temperature variation and stress caused by horizontal temperature variation, wherein the heater element is located near the corresponding first local temperature sensor or the second local temperature sensor. 16 . The method of claim 15 , wherein determining that the difference based on the comparison is not within the predetermined range comprises determining that a temperature difference between the first local temperature and the second local temperature is not within the predetermined range.

17. The method of claim 15 , wherein determining that the difference based on the comparing is not within the predetermined range comprises determining that a difference between a first product of a first coefficient of thermal expansion (CTE) of the chip and the first local temperature and a second product of a second CTE of the chip carrier and the second local temperature is not within the predetermined range.

18. The method of claim 17, wherein the chip comprises a silicon material having a CTE of 2.6 parts per million per degree Celsius (°C), and the chip carrier comprises one or more organic laminate materials having a composite CTE of 15 ppm / °C. 19 . The method of claim 15 , wherein each of the plurality of first local temperature sensors is an on-chip temperature sensor diode (OCTS), and each of the plurality of second local temperature sensors is an OCTS.

20. The method of claim 15, wherein independently activating one of the plurality of heater elements in one of the chip or the chip carrier comprises applying a current to a resistor configured to generate heat in response to the applied current.

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