Electrostatic protection GGNMOS structure

Abstract

The application discloses a static protection GGNMOS structure and belongs to the field of semiconductor devices and manufacturing. Based on an SOI process, the structure introduces an N-type well, forms P-type heavily doped regions and N-type heavily doped regions alternately in the N-type well, and forms an SCR structure by the P-type heavily doped regions at the N-type well, the N-type well, the P-type well and the N-type heavily doped regions at the source end to open a discharge current; the P-type heavily doped regions at the N-type well, the N-type heavily doped regions and the N-type heavily doped regions at the drain end are short-circuited to form an anode, the N-type heavily doped regions at the source end are short-circuited to the gate end to form a cathode, the SCR structure is used to open the discharge current when an ESD voltage is added to the anode, additional ESD current discharge channels are increased, and the ESD protection capability of the SOI GGNMOS is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and manufacturing, specifically to an electrostatic protection GGNMOS structure. Background Technology

[0002] As the feature size of semiconductor integrated circuit manufacturing processes shrinks, the size of chip cells also decreases, making the chip's anti-electrostatic discharge (ESD) capability increasingly important. ESD can cause permanent damage to semiconductor components and computer systems, thus affecting the circuit function of integrated circuits and causing electronic products to malfunction. Therefore, it is necessary to design protective measures or functions to protect chips from ESD damage.

[0003] Common ESD protection devices include diodes, GGNMOS (Gate Ground NMOS), and silicon controlled rectifiers (SCRs). SCRs are commonly used as ESD protection devices.

[0004] In SOI-based GGNMOS ESD devices, the N+ (heavily doped N-type region) is typically in direct contact with the Oxide Layer, lacking the PN junction formed by the N+ bottom and the PW (P-type well) compared to bulk silicon GGNMOS. When an ESD voltage is applied to the anode, the junction area for discharge current is reduced, resulting in very weak ESD protection for GGNMOS in related technologies. Summary of the Invention

[0005] This application provides an electrostatic protection GGNMOS structure that can solve the problem of weak ESD protection capability of GGNMOS in related technologies.

[0006] This application provides an electrostatic protection GGNMOS structure, which includes at least:

[0007] A silicon substrate having a buried oxide layer formed by SOI process; a source terminal defined by STI process, with a P-type well formed at the buried oxide layer; a ring of N-type wells formed around the P-type wells, with alternating blocky heavily doped regions of heavily doped P-type and heavily doped N-type regions formed at the N-type wells; and heavily doped N-type regions formed between the P-type wells, with spaced gate and drain terminals formed between the P-type wells.

[0008] The P-type heavily doped region at the N-type well, the N-type heavily doped region and the N-type heavily doped region at the drain are shorted to form an anode, and the N-type heavily doped region at the source is shorted to form a cathode; the P-type heavily doped region at the N-type well, the N-type well, the P-type well and the N-type heavily doped region at the source form an SCR structure, and the SCR structure is used to open the discharge current when the ESD voltage is applied to the anode.

[0009] Optionally, an isolation layer is provided between the P-type heavily doped region and the N-type heavily doped region at the N-type well and the source end, the isolation layer being used to prevent the P-type heavily doped region and the N-type heavily doped region at the N-type well from being short-circuited with the N-type heavily doped region at the source end.

[0010] Optionally, the isolation layer is a gate polysilicon (Poly) or a metal silicide barrier layer.

[0011] Optionally, the heavily doped P-type region in the N-type well, together with the N-type well, the P-type well, and the heavily doped N-type region at the source end, forms an NPN structure, which is turned on when an ESD voltage is applied to the anode.

[0012] Optionally, the N-type heavily doped region and the P-type heavily doped region at the N-type well form a polysilicon isolation with the N-type heavily doped region at the P-type well.

[0013] Optionally, the source, gate, and drain terminals are alternately formed in the heavily doped N-type region located between the P-type wells.

[0014] Optionally, the alternating formation order is the source end, the gate end, the drain end, and the gate end in sequence.

[0015] Optionally, the buried oxide layer is located around the P-type well, the N-type well, and the alternating blocky heavily doped region.

[0016] In summary, this invention provides an electrostatic discharge (ESD) protection GGNMOS structure based on SOI technology. This structure introduces an N-type well, and forms a blocky doped region with alternating P-type and N-type heavily doped regions within the N-type well. The P-type heavily doped region, N-type well, and P-type well at the N-type well, together with the N-type heavily doped region at the source, form an SCR structure to open the discharge current. The P-type heavily doped region and N-type heavily doped region at the N-type well are shorted to the N-type heavily doped region at the drain to form an anode, and the N-type heavily doped region at the source is shorted to the gate to form a cathode. The SCR structure is used to open the discharge current when an ESD voltage is applied to the anode, increasing the additional ESD current discharge channel and improving the ESD protection capability of the SOI GGNMOS. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A top view of an electrostatic protection GGNMOS structure provided in an embodiment of this application is shown;

[0019] Figure 2 It shows Figure 1 Cross-sectional view of the corresponding structure;

[0020] Figure 3 A top view of another electrostatic protection GGNMOS structure provided in an embodiment of this application is shown;

[0021] Figure 4 It shows Figure 3 Cross-sectional view of the corresponding structure;

[0022] Figure 5 A schematic diagram of the structure of a GGNMOS ESD based on SOI technology is shown. Detailed Implementation

[0023] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0027] Please refer to Figure 1 and Figure 2 , Figure 1 This paper shows a top view of an electrostatic protection GGNMOS structure provided in an embodiment of this application. Figure 2 It shows Figure 1 Cross-sectional view of the corresponding structure.

[0028] like Figure 1 and Figure 2 As shown, the structure includes at least a silicon substrate (Sub), on which a buried oxide layer is formed by SOI process; a source terminal S defined by STI process, with a P-type well PW formed at the buried oxide layer; a ring of N-type wells NW formed around the P-type wells, with alternating blocky heavily doped regions of P-type heavily doped regions P+ and N-type heavily doped regions N+ formed at the N-type wells; and N-type heavily doped regions formed between the P-type wells, with spaced gate terminals G and drain terminals D between the P-type wells.

[0029] In this structure, the P-type heavily doped region at the N-type well, the N-type heavily doped region at the drain are shorted to form the anode, and the N-type heavily doped region at the source is shorted to form the cathode. The P-type heavily doped region at the N-type well, the N-type well, the P-type well at the source, and the N-type heavily doped region at the source form the SCR structure. The SCR structure is used to open the discharge current when the ESD (ESD discharge channel structure: Drain / PW / Source) voltage is applied to the anode.

[0030] In summary, this invention provides an electrostatic discharge (ESD) protection GGNMOS structure based on SOI technology. This structure introduces an N-type well, within which alternating blocky doped regions of heavily P-type and heavily N-type doped regions are formed. The heavily P-type doped region at the N-type well, the N-type well, the P-type well, and the heavily N-type doped region at the source end form an SCR structure, opening the discharge current. The heavily P-type and heavily N-type doped regions at the N-type well are shorted to the heavily N-type doped region at the drain end to form the anode, and the heavily N-type doped region at the source end is shorted to the gate end to form the cathode. The SCR structure is used to open the discharge current when an ESD voltage is applied to the anode, increasing the additional ESD current discharge channel and improving the ESD protection capability of the SOI GGNMOS.

[0031] Further reference Figure 1 and Figure 2 .

[0032] Based on the above embodiments, an isolation layer is provided between the P-type heavily doped region and the N-type heavily doped region at the N-type well and the source end. The isolation layer is used to prevent the P-type heavily doped region and the N-type heavily doped region at the N-type well from being short-circuited with the N-type heavily doped region at the source end.

[0033] Optional, such as Figure 1 and 2 As shown, the isolation layer can be gate polysilicon (Poly); as Figure 3 and 4 As shown, the isolation layer can be a metal silicide barrier layer (Salicide block).

[0034] In the embodiments of this application, the buried oxide layer is located around the P-type well, N-type well, and alternating blocky heavily doped regions.

[0035] The heavily doped N-type regions between the P-type wells form an NPN structure with the P-type wells. The NPN structure is activated when an ESD voltage is applied to the anode. In addition, the heavily doped N-type regions in the N-type wells and the heavily doped P-type regions form polysilicon isolation with the heavily doped N-type regions in the P-type wells.

[0036] like Figure 1-4 As shown, in the heavily doped N-type region between P-type wells, the source, gate, and drain terminals are formed alternately, in the order of source, gate, drain, and gate, and are centrally symmetrical according to this alternation order.

[0037] In addition, an isolation layer is provided between the heavily doped P-type region and the heavily doped N-type region at the N-type well and the source end to prevent the heavily doped N-type region and the heavily doped P-type region in the N-type well from short-circuiting with the heavily doped N-type region at the source end, thereby further improving the ESD protection capability of SOI GGNMOS.

[0038] Furthermore, based on the above embodiments, combined with, as follows Figure 5The electrostatic protection GGNMOS structure shown in the related technology is used to further illustrate the improvement of the present invention.

[0039] like Figure 5 As shown in the figure, the GGNMOS ESD device based on SOI technology can be seen that the N-type heavily doped region (N+) is in direct contact with the buried oxide layer. Compared with bulk silicon GGNMOS, this results in the lack of a PN junction formed between the N+ bottom and the PW.

[0040] When an ESD voltage is applied to the Anode, the NPN junction formed by the N+ side of the Drain terminal, the PW junction, and the N+ side of the Source terminal opens to discharge current. However, due to the lack of a PN junction at the bottom of the N+ junction, the junction area for discharging current is reduced, thus... Figure 5 Among the related technologies shown, GGNMOS based on SOI technology has very weak ESD protection capabilities.

[0041] The electrostatic discharge (ESD) protection GGNMOS structure provided in the above embodiments introduces an N-type well on the basis of conventional GGNMOS, and forms alternating blocky heavily doped regions of P+ / N+ / P+ / N+ in the N-type well. The heavily doped regions of P-type, N-type, and P-type wells at the N-type wells and the heavily doped regions of N-type at the source end form an SCR structure to open the discharge current. The heavily doped regions of P-type and N-type at the N-type wells and the heavily doped regions of N-type at the drain end are shorted to form an anode, and the heavily doped regions of N-type at the source end are shorted to form a cathode. The SCR structure is used to open the discharge current when ESD voltage is applied to the anode, which increases the additional ESD current discharge channel and improves the ESD protection capability of SOI GGNMOS.

[0042] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. An electrostatic protected GGNMOS structure, characterized in that, The structure includes at least: A silicon substrate having a buried oxide layer formed by SOI process; a source terminal defined by STI process, with a P-type well formed at the buried oxide layer; a ring of N-type wells formed around the P-type wells, with alternating blocky heavily doped regions of heavily doped P-type and heavily doped N-type regions formed at the N-type wells; and heavily doped N-type regions formed between the P-type wells, with spaced gate and drain terminals formed between the P-type wells. The P-type heavily doped region at the N-type well, the N-type heavily doped region and the N-type heavily doped region at the drain are shorted to form an anode, and the N-type heavily doped region at the source is shorted to form a cathode; the P-type heavily doped region at the N-type well, the N-type well, the P-type well and the N-type heavily doped region at the source form an SCR structure, and the SCR structure is used to open the discharge current when the ESD voltage is applied to the anode.

2. The electrostatic protection GGNMOS structure according to claim 1, characterized in that, An isolation layer is provided between the P-type heavily doped region and the N-type heavily doped region at the N-type well and the source end. The isolation layer is used to prevent the P-type heavily doped region and the N-type heavily doped region at the N-type well from being short-circuited with the N-type heavily doped region at the source end.

3. The electrostatic protection GGNMOS structure according to claim 2, characterized in that, The isolation layer is a gate polysilicon or a metal silicide barrier layer.

4. The electrostatic protection GGNMOS structure according to claim 1, characterized in that, The heavily doped P-type region in the N-type well, together with the N-type well, the P-type well, and the heavily doped N-type region at the source end, forms an NPN structure. The NPN structure is activated when an ESD voltage is applied to the anode.

5. The electrostatic protection GGNMOS structure according to claim 1, characterized in that, The N-type heavily doped region and the P-type heavily doped region at the N-type well form a polysilicon isolation with the N-type heavily doped region at the P-type well.

6. The electrostatic protection GGNMOS structure according to claim 1, characterized in that, The source, gate, and drain terminals are alternately formed in the N-type heavily doped region located between the P-type wells.

7. The electrostatic protection GGNMOS structure according to claim 6, characterized in that, The alternating formation sequence is, in order, the source end, the gate end, the drain end, and the gate end.

8. The electrostatic protection GGNMOS structure according to claim 1, characterized in that, The buried oxide layer is located around the P-type well, the N-type well, and the alternating blocky heavily doped region.

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