Semiconductor element and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a storage capacitor, an access transistor, and at least one conductive feature, wherein the at least one conductive feature electrically couples the storage capacitor to the access transistor. The substrate comprises at least one insulating feature, wherein the at least one insulating feature defines a plurality of active regions, wherein a plurality of doped regions of the access transistor are located in the active regions. The storage capacitor is disposed on the substrate, and the conductive feature extends from the storage capacitor into a portion of the substrate where one of the doped regions is disposed. This increases the contact area between the access transistor and the conductive feature, and improves the operating speed of the compact semiconductor device.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 17 / 098,033, filed on November 13, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, the disclosure relates to a semiconductor device and a method for fabricating the same, wherein the semiconductor device has a plurality of conductive features connecting a plurality of capacitors to a plurality of access transistors, wherein the conductive features extend into a plurality of doped regions of the access transistors. Background Art

[0003] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this continuous improvement in integration density comes from repeated reductions in minimum feature size (e.g., shrinking semiconductor process nodes toward sub-20nm nodes), which allows more components to be integrated into a given area.

[0004] As semiconductor devices become highly integrated, the footprint of the conductive contacts used to electrically couple multiple storage capacitors and multiple access transistors decreases. Consequently, the contact resistance between each conductive contact and the access transistor increases. This contact resistance can deteriorate the performance of the semiconductor device (e.g., reduce operating speed).

[0005] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0006] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature. The substrate includes at least one insulating feature that defines a plurality of active regions. The storage capacitor is located on the substrate. The access transistor includes a plurality of doped regions located in the active regions. The conductive feature extends from the storage capacitor into the substrate, electrically coupling the storage capacitor to the access transistor.

[0007] In some embodiments, the conductive feature is inserted into the associated doped region.

[0008] In some embodiments, a portion of the conductive feature in the substrate has a funnel shape.

[0009] In some embodiments, the conductive feature includes a lower portion and an upper portion, the lower portion is located in the substrate, the upper portion is interposed between the substrate and the storage capacitor, the lower portion has a first critical dimension, and the upper portion has a second critical dimension that is greater than the first critical dimension.

[0010] In some embodiments, the first critical dimension of the lower portion of the conductive feature tapers at increasing distances from the upper portion.

[0011] In some embodiments, the lower portion of the conductive feature has a peripheral surface that is discontinuous with a peripheral surface of the upper portion of the conductive feature.

[0012] In some embodiments, the lower portion and the upper portion of the conductive feature are integrally formed.

[0013] In some embodiments, the access transistor further includes a word line and an isolation pad, wherein the word line is disposed in the substrate and crosses the active region, and the doped region is disposed on either side of the word line; the isolation pad is sandwiched between the substrate and the word line.

[0014] In some embodiments, the semiconductor device further includes a dielectric layer, a bit line, and a conductive plug. The dielectric layer is located between the storage capacitor and the substrate to encapsulate the access transistor and surround the conductive feature. The bit line is buried in the dielectric layer. The conductive plug extends from the bit line and into the substrate to electrically couple the bit line to the access transistor.

[0015] In some embodiments, a portion of the conductive plug inserted into the doped region has a third critical dimension, and another portion of the conductive plug inserted between the bit line and the substrate has a fourth critical dimension, and the fourth critical dimension is larger than the third critical dimension.

[0016] In some embodiments, the storage capacitor includes at least a storage node, a capacitor insulator, and a top electrode, wherein the storage node contacts the conductive feature, the capacitor insulator encapsulates the storage node, and the top electrode is located on the capacitor insulator.

[0017] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate including one or more insulating features, the one or more insulating features defining a plurality of active regions; forming at least one access transistor, the at least one access transistor including a plurality of doped regions, wherein the doped regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated doped regions; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first contact hole and the second contact hole.

[0018] In some embodiments, the fabrication method further comprises removing the sacrificial liner before forming the conductive feature.

[0019] In some embodiments, the first contact hole has a first width, and the second contact hole has a second width, the second width being smaller than the first width.

[0020] In some embodiments, the second width of the second contact hole gradually decreases at positions increasing in distance from the first contact hole.

[0021] In some embodiments, the formation of the sacrificial liner includes the following steps: depositing a sacrificial film on the dielectric layer and on a portion of the substrate exposed to the first contact hole, wherein the sacrificial film does not fill the first contact hole; and removing some portions of the sacrificial film to expose the substrate.

[0022] In some embodiments, forming the access transistor includes the following steps: creating at least one trench in the substrate and crossing the active region; depositing a gate insulator in the trench, wherein a portion of the trench remains unfilled; forming a word line to occupy a bottom of the trench; depositing a capping layer in the trench to cover the word line; and introducing a plurality of dopants into the substrate to form the doped region.

[0023] Due to the aforementioned structure of a semiconductor device having the conductive feature partially extending into the substrate, the contact area between the conductive feature and the access transistor is increased, thereby reducing the contact resistance between the conductive feature and the access transistor and improving the operating speed of the compact semiconductor device.

[0024] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0026] Figure 1 A schematic cross-sectional view of a semiconductor device illustrating some embodiments of the present disclosure is shown.

[0027] Figure 2 A schematic plan view of a substrate illustrating some embodiments of the present disclosure.

[0028] Figure 3 A schematic cross-sectional view of a semiconductor device illustrating some embodiments of the present disclosure is shown.

[0029] Figure 4 A schematic flow chart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure is provided.

[0030] Figure 5 and Figure 6 Schematic cross-sectional views illustrating various intermediate stages of fabricating the semiconductor device according to some embodiments of the present disclosure.

[0031] Figure 7 A schematic plan view of a substrate having a plurality of grooves formed thereon is shown, illustrating some embodiments of the present disclosure.

[0032] Figure 8 Example edge Figure 7 Schematic cross-sectional view of section line AA.

[0033] Figures 9 to 24 Schematic cross-sectional views illustrating various intermediate stages of fabricating the semiconductor device according to some embodiments of the present disclosure.

[0034] The description of the accompanying drawings is as follows:

[0035] 10: Semiconductor components

[0036] 10A: semiconductor components

[0037] 100: Semiconductor wafers

[0038] 1002: Upper surface

[0039] 102: Depression

[0040] 104: Active Zone

[0041] 106: Groove

[0042] 108: Second contact hole

[0043] 110: Base

[0044] 1102: Upper surface

[0045] 120: Isolation material

[0046] 130: Insulation characteristics

[0047] 20: Storage capacitor

[0048] 210: Storage node

[0049] 220: Capacitor insulator

[0050] 230: Upper electrode

[0051] 232: Upper surface

[0052] 30: Access transistor

[0053] 310: Gate isolation layer

[0054] 312: Isolation pad

[0055] 320: Gate material

[0056] 321: Gate column

[0057] 322: Character line

[0058] 330: Cover layer

[0059] 340: Doping area

[0060] 350: Doping area

[0061] 40: Dielectric layer

[0062] 402: First dielectric layer

[0063] 403: Opening

[0064] 404: Second dielectric layer

[0065] 405: first contact hole

[0066] 42: Conductive embolism

[0067] 42A: Conductive embolism

[0068] 44: Bit line

[0069] 50: Conductive characteristics

[0070] 500: Sacrificial film

[0071] 502: Sacrificial liner

[0072] 510: Lower part

[0073] 512: Surrounding surface

[0074] 520: Upper part

[0075] 522: Surrounding surface

[0076] 600: Preparation method

[0077] 610: Sacrifice Pattern

[0078] CD1: First critical dimension

[0079] CD2: Second critical dimension

[0080] CD3: Third critical dimension

[0081] CD4: The Fourth Critical Dimension

[0082] S602: Step

[0083] S604: Step

[0084] S606: Step

[0085] S608: Steps

[0086] S610: Steps

[0087] S612: Steps

[0088] S614: Steps

[0089] S616: Steps

[0090] S618: Steps

[0091] S620: Steps

[0092] S621: Steps

[0093] S622: Steps

[0094] S624: Steps

[0095] S626: Steps

[0096] S628: Steps

[0097] S630: Steps

[0098] S632: Steps

[0099] W1: first width

[0100] W2: Second width DETAILED DESCRIPTION

[0101] Specific language will now be used to describe the embodiments or examples of the present disclosure shown in the accompanying drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, will be considered as generally occurring by those of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that the features of one embodiment are applicable to another embodiment, even if they share the same element number.

[0102] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe different elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a "first element," "component," "region," "layer," or "section" discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

[0103] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0104] Figure 1 A cross-sectional view of a semiconductor device 10 illustrating some embodiments of the present disclosure is shown in FIG. Figure 1The semiconductor device 10 may be a semiconductor memory device, such as a dynamic random access memory (DRAM), which includes one or more storage capacitors 20 and one or more access transistors 30, which are turned on in response to a potential conducted thereon to couple the storage capacitors 20 to the associated bit lines 44. Figure 1 The access transistor 30 is shown in the form of a recessed access device (RAD) transistor; however, in some embodiments, the access transistor 30 may be a planar access device (PAD) transistor.

[0105] The semiconductor device 10 further includes a dielectric layer 40 and a plurality of conductive features 50. The dielectric layer 40 is positioned between the storage capacitor 20 and the access transistor 30. The conductive features 50 extend from the storage capacitor 20 and into the substrate 110 to electrically couple the storage capacitor 20 to the access transistor 30. In other words, the conductive features 50 serve as an electrical connection between the storage capacitor 20 and the access transistor 30, and the dielectric layer 40 insulates the conductive features 50. A bit line 44 may be embedded in the dielectric layer 40 and electrically coupled to the access transistor 30 via at least one conductive plug 42 positioned in the dielectric layer 40.

[0106] The storage capacitor 20 located on the access transistor 30 has a plurality of storage nodes 210, a capacitor insulator 220, and a top electrode 230. The storage nodes 210 are each in contact with the conductive feature 50. The capacitor insulator 220 encapsulates the storage nodes 210. The top electrode 230 is disposed on the capacitor insulator 220. In some embodiments, the storage nodes 210 located on the conductive feature 50 and the dielectric layer 40 are spaced apart from each other and electrically insulated from each other. In some embodiments, the storage nodes 210 have a U-shaped structure and serve as the bottom electrodes of the storage capacitor 20. The capacitor insulator 220 may have a topology that mimics the topology of the storage nodes 210 and the dielectric layer 40. The top electrode 230, serving as a top electrode of the storage capacitor 20, may have a substantially planar top surface 232; however, in some embodiments, the top electrode 230 may be a conformal layer.

[0107] The access transistor 30 may be arranged in a Figure 2 In a substrate 110 shown. Figure 1 and Figure 2The substrate 110 has one or more insulating features 130 that define a plurality of active regions 104 where the access transistor 30 is formed. The active regions 104 can be elongated into island-shaped regions. For example, when viewed in plan, the active regions 104 can have an elliptical shape. Furthermore, the active regions 104 can be arranged such that the principal axes (along a longitudinal direction) of the active regions 104 are not parallel to the x-axis or y-axis of an orthogonal coordinate system.

[0108] The access transistor 30 in the active region 104 has a plurality of word lines 322, a plurality of isolation pads 312, and a plurality of doped regions 340 and 350. The word lines 322 are buried in the substrate 110 and covered by a capping layer 330. The isolation pads 312 are disposed between the substrate 110 and the word lines 322 and between the substrate 110 and the capping layer 330. The doped regions 340 and 350 are disposed on either side of the word lines 322. The word lines 322 extend longitudinally along the y-axis and traverse the active region 104, while the bit lines 44 extend longitudinally along the x-axis, which is orthogonal to the y-axis. The active region 104 can be oriented so that its major axis is tilted relative to the word lines 322 and the bit lines 44. The active region 104 can also be sized so that one active region 104 intersects two word lines 322 and one bit line 44.

[0109] Please refer to Figure 1 The doped regions 340 and 350 serve as the drain and source regions of the access transistor 30. The doped regions 340 and 350 can be connected to an upper surface 1102 of the substrate 110. The doped region 340 is electrically coupled to each storage node 210 of the storage capacitor 20 through the conductive features 50. At the same time, the doped region 350 is electrically coupled to the bit line 44 through the conductive plug 42. The word line 322 serves as the gate of the access transistor 30, and the bit line 44, which is fabricated using a damascene process, is electrically coupled to the source of the access transistor 30.

[0110] The conductive features 50 are disposed on either side of the conductive plug 42. Because the active region 104 has an elliptical shape, the landing area of ​​each conductive feature 50 is smaller than the landing area of ​​the conductive plug 42. As a result, the contact area between the access transistor 30 and the conductive feature 50 is reduced, and the contact resistance therebetween is increased. To overcome this problem, the conductive features 50 of the present disclosure are designed to extend into the substrate 110.

[0111] In some embodiments, each conductive feature 50 has a lower portion 510 and an upper portion 520. The lower portion 510 is inserted into the doped region 340 of the access transistor 30, while the upper portion 520 is interposed between the upper surface 1102 of the substrate 110 and the storage capacitor 20. The lower portion 510 of the conductive feature 50 extending into the substrate 110 increases the contact area between the conductive feature 50 and the substrate 110 on which the access transistor 30 is disposed. Thus, the contact resistance between the access transistor 30 and the associated conductive feature 50 is effectively reduced. The upper portion 520 of the conductive feature 50 is surrounded by a dielectric layer 40. The dielectric layer 40 includes a first dielectric layer 402 and a second dielectric layer 404. The first dielectric layer 402 covers the substrate 110, while the second dielectric layer 404 is interposed between the first dielectric layer 402 and the storage capacitor 20.

[0112] Please still refer to Figure 1 The lower portion 510 of the conductive feature 50 located below the upper surface 1102 of the substrate 110 may have a first critical dimension CD1, and the upper portion 520 of the conductive feature 50 located above the upper surface 1102 of the substrate 110 may have a second critical dimension CD2, which is greater than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases with increasing distance from the upper surface 1102 of the substrate 110, while the second critical dimension CD2 remains constant. In particular, a peripheral surface 512 of the lower portion 510 of the conductive feature 50 is discontinuous with a peripheral surface 522 of the upper portion 520 of the conductive feature 50. In particular, the lower portion 510 and the upper portion 520 of the conductive feature 50 comprise polysilicon and are integrally formed.

[0113] Figure 3 Schematic cross-sectional view of a semiconductor device 10A illustrating some embodiments of the present disclosure. It should be understood that Figure 3 The semiconductor device 10A shown includes many features that are the same as or similar to the corresponding Figure 1 For the sake of clarity and simplicity, detailed descriptions of identical or similar features may be omitted, and identical or similar element numbers denote identical or similar elements.

[0114] like Figure 3 The semiconductor device 10A shown is similar to the Figure 1 The main differences between the semiconductor devices 10 shown are described below. Figure 3 The conductive plug 42A, which is used to electrically couple the bit line 44 to the doped region 350, extends from the bit line 44 into the substrate 110. Therefore, a contact resistance between the access transistor 30 and the associated conductive plug 42A can be effectively reduced.

[0115] In some embodiments, a portion of the conductive plug 42A in the substrate 110 has a third critical dimension CD3, and a portion of the conductive plug 42A between the substrate 110 and the bit line 44 has a substantially uniform fourth critical dimension CD4, where the fourth critical dimension CD4 is greater than the third critical dimension CD3. Furthermore, the third critical dimension CD3 may gradually decrease as the distance from the upper surface 1102 of the substrate 110 increases.

[0116] Figure 4 A schematic flow chart illustrating a method 600 for manufacturing a semiconductor device 10 according to some embodiments of the present disclosure is shown. Figures 5 to 24 Schematic cross-sectional views illustrating various intermediate stages of manufacturing a semiconductor device 10 according to some embodiments of the present disclosure. Figures 5 to 24 The stages shown are referenced in Figure 4 In the following discussion, if Figures 5 to 24 The manufacturing stages shown are based on Figure 4 The processing steps shown are discussed.

[0117] Please refer to Figure 5 ,in accordance with Figure 4 In step S602, one or more recesses 102 are formed in a semiconductor wafer 100. For example, semiconductor wafer 100 includes a silicon-containing material. Alternatively or in addition, semiconductor wafer 100 may include other elemental semiconductor materials, such as germanium. Semiconductor wafer 100 is a bulk semiconductor, and a sacrificial pattern 610 including a repeating pattern of multiple lines is applied to semiconductor wafer 100. The sacrificial pattern 610 can be fabricated using a fine pattern formation technology, such as a spacer-patterning technology (SPT), which is suitable for forming a line or space array. Alternatively, the fabrication technology of the sacrificial pattern 610 having a line or space array may include using a double-patterning technology (DPT), a double-exposure technology (DET), a lithography-lithography-etch (LLE) technology, or a lithography-etch-lithography-etch (LELE) technology.

[0118] Next, portions of the semiconductor wafer 100 are etched away using the sacrificial pattern 610 as a mask, thereby forming the recesses 102 in the semiconductor wafer 100 to separate each of the plurality of active regions 104 from one another. The recesses 102 are formed by using at least one etching process to remove portions of the semiconductor wafer 100 not protected by the sacrificial pattern 610. In some embodiments, the recesses 102 may have a uniform width, but the present disclosure is not limited thereto. After the recesses 102 are formed, the sacrificial pattern 610 is removed by any suitable operation.

[0119] Please refer to Figure 6 , based on Figure 4 In step S604 of the present invention, an isolation material 120 is deposited in the recess 102. Thus, a substrate 110 having one or more isolation features 130 is formed. More specifically, the process for fabricating the isolation features 130 includes filling the spaces between the active regions 104 with the isolation material 120. More specifically, the isolation material 120 is conformally and uniformly deposited in the recess 102 and on an upper surface 1002 of the semiconductor wafer 100 (e.g., Figure 5 ) until the isolation material 120 completely fills the recess 102, and then a planarization process is performed to remove the isolation material 120 above the upper surface 1002 of the semiconductor wafer 100. The isolation material 120 comprising oxide or nitride can be deposited using a (plasma) chemical vapor deposition (CVD) process, and the planarization of the isolation material 120 on the recess 102 can be completed, for example, by a chemical mechanical polishing (CMP) process.

[0120] Please refer to Figure 7 and Figure 8 , based on Figure 4 In a step S606, a plurality of grooves 106 are formed to approximately intersect the active region 104. In a plan view, the grooves 106 can be formed to be parallel to the y-axis. In addition, each active region 104 can be divided into three regions by a pair of grooves 106 intersecting the active region 104. The grooves 106 can be made by a process comprising the following steps: (1) applying a groove pattern (not shown) on the substrate 110; and (2) removing portions of the substrate 110 by an etching process. For example, the groove pattern is used as a mask to etch the substrate 110, and for example, the etching is a reactive ion etching (RIE) process. As Figure 8 As shown, the trenches 106 have a uniform width; however, in some embodiments, the bottoms of the trenches 106 may be rounded to reduce defect density and lower electric field concentration during device operation.

[0121] Please refer to Figure 9 , based on Figure 4 In step S608, a gate isolation layer 310 is formed on an exposed portion of the substrate 110. The gate isolation layer 310, which has a substantially uniform thickness, covers the exposed portion of the substrate 110 but does not fill the trench 106. That is, the gate isolation layer 310 is conformally coated on the exposed portion of the semiconductor wafer 100 and on the insulating feature 130. The gate isolation layer 310 may include oxide, nitride, oxynitride, or a high-k dielectric constant (high-k) material, and its fabrication technique may include deposition using a CVD process, an ion layer deposition (ALD) process, or the like. Alternatively, if the semiconductor wafer 100 includes silicon, the gate isolation layer 310 including oxide may be grown on the exposed portion of the semiconductor wafer 100 using a thermal oxidation process.

[0122] Next, based on Figure 4 In step S610, a gate material 320 is deposited to fill the trench 106. The gate material 320 may be conformally and uniformly deposited on the gate isolation layer 310 until the trench 106 is completely filled. The gate material 320 comprising polysilicon may be deposited in the trench 106 using a CVD process, a physical vapor deposition (PVD) process, an ALD process, or other suitable process. In some embodiments, the polysilicon is not doped.

[0123] Please refer to Figure 10 , a portion of the gate material 320 located on the upper surface 1102 of the substrate 110 and some portions of the gate isolation layer 310 located on the upper surface 1102 of the substrate 110 are removed. Thus, a plurality of isolation liners 312 and a plurality of gate pillars 321 are formed. An etching process and / or a polishing process can be used to remove the portions of the gate isolation layer 310 and the gate material 320 that overflow the trench 106. After the removal process, the trench 106 is completely occupied by the gate pillars 321 and the isolation liners 312 located between the substrate 110 and the gate pillars 321.

[0124] Please refer to Figure 11 , based on Figure 4 In step S612, the gate pillars 321 are recessed below the upper surface 1102 of the substrate 110. Thus, a plurality of word lines 322 are formed. The fabrication technique for the word lines 322 includes using an etching process, such as an RIE process, to recess the gate pillars 321 into the substrate 110. In some embodiments, the isolation liner 312 may optionally be recessed below the upper surface 1102 of the substrate 110.

[0125] Based on Figure 4In step S614, after the word lines 322 are formed, a cap layer 330 is formed on the word lines 322. The cap layer 330 serves as a passivation layer to protect the word lines 322. The cap layer 330 may be formed by depositing an insulator in the trenches 106. For example, the insulator may include silicon oxide, silicon nitride, silicon oxynitride, hafnium dioxide, or zirconium dioxide.

[0126] Please refer to Figure 12 , based on Figure 4 In step S616, a plurality of dopants are introduced into the substrate 110 to form doped regions 340 and 350 on either side of the word line 322. Accordingly, the (recessed) access transistor 30 is completely formed. The doped regions 340 and 350 can serve as the source and drain regions of the access transistor 30. The introduction of the dopants into the substrate 110 is achieved by a diffusion process or an ion implantation process. If the respective access transistor 30 is a p-type transistor, the dopant introduction can be performed using boron or indium; or, if the respective access transistor 30 is an n-type transistor, the dopant introduction can be performed using phosphorus, arsenic or antimony.

[0127] Based on Figure 4 In step S618 of FIG. 1 , after the access transistor 30 is formed, a first dielectric layer 402 is formed thereon. The fabrication technique for the first dielectric layer 402 may include using a CVD process to uniformly deposit a first dielectric material to cover the upper surface 1102 of the substrate 110 and the access transistor 30. Alternatively, the first dielectric material 402 may be formed on the substrate 110 and the access transistor 30 using a spin coating process. For example, a CMP process may be used to planarize the first dielectric layer 402 to produce an acceptable flat topology. The first dielectric layer 402 may include oxide, tetraethylorthosilicate (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin-on glass (SOG), tonnensilazane (TOSZ), or a combination thereof.

[0128] Please refer to Figure 13 and Figure 14 , based on Figure 4 In step S620, a conductive plug 42 is formed to contact the doped region 350. The fabrication technique of the conductive plug 42 may include: (1) applying a photoresist pattern (not shown) to define an area to be etched and to protect other areas of the first dielectric layer 402; (2) performing an etching process using the photoresist pattern as a mask to produce an opening 403 through the first dielectric layer 402, thereby exposing the associated doped region 350; and (3) depositing a first conductive material in the opening 403. For example, before the first conductive material is deposited, an ashing process or a wet etching process may be used to remove the photoresist pattern, and a planarization process may be optionally performed to remove excess portions of the first conductive material on the first dielectric layer 402. That is, during the planarization process, the first dielectric layer 402 acts as a stop layer. The first conductive material may include tungsten and be deposited using a CVD process.

[0129] Please refer to Figure 15 , based on Figure 4 In step S621, a bit line 44 is formed to contact the conductive plug 42. The fabrication technique of the bit line 44 may include depositing a second conductive material to bury the first dielectric layer 402 and the conductive plug 42, and patterning the second conductive material with a bit line pattern using an anisotropic process, for example.

[0130] Next, based on Figure 4 In step S622 of the present invention, a second dielectric layer 404 is deposited over the first dielectric layer 402 and the bit line 44. A CVD process can be used to conformally deposit the second dielectric layer; however, in some embodiments, the second dielectric layer formation technique may include spin coating. Furthermore, a CMP process is used to provide a planar topography over the second dielectric layer 404. The second dielectric layer 404 comprises a dielectric material having different etching characteristics than the substrate 110. Therefore, the substrate 110 can be selectively etched relative to the second dielectric layer 404.

[0131] Please refer to Figure 16 , based on Figure 4In step S624, portions of the first dielectric layer 402 and the second dielectric layer 404 are removed to form a plurality of first contact holes 405 exposing the doped regions 340. For example, an etching process including at least one RIE process is used to sequentially etch the second dielectric layer 404 and the first dielectric layer 402, which are made of the same material or have the same etching characteristics. Alternatively, the first dielectric layer 402 and the second dielectric layer 404, which are made of different materials, are anisotropically dry-etched using different etchants, and the etchants are selected based on the materials of the first dielectric layer 402 and the second dielectric layer 404, so as to sequentially etch the second dielectric layer 404 and the first dielectric layer 402.

[0132] Please refer to Figure 17 A sacrificial film 500 is conformally formed on the doped regions 340, the exposed portions of the first dielectric layer 402, and the second dielectric layer 404. The sacrificial film 500 has a substantially uniform thickness and a configuration that mimics the exposed portions of the doped regions 340, the first dielectric layer 402, and the second dielectric layer 404. It should be understood that the sacrificial film 500 comprises a dielectric material having different etching characteristics than the substrate 110. For example, the sacrificial film 500 may comprise nitride and be deposited using a CVD process, an ALD process, or the like.

[0133] Please refer to Figure 18 , a removal process is performed to remove at least some portions of the sacrificial film 500 covering the doped regions 340. In particular, an anisotropic etching process is performed to remove the horizontal portions of the sacrificial film 500 on the doped regions 340 and above the second dielectric layer 404, while the vertical portions of the sacrificial film 500 remain on the first dielectric layer 402 and the second dielectric layer 404, thereby forming a plurality of sacrificial liners 502 in the first contact holes 405 (at Figure 4 An anisotropic etching process is used to remove the horizontal portion of the sacrificial film 500. The chemistry of the anisotropic etching process may be selective to the material of the sacrificial film 500. In other words, during the etching of the horizontal portion of the sacrificial film 500, a substantial amount of material from the substrate 110 and the first and second dielectric layers 402, 404 is not removed.

[0134] Please refer to Figure 19 , based on Figure 4In step S628, portions of the substrate 110 exposed through the first and second dielectric layers 402, 404, and the sacrificial liner 502 are etched away. Thus, a plurality of second contact holes 108 connected to the first contact holes 405 are formed. For example, at least one RIE process is used to anisotropically dry etch the portions of the substrate 110 exposed through the first and second dielectric layers 402, 404, and the sacrificial liner 502 through the first contact holes 405, thereby forming the second contact holes 108 in the substrate 110. During the etching of the substrate 110, the second dielectric layer 404 and the sacrificial liner 502 function as a mask.

[0135] Please refer to Figures 19 to 21 , based on Figure 4 In step S630, after the second contact hole 108 is formed, the sacrificial liner 502 is removed, and a conductive material is deposited in the first contact hole 405 and the second contact hole 108 to form the conductive feature 50. A stable process is used to remove the sacrificial liner 502, and the stable process is, for example, a wet etching process. Figure 20 As shown, the first contact hole 405 has a substantially uniform first width W1, and the second contact hole 108 has a non-uniform second width W2. In some embodiments, the second width W2 gradually decreases with increasing distance from the upper surface 1102 of the substrate 110. For example, a conductive feature 50 comprising polysilicon is deposited in the first and second contact holes 405 and 108 using a CVD process. The portion of the conductive feature 50 in the substrate 110 may have a funnel shape. In particular, if the sacrificial liner 502 is removed before the conductive feature 50 is formed, the conductive feature 50 surrounded by the first dielectric layer 402 and the second dielectric layer 404 may have a larger critical dimension, thereby reducing the resistance of the conductive feature 50. However, in some embodiments, if the material of the conductive feature 50 has an acceptable resistivity, the sacrificial liner 502 may remain in the resulting semiconductor device 10. In these embodiments, a diffusion barrier layer having a substantially uniform thickness may be deposited on the exposed portions of the substrate 110 and the sacrificial liner 502 to prevent flaking or spalling of the conductive features 50 from the sacrificial liner 502 comprising nitride.

[0136] Please refer to Figure 7 、 Figure 19 and Figure 20The doped region 350 is disposed at the center of the elliptical active region 104, and the doped regions 340 are disposed on either side of the doped region 350; therefore, the area used to form the conductive feature 50 is smaller than the area used to land the conductive plug 42. The sacrificial liner 502 limits the location where the substrate 110 is etched through the first contact hole 405, thereby preventing cracks from occurring at the location where the conductive feature 50 is disposed.

[0137] Please refer to Figures 22 to 24 , based on Figure 4 In step S632, a plurality of storage capacitors 20 are formed on the second dielectric layer 404 and the conductive features 50. Thus, the semiconductor device 10 is completely formed. In particular, the storage capacitors 20 have a plurality of storage nodes 210, each of which contacts the conductive features 50.

[0138] The fabrication of the storage node 210 includes sequentially depositing a blanket sacrificial layer having a sufficient thickness on the second dielectric layer 404 and the conductive feature 50; patterning the sacrificial layer using lithography and etching processes to create a plurality of windows to expose the conductive feature 50 and portions of the second dielectric layer 404 contacting the conductive feature 50; conformally depositing a conductive layer on the remaining sacrificial layer, the conductive feature 50, and portions of the second dielectric layer 404 exposed through the windows; and removing portions of the conductive layer located on an uppermost surface of the remaining sacrificial layer. The remaining sacrificial layer is then removed from the second dielectric layer 404, and the conductive feature 50 is then removed. Figure 22 The U-shaped storage node 210 is shown as being left in its original position. The sacrificial layer comprises a dielectric layer having different etching characteristics than the second dielectric layer. Thus, the sacrificial layer can be selectively etched relative to the second dielectric layer. The storage node 210 comprises doped polysilicon or a metal, such as titanium nitride (TiN) or ruthenium.

[0139] Please refer to Figure 23 A capacitor insulator 220 having a substantially uniform thickness is formed to cover the second dielectric layer 404 and the storage node 210. That is, the capacitor insulator 220 is a conformal layer. That is, the capacitor insulator 220 has a configuration that mimics the configuration of the storage node 210 and the second dielectric layer 404. The capacitor insulator 220 may comprise silicon dioxide (SiO2), silicon nitride (Si3N4), or a high-k dielectric material such as zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), or aluminum oxide (Al2O3). In some embodiments, the capacitor insulator 220 may comprise a double layer of nitride / oxide film or a triple layer of oxide / nitride / oxide.

[0140] Please refer to Figure 24 , a top electrode 230 is deposited on the capacitor insulator 220. In some embodiments, the top electrode 230 may be a substantially conformal layer, and its fabrication technique may include a CVD process. In other embodiments, the top electrode 230 may have a substantially flat top surface 232, such as Figure 1 and Figure 3 The upper electrode 230 may include a low resistivity material such as titanium nitride or a combination of titanium nitride, tantalum nitride (TaN), tungsten nitride (WN), ruthenium, iridium (Ir), and platinum (Pt).

[0141] In summary, the structure of the conductive feature 50 extending into the lower portion 510 of the substrate 110 forming the access transistor 30 increases the contact area between the conductive feature 50 and the access transistor 30. Therefore, the contact resistance between the conductive feature 50 and the access transistor 30 can be effectively reduced.

[0142] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature. The substrate includes at least one insulating feature that defines a plurality of active regions. The storage capacitor is located on the substrate. The access transistor includes a plurality of doped regions located in the active regions. The conductive feature extends from the storage capacitor into the substrate to electrically couple the storage capacitor to the access transistor.

[0143] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate including one or more insulating features, the one or more insulating features defining a plurality of active regions; forming at least one access transistor, the at least one access transistor including a plurality of doped regions, wherein the doped regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated doped regions; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first contact hole and the second contact hole.

[0144] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0145] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor element comprising: a substrate comprising a plurality of insulating features defining a plurality of active regions; a storage capacitor located on the substrate; an access transistor comprising a plurality of doped regions located in the active region; as well as at least one conductive feature extending from the storage capacitor into the substrate for electrically coupling the storage capacitor to the access transistor, The conductive feature includes a lower portion and an upper portion, the lower portion is located in the substrate, the upper portion is inserted between the substrate and the storage capacitor, the lower portion has a first critical dimension, and the upper portion has a second critical dimension, the second critical dimension is larger than the first critical dimension; wherein the lower portion of the conductive feature in the substrate does not contact any of the multiple insulating features in the substrate. 2 . The semiconductor device of claim 1 , wherein the conductive feature is inserted into the associated doped region. 3 . The semiconductor device of claim 2 , wherein a portion of the conductive feature in the substrate has a funnel shape. 4 . The semiconductor device of claim 1 , wherein the first critical dimension of the lower portion of the conductive feature gradually decreases as the distance from the upper portion increases. 5 . The semiconductor device of claim 1 , wherein the lower portion of the conductive feature has a peripheral surface that is discontinuous with a peripheral surface of the upper portion of the conductive feature. The semiconductor device of claim 1 , wherein the lower portion and the upper portion of the conductive feature are integrally formed.

7. The semiconductor device according to claim 1 , wherein the access transistor further comprises: a plurality of word lines disposed in the substrate and crossing the active region, wherein the doped regions are disposed on either side of the word lines; and A plurality of isolation pads are sandwiched between the substrate and the word lines.

8. The semiconductor device according to claim 7, further comprising: a dielectric layer between the storage capacitor and the substrate to encapsulate the access transistor and surround the conductive feature; a bit line buried in the dielectric layer; and A conductive plug extends from the bit line and into the substrate to electrically couple the bit line to the access transistor.

9. The semiconductor device of claim 8 , wherein a portion of the conductive plug inserted into the doped region has a third critical dimension, and another portion of the conductive plug inserted between the bit line and the substrate has a fourth critical dimension, and the fourth critical dimension is larger than the third critical dimension.

10. The semiconductor device according to claim 7, wherein the storage capacitor comprises: at least one storage node in contact with the conductive feature; a capacitor insulator encapsulating the storage node; as well as An upper electrode is located on the capacitor insulator.

11. A method for preparing a semiconductor element, comprising: Providing a substrate comprising one or more insulating features, wherein the one or more insulating features define a plurality of active regions; forming at least one access transistor, the at least one access transistor comprising a plurality of doped regions, wherein the doped regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated doped region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first contact hole and the second contact hole, The forming of the sacrificial liner includes: depositing a sacrificial film on the dielectric layer and on a portion of the substrate exposed in the first contact hole, wherein the sacrificial film does not fill the first contact hole; and Portions of the sacrificial film are removed to expose the substrate. 12 . The method of claim 11 , further comprising removing the sacrificial liner before forming the conductive feature. 13 . The method according to claim 11 , wherein the first contact hole has a first width, and the second contact hole has a second width, and the second width is smaller than the first width. 14 . The manufacturing method according to claim 13 , wherein the second width of the second contact hole gradually decreases at a position increasing in distance from the first contact hole.

15. The method according to claim 11, wherein forming the access transistor comprises: creating at least one trench in the substrate and traversing the active region; depositing a gate insulator in the trench, wherein a portion of the trench remains unfilled; forming a word line to occupy a bottom portion of the trench; depositing a cap layer in the trench to cover the word line; and A plurality of dopants are introduced into the substrate to form the doped regions.

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