Three-dimensional storage structure and manufacturing method thereof, three-dimensional memory, and storage system

Abstract

The present disclosure relates to a three-dimensional memory structure and a manufacturing method thereof, a three-dimensional memory, and a storage system. The method for manufacturing the three-dimensional memory structure includes: forming a stacked structure on a substrate, wherein the stacked structure includes multiple stacked layers formed by stacking a first material layer and a second material layer; forming multiple contact holes in the stacked structure, the contact holes extending from a side of the stacked structure away from the substrate along the stacking direction of the multiple stacked layers, the multiple contact holes including at least two groups of contact holes; extending at least one of the contact holes in each group so that each contact hole in the same group extends to a first material layer at a different height; extending at least one group of contact holes so that any contact hole in each group of contact holes extends to a different height than any contact hole in another group of contact holes; and forming a conductive channel structure in the contact hole.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more specifically, to a three-dimensional storage structure and a manufacturing method thereof, a three-dimensional memory, and a storage system. Background Art

[0002] Three-dimensional memory structures offer significant storage capacity, but researchers are still pursuing further improvements. When manufacturing these structures, a step structure can be formed on top of a stacked structure. The exposed surface of the step structure is then used to connect to the conductive path.

[0003] As the number of stacked layers in a three-dimensional memory structure increases, the process of forming the stepped structure becomes increasingly difficult, as does the process of forming the conductive channel structure to connect to the gate layer. Furthermore, during the manufacturing process of the stepped structure, various stresses are generated within the stacked structure. These stresses can cause wafer bowing, making it more difficult to control processing accuracy, such as offsetting fiducial markers and dimensional distortion. Furthermore, to mitigate the effects of these stresses, more complex steps, such as annealing, are required. Summary of the Invention

[0004] The embodiments of the present disclosure may at least solve one or more technical problems in the above-mentioned prior art, or be used to solve other technical problems in the prior art.

[0005] In one aspect, an embodiment of the present disclosure provides a method for manufacturing a three-dimensional storage structure, the method comprising: forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of stacked layers formed by stacking a first material layer and a second material layer; forming a plurality of contact holes in the stacked structure, the contact holes extending from a side of the stacked structure away from the substrate along a stacking direction of the plurality of stacked layers, the plurality of contact holes comprising at least two groups of contact holes; extending at least one of the contact holes in each group so that each contact hole in the same group of contact holes extends to a first material layer at a different height position; extending at least one group of contact holes so that any one contact hole in each group of contact holes extends to a different height position from any one contact hole in other groups of contact holes; and forming a conductive channel structure in the contact hole.

[0006] In some embodiments, the step of forming the plurality of contact holes includes: forming a first mask layer on the stacked structure; patterning the first mask layer to form a plurality of through-hole patterns; and etching the stacked structure using the plurality of through-hole patterns to form the plurality of contact holes.

[0007] In some embodiments, at least two groups of contact holes are arranged along a first direction perpendicular to the stacking direction, and the method further includes: forming a patterned second mask layer on the first mask layer; and based on the second mask layer, cyclically performing an etching process and a trimming process so that in at least one group of contact holes, the extension depth difference between any two conductive channel structures adjacent along the first direction is the same.

[0008] In some embodiments, the steps of cyclically performing the etching process and the trimming process include: cyclically performing the etching process and the trimming process according to a pattern in the second mask layer located between two adjacent groups of contact holes, so that in the two adjacent groups of contact holes, the number of stacked layers extended through by one group of contact holes increases successively, and the number of stacked layers extended through by the other group of contact holes decreases successively.

[0009] In some embodiments, in a second direction perpendicular to the stacking direction and perpendicular to the first direction, the stacked structure is divided into at least a first partition and a second partition, and the method further includes: extending the contact hole located in the first partition so that the contact hole located in the first partition and the contact hole located in the second partition extend through different numbers of first material layers.

[0010] In some embodiments, each of at least two groups of contact holes has the same number of contact holes, and each group of contact holes extends to a group of continuous stacked layers, wherein the step of extending at least one group of contact holes includes: making the depth of each group of contact holes extended to an integer multiple of the height of a group of continuous stacked layers.

[0011] In some embodiments, the first material layer is a gate sacrificial layer, and the second material layer is an insulating layer, wherein the step of extending multiple contact holes so that each contact hole in the same group of contact holes extends to the first material layer at a different height position includes: extending the contact hole to the second material layer adjacent to the target first material layer, or extending the contact hole to the target first material layer; forming an insulating wall on the inner surface of the contact hole; and exposing the first material layer at the bottom end of the contact hole; and wherein the conductive channel structure extends from the top of the contact hole to the exposed first material layer.

[0012] In some embodiments, the method further includes: forming a functional layer covering the conductive channel structure on a side of the stacked structure away from the substrate.

[0013] In some embodiments, the method further includes: forming a virtual channel structure penetrating the substrate and the stacked structure from a side of the substrate away from the functional layer.

[0014] In some embodiments, the method further includes: forming a gate line gap groove penetrating the substrate and the stacked structure from a side of the substrate away from the functional layer; and replacing the first material layer with a gate layer electrically connected to the conductive channel structure through the gate line gap groove.

[0015] In some embodiments, in a first direction perpendicular to the stacking direction, the stacked structure is divided into at least a storage area and a step area, and the step of forming a gate line slit groove includes: forming a first gate line slit groove segment in the storage area; and forming a second gate line slit groove segment in the step area; the step of replacing the first material layer with a gate layer electrically connected to the conductive channel structure includes: replacing a portion of the first material layer located in the storage area with a first gate portion through the first gate line slit groove segment; and replacing a portion of the first material layer located in the step area with a second gate portion electrically connected to the first gate portion and the conductive channel structure through the second gate line slit groove segment.

[0016] In some embodiments, the step of replacing a portion of the first material layer located in the storage area with a first gate portion includes: removing the portion of the first material layer located in the storage area to obtain a first sacrificial space; forming a high dielectric layer in the first sacrificial space; and forming a first gate portion in the first sacrificial space; the step of replacing a portion of the first material layer located in the step area with a second gate portion includes: removing the portion of the first material layer located in the step area to obtain a second sacrificial space exposing the conductive channel structure; and forming a second gate portion electrically connected to the first gate portion and the conductive channel structure in the second sacrificial space.

[0017] In some embodiments, the cross-sectional shape of the contact hole includes at least one of a circle, an ellipse, and a polygon.

[0018] In a second aspect, an embodiment of the present disclosure provides a three-dimensional storage structure, which includes: a stacked structure, including multiple stacked layers formed by stacking gate layers and insulating layers; multiple conductive channel structures, in the stacking direction of the stacked structure, the conductive channel structure extends from one side of the stacked structure into the stacked structure, and at least one conductive channel structure passes through at least one gate layer, and the multiple conductive channel structures are electrically connected to gate layers at different heights.

[0019] In some embodiments, the stacked structure includes at least two groups of conductive channel structures along a first direction perpendicular to the stacking direction, and in at least one group of conductive channel structures, the difference in extension depth between any two adjacent conductive channel structures along the first direction is the same.

[0020] In some embodiments, in two adjacent groups of conductive channel structures, along the first direction, the number of stacked layers through which the conductive channel structures of one group extend increases sequentially, and the number of stacked layers through which the conductive channel structures of the other group extend decreases sequentially.

[0021] In some embodiments, each of at least two groups of conductive channel structures includes the same number of conductive channel structures, and the stacking layers of a group to which each group of conductive channel structures extends are arranged continuously along the stacking direction, wherein the distance between the two groups of stacking layers corresponding to any two groups of conductive channel structures is an integer multiple of the height of a group of stacking layers.

[0022] In some embodiments, an insulating wall surrounds the conductive channel structure, and the insulating wall isolates the conductive channel structure from the gate layer through which the conductive channel passes.

[0023] In some embodiments, the three-dimensional storage structure further includes: a first functional layer, disposed on one side of the stacked structure and electrically connected to the conductive channel structure; a second functional layer, disposed on the other side of the stacked structure; and a virtual channel structure, running through the second functional layer and the stacked structure.

[0024] In some embodiments, in a first direction perpendicular to the stacking direction, the stacked structure is divided into a storage area and a step area, and a high dielectric layer is provided between the first gate portion of the storage area and the insulating layer of the gate layer; and the second gate portion of the gate layer in the step area is electrically connected to the first gate portion and the conductive channel structure.

[0025] In some embodiments, the cross-sectional shape of the conductive channel structure includes at least one of a circle, an ellipse, and a polygon.

[0026] In a third aspect, an embodiment of the present disclosure provides a memory comprising: the aforementioned three-dimensional memory structure; and a peripheral circuit electrically connected to the three-dimensional memory structure.

[0027] In a fourth aspect, an embodiment of the present disclosure provides a storage system, which includes: the aforementioned memory; and a controller electrically connected to the memory and used to control the memory.

[0028] The method for fabricating a three-dimensional memory structure provided by the embodiments of this disclosure differs from the conventional method of forming steps within a stacked structure. Instead, it utilizes contact holes to introduce a conductive channel structure into the stacked structure, thereby extending multiple gate layers to the top surface. This method avoids the various problems encountered in the formation of step structures, and the method itself has fewer process steps and lowers process costs.

[0029] Furthermore, the three-dimensional memory structure formed by this method exhibits excellent processability during the gate replacement step. The stacked structure is well supported, making it less susceptible to adverse conditions such as bending and collapse. This three-dimensional memory structure and the memory and storage systems incorporating it offer improved performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objects and advantages of the present disclosure will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0031] Figure 1 is a flowchart of a method for manufacturing a three-dimensional storage structure according to an embodiment of the present disclosure;

[0032] Figures 2 to 22 is a process diagram of a method for manufacturing a three-dimensional storage structure according to an embodiment of the present disclosure;

[0033] Figure 23 is a structural schematic diagram of a first mask according to an embodiment of the present disclosure;

[0034] Figure 24 is a structural schematic diagram of another first mask according to an embodiment of the present disclosure;

[0035] Figure 25 is a structural schematic diagram of another first mask according to an embodiment of the present disclosure;

[0036] Figures 26 to 32 is a process diagram of a method for manufacturing a three-dimensional storage structure according to other embodiments of the present disclosure;

[0037] Figure 33 is a three-dimensional memory according to an embodiment of the present disclosure; and

[0038] Figure 34 A storage system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] To better understand the present disclosure, various aspects of the present disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present disclosure and are not intended to limit the scope of the present disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features. Therefore, without departing from the teachings of the present disclosure, the following discussion of the first, second, third, etc. and vice versa are also applicable.

[0041] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are for illustration purposes only and are not drawn strictly to scale. For example, as used herein, the terms "substantially," "approximately," and similar terms are intended to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0042] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present disclosure, "may" is used to mean "one or more embodiments of the present disclosure." And, the term "exemplary" is intended to refer to an example or illustration.

[0043] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure pertains. It should also be understood that, unless otherwise expressly stated in the present disclosure, words defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0044] It should be noted that, unless otherwise specified or inconsistent with the context, the embodiments and features of the embodiments in this disclosure may be combined with each other. Furthermore, unless expressly limited or inconsistent with the context, the specific steps included in the methods described in this disclosure are not necessarily limited to the order in which they are described, but may be performed in any order or in parallel. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0045] Figure 1 1 is a flowchart of a method for manufacturing a three-dimensional storage structure according to an embodiment of the present disclosure. Figure 1 , the method 1000 provided in the embodiment of the present disclosure includes the following steps.

[0046] Step S101: Forming a stacked structure. Specifically, a stacked structure can be formed by alternately stacking a first material layer and a second material layer on a substrate. Adjacent first and second material layers can form a stacked layer. For example, the second material layer can be on the first material layer. There can be etching selectivity between the first and second material layers. In some exemplary embodiments, the material of the first material layer may include silicon nitride, and the material of the second material layer may include silicon oxide. In other embodiments, the first material layer may be conductive, such as polysilicon, while the second material layer is an insulating layer.

[0047] Step S102: forming a plurality of contact holes in the stacked structure. The contact holes extend from a side of the stacked structure away from the substrate along the stacking direction of the plurality of stacked layers. The plurality of contact holes includes at least two groups of contact holes.

[0048] Step S103 , extending the plurality of contact holes so that each contact hole in the same group of contact holes extends to the first material layer at a different height.

[0049] In step S104, at least one group of contact holes is extended to a different height than the contact holes in the other groups. Specifically, each group of contact holes is extended to a different height than the other groups. It should be noted that the extension process used in steps S103 and S104 can be performed in stages.

[0050] Step S105: forming a conductive channel structure in the contact hole. The conductive structure is in contact with the first material layer and can be exposed on the top surface of the stacked structure.

[0051] The method for manufacturing a three-dimensional storage structure provided by the embodiment of the present disclosure can avoid multi-level etching of the stacked structure, thereby avoiding steps such as forming steps and filling insulating materials. In addition, after grouping multiple contact holes, the contact holes can be extended by using some steps to reduce the number of process steps. When the logarithm of the number of contact holes with base 2 is between n-1 and n, n+1 mask templates can be used to etch all the contact holes. For example, when the stacked structure has sixteen stacked layers, that is, sixteen first material layers that need to be led out, sixteen contact holes need to be formed accordingly, then a mask template is required to pattern the first mask layer, and then four mask templates can be used to etch all the contact holes into place. For example, when the number of stacked layers of the stacked structure is between two hundred and fifty-six and five hundred and twelve, ten mask templates are required to etch all the contact holes into place. The present disclosure does not limit the number of stacked layers in the stacked structure, and those skilled in the art can design it according to actual conditions.

[0052] The following is combined with Figures 2 to 30 Some embodiments provided by the present disclosure are described in detail.

[0053] A method for fabricating a three-dimensional storage structure is provided. Figures 2 to 21 A process diagram of an embodiment is shown.

[0054] Illustratively, a stacked structure 2 is formed on a substrate 1. The substrate 1 may be made of any suitable semiconductor material, including, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Illustratively, the substrate 1 may be a composite substrate comprising multiple layers made of different materials.

[0055] The stacked structure 2 includes a plurality of stacked layers 21 formed by stacking first material layers 201 and second material layers 202. The stacked structure 2 may further include a top second material layer 203. The top second material layer 203 may be thicker than the second material layer 202, and the top second material layer 203 and the top second material layer 203 may be made of the same material. The bottom half of the top second material layer 203 may be considered as a stacked layer together with the adjacent first material layer 201. The first material layer 201, the second material layer 202, and the top second material layer 203 may be formed by a thin film deposition process.

[0056] Figure 2 FIG2 shows an exemplary embodiment of the stacked structure 2 including eight stacked layers 21. The first material layer 201 may include a gate sacrificial layer. The second material layer 202 and the top second material layer 203 may include insulating layers.

[0057] After forming the stacked structure 2, a plurality of contact holes 204 ( Figure 4 Specifically, a first mask layer 3 can be formed on the stacked structure 2 to obtain the following: Figure 3 The structure shown. The first mask layer 3 is located on the side of the stacked structure 2 facing away from the substrate 1, which can be a hard mask. The first mask layer 3 can then be patterned, for example, by etching to form a plurality of through-hole patterns 301. For an exemplary embodiment including eight stacked layers 21, for example, eight through-hole patterns 301 can be formed in the x-direction. The z-direction is the stacking direction of the stacked structure 2, the x-direction is the first direction perpendicular to the stacking direction, and the y-direction is the second direction perpendicular to the x-direction and the z-direction. In the process of forming the through-hole pattern 301, the top second material layer 203 can also be etched. As shown Figure 3 As shown, the bottom of the contact hole 204 formed during the formation of the through hole pattern 301 may remain above the uppermost first material layer 201 .

[0058] In an exemplary embodiment, the contact holes 204 may be extended respectively according to the divided groups, and then the contact holes 204 within the groups may be extended to different height positions.

[0059] like Figure 5 As shown, eight contact holes 204 are located in four stepped regions G1 to G4 arranged in the x-direction, and two contact holes 204 in each stepped region G1 to G4 are considered as one group. A first mask 31 is set in the third stepped region G3 and the fourth stepped region G4 to cover the two groups of contact holes 204 on the right side of the figure and expose the through-hole pattern 301 in the first stepped region G1 and the second stepped region G2, and also expose the two groups of contact holes 204 on the left side. Then the two groups of contact holes 204 on the left are extended through a stacked layer 21 to obtain Figure 5 The structure shown.

[0060] The first mask 31 is removed, and then a second mask 32 is formed. The second mask 32 covers the two groups of contact holes 204 in the second step region G2 and the third step region G3, and exposes the two groups of contact holes 204 in the first step region G1 and the fourth step region G4. The two groups of contact holes 204 on both sides are extended, specifically penetrating a stacked layer 21, to obtain the following: Figure 6 The structure shown. Figure 6 The contact holes 204 of different groups are located at different heights.

[0061] After the different groups of contact holes 204 are positioned at different heights, the second mask plate 32 can be removed to form a third mask plate 33. The third mask plate 33 covers one contact hole 204 in each group and exposes the other. The exposed contact holes 204 are extended through the four stacked layers 21 using the third mask plate 33. Each contact hole 204 in the same group of contact holes 204 extends to a different height.

[0062] When the stacked structure 2 is etched using the first mask plate 31 to the third mask plate 33 , the exposed portion of the first mask layer 3 is also etched each time, so a margin must be left in the thickness of the first mask layer 3 .

[0063] like Figure 8 As shown, the third mask plate 33 and the first mask layer 3 have been removed. Eight contact holes 204 extend to different heights. In some embodiments, the contact holes 204 can be extended to the surface of the first material layer 201. In this embodiment, the contact holes 204 can be extended to the second material layer 202 above the first material layer 201 to be exposed.

[0064] After removing the first mask layer 3, an insulating wall 22 is formed in the contact hole 204. The insulating wall 22 is located on the inner sidewall of the contact hole 204 and has a hollow core. When the insulating wall 22 is formed, an insulating bottom 221 is also formed at the bottom of the contact hole 204. Figure 9 shown.

[0065] In this embodiment, after forming the insulating wall 22, the first material layer 201 is exposed at the bottom of the contact hole 204. The insulating bottom 221 can be removed by etching, and the second material layer 202 on the first material layer 201 to be exposed is etched to obtain the following: Figure 10 The structure shown. Figure 10 As shown, each contact hole 204 exposes the first material layer 201 corresponding thereto, and the insulating wall 22 shields the first material layer 201 through which the contact hole 204 passes.

[0066] A conductive channel structure 23 is formed in the contact hole 204. The conductive channel structure 23 extends from the top of the contact hole 204 to the exposed first material layer 201. Figure 11 As shown, the insulating wall 22 surrounds the conductive channel structure 23 in the horizontal direction to isolate the first material layer 201 through which the conductive channel structure 23 passes.

[0067] like Figure 12 As shown, the conductive channel structure 23 may be filled with a filling structure 24. The stacked structure 2 may be divided into a storage region GB and a step region SS in the x-direction. Each conductive channel structure 23 formed in the stacked structure 2 may be located in the step region SS. A channel structure 25 may be provided in the portion of the stacked structure 2 located in the storage region GB.

[0068] The channel structure 25 can extend through the plurality of stacked layers 21 into the substrate 1. In some embodiments, the channel structure 25 can be formed before the top second material layer 203 of the stacked structure 2 is formed, so that the top second material layer 203 covers the channel structure 25. The channel structure 25 includes a charge blocking layer 251, a charge trapping layer 252, a tunneling layer 253, and a channel layer 254, which are sequentially arranged from the outside to the inside in a vertical plane relative to the direction of its extension. A filling layer 255 may also be disposed inside the channel layer 254.

[0069] The first functional layer 4 can be formed on the laminate structure 2 to obtain Figure 13 The structure shown. The first functional layer 4 may include an interconnection layer and other structures (not shown) to electrically connect the various conductive channel structures 23. The interconnection pattern of the interconnection layer and other structures can be designed accordingly based on the number and actual extension depth of the conductive channel structures 23. For example, a single layer of the first functional layer 4 covering the conductive channel structures 23 can also be formed in this step, and then the first functional layer 4 can be further processed in subsequent steps.

[0070] In some embodiments, before forming the first functional layer 4 , a dummy channel structure penetrating the stacked structure 2 and extending into the substrate 1 may be formed first.

[0071] In this embodiment, a dummy channel structure 26 is formed from the substrate 1 and penetrates the substrate 1 and the stacked structure 2. The dummy channel structure 26 may also extend into the first functional layer 4, such as Figure 14As shown. Since the stacked structure 2 is relatively thick, when etching the virtual channel hole for forming the virtual channel structure 26 therein, the diagonal size of the bottom end of the virtual channel hole will be smaller than the diagonal size of the top end thereof, so that the top end of the virtual channel structure 26 is larger than the bottom end when it is formed. In this embodiment, a virtual channel structure 26 is formed on the side where the substrate 1 is located, which passes through the stacked structure 2, so that the larger end of the virtual channel structure 2 is located on the substrate 1, thereby providing stronger support for the stacked layer 21 close to the substrate 1. In addition, the virtual channel structure 26 and the conductive channel structure 23 can be better avoided to avoid connection between the two when they are formed. In addition, the etching path passed by each virtual channel structure 26 in the stacked structure 2 is the same, which avoids the phenomenon of poor consistency caused by different virtual channel structures 26 passing through different paths.

[0072] The dummy channel structure 26 may be used to support the stacked structure 2 . Specifically, when a gate replacement process is performed on the stacked structure 2 , the dummy channel structure 26 may be used to support the stacked structure 2 to reduce the risk of collapse.

[0073] In this embodiment, the first material layer 201 serves as a gate sacrificial layer and may include silicon nitride. The first material layer 201 portions located in the storage region GB and the step region SS may be replaced separately. Adjustments may be made in the two replacement steps, so that the stacked structure 2 has different structures in the storage region GB and the step region SS, achieving different targeted functions.

[0074] like Figure 15 As shown, in some embodiments, a gate line slot trench penetrating the substrate 1 and the stacked structure 2 may be formed first, and the gate line slot trench includes a first gate line slot segment 205 and a second gate line slot segment 211. A mask may then be used to cover the second gate line slot segment 211, so that the gate of the portion of the first material layer 201 located in the storage area GB may be replaced by the second gate line slot segment 205. In other embodiments, the first gate line slot segment 205 ( Figure 17 ), a gate replacement process is performed on the portion of the first material layer 201 located in the storage area GB through the first gate line slot segment 205. Then, a second gate line slot segment 211 ( Figure 18 ), a gate replacement process is performed on a portion of the first material layer 201 located in the step area SS through the second gate line gap groove segment 211.

[0075] Figure 16 yes Figure 15 Cross-sectional view at CC in the middle. Figure 16As shown, the portion of the first material layer 201 located in the storage region GB has been replaced with the first gate portion 206. Specifically, the portion of the first material layer 201 located in the storage region GB can be removed to obtain a first sacrificial space (not shown). A high dielectric layer can be formed in the first sacrificial space, and then the first gate portion 206 can be formed in the first sacrificial space. Figure 17 yes Figure 15 For example, as Figure 17 As shown, a high dielectric layer 208 , a connecting layer 207 and a first gate portion 206 may be sequentially formed between two adjacent second material layers 202 through the first gate line gap segment 205 .

[0076] Figure 18 yes Figure 15 The cross-sectional view at BB. Figure 18 As shown, the second gate line gap groove segment 211 exposes the portion of each first material layer 201 located in the step area SS. The first material layer 201 is removed so that a second sacrificial space 212 is formed between any two adjacent second material layers 202, as shown in FIG. Figure 19 As shown, the end of the conductive channel structure 23 facing away from the first functional layer 4 is exposed to the second sacrificial space 212. When forming the second sacrificial space 212, the portion of the high dielectric layer 208 exposed to the second sacrificial space 212 is also removed. For example, the portion of the connecting layer 207 exposed to the second sacrificial space 201 can also be removed, so that the first gate layer 206 is exposed to the second sacrificial space 212.

[0077] In addition, if Figure 18 and Figure 19 As shown, a plurality of conductive channel structures 23 may be formed in the y direction, and the number of the conductive channel structures 23 between two adjacent second gate line gap segments 211 may be set according to requirements.

[0078] A second gate portion 213 is formed in the second sacrificial space 212. Figure 20 Because the conductive channel structure 23 and the first gate portion 206 are both exposed to the second sacrificial space 212, the second gate portion 213 is connected to the conductive channel structure 23 and to the first gate portion 206. For example, the first gate portion 206, the second gate portion 213 on the same layer, and the conductive channel structure 23 extending to the same layer all comprise a conductive material such as tungsten, thereby electrically connecting the three as a whole.

[0079] After the gate layer is formed, a gate line gap spacer structure 27 may be formed in the gate line gap groove. Figure 21 and Figure 22As shown, the gate line slit spacer structure 27 can separate the three-dimensional memory structure into multiple electrically isolated blocks in the y-direction. The gate line slit spacer structure 27 can also be used to provide a common source. The portion of the gate line slit spacer structure 27 located in the memory area GB and the portion located in the step area SS can be manufactured in separate steps. For example, after forming the first gate portion 206, the portion of the gate line slit spacer structure 27 located in the memory area GB is formed; then, after forming the second gate portion 213, the portion of the gate line slit spacer structure 27 located in the step area SS is formed.

[0080] Exemplarily, the substrate 1 is subjected to a subsequent processing process so that the substrate 1 is transformed into a second functional layer.

[0081] The method for manufacturing a three-dimensional memory structure provided by the disclosed embodiments simplifies the process by grouping contact holes and then extending the contact holes in each group. By forming a dummy channel structure from one side of the substrate, the strength of the stacked structure can be improved during the gate replacement process.

[0082] For example, Figures 23 to 25 As shown, the shape of the through-hole pattern 301 of the first mask layer 3 used in this embodiment can be designed in a variety of styles, including but not limited to circular, octagonal, and rectangular. For example, the shape of the through-hole pattern 301 of the first mask layer 3 can also be an ellipse, a rounded rectangle, or a polygon such as a diamond or hexagon. The top of the contact hole 204 has a similar shape to the through-hole pattern 301. As the etching depth increases, the cross-sectional shape of the contact hole 204 approaches a circle and the diameter decreases.

[0083] The present disclosure provides methods for manufacturing three-dimensional storage structures according to other embodiments. Figures 26 to 32 Process diagrams of other embodiments are shown.

[0084] Reference may be made to some of the contents of the aforementioned embodiments, for example, including forming a stacked structure 2 on a substrate (not shown). Exemplarily, the stacked structure 2 may include three hundred stacked layers, and is prepared to form three hundred conductive channel structures in each memory block separated by the gate line gap spacer structure.

[0085] like Figure 26 As shown, the first mask layer 3 formed on the stacked structure 2 in this embodiment has a rectangular through-hole pattern 301 obtained after patterning. Figure 26 The first mask layer 3 shown in FIG. 1 can cover two memory blocks and can be further expanded in the y-direction to cover more memory blocks. The first mask layer 3 can be provided with 150 through-hole patterns 301 in the x-direction and multiple rows of through-hole patterns 301 in the y-direction, where every two rows are used to etch one memory block.

[0086] like Figure 27 As shown, by Figure 26 The first mask layer 3 shown (not shown) Figure 17 The through-hole pattern 301 (shown in FIG) forms a plurality of contact holes 204 in the stacked structure 2. Specifically, three hundred contact holes 204 are formed for each memory block. These three hundred contact holes 204 are arranged in two rows, with one hundred and fifty contact holes 204 arranged in each row along the x-direction. Thirty stepped regions G1 to G30 are divided in the x-direction, so that each region has a group of ten contact holes 204. The ten contact holes 204 in each group are arranged in two rows, with five contact holes 204 in each row along the x-direction. It is understandable that this grouping and arrangement is related to the stepped partitioning of the stacked structure 2 in the y-direction. Figure 27 The two-partition method is illustrated, but in other embodiments, the method can be divided into more partitions in the y direction, and the number of each group of contact holes 204 and the number of each row of contact holes 204 can be set according to actual conditions.

[0087] In this embodiment, the contact holes 204 in each group may be extended to different depths, and then different groups may be extended to different depths. The depth difference between any two groups of contact holes 204 after extension may be an integer multiple of the height of a group of continuous stacked layers.

[0088] Figure 28 This is a schematic diagram of the structure of the second mask layer 34. The first memory block to be formed occupies the first and second subareas A1 and A2, while the second memory block to be formed occupies the third and fourth subareas B1 and B2. The space between the two memory blocks will be used to provide a gate line gap structure in a subsequent step. The second mask layer 34 covers the through-hole pattern 301 in the second and fourth subareas A2 and B2, while exposing the through-hole pattern 301 in the first and third subareas A1 and B1.

[0089] In one embodiment, for the first storage block, the first contact hole 204A located in the first partition A1 is further etched through one second material layer 202 and one first material layer 201 through the first mask layer 3 and the second mask layer 34, so that the first contact hole 204A extends through one more stacked layer than the second contact hole 204B located in the second partition A2. Figure 29 shown.

[0090] This embodiment also utilizes a "trim-etch" cycle process to etch the contact holes 204 arranged in the x direction in each group of contact holes 204 to different height positions. For example, Figure 30As shown, a patterned third mask layer 35 is formed on the stacked structure 2. Based on the third mask layer 35, an etching process and a trimming process are performed cyclically to achieve a stepwise variation in the extension depth of the contact holes 204 in the x-direction within each group of contact holes 204. It should be noted that the terms "first," "second," and so on in this embodiment are used solely to distinguish technical features. Therefore, the third mask layer 35 may also be referred to as the second mask layer, and the second mask layer 34 may also be referred to as the third mask layer.

[0091] The third mask layer 35 includes a pattern located between the second step region G2 and the third step region G3, which exposes the contact hole 204 closest to the second step region G2 and the third step region G3. Figure 30 The contact holes 204 exposed in the middle are etched the deepest, and the contact holes 204 farther away from these contact holes 204 are exposed later and etched shallower.

[0092] like Figure 31 As shown, along the x-direction, the extension depth of each group of contact holes 204 varies gradually. For example, the extension depth of the first group of contact holes 204 located in the first stepped region G1 gradually decreases from left to right. Each contact hole 204 in the first group of contact holes 204 located in the first stepped region G1 extends two layers less than the previous one from left to right. Assuming the top is the positive Z direction and the right is the positive X direction, the difference in extension depth between two adjacent contact holes 204 along the positive x-direction is -2. This value is a dimensionless quantity, with the negative sign indicating that the later contact hole 204 extends shallower. In the second group of contact holes 204 located in the second stepped region G2, the difference in extension depth between two adjacent contact holes 204 along the positive x-direction is 2. Exemplarily, within two adjacent groups of contact holes 204, the extension depth of one group of contact holes 204 gradually increases, while the extension depth of the other group of contact holes 204 gradually decreases.

[0093] Table 1

[0094]

[0095] Refer to Table 1, which shows an example of Figure 31 The number of stacked layers through which each of the forty contact holes 204 in the first stepped region G1 to the fourth stepped region G4 in the structure shown is shown. For example, in a group of ten contact holes 204 in the first stepped region G1, the first contact hole 204A located on the leftmost side of the first subarea A1 extends through ten stacked layers, and the third contact hole 204C located on the rightmost side of the first subarea A1 extends through two stacked layers.

[0096] Understandably, in this embodiment, each memory block to be formed is divided into more partitions in the y-direction, and the contact holes 204 in each partition need to extend to different depths. Thus, the difference in the number of stacking layers between two adjacent contact holes 204 in the x-direction is the same as the number of partitions.

[0097] For example, from the first stepped region G1 to the thirtieth stepped region G30, each group of contact holes 204 in each stepped region G1-G30 has ten contact holes 204, and each group of contact holes 204 extends to a set of continuous stacked layers. In this embodiment, the data in Table 2 can be used to perform the step of extending each group of contact holes 204.

[0098] Table 2

[0099]

[0100]

[0101] For example, five masks were used to extend thirty groups of contact holes 204 in five steps. Blank spaces in Table 2 indicate that the contact holes 204 in that area were not extended in this step. The number of stacked layers traversed in each extension step is an integer multiple of ten. The group of contact holes 204 corresponding to the first stepped region G1 was always covered by the mask during this step and was not etched. Therefore, this group of contact holes 204 penetrated from one to ten stacked layers.

[0102] like Figure 32 As shown, a group of contact holes 204 in the 22nd stepped region G22 extends through 291 to 300 stacked layers. For example, a group of contact holes 204 in the 15th stepped region G15 is extended by 10 stacked layers in the first step and by 80 stacked layers in the fourth step, so that the group of contact holes 204 extends through 91 to 100 stacked layers. Figure 32 The stacked structure 2 is simplified in FIG. 1 , mainly showing the height position to which the bottom end of each group of contact holes 204 extends.

[0103] Other methods can be used to extend the twenty-nine groups of contact holes 204 , but only five masks are sufficient, and the number of stacked layers through which each group of contact holes 204 is extended is an integer multiple of the number of contact holes 204 in a group.

[0104] After the three hundred contact holes formed in a memory block are extended to different heights, a conductive channel structure can be formed in the contact hole 204. The subsequent specific steps can refer to the first embodiment to form a three-dimensional memory structure.

[0105] The method for manufacturing a three-dimensional memory structure provided in this embodiment forms three hundred contact holes using only eight masks (layers) when forming a three-dimensional memory structure comprising three hundred stacked layers. This saves two masks compared to the first embodiment and reduces the number of process steps.

[0106] Reference again Figures 20 to 22 The present disclosure provides a three-dimensional memory structure including a stacked structure 2, a plurality of conductive channel structures 23, a channel structure 25, and a gate line gap spacer structure 27.

[0107] The stacked structure 2 is divided into a storage region GB and a step region SS. The conductive channel structure 23 can be provided in the step region SS, and the channel structure 25 can be provided in the storage region GB. A gate line gap spacer 27 penetrates the stacked structure 2 in the z-direction and extends in the x-direction. The gate line gap spacer 27 separates the multiple channel structures 25 into different sub-regions. The number of channel structures 25 in each sub-region can be set as needed, and the number of conductive channel structures 23 in each sub-region can be designed based on the stacked structure 2.

[0108] The stacked structure 2 includes alternating gate layers 206 / 213 and an insulating layer 202. Adjacent gate layers 206 / 213 and insulating layers 202 can be used to form a stacked layer. For example, in the x-direction, the stacked structure 2 includes a storage region GB and a step region SS, with the gate layer separated by a high dielectric layer between the first gate portion 206 of the storage region GB and the insulating layer 202. For example, the first gate portion 206 and the channel structure 25 can also be separated by a high dielectric layer. The first gate portion 206 can then be thinner than the second gate portion 213 of the gate layer in the step region SS. The second gate portion 213 is electrically connected to the first gate portion 206.

[0109] At least one conductive channel structure 23 extends from one side of the stacked structure 2 into the stacked structure 2. The conductive channel structure 23 is insulated from the gate layer it passes through and electrically connected to the gate layer it reaches. The conductive channel structures 23 can be divided into at least two groups. Multiple conductive channel structures 23 in a group are electrically connected to gate layers 206 / 213 at different heights. The gate layers 206 / 213 are controlled by the conductive channel structures 23, which in turn control the channel structure 25 to achieve storage functionality.

[0110] In some embodiments, reference Figure 32 , Figure 32The morphology of the contact holes 204 in the embodiment corresponds to the morphology of the conductive channel structures formed therein. The extension depth of each group of contact holes 204 can be used to determine the extension depth of the conductive channel structures. In the x-direction, within each group of conductive channel structures, the difference in extension depth between any two adjacent conductive channel structures along the x-direction, i.e., the first direction, is the same. This difference is a dimensionless integer representing the difference in the number of stacked layers through which the conductive channel structures extend.

[0111] For example, in two adjacent groups of conductive channel structures, the extension depth of one group of conductive channel structures increases in a stepwise manner, i.e., the number of stacked layers through which the conductive channel structures of one group extend increases in sequence. The extension depth of the other group of conductive channel structures decreases in a stepwise manner, i.e., the number of stacked layers through which the conductive channel structures of this group extend decreases in sequence.

[0112] Illustratively, each of the at least two groups of conductive channel structures includes the same number of conductive channel structures, and the stacking layers to which each group of conductive channel structures extends are stacked continuously in a stacking direction. The distance between the two stacking layers corresponding to the two groups of conductive channel structures is an integer multiple of the height of the stacking layers of the first group.

[0113] Exemplarily, an insulating wall surrounds the conductive channel structure, and the insulating wall isolates the conductive channel structure from the gate layer through which it passes, so as to ensure that the conductive channel is only electrically connected to the gate layer to which it extends.

[0114] Exemplarily, the three-dimensional storage structure further includes a first functional layer disposed on one side of the stacked structure and electrically connected to the conductive channel structure, and a second functional layer disposed on the other side of the stacked structure. The three-dimensional storage structure further includes a dummy channel structure extending through the stacked structure, wherein the smaller end of the dummy channel structure is located in the first functional layer. Exemplarily, the dummy channel structure also extends through the second functional layer. The first or second functional layer may, as needed, be provided with composite layers such as interconnect layers, dielectric layers, and bonding layers to achieve different functions.

[0115] Exemplarily, the cross-sectional shape of the conductive channel structure includes at least one of a circle, an ellipse, and a polygon.

[0116] like Figure 33As shown, the present disclosure provides a memory 61, including a three-dimensional memory structure 611 and a peripheral circuit 612. Exemplarily, the three-dimensional memory structure 611 and the peripheral circuit 612 can be arranged in parallel and electrically connected; the three-dimensional memory structure 611 and the peripheral circuit 612 can also be stacked and electrically connected by bonding. The three-dimensional memory structure 611 can be the three-dimensional memory structure mentioned above. The peripheral circuit 612 is electrically connected to the three-dimensional memory structure 611 to help the three-dimensional memory structure 611 realize the function in the circuit. The peripheral circuit 612 may, for example, include: a page buffer / sense amplifier, a column decoder / bit line (BL) driver, a row decoder / word line (WL) driver, a voltage generator, a control logic unit, a register, an interface and a data bus.

[0117] like Figure 34 As shown, the present disclosure further provides a storage system 6, comprising at least one memory 61, a controller 62, and a connector 63. The connector 63 is used to couple the storage system 6 with an external device.

[0118] Exemplarily, the controller 62 and the at least one memory 61 may be integrated into a memory card. Memory cards may include PC cards (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), universal flash storage cards (UFS), etc. Exemplarily, the controller 62 and the at least one memory 61 may be integrated into a solid-state drive (SSD).

[0119] The memory or storage system provided by the present disclosure has a good three-dimensional storage structure and a high manufacturing yield, and can provide good storage capacity stably and permanently.

[0120] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection provided by the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions in the present disclosure.

Claims

1. A method for manufacturing a three-dimensional storage structure, characterized in that include: forming a stacked structure on a substrate, wherein the stacked structure includes a plurality of stacked layers formed by stacking a first material layer and a second material layer; forming a plurality of contact holes in the stacked structure, the contact holes extending from a side of the stacked structure away from the substrate along a stacking direction of the plurality of stacked layers, the plurality of contact holes comprising at least two groups of contact holes; Extending at least one of the contact holes in each group so that each of the contact holes in the same group extends to the first material layer at a different height; Extending at least one group of the contact holes so that any contact hole in each group of the contact holes extends to a different height than any contact hole in another group of the contact holes; and forming a conductive channel structure in the contact hole; A virtual channel structure is formed that penetrates the substrate and the stacked structure. Along a direction parallel to the surface of the substrate, the size of the portion of the virtual channel structure that penetrates the substrate is larger than the size of the portion of the virtual channel structure that penetrates the stacked structure. The virtual channel structure is provided between adjacent conductive channel structures.

2. The method according to claim 1, wherein The step of forming the plurality of contact holes comprises: forming a first mask layer on the stacked structure; patterning the first mask layer to form a plurality of through-hole patterns; and The stacked structure is etched using the plurality of through hole patterns to form the plurality of contact holes.

3. The method according to claim 2, wherein: The at least two groups of contact holes are arranged along a first direction perpendicular to the stacking direction, and the method further comprises: forming a patterned second mask layer on the first mask layer; and Based on the second mask layer, an etching process and a trimming process are cyclically performed to ensure that, in at least one group of the contact holes, the extension depth differences between any two adjacent conductive channel structures along the first direction are the same.

4. The method according to claim 3, wherein: The steps of cyclically performing the etching process and the trimming process include: An etching process and a trimming process are cyclically performed according to the pattern between two adjacent groups of contact holes in the second mask layer, so that in the two adjacent groups of contact holes, the number of stacked layers extended through by one group of contact holes increases successively, and the number of stacked layers extended through by the other group of contact holes decreases successively.

5. The method according to claim 3, wherein: In a second direction perpendicular to the stacking direction and perpendicular to the first direction, the stacked structure is divided into at least a first partition and a second partition. The method further comprises: The contact hole in the first sub-area is extended so that the contact hole in the first sub-area and the contact hole in the second sub-area extend through different numbers of first material layers.

6. The method according to claim 2, wherein: Each of the at least two groups of contact holes has the same number of contact holes, and each group of contact holes extends to a set of continuous stacked layers, The step of extending at least one group of contact holes comprises: The depth of each group of contact holes is extended to an integer multiple of the height of the group of continuous stacked layers.

7. The method according to claim 1, wherein The first material layer is a gate sacrificial layer, and the second material layer is an insulating layer. The step of extending the plurality of contact holes so that each of the contact holes in the same group of contact holes extends to the first material layer at a different height position includes: Extending the contact hole to a second material layer adjacent to the target first material layer, or extending the contact hole to the target first material layer; forming an insulating wall on an inner surface of the contact hole; and exposing the first material layer at the bottom end of the contact hole; and The conductive channel structure extends from the top of the contact hole to the exposed first material layer.

8. The method according to claim 1, further comprising: A functional layer covering the conductive channel structure is formed on a side of the stacked structure away from the substrate.

9. The method according to claim 8, further comprising: A virtual channel structure penetrating the substrate and the stacked structure is formed from a side of the substrate away from the functional layer.

10. The method according to claim 8, further comprising: forming a gate line gap groove penetrating the substrate and the stacked structure from a side of the substrate away from the functional layer; as well as The first material layer is replaced by a gate layer electrically connected to the conductive channel structure through the gate line gap groove.

11. The method according to claim 10, wherein: In a first direction perpendicular to the stacking direction, the stacked structure is divided into at least a storage area and a step area. The steps of forming the gate line gap groove include: forming a first gate line gap groove segment in the storage area; and forming a second gate line gap groove segment in the step area; The step of replacing the first material layer with a gate layer electrically connected to the conductive channel structure comprises: replacing a portion of the first material layer located in the storage area with a first gate portion through the first gate line gap segment; and The portion of the first material layer located in the step area is replaced by a second gate portion electrically connected to the first gate portion and the conductive channel structure through the second gate line gap segment.

12. The method according to claim 11, wherein The step of replacing a portion of the first material layer located in the storage area with a first gate portion includes: removing a portion of the first material layer located in the storage area to obtain a first sacrificial space; forming a high dielectric layer in the first sacrificial space; and forming the first gate portion in the first sacrificial space; The step of replacing the portion of the first material layer located in the step area with the second gate portion includes: removing a portion of the first material layer located in the step area to obtain a second sacrificial space exposing the conductive channel structure; and A second gate portion electrically connected to the first gate portion and the conductive channel structure is formed in the second sacrificial space.

13. The method according to any one of claims 1 to 12, wherein The cross-sectional shape of the contact hole includes at least one of a circle, an ellipse, and a polygon.

14. A three-dimensional storage structure, characterized in that include: A stacked structure comprising a plurality of stacked layers formed by stacking gate layers and insulating layers; a plurality of conductive channel structures, wherein in the stacking direction of the stacked structure, the conductive channel structures extend from one side of the stacked structure into the stacked structure, and at least one of the conductive channel structures penetrates at least one of the gate layers, and the plurality of conductive channel structures are electrically connected to the gate layers at different heights; A first functional layer is provided on one side of the stacked structure and is electrically connected to the conductive channel structure; a second functional layer, disposed on a side of the laminated structure away from the first functional layer; A virtual channel structure passes through the second functional layer and the stacked structure. Along a direction parallel to the surface of the second functional layer, the size of the portion of the virtual channel structure passing through the second functional layer is larger than the size of the portion of the virtual channel structure passing through the stacked structure. The virtual channel structure is provided between adjacent conductive channel structures.

15. The three-dimensional storage structure according to claim 14, wherein: The stacked structure includes at least two groups of conductive channel structures along a first direction perpendicular to the stacking direction, In at least one group of the conductive channel structures, the difference in extension depth between any two adjacent conductive channel structures along the first direction is the same.

16. The three-dimensional storage structure according to claim 15, wherein: In two adjacent groups of the conductive channel structures, along the first direction, the number of stacked layers through which the conductive channel structures of one group extend increases successively, and the number of stacked layers through which the conductive channel structures of the other group extend decreases successively.

17. The three-dimensional storage structure according to claim 14, wherein: Each of the at least two groups of the conductive channel structures includes the same number of the conductive channel structures, and the stacking layers of the group to which each group of the conductive channel structures extends are arranged continuously along the stacking direction. Wherein, the distance between two groups of stacked layers corresponding to any two groups of the conductive channel structures is an integer multiple of the height of one group of the stacked layers.

18. The three-dimensional storage structure according to claim 14, wherein: An insulating wall surrounds the conductive channel structure, and the insulating wall isolates the conductive channel structure from the gate layer it passes through.

19. The three-dimensional storage structure according to claim 14, wherein: In a first direction perpendicular to the stacking direction, the stacked structure is divided into a storage area and a step area. The gate layer is provided with a high dielectric layer between the first gate portion of the storage region and the insulating layer; and The second gate portion of the gate layer in the step region is electrically connected to the first gate portion and the conductive channel structure.

20. The three-dimensional storage structure according to any one of claims 14 to 19, wherein: The cross-sectional shape of the conductive channel structure includes at least one of a circle, an ellipse, and a polygon.

21. A memory, characterized in that include: The three-dimensional storage structure according to any one of claims 14 to 20; as well as The peripheral circuit is electrically connected to the three-dimensional storage structure.

22. A storage system, characterized in that include: The memory as claimed in claim 21; as well as A controller is electrically connected to the memory and is used to control the memory.

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