Three-dimensional memory device and method of making the same
By arranging an interconnection layer on the first semiconductor structure, it is avoided to arrange a wiring structure on the second semiconductor structure, thereby solving the adverse effect of wiring on performance, simplifying the preparation process of the three-dimensional storage device and reducing costs.
Patent Information
- Application Number
- CN202111683386.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-31
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2041-12-31
AI Technical Summary
In conventional three-dimensional memory devices, the wiring structure on the second semiconductor structure can easily have an adverse effect on the performance of the device.
An interconnection layer is arranged on the first semiconductor structure, a wiring structure of a three-dimensional memory device is arranged on the first semiconductor structure, and no wiring structure is arranged on the second semiconductor structure, and the first and second semiconductor structures are connected by interface bonding.
The adverse effect of setting a wiring structure on the second semiconductor structure on its performance is avoided, the preparation process is simplified, time and cost are saved, and interference between the circuit and the wiring structure on the peripheral circuit chip is reduced.
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Figure CN114497069B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a three-dimensional storage device and a preparation method thereof. Background Art
[0002] Conventional 3D memory device fabrication processes typically involve integrating the wiring on the first and second semiconductor structures to a certain degree before connecting them together. However, since both the first and second semiconductor structures have wiring structures, the wiring on the second semiconductor structure can adversely affect the performance of the second semiconductor. Summary of the Invention
[0003] The object of the present invention is to provide a three-dimensional storage device and a manufacturing method thereof to solve the above-mentioned technical problems.
[0004] The present invention provides a three-dimensional storage device, comprising: a first semiconductor structure and a second semiconductor structure; the first semiconductor structure comprises a first substrate, an interconnection layer and a first bonding layer provided on the first substrate, and a first bonding contact is formed in the first bonding layer; the second semiconductor structure comprises a second substrate and a second bonding layer provided on the second substrate, and a second bonding contact is formed in the second bonding layer; the first bonding layer and the second bonding layer are bonded to each other at an interface, so that the first semiconductor structure and the second semiconductor structure are connected.
[0005] The interconnection layer includes a first interconnection layer and a second interconnection layer.
[0006] The first semiconductor structure further includes a storage structure array formed between the first substrate and the interconnection layer; the second semiconductor structure further includes a peripheral circuit layer formed between the second substrate and the second bonding layer.
[0007] The storage structure array includes: a stacking structure and a channel structure. The stacking structure is located on the first substrate and includes alternatingly stacked conductive layers and interlayer insulating layers. The channel structure extends through the stacking structure to the first substrate.
[0008] The peripheral circuit layer includes a dielectric layer and peripheral devices, the peripheral devices are formed on the second substrate, the dielectric layer is formed on the second substrate and covers the peripheral devices, and the peripheral devices are connected to the second bonding contacts.
[0009] A first interconnect structure is formed in the first interconnect layer; a second interconnect structure is formed in the second interconnect layer; the channel structure, the first interconnect structure, the second interconnect structure, the first bonding contact, the second bonding contact and the peripheral device are connected in sequence.
[0010] The first semiconductor structure further includes: an insulating layer covering the first substrate and the stacked structure; a first contact extending through the insulating layer to the first substrate; and a second contact passing through the insulating layer and connected to the conductive layer of the stacked structure.
[0011] The present invention provides a method for preparing a three-dimensional storage device, comprising: providing a first semiconductor structure and a second semiconductor structure; wherein the first semiconductor structure comprises a first substrate, an interconnection layer and a first bonding layer provided on the first substrate, and a first bonding contact is formed in the first bonding layer; wherein the second semiconductor structure comprises a second substrate and a second bonding layer provided on the second substrate, and a second bonding contact is formed in the second bonding layer; and interfacially bonding the first bonding layer and the second bonding layer to connect the first semiconductor structure and the second semiconductor structure.
[0012] The interconnection layer includes a first interconnection layer and a second interconnection layer.
[0013] The first semiconductor structure further includes a storage structure array formed between the first substrate and the interconnection layer; the second semiconductor structure further includes a peripheral circuit layer formed between the second substrate and the second bonding layer.
[0014] Among them, the method for forming a storage structure array includes: forming an initial stacking structure on the first substrate, wherein the initial stacking structure includes alternatingly stacked gate sacrificial layers and interlayer insulating layers; forming a channel structure on the initial stacking structure, wherein the channel structure extends through the initial stacking structure to the first substrate; replacing the gate sacrificial layer with a conductive layer so that the initial stacking structure is converted into a stacking structure.
[0015] The method for forming the peripheral circuit layer includes: forming a peripheral device on the second substrate; and forming a dielectric layer on the second substrate, wherein the dielectric layer covers the peripheral device and enables the peripheral device to be connected to the second bonding contact.
[0016] The method for forming the interconnection layer includes: forming the first interconnection layer on the storage structure array, wherein a first interconnection structure is formed in the first interconnection layer, and the first interconnection structure is connected to the channel structure; forming the second interconnection layer on the first interconnection layer, wherein a second interconnection structure is formed in the second interconnection layer, the second interconnection structure is connected to the first interconnection structure, and the second interconnection structure is connected to the first bonding contact.
[0017] Among them, the method of forming the first semiconductor structure also includes: forming an insulating layer covering the first substrate and the stacking structure; forming a first contact extending to the first substrate on the insulating layer; and forming a second contact extending to the conductive layer of the stacking structure on the insulating layer.
[0018] Before performing interface bonding on the first bonding layer and the second bonding layer, the preparation method further includes: planarizing the first bonding layer and planarizing the second bonding layer.
[0019] To summarize, in the present application, by setting the interconnection layer on the first semiconductor structure, the wiring structure of the three-dimensional storage device is set on the first semiconductor structure, and there is no need to set the wiring structure on the second semiconductor structure, which avoids the impact of setting the wiring structure on the second semiconductor structure on the second semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 1 is a schematic structural diagram of a first semiconductor structure.
[0022] Figure 2 2 is a schematic structural diagram of a second semiconductor structure.
[0023] Figure 3 It is a schematic structural diagram of the three-dimensional storage device of the present invention.
[0024] Figure 4 It is a schematic flow chart of a method for preparing a three-dimensional storage device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0026] The present invention provides a three-dimensional memory device, including a first semiconductor structure 10 and a second semiconductor structure 20 .
[0027] See also Figure 1 The first semiconductor structure 10 includes a first substrate 101 , an interconnection layer 102 and a first bonding layer 103 disposed on the first substrate 101 , and a first bonding contact 104 is formed in the first bonding layer 103 .
[0028] See also Figure 2 The second semiconductor structure 20 includes a second substrate 201 and a second bonding layer 203 disposed on the second substrate 201. Second bonding contacts 204 are formed in the second bonding layer 203. It is understood that the wiring structure for the three-dimensional memory device provided in the interconnect layer 102 is specifically the wiring structure for the first semiconductor structure 10 and the wiring structure for the second semiconductor structure 20.
[0029] See also Figure 3 The first bonding layer 103 is interface-bonded to the second bonding layer 203, so that the first semiconductor structure 10 is connected to the second semiconductor structure 20. The interface bonding connection here is a hybrid bonding connection or other bonding connection.
[0030] It can be understood that the material of the first substrate 101 and the second substrate 201 can be, for example, single crystal silicon, and of course can also be other silicon-containing materials, such as silicon on insulator (SOI), SiGe, Si:C, etc., and various p-type / n-type deep or shallow potential wells required by the device can be formed in the first substrate 101 and the second substrate 201 through processes such as ion implantation.
[0031] In the present application, by setting the interconnection layer 102 on the first semiconductor structure 10, the wiring structure of the three-dimensional storage device is set on the first semiconductor structure 10, and there is no need to set the wiring structure on the second semiconductor structure 20, which avoids the impact of setting the wiring structure on the second semiconductor structure 20 on the second semiconductor structure 20.
[0032] In a specific embodiment, the interconnect layer 102 includes a first interconnect layer 102a and a second interconnect layer 102b. The first interconnect layer 102a and the second interconnect layer 102b are connected. The first interconnect layer 102a and the second interconnect layer 102b can be the same layer structure. It is understood that the first interconnect layer 102a is used to set the wiring structure of the first semiconductor structure 10, and the second interconnect layer 102b is used to set the wiring structure of the second semiconductor structure 20.
[0033] In the present application, the wiring structure of the second semiconductor structure 20 is disposed in the second interconnect layer 102 b of the first semiconductor structure 10 , thereby avoiding the influence of the wiring structure disposed on the second semiconductor structure 20 on the second semiconductor structure 20 .
[0034] In a specific embodiment, the first semiconductor structure 10 further includes a memory structure array 105 formed between the first substrate 101 and the interconnect layer 102; the second semiconductor structure 20 further includes a peripheral circuit layer 205 formed between the second substrate 201 and the second bonding layer 203. It is understood that the first semiconductor structure 10 of the present application may be a memory array wafer. The second semiconductor structure 20 may be a peripheral circuit wafer. The memory array wafer is connected to the peripheral circuit wafer.
[0035] In the present application, the interconnection layer 102 is set on the storage array chip, that is, the wiring structure is set on the storage array chip, and there is no need to set the wiring structure on the peripheral circuit chip. This avoids the influence of the wiring structure on the peripheral circuit chip, and makes the preparation process of the three-dimensional storage device simple, saves time, and reduces manpower and material costs.
[0036] In a specific embodiment, the storage structure array 105 includes: a stacked structure 30 and a channel structure 40, the stacked structure 30 is located on the first substrate 101, and the stacked structure 30 includes alternating conductive layers 301 and interlayer insulating layers 302; the channel structure 40 extends through the stacked structure 30 to the first substrate 101. It is understandable that the stacked structure 30 can be formed by converting the initial stacked structure. The initial stacked structure is a stack of interlayer insulating layers 302 and gate sacrificial layers, which can be alternately deposited on the first substrate 101 in sequence by chemical vapor deposition (CV), atomic layer deposition (AL) or other suitable deposition methods. The insulating layer is composed of, for example, silicon oxide, and the gate sacrificial layer is composed of, for example, silicon nitride, which will be replaced by metal in subsequent processes and serve as the conductive layer 301. It is understandable that after the gate sacrificial layer is replaced by the conductive layer 301, the initial stacked structure is converted into the stacked structure 30. The interlayer insulating layer 302 can also be silicon oxynitride, etc., and the gate sacrificial layer can also be amorphous silicon, polysilicon, aluminum oxide, etc. A channel hole can be formed on the stacked structure 30, and a channel structure 40 can be formed in the channel hole. The channel structure 40 includes a charge storage layer and a channel layer. The charge storage layer includes a blocking insulating layer, a charge capture layer, and a tunneling insulating layer along the sidewall of the channel hole to the center of the hole. Exemplary materials for the blocking insulating layer and the tunneling insulating layer are silicon oxide, and an exemplary material for the charge capture layer is silicon nitride. The charge storage layer forms a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO). An exemplary material for the channel layer is silicon (Si). Other materials can be selected for the blocking insulating layer, the charge capture layer, and the tunneling insulating layer, which are not limited here.
[0037] In a specific embodiment, the peripheral circuit layer 205 includes a dielectric layer 50 and a peripheral device 60. The peripheral device 60 is formed on the second substrate 201. The dielectric layer 50 is formed on the second substrate 201 and covers the peripheral device 60. The peripheral device 60 is connected to the second bonding contact 204. Optionally, the peripheral device 60 includes a transistor, and the transistor includes a source, a drain, and a gate. The source and the drain are respectively located on both sides of the gate, and the source and the drain are both located in the first substrate 101, and the gate is located in the dielectric layer 50. The dielectric layer 50 also has a connecting contact 70. For example, the source, the drain, and the gate can be connected to the second bonding contact 204 through the connecting contact 70. The connecting contact 70 is also connected to the source line in the second substrate 201. It can be understood that the peripheral device 60 also includes a page buffer, a logic circuit, a reference voltage, a regulator, a switch, an input / output interface I / O bar, etc. This application does not specifically limit the specific circuit structure contained in the peripheral device 60.
[0038] In the present application, since the interconnect layer 102 is disposed on the first semiconductor structure 10, that is, the interconnect layer 102 is disposed on the memory array wafer, and the interconnect layer 102 is not disposed on the peripheral circuit wafer, the wiring of the three-dimensional memory device is fully integrated within the memory array wafer. This reduces the process of forming the interconnect layer 102 on the peripheral circuit wafer and eliminates the need for polishing the interconnect layer 102, simplifying the structure of the peripheral circuit wafer and simplifying the process of forming the peripheral circuit wafer. Furthermore, since there is no wiring structure on the peripheral circuit wafer, the mutual interference between the circuit on the peripheral circuit wafer and the wiring structure is reduced, and the interference between the peripheral device 60 and the wiring structure is also reduced. In other words, after the peripheral device 60 is formed on the peripheral circuit wafer, there is no need to form a wiring structure on the peripheral circuit wafer. This avoids the adverse effects of the wiring structure on the peripheral device 60 when the wiring structure is subsequently formed on the peripheral circuit wafer after the peripheral device 60 is formed on the peripheral circuit wafer. In the present application, the peripheral device 60 is connected to the memory array structure by providing a second bonding contact 204 connected to the peripheral device 60.
[0039] In a specific embodiment, a first interconnect structure 80 is formed in the first interconnect layer 102a; a second interconnect structure 90 is formed in the second interconnect layer 102b. The channel structure 40, the first interconnect structure 80, the second interconnect structure 90, the first bonding contact 104, the second bonding contact 204, and the peripheral device 60 are sequentially connected. It can be understood that the first interconnect structure 80 is a wiring structure connecting the first semiconductor structure 10, and the second interconnect structure 90 is a wiring structure connecting the second semiconductor structure 20. For example, the first interconnect structure 80 is a wiring structure connecting a memory array chip, and the second interconnect structure 90 is a wiring structure connecting a peripheral circuit chip.
[0040] In the present application, the connection between the memory array chip and the peripheral circuit chip is achieved by sequentially connecting the channel structure 40, the first interconnection structure 80, the second interconnection structure 90, the first bonding contact 104, the second bonding contact 204 and the peripheral device 60.
[0041] In a specific embodiment, the first semiconductor structure 10 further includes:
[0042] The insulating layer 130 covers the first substrate 101 and the stacked structure 30 . Optionally, the insulating layer is made of silicon oxide.
[0043] The first contact 110 extends through the insulating layer 130 to the first substrate 101; the material of the first contact 110 can be tungsten (W). In the present application, by setting the first contact 110, the first contact 110 can be connected to the lead-out structure (not shown) of the three-dimensional storage device, so that the internal structure of the three-dimensional storage device can be connected to an external device through the first contact 110. The second contact 120 passes through the insulating layer 130 and is connected to the conductive layer 301 of the stacked structure 30. The material of the second contact 120 can be tungsten (W). It can be understood that the conductive layer 301 is formed in a stepped shape, and there are multiple second contacts 120, and multiple second contacts 120 are connected to the stepped conductive layer 301. In the present application, by setting the second contact 120 to be connected to the conductive layer 301, the conductive layer 301 can be connected to other structures of the three-dimensional storage device through the second contact 120.
[0044] In the present application, the connection between the memory array chip and other structures is achieved by providing the first contact 110 and the second contact 120 .
[0045] Figure 3 In the embodiment, a gate trench is formed between the two channel structures 40 , and an insulating layer 130 is formed in the gate trench.
[0046] See also Figure 4 In addition to the aforementioned three-dimensional storage device, embodiments of the present invention also provide a method for fabricating a three-dimensional memory device. Both the three-dimensional storage device and the method for fabricating the three-dimensional storage device achieve the advantages of the present invention and can be used together or separately, without particular limitation in the present invention. In a specific embodiment, the three-dimensional storage device is fabricated using the aforementioned method for fabricating the three-dimensional storage device.
[0047] See also Figure 4 , Figure 4 The present invention provides a method for fabricating a three-dimensional memory device. In this application, by disposing the interconnect layer 102 on the first semiconductor structure 10, the wiring structure of the three-dimensional memory device is disposed on the first semiconductor structure 10, eliminating the need to dispose the wiring structure on the second semiconductor structure 20. This avoids the impact of disposing the wiring structure on the second semiconductor structure 20 on the second semiconductor structure 20.
[0048] Preparation method of three-dimensional storage device Figure 4 As shown in Figure 4 As shown, the method can be roughly summarized as follows: providing a first semiconductor structure 10 and a second semiconductor structure 20 (S1), and performing interface bonding between the first bonding layer 103 and the second bonding layer 203 (S2).
[0049] See also Figure 4, the method first performs the operations of S1-S2:
[0050] S1. Provide a first semiconductor structure 10 and a second semiconductor structure 20. The first semiconductor structure 10 includes a first substrate 101, an interconnect layer 102 and a first bonding layer 103 disposed on the first substrate 101, and a first bonding contact 104 is formed in the first bonding layer 103. The second semiconductor structure 20 includes a second substrate 201 and a second bonding layer 203 disposed on the second substrate 201, and a second bonding contact 204 is formed in the second bonding layer 203.
[0051] S2, interface bonding the first bonding layer 103 and the second bonding layer 203 to connect the first semiconductor structure 10 and the second semiconductor structure 20. It is understandable that the first bonding layer 103 and the second bonding layer 203 are bonded together by hybrid bonding.
[0052] In the present application, by setting the interconnection layer 102 on the first semiconductor structure 10, the wiring structure of the three-dimensional storage device is set on the first semiconductor structure 10, and there is no need to set the wiring structure on the second semiconductor structure 20, which avoids the impact of setting the wiring structure on the second semiconductor structure 20 on the second semiconductor structure 20.
[0053] In a specific embodiment, the interconnect layer 102 includes a first interconnect layer 102a and a second interconnect layer 102b. The first interconnect layer 102a and the second interconnect layer 102b are connected. The first interconnect layer 102a and the second interconnect layer 102b can be the same layer structure. It is understood that the first interconnect layer 102a is used to set the wiring structure of the first semiconductor structure 10, and the second interconnect layer 102b is used to set the wiring structure of the second semiconductor structure 20.
[0054] In the present application, the wiring structure of the second semiconductor structure 20 is disposed in the second interconnect layer 102 b on the first semiconductor structure 10 , thereby avoiding the influence of the wiring structure disposed on the second semiconductor structure 20 on the second semiconductor structure 20 .
[0055] In a specific embodiment, the first semiconductor structure 10 further includes a memory structure array 105 formed between the first substrate 101 and the interconnect layer 102; the second semiconductor structure 20 further includes a peripheral circuit layer 205 formed between the second substrate 201 and the second bonding layer 203. It is understood that the first semiconductor structure 10 of the present application may be a memory array wafer. The second semiconductor structure 20 may be a peripheral circuit wafer. The memory array wafer is connected to the peripheral circuit wafer.
[0056] In the present application, the interconnection layer 102 is set on the storage array chip, that is, the wiring structure is set on the storage array chip, and there is no need to set the wiring structure on the peripheral circuit chip. This avoids the influence of the wiring structure on the peripheral circuit chip, and makes the preparation process of the three-dimensional storage device simple, saves time, and reduces manpower and material costs.
[0057] In a specific embodiment, a method of forming the memory structure array 105 includes:
[0058] forming an initial stacking structure on the first substrate 101, wherein the initial stacking structure includes alternately stacked gate sacrificial layers and interlayer insulating layers 302;
[0059] A channel structure 40 is formed on the initial stacked structure, wherein the channel structure 40 extends through the initial stacked structure to the first substrate 101. Specifically, a channel hole can be formed on the initial stacked structure 30, and the channel structure 40 is formed within the channel hole. The channel structure 40 includes a charge storage layer and a channel layer. The charge storage layer includes a blocking insulating layer, a charge trapping layer, and a tunneling insulating layer extending along the sidewalls of the channel hole toward the center of the hole.
[0060] The gate sacrificial layer is replaced with the conductive layer 301 , so that the initial stacking structure is converted into the stacking structure 30 .
[0061] It is understood that the gate sacrificial layer is made of, for example, silicon nitride, and may also be amorphous silicon, polysilicon, aluminum oxide, etc. After the gate sacrificial layer is replaced by the conductive layer 301 , the initial stacking structure is converted into the stacking structure 30 .
[0062] In a specific embodiment, the method for forming the peripheral circuit layer 205 includes:
[0063] forming a peripheral device 60 on the second substrate 201;
[0064] A dielectric layer 50 is formed on the second substrate 201 , wherein the dielectric layer 50 covers the peripheral device 60 and enables the peripheral device 60 to be connected to the second bonding contact 204 .
[0065] In the present application, the peripheral device 60 is connected to the memory array structure by providing the second bonding contact 204 to connect to the peripheral device 60 .
[0066] In a specific embodiment, the method for forming the interconnect layer 102 includes:
[0067] A first interconnect layer 102 a is formed on the memory structure array 105 , wherein a first interconnect structure 80 is formed in the first interconnect layer 102 a , and the first interconnect structure 80 is connected to the channel structure 40 ;
[0068] A second interconnect layer 102 b is formed on the first interconnect layer 102 a , wherein a second interconnect structure 90 is formed in the second interconnect layer 102 b . The second interconnect structure 90 is connected to the first interconnect structure 80 , and the second interconnect structure 90 is connected to the first bonding contact 104 .
[0069] In the present application, the connection between the memory array chip and the peripheral circuit chip is achieved by sequentially connecting the channel structure 40 , the first interconnection structure 80 , the second interconnection structure 90 , the first bonding contact 104 , the second bonding contact 204 and the peripheral device 60 .
[0070] In a specific embodiment, the method of forming the first semiconductor structure 10 further includes:
[0071] forming an insulating layer 130 covering the first substrate 101 and the stacked structure 30;
[0072] forming a first contact 110 on the insulating layer 130 and extending to the first substrate 101;
[0073] A second contact 120 is formed on the insulating layer 130 and extends to the conductive layer 301 of the stack structure 30 .
[0074] In the present application, the connection between the memory array chip and other structures is achieved by providing the first contact 110 and the second contact 120 .
[0075] In a specific embodiment, before interfacial bonding the first bonding layer and the second bonding layer, the preparation method further includes:
[0076] Planarizing the first bonding layer 103 and planarizing the second bonding layer 203. It is understood that the planarizing methods of the first bonding layer 103 and the second bonding layer 203 may be chemical mechanical polishing (CMP).
[0077] In the present application, by planarizing the first bonding layer 103 and the second bonding layer 203, the first bonding layer 103 and the second bonding layer 203 can be evenly connected, the first bonding layer 103 and the second bonding layer 203 are more firmly connected, and the first semiconductor structure 10 and the second semiconductor structure 20 are more firmly connected. For example, the memory array chip and the peripheral circuit chip can be more firmly connected.
[0078] The above disclosure is only a preferred embodiment of the present invention, and it is certainly not intended to limit the scope of the present invention. A person skilled in the art can understand that all or part of the processes of the above embodiment and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.
Claims
1. A three-dimensional storage device, characterized in that: include: a first semiconductor structure and a second semiconductor structure; The first semiconductor structure includes a first substrate, an interconnection layer and a first bonding layer provided on the first substrate, the interconnection layer includes a first interconnection layer and a second interconnection layer, the first interconnection layer includes a wiring structure of the first semiconductor structure, the second interconnection layer includes a wiring structure of the second semiconductor structure, and a first bonding contact is formed in the first bonding layer; The second semiconductor structure includes a second substrate and a second bonding layer provided on the second substrate, wherein a second bonding contact is formed in the second bonding layer; The first bonding layer is bonded to the second bonding layer at an interface, so that the first semiconductor structure is connected to the second semiconductor structure.
2. The three-dimensional storage device according to claim 1, wherein: The first semiconductor structure further includes a storage structure array formed between the first substrate and the interconnection layer; the second semiconductor structure further includes a peripheral circuit layer formed between the second substrate and the second bonding layer.
3. The three-dimensional storage device according to claim 2, wherein: The storage structure array includes: a stacking structure and a channel structure. The stacking structure is located on the first substrate and includes alternately stacked conductive layers and interlayer insulating layers. The channel structure extends through the stacking structure to the first substrate.
4. The three-dimensional storage device according to claim 3, wherein: The peripheral circuit layer includes a dielectric layer and peripheral devices. The peripheral devices are formed on the second substrate. The dielectric layer is formed on the second substrate and covers the peripheral devices. The peripheral devices are connected to the second bonding contacts.
5. The three-dimensional storage device according to claim 4, wherein: The wiring structure of the first semiconductor structure includes a first interconnect structure; the wiring structure of the second semiconductor structure includes a second interconnect structure, and the channel structure, the first interconnect structure, the second interconnect structure, the first bonding contact, the second bonding contact and the peripheral device are connected in sequence.
6. The three-dimensional storage device according to claim 3, wherein: The first semiconductor structure further includes: an insulating layer covering the first substrate and the stacked structure; a first contact extending through the insulating layer to the first substrate; The second contact passes through the insulating layer and is connected to the conductive layer of the stacked structure.
7. A method for preparing a three-dimensional storage device, characterized in that: include: A first semiconductor structure and a second semiconductor structure are provided; wherein the first semiconductor structure includes a first substrate, an interconnection layer and a first bonding layer provided on the first substrate, the interconnection layer includes a first interconnection layer and a second interconnection layer, the first interconnection layer includes a wiring structure of the first semiconductor structure, the second interconnection layer includes a wiring structure of the second semiconductor structure, and a first bonding contact is formed in the first bonding layer; wherein the second semiconductor structure includes a second substrate and a second bonding layer provided on the second substrate, and a second bonding contact is formed in the second bonding layer; The first bonding layer and the second bonding layer are interface-bonded to connect the first semiconductor structure and the second semiconductor structure.
8. The preparation method according to claim 7, characterized in that The first semiconductor structure further includes a storage structure array formed between the first substrate and the interconnection layer; the second semiconductor structure further includes a peripheral circuit layer formed between the second substrate and the second bonding layer.
9. The preparation method according to claim 8, characterized in that The method of forming a storage structure array includes: forming an initial stacking structure on the first substrate, wherein the initial stacking structure comprises alternately stacked gate sacrificial layers and interlayer insulating layers; forming a channel structure on the initial stacked structure, wherein the channel structure extends through the initial stacked structure to the first substrate; The gate sacrificial layer is replaced with a conductive layer, so that the initial stacking structure is converted into a stacking structure.
10. The preparation method according to claim 9, characterized in that The method for forming the peripheral circuit layer includes: forming peripheral devices on the second substrate; A dielectric layer is formed on the second substrate, wherein the dielectric layer covers the peripheral device and enables the peripheral device to be connected to the second bonding contact.
11. The preparation method according to claim 10, characterized in that: The method for forming the interconnection layer includes: forming the first interconnect layer on the memory structure array, wherein the wiring structure of the first semiconductor structure includes a first interconnect structure connected to the channel structure; A second interconnect layer is formed on the first interconnect layer, wherein the wiring structure of the second semiconductor structure includes a second interconnect structure connected to the first interconnect structure, and the second interconnect structure is connected to the first bonding contact.
12. The preparation method according to claim 9, characterized in that The method of forming the first semiconductor structure further includes: forming an insulating layer covering the first substrate and the stacked structure; forming a first contact on the insulating layer extending to the first substrate; A second contact is formed on the insulating layer and extends to the conductive layer of the stacked structure.
13. The preparation method according to claim 7, characterized in that Before performing interface bonding on the first bonding layer and the second bonding layer, the preparation method further includes: The first bonding layer is planarized and the second bonding layer is planarized.
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