Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first region; forming a first gate on the first region; forming two or more second gate structures on the first gate, the second gate structures comprising a second gate, the second gate and the first gate being made of different materials, the second gate structure being located on top of the first gate and being used to protect the first gate, and being less likely to produce "depression" defects during mechanical chemical polishing, thereby achieving the purpose of improving the integrity of the first gate structure and obtaining a gate structure with more optimized performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, integrated circuit chips are moving towards higher device density and higher integration levels to achieve faster computing speeds, larger data storage capacities, and more functionality. Typically, a complete integrated circuit comprises a first-region device and a second-region device integrated on the same semiconductor substrate. There is at least one first-region device, which is at least one input / output device. The second-region device, formed within the second region, implements the primary functions of the integrated circuit. The input / output device provides corresponding input signals to the second-region device or outputs corresponding signals from the second-region device. The operating voltage of the input / output device is higher than that of the second-region device. Due to the different operating voltages of the first-region and second-region devices, the corresponding device structures also differ.

[0003] As integrated circuit technology continues to develop below the nanometer level, incompatibility issues may arise between integrated circuit design requirements and existing device processes. For example, the performance of existing devices cannot meet circuit design requirements. Therefore, new advanced processes need to be continuously introduced to continuously improve device performance. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

[0005] To solve the above technical problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a first region; a first gate located on the first region; two or more second gate structures located on part of the first gate, the second gate structure including a second gate, and the second gate and the first gate are made of different materials.

[0006] Optionally, the resistivity of the material of the second gate is lower than the resistivity of the material of the first gate.

[0007] Optionally, the material of the second gate includes metal; the metal includes copper, aluminum or tungsten; and the material of the first gate includes polysilicon.

[0008] Optionally, the first gate has first doping ions therein; the first doping ions are N-type ions or P-type ions.

[0009] Optionally, it further includes: a modified layer located on the surface of the first gate, and the modified layer is located between the second gate structures.

[0010] Optionally, the material of the modified layer includes metal silicide.

[0011] Optionally, the method further includes: first source and drain regions located in the first region on both sides of the first gate; and second doping ions are present in the first source and drain regions.

[0012] Optionally, the substrate further includes a second region.

[0013] Optionally, it further includes: a third gate structure located on the second region; the third gate structure includes a third gate, and the material of the third gate includes metal.

[0014] Optionally, the third gate structure further includes: a third gate dielectric layer located between the third gate and the second region.

[0015] Optionally, the material of the third gate dielectric layer includes a high-K dielectric material.

[0016] Optionally, the third gate structure further includes: an oxide layer located between the second region and the third gate dielectric layer; and a metal compound layer located between the third gate dielectric layer and the third gate.

[0017] Optionally, the method further includes: second source and drain regions located in the second region on both sides of the third gate structure; and third doping ions are present in the second source and drain regions.

[0018] Optionally, a dimension of the second gate structure along a gate width direction is less than or equal to 2 microns.

[0019] Optionally, the method further includes: a first gate dielectric layer located between the first gate and the first region.

[0020] Optionally, the material of the first gate dielectric layer includes silicon oxide.

[0021] Optionally, the method further includes: a second gate dielectric layer located between the second gate and the first gate.

[0022] Optionally, the material of the second gate dielectric layer includes a high-K dielectric material.

[0023] Optionally, the method further includes: an oxide layer located between the first gate and the second gate dielectric layer; and a metal compound layer located between the second gate dielectric layer and the second gate.

[0024] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region; forming a first gate on the first region; forming two or more second gate structures on the first gate, the second gate structure including a second gate, and the material of the second gate is different from that of the first gate.

[0025] Optionally, the material of the first gate includes polysilicon.

[0026] Optionally, the method further includes: forming a first gate dielectric layer between the first gate and the first region.

[0027] Optionally, the material of the first gate dielectric layer includes silicon oxide.

[0028] Optionally, the method for forming the first gate includes: forming a first gate layer on the first region; and patterning the first gate layer to form the first gate.

[0029] Optionally, the method for forming the first gate further includes: doping first doping ions in the first gate layer; the first doping ions are N-type or P-type.

[0030] Optionally, the material of the second gate includes metal.

[0031] Optionally, the second gate structure further includes a second gate dielectric layer located between the second gate and the first gate.

[0032] Optionally, the material of the second gate dielectric layer includes a high-K dielectric material.

[0033] Optionally, the second gate structure further includes: an oxide layer located between the first gate and the second gate dielectric layer; and a metal compound layer located between the second gate dielectric layer and the second gate.

[0034] Optionally, the method for forming the second gate structure includes: forming two or more first dummy gate structures on the first gate, the first dummy gate structure including a first dummy gate; and replacing the first dummy gate with the second gate.

[0035] Optionally, the method for forming the second gate structure also includes: forming an interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer is also located on the sidewall and surface of the first gate, and the sidewall of the first dummy gate, and the interlayer dielectric layer exposes the first dummy gate; etching and removing the first dummy gate, forming a plurality of first trenches in the interlayer dielectric layer; and filling the first trenches to form a second gate.

[0036] Optionally, a first dummy gate structure is formed at the same time as the first gate is formed; the method for forming the first gate and the first dummy gate structure includes: forming a first gate layer on the first region; etching part of the first gate layer to form the first gate and two or more first dummy gates on the first gate.

[0037] Optionally, the method for forming the first dummy gate structure includes: forming a first gate layer on the first region, and forming a first dummy gate layer on the surface of the first gate layer; patterning the first dummy gate layer and the first gate layer to form a first gate and two or more of the first dummy gates on the first gate.

[0038] Optionally, the first dummy gate structure also includes: a first hard mask layer located on the first dummy gate; the method for forming the first dummy gate structure and the first gate also includes: forming the first hard mask layer on the first dummy gate layer; using the first hard mask layer as a mask, etching the first dummy gate layer until the surface of the first gate layer is exposed to form the first dummy gate; using the first hard mask layer as a mask, etching the first gate layer exposed by the first dummy gate layer until the surface of the first region is exposed to form the first gate.

[0039] Optionally, the method for forming the first hard mask layer includes: forming an initial first hard mask layer on the surface of the first dummy gate layer, and etching the initial first hard mask layer until a portion of the surface of the first dummy gate layer is exposed.

[0040] Optionally, after forming the first gate and before forming the second gate structure, the method further includes: forming first source and drain regions in the first region on both sides of the first gate, wherein the first source and drain regions have second doping ions.

[0041] Optionally, after forming the first dummy gate structure and before forming the second gate structure, the method further includes: forming a modified layer on the surface of the first gate, wherein the modified layer is located between the first dummy gate structures.

[0042] Optionally, the material of the modified layer includes metal silicide; and the process for forming the modified layer includes a self-aligned metal silicide process.

[0043] Optionally, the substrate further includes a second region; the formation method further includes: forming a third gate structure on a portion of the second region, the third gate structure including a third gate, and the material of the third gate is the same as that of the second gate.

[0044] Optionally, the method for forming the third gate structure includes: forming a second trench in the interlayer dielectric layer on the second region; and forming a third gate in the second trench.

[0045] Optionally, the method for forming the second trench includes: before forming the interlayer dielectric layer, forming a second dummy gate structure on the second region, the second dummy gate structure including a second dummy gate; the interlayer dielectric layer is also located on the sidewall of the second dummy gate structure and exposes the top surface of the second dummy gate structure; removing the second dummy gate and forming the second trench in the interlayer dielectric layer.

[0046] Optionally, while forming the second gate, a third gate is formed in the second trench; the method for forming the second gate and the third gate includes: forming a third gate material layer on the surface of the interlayer dielectric layer, in the first trench and in the second trench; flattening the third gate material layer until the surface of the interlayer dielectric layer is exposed, thereby forming the second gate and the third gate.

[0047] Optionally, the process of planarizing the third gate material layer is a mechanical chemical polishing process.

[0048] Optionally, the method for forming the second dummy gate structure includes: forming a second dummy gate material layer in the second region, and patterning the second dummy gate material layer to form the second dummy gate.

[0049] Optionally, the first dummy gate structure and the first gate are formed at the same time as the second dummy gate is formed; the method for forming the first dummy gate structure, the first gate and the second dummy gate includes: forming a first gate layer on the first region; forming a first dummy gate material layer on the first gate layer and on the second region; forming a first hard mask material layer on the first dummy gate material layer; etching the first hard mask material layer until the first dummy gate layer on a portion of the first region and a portion of the second region is exposed to form an initial first hard mask layer; etching the first dummy gate material layer on the first region with the initial first hard mask layer until the surface of the first gate layer is exposed to form a first dummy gate on a portion of the first gate layer layer, forming a second dummy gate layer on the second area; after forming the first dummy gate layer and the second dummy gate layer, removing part of the initial first mask layer to expose part of the surface of the first dummy gate layer and part of the second dummy gate layer, respectively forming a first hard mask layer on the first area and a second hard mask layer on the second area; using the first hard mask layer as a mask, etching the first dummy gate layer until part of the surface of the first gate layer is exposed, so as to form the first dummy gate; using the first hard mask layer as a stencil, etching the first gate layer exposed by the first dummy gate layer until the surface of the first area is exposed, so as to form a first gate; using the second hard mask layer as a stencil, etching the second dummy gate layer until the surface of the second area is exposed, so as to form a second dummy gate.

[0050] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0051] The method for forming a semiconductor structure in the technical solution of the present invention forms a first gate on the first region, and forms two or more second gate structures on the first gate. The second gate structure includes a second gate. The second gate and the first gate are made of different materials. The second gate structure is located on the upper part of the first gate and is used to protect the first gate. During the mechanical chemical polishing process, it is not easy to produce "depression" defects, thereby achieving the purpose of improving the integrity of the first gate structure, thereby obtaining a gate structure with more optimized performance.

[0052] Furthermore, the dimension of the second gate structure along the gate width direction is less than or equal to 2 microns, so the size of the second gate structure is relatively small. When the second gate material is flattened by a mechanical chemical polishing process, it is not easy to produce a "depression" defect on the surface of the second gate structure, thereby not causing the second gate to be worn away, further protecting the first gate under the second gate, thereby improving the performance of the first gate in the first area.

[0053] Furthermore, the material of the first gate includes polysilicon, and the material of the first gate dielectric layer includes silicon oxide, so the threshold voltage of the first gate structure is low.

[0054] Furthermore, a modified layer is formed on the surface of the first gate, located between the second gate structure. This modified region can reduce the contact resistance between the first gate and the subsequently formed conductive plug. During the planarization process, because the modified layer is covered by the interlayer dielectric layer and the second gate structure has a dimension of less than or equal to 2 microns along the gate width, it is less likely to produce "depression" defects. Therefore, the modified layer is not easily exposed, preventing metal silicide from contaminating the mechanical chemical polishing machine and further causing device performance abnormalities. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure;

[0056] Figures 2 to 10 Schematic diagram of cross-sectional structures corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0057] Figures 11 to 19 Schematic diagram of cross-sectional structures corresponding to each step in a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0058] As described in the background art, the performance of semiconductor structures formed in the prior art needs to be improved. This is now explained and analyzed in conjunction with a semiconductor structure.

[0059] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0060] Please refer to Figure 1 , substrate 100, the substrate 100 includes a base 101, a first region I and a second region II located on the substrate 101, and an isolation structure 102 located in the substrate 100; a polysilicon gate 103 located on the first region I, a metal gate 104 located on the second region II; a first source and drain region 105 located in the first region I on both sides of the polysilicon gate 103, and a second source and drain region 106 located in the second region II on both sides of the metal gate 104; an interlayer dielectric layer 107 located on the substrate 100, and the interlayer dielectric layer 107 is also respectively located on the sidewalls of the polysilicon gate 103 and the metal gate 104.

[0061] When the above structure is used in a circuit integrating low-voltage, medium-voltage, and high-voltage devices, the second region II is used to form low-voltage devices, which utilize metal gates due to their smaller size. The first region I is used for medium-voltage and high-voltage devices. The polysilicon gate 103 in the first region I is typically larger than 2 microns, while the metal gate is typically smaller than 2 microns. Forming the metal gate 104 typically requires planarization until a gate opening is formed within the interlayer dielectric layer 107. A metal material layer is then formed on the surface of the gate opening and the interlayer dielectric layer 107. This metal material layer is then planarized until the interlayer dielectric layer 107 and the polysilicon gate 103 are exposed, thereby forming the metal gate 104. During this planarization process, the polysilicon gate 103, due to its large size, is prone to forming "depression" defects, which can even lead to wear away of the polysilicon gate 103, resulting in damage or failure of the polysilicon gate 103 and thus affecting device performance. The "depression" defect refers to the fact that during the mechanical chemical grinding process, the middle part of a large-sized pattern is easily over-grinded to produce a "depression".

[0062] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a first gate is formed on the first region, and two or more second gate structures are formed on the first gate, the second gate structure including a second gate, the second gate and the first gate having different materials, the second gate structure being located on the upper portion of the first gate and being used to protect the first gate, so that “depression” defects are not easily generated during the mechanical chemical polishing process, thereby achieving the purpose of improving the integrity of the first gate structure and obtaining a gate structure with more optimized performance.

[0063] In order to make the above-mentioned objects, characteristics and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0064] Figures 2 to 10 Schematic diagram of cross-sectional structures corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0065] Please refer to Figure 2 , providing a substrate 200, wherein the substrate includes a first region 201.

[0066] In this embodiment, the substrate 200 further includes a base 202, an isolation structure 203 located on top of the substrate 200, and a deep well 204 located within the substrate 200. The isolation structure 203 is used to achieve electrical isolation between different semiconductor devices. The deep well 204 is used to isolate external noise from devices subsequently formed on the substrate.

[0067] The substrate 202 is made of single crystal silicon, and the isolation structure 203 is made of silicon oxide.

[0068] In this embodiment, the deep well 204 is an N-type well, and its formation method includes: injecting phosphorus ions into the substrate along a direction perpendicular to the substrate 200, with an injection energy of 10 KeV to 3000 KeV and an injection dose of 10 12 cm -2 to 10 14 cm -2 , to form the deep well 204. In other embodiments, the deep well is formed by implanting boron ions into the substrate to form a P-type well.

[0069] refer to Figure 3 , a first gate layer 205 is formed on the first region 201 .

[0070] The material of the first gate layer 205 includes polysilicon.

[0071] In this embodiment, the first gate layer 205 further comprises first dopant ions, which are N-type or P-type. The dopant ions are introduced by ion implantation. In this embodiment, the first gate layer 205 is used to subsequently form a first gate. In other embodiments, the first gate layer is further used to form a first dummy gate located above the first gate. The first dopant ions can adjust the threshold voltage of the first gate, thereby reducing the resistance of the first gate.

[0072] In this embodiment, before forming the first gate layer 205 , the process further includes forming a first gate dielectric material layer 206 on the surface of the first region 201 .

[0073] The first gate dielectric material layer 206 is made of silicon oxide and is used to form a first gate dielectric layer.

[0074] refer to Figure 4 , a first dummy gate layer 207 is formed on the surface of the first gate layer 205 .

[0075] The method for forming the first dummy gate layer 207 includes forming a first dummy gate material layer on the surface of the first gate layer 205, and patterning the first dummy gate material layer to form the first dummy gate layer 207. The first dummy gate layer 207 is used for subsequently forming a first dummy gate.

[0076] The material of the first dummy gate layer 207 includes silicon.

[0077] In this embodiment, an initial first hard mask layer 208 is further provided on the first dummy gate layer 207; and an initial second gate dielectric layer 209 is further provided between the first gate layer 205 and the first dummy gate layer 207. The method for forming the initial first hard mask layer 208, the first dummy gate layer 207, and the initial second gate dielectric layer 209 includes: forming a second gate dielectric material layer on the surface of the first gate layer 205 before forming the first dummy gate material layer; forming a first hard mask material layer on the first dummy gate material layer; etching the first hard mask material layer to form the initial first hard mask layer 208, and etching the first dummy gate material layer using the initial first hard mask layer 208 as a mask until the surface of the first gate layer 205 is exposed to form the first dummy gate layer 207, and etching the second gate dielectric material layer to form the initial second gate dielectric layer 209.

[0078] In other embodiments, there is an initial second gate dielectric layer between the first gate layer and the first dummy gate layer, but the first dummy gate layer does not include an initial first hard mask layer; or there is no initial second gate dielectric layer between the first gate layer and the first dummy gate layer, but the first dummy gate layer has an initial first hard mask layer; or there is only a first dummy gate layer on the first gate layer, but does not include an initial first hard mask layer and an initial second gate dielectric layer.

[0079] The process of etching the first hard mask material layer, the first dummy gate material layer, and the second gate dielectric material layer includes a dry etching process.

[0080] The material of the initial first hard mask layer 208 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. The initial first hard mask layer 208 is subsequently used to form the first hard mask layer 214.

[0081] The material of the second gate dielectric layer 209 includes a high-K dielectric material. The high-K dielectric material (ie, dielectric constant K≧3.9) includes HfO 2 .

[0082] Please refer to Figure 5, patterning the first dummy gate layer 207 (eg Figure 4 As shown) and the first gate layer 205 to form a first gate 210 and two or more first dummy gates 212 on the first gate 210.

[0083] The first dummy gate structure 213 includes a first dummy gate 212 .

[0084] In this embodiment, the first dummy gate structure 213 further includes: a first hard mask layer 214 located on the first dummy gate 212, and a second gate dielectric layer 215 located between the first gate 210 and the first dummy gate 212. In other embodiments, the first dummy gate structure includes the first dummy gate and the first hard mask layer located on the first dummy gate, but does not include the second gate dielectric layer located between the first dummy gate and the first gate; or includes the first dummy gate and the second gate dielectric layer located between the first dummy gate and the first gate, but does not include the first hard mask layer located on the first dummy gate; or includes the first dummy gate structure, but does not include the second gate dielectric layer located between the first dummy gate and the first gate, and does not include the first hard mask layer located on the first dummy gate.

[0085] The first hard mask layer 214 is formed by etching the initial first hard mask layer 208 (eg Figure 4 as shown), until a portion of the surface of the first dummy gate layer 207 is exposed.

[0086] The process of etching the initial first hard mask layer 208 includes a dry etching process.

[0087] The method for forming the first dummy gate structure 213 and the first gate 210 includes: using the first hard mask layer 214 as a mask, etching the first dummy gate layer 207 (such as Figure 4 ), until a portion of the first gate layer 205 is exposed (as shown Figure 4 After forming the first dummy gate 212, the initial second gate dielectric layer 209 (as shown) is etched. Figure 4 ) to form a second gate dielectric layer 215; using the first hard mask layer 214 as a mask, the first gate layer 205 exposed by the first dummy gate layer 207 is etched until the surface of the first region 201 is exposed, thereby forming a first gate 210. In this embodiment, the first gate 210 and the first dummy gate 212 are etched simultaneously, saving production steps.

[0088] In other embodiments, the method for forming the first dummy gate and the first gate includes: etching a portion of the first gate layer to form a first gate and two or more first dummy gates on the first gate.

[0089] Please refer to Figure 6 , first source / drain regions 216 are formed in the first region 201 on both sides of the first gate 210 , and second doping ions are present in the first source / drain regions 216 .

[0090] The second doping ions are N-type or P-type ions.

[0091] The region between the first source and drain regions 216 and below the first gate 210 forms a channel of the first region device, and the direction of the gate width refers to the direction of the channel length.

[0092] Please refer to Figure 7 , a modified layer 217 is formed on the surface of the first gate 210 , and the modified layer 217 is located between the first dummy gate structures 213 .

[0093] In this embodiment, a contact layer 218 is further formed on the surface of the first source and drain region 216 .

[0094] The modified layer 217 and the contact layer 218 are made of metal silicide. They have low resistance. The contact layer 218 can reduce the contact resistance between the first source / drain region 216 and a subsequently formed conductive plug; the modified layer 217 can reduce the contact resistance between the first gate 210 and a subsequently formed conductive plug.

[0095] The formation process of the modified layer 217 and the contact layer 218 includes a self-aligned metal silicidation process. In this embodiment, the modified layer 217 and the contact layer 218 are formed simultaneously.

[0096] Please refer to Figure 8 An interlayer dielectric layer 219 is formed on the surface of the substrate 200 . The interlayer dielectric layer 219 is also located on the sidewalls and surface of the first gate 210 and the sidewalls of the first dummy gate 212 , and the interlayer dielectric layer 219 exposes the first dummy gate 212 .

[0097] The method for forming the interlayer dielectric layer 219 includes: forming an interlayer dielectric material film on the surface of the substrate 200, on the sidewalls of the first gate 210, and on the sidewalls and top of the dummy gate structure 213; and planarizing the interlayer dielectric material film until the top surface of the first dummy gate 212 is exposed, thereby forming the interlayer dielectric layer 219. In this embodiment, the interlayer dielectric layer 320 is also located on the surface of the contact layer 218 and on the sidewalls of the first gate dielectric layer 211. In this embodiment, the planarization process exposes the top surface of the first dummy gate 212. In other embodiments, the planarization process may cause the first dummy gate to be thinned.

[0098] The interlayer dielectric layer 219 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0099] The planarization process includes a mechanical chemical polishing process.

[0100] Please refer to Figure 9 , the first dummy gate 212 is removed by etching (eg Figure 8 As shown), a plurality of first trenches 220 are formed in the interlayer dielectric layer 219 .

[0101] The method of etching and removing the first dummy gate 212 includes one or both of dry etching and wet etching.

[0102] In this embodiment, the second gate dielectric layer 215 is exposed at the bottom of the first trench 220, and the interlayer dielectric layer 219 is exposed on the sidewall. In other embodiments, the first gate is exposed at the bottom of the first trench, and the interlayer dielectric layer is exposed on the sidewall.

[0103] In this embodiment, the method for etching and removing the first dummy gate 212 is a wet etching process.

[0104] The solution used in the wet etching process includes tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process of removing the dummy gate 212 , the first dummy gate 212 can have a larger etching selectivity relative to the interlayer dielectric layer 219 and the second gate dielectric layer 215 .

[0105] Please refer to Figure 10 , in the first groove 220 (such as Figure 9 As shown) is filled inside to form a second gate 221.

[0106] The second gate structure 222 includes a second gate 221. In this embodiment, the second gate structure 222 also includes a second gate dielectric layer 215 located between the second gate 221 and the first gate 210. In other embodiments, the second gate structure includes the second gate 221 but does not include the second gate dielectric layer 215 located between the second gate 221 and the first gate 210.

[0107] The second gate 221 is formed by filling the first trench 220 with a second gate material layer and planarizing the second gate material layer to form the second gate 221 until the surface of the interlayer dielectric layer 219 is exposed. During the planarization process, the interlayer dielectric layer 219 may be lost.

[0108] The process of filling the first trench 220 with the second gate material layer includes atomic layer deposition, physical vapor deposition, or electroplating. In this embodiment, the process of filling the first trench 220 with the second gate material layer is physical vapor deposition.

[0109] The second gate 221 is made of metal, such as copper, aluminum, or tungsten.

[0110] The dimension of the second gate structure 222 along the gate width direction is less than or equal to 2 micrometers.

[0111] The process for planarizing the second gate material layer includes a mechanochemical polishing process. Due to the small size of the second gate structure 222, a "depression" defect is less likely to occur on the surface of the second gate structure 222, thereby protecting the first gate 210 below it and preventing the first gate 210 from being worn away, thereby improving device performance.

[0112] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 10 , including: a substrate 200, the substrate 200 including a first region 201; a first gate 210 located on the first region 201; two or more second gate structures 222 located on part of the first gate 210, the second gate structure 222 including a second gate 221, and the material of the second gate 221 is different from that of the first gate 210.

[0113] The resistivity of the material of the second gate 221 is lower than the resistivity of the material of the first gate 210 .

[0114] The material of the second gate 221 includes metal; the metal includes copper, aluminum or tungsten; the material of the first gate 210 includes polysilicon.

[0115] The first gate 210 has first doping ions therein; the first doping ions are N-type ions or P-type ions.

[0116] The modified layer 217 is located on the surface of the first gate 210 , and the modified layer is located between the second gate structures 222 .

[0117] The material of the modified layer 217 includes metal silicide.

[0118] The first source and drain regions 210 are located in the first area 200 on both sides of the first gate 210 ; the first source and drain regions 210 have second doping ions.

[0119] The dimension of the second gate structure 222 along the gate width direction is less than or equal to 2 micrometers.

[0120] The semiconductor structure further includes a first gate dielectric layer 211 located between the first gate 210 and the first region 201 .

[0121] The material of the first gate dielectric layer 211 includes silicon oxide.

[0122] The semiconductor structure further includes a second gate dielectric layer 215 located between the second gate 221 and the first gate 210 .

[0123] The material of the second gate dielectric layer 215 includes a high-K dielectric material.

[0124] The semiconductor structure further includes: an oxide layer located between the first gate 210 and the second gate dielectric layer 215 ; and a metal compound layer located between the second gate dielectric layer 215 and the second gate 221 .

[0125] Figures 11 to 18 Schematic diagram of cross-sectional structures corresponding to each step in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0126] Please refer to Figure 11 , providing a substrate 300 , wherein the substrate 300 includes a first region 301 and a second region 302 .

[0127] In this embodiment, the first region 301 is used to form first-region devices; and the second region 302 is used to form second-region devices.

[0128] The substrate 300 also includes a base 303, a deep well 304 within the substrate 300, and an insulating isolation structure 305 located above the substrate 300. The isolation structure is used to electrically isolate different semiconductor devices. The deep well 304 is used to isolate external noise from devices subsequently formed on the substrate.

[0129] The material of the substrate 303 includes single crystal silicon, and the material of the isolation structure 305 includes silicon oxide.

[0130] In this embodiment, the deep well 304 is an N-type well, and its formation method includes: injecting phosphorus ions into the substrate along a direction perpendicular to the substrate 200, with an injection energy of 10KeV to 3000KeV and an injection dose of 10 12 cm -2 ~10 14 cm -2 , to form the deep well 304. In other embodiments, the deep well is formed by implanting boron ions into the substrate to form a P-type well.

[0131] Subsequently, a first gate is formed on the first region 301, and two or more first dummy gate structures are formed on the first gate, wherein the first dummy gate structure includes a first dummy gate; a second dummy gate structure is formed on the second region 302, wherein the second dummy gate structure includes a second dummy gate. The formation process of the first gate, the first dummy gate structure and the second dummy gate structure is as follows: Figures 12 to 15 shown.

[0132] Please refer to Figure 12 , a first gate layer 306 is formed on the first region 301 .

[0133] The material of the first gate layer 306 includes polysilicon. In other embodiments, the first gate layer also covers the second region and is used to subsequently form a second dummy gate on the second region.

[0134] In this embodiment, the first gate layer 306 further has first dopant ions, which are N-type or P-type. The dopant ions are introduced by ion implantation. The first dopant ions can adjust the threshold voltage of the semiconductor device formed subsequently.

[0135] In this embodiment, the first gate layer 306 is used to subsequently form a first gate. In other embodiments, the first gate layer is also used to form a first dummy gate layer located on the first gate and a second dummy gate on the second region.

[0136] In this embodiment, before forming the first gate layer 306 , the process further includes forming a first gate dielectric material layer 307 on the surface of the first region 301 .

[0137] The first gate dielectric material layer 307 is made of silicon oxide and is used to form a first gate dielectric layer.

[0138] refer to Figure 13 , a first dummy gate material layer 308 is formed on the first gate layer 306 and the second region 302 ; and a first hard mask material layer 401 is formed on the first dummy gate material layer 308 .

[0139] The material of the first dummy gate material layer 308 includes silicon. The first dummy gate material layer 308 is used to subsequently form a first dummy gate on the first region 301 and a second dummy gate on the second region 302 .

[0140] In this embodiment, the method further includes: before forming the first dummy gate material layer 308 , forming a second gate dielectric material layer 310 on the first gate layer 306 and the second region 302 .

[0141] The material of the second gate dielectric material layer 310 includes a high-K dielectric material. The second gate dielectric material layer 310 is used to subsequently form a second gate dielectric layer and a third gate dielectric layer. The high-K (i.e., dielectric constant K≧3.9) material includes HfO2. The third gate dielectric layer can significantly reduce the quantum tunneling effect of the gate dielectric layer, thereby effectively improving the third gate leakage current and the power consumption caused by it. In other embodiments, there is also an oxide layer located between the second region and the second gate dielectric material layer, and the material of the oxide layer includes silicon oxynitride, the purpose of which is to improve the interface state between the second gate dielectric material layer and the second region. In other embodiments, the metal compound layer located between the second gate dielectric material layer and the first pseudo gate material layer, the material of the metal compound layer includes titanium nitride, which is used to adjust the threshold voltage of the device subsequently formed.

[0142] The material of the hard mask material layer 401 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. The hard mask material layer 401 is used to subsequently form a first hard mask layer and a second hard mask layer.

[0143] In this embodiment, the first gate dielectric material layer 307 used to form the first gate dielectric layer and the second gate dielectric material layer 310 used to form the third gate dielectric layer are formed twice, using different materials. The first gate dielectric material layer 307 is an oxide layer, that is, the first gate dielectric layer formed subsequently is an oxide layer. Therefore, the threshold voltage of the first gate structure formed subsequently is low. If the first gate dielectric material layer 307 and the second gate dielectric material layer 310 are formed simultaneously using the same material, such as a high-K dielectric material, the threshold voltage of the first gate structure is high and cannot meet the device requirements.

[0144] refer to Figure 14 , etching the first hard mask material layer 401 until the first dummy gate material layer 308 on a portion of the first region 301 and a portion of the second region 302 is exposed to form an initial first hard mask layer 309; etching the first dummy gate material layer 308 on the first region 301 with the initial first hard mask layer 309 until the surface of the first gate layer 306 is exposed, forming a first dummy gate layer 311 on a portion of the first gate layer 306, and forming a second dummy gate layer 312 on the second region 302.

[0145] The process of etching the first hard mask material layer 401 includes a dry etching process.

[0146] The process of etching the first dummy gate material layer 308 on the first region 301 includes a dry etching process.

[0147] The first dummy gate layer 311 is used to form a first dummy gate later. The second dummy gate layer 312 is used to form a second dummy gate later.

[0148] In this embodiment, the second gate dielectric material layer 310 is etched to form an initial second gate dielectric layer 313 , and simultaneously an initial third gate dielectric layer 314 is formed on the second region 302 .

[0149] refer to Figure 15 , patterning the first dummy gate layer 311 (eg Figure 14 As shown) and the first gate layer 306 (as shown Figure 14 As shown), to form a first gate 315 and two or more first dummy gates 316 on the first gate 315; patterning the second dummy gate layer 312 (as shown Figure 14 ), to form a second dummy gate 317.

[0150] The first dummy gate structure 318 includes a first dummy gate 316 .

[0151] In this embodiment, the first dummy gate structure 318 further includes: a first hard mask layer 319 located on the first dummy gate 316, and a second gate dielectric layer 320 located between the first gate 315 and the first dummy gate 316. In other embodiments, the first dummy gate structure includes the first dummy gate and the first hard mask layer located on the first dummy gate, but does not include the second gate dielectric layer located between the first dummy gate and the first gate; or includes the first dummy gate and the second gate dielectric layer located between the first dummy gate and the first gate, but does not include the first hard mask layer located on the first dummy gate; or includes the first dummy gate, but does not include the second gate dielectric layer located between the first dummy gate and the first gate, and does not include the first hard mask layer located on the first dummy gate.

[0152] The second dummy gate structure 321 includes a second dummy gate 317 .

[0153] In this embodiment, the second dummy gate structure 321 further includes: a second hard mask layer 322 located on the second dummy gate 317, and a third gate dielectric layer 323 located between the second region 302 and the second dummy gate 317. In other embodiments, the second dummy gate structure includes the second dummy gate and the second hard mask layer located on the second dummy gate, but does not include the third gate dielectric layer located between the second region and the second dummy gate; or the second dummy gate structure includes the second dummy gate and the third gate dielectric layer located between the second region and the second dummy gate, but does not include the second hard mask layer located on the second dummy gate; or the second dummy gate structure includes the second dummy gate, but does not include the second hard mask layer and the third gate dielectric layer.

[0154] The formation method of the first hard mask layer 319 and the second hard mask layer 322 includes: removing part of the initial first mask layer 309, exposing part of the surface of the first pseudo gate layer 311 and part of the second pseudo gate layer 312, and forming the first hard mask layer 319 on the first area 301 and the second hard mask layer 322 on the second area 302 respectively.

[0155] The method for forming the first dummy gate structure 318, the second dummy gate structure 321 and the first gate 315 includes: using the first hard mask layer 319 as a mask, etching the first dummy gate layer 311 (such as Figure 14 ), until a portion of the first gate layer 306 is exposed (as shown Figure 14 ) surface, forming the first dummy gate 316; using the first hard mask layer 319 as a mask, the first gate layer 306 exposed by the first dummy gate layer 311 is etched until the surface of the first region 301 is exposed, forming the first gate 315; using the second hard mask layer 322 as a mask, the second dummy gate layer 312 is etched until the surface of the second region 302 is exposed, forming the second dummy gate 317. In this embodiment, the first dummy gate 316, the first gate 315, and the second dummy gate 317 are formed by etching simultaneously, saving production steps and reducing production costs.

[0156] In this embodiment, the first gate dielectric material layer 307 (such as Figure 14 ) is etched to form a first gate dielectric layer 324; the initial second gate dielectric layer 313 (as shown Figure 14 ) is etched to form a second gate dielectric layer 320; the initial third gate dielectric layer 314 (as shown Figure 14 As shown in FIG, the third gate dielectric layer 323 is formed by etching.

[0157] The process of etching to form the first gate 315 , the first dummy gate structure 318 and the second dummy gate structure 321 is a dry etching process.

[0158] refer to Figure 16 A first source / drain region 325 is formed in the first region 301 on both sides of the first gate 315, and the first source / drain region 325 has second doping ions; a second source / drain region 326 is formed in the second region 302 on both sides of the second dummy gate structure 321, and the second source / drain region 326 has third doping ions; a modified layer 327 is formed on the surface of the first gate 315, and the modified layer 327 is located between the first dummy gate structures 318.

[0159] In this embodiment, the further step includes forming a contact layer 328 on the surfaces of the first source / drain region 325 and the second source / drain region 326 .

[0160] The modified region 327 is made of metal silicide. The first gate 315 is connected to an external circuit via a conductive plug subsequently formed on the modified region 327. The modified region 327 has a low resistance and can reduce the contact resistance between the first gate 315 and the conductive plug subsequently formed.

[0161] The material of the contact layer 328 is metal silicide. The contact layer 328 has a low resistance and can reduce the contact resistance between the first source / drain region 325 and the second source / drain region 326 and the conductive plug formed subsequently.

[0162] The formation process of the modified layer 327 and the contact layer 328 includes a self-aligned metal silicide process. In this embodiment, the modified layer 327 and the contact layer 328 are formed in a one-time process, which saves process steps and reduces production costs. Subsequently, an interlayer dielectric layer is formed on the surface of the substrate 300; after the interlayer dielectric layer is formed, the interlayer dielectric layer is flattened until the second dummy gate is exposed. During the flattening process, since the modified layer 327 and the contact layer 328 are covered by the interlayer dielectric layer, and the size of the first dummy gate structure 318 along the gate width direction is less than or equal to 2 microns, it is not easy to produce "depression" defects. Therefore, the modified layer 327 and the contact layer 328 are not easily exposed, and will not cause metal silicide to contaminate the mechanical chemical polishing machine, further polluting the performance of the device.

[0163] Please refer to Figure 17 An interlayer dielectric layer 329 is formed on the surface of the substrate 300. The interlayer dielectric layer 329 is also located on the sidewall and surface of the first gate 315 and the sidewall of the first dummy gate 316, and the interlayer dielectric layer 329 exposes the first dummy gate 316. The interlayer dielectric layer 329 is also located on the sidewall of the second dummy gate 317 and exposes the top surface of the second dummy gate 317.

[0164] The method for forming the interlayer dielectric layer 329 includes: forming the sidewalls of the first gate 315 and the dummy gate structure 318 (such as Figure 16 As shown) sidewalls and top, and the second dummy gate structure 321 (as shown Figure 16 An interlayer dielectric material film is formed on the sidewalls and top of the first dummy gate 316 and the second dummy gate 317; the interlayer dielectric material film is planarized until the top surfaces of the first dummy gate 316 and the second dummy gate 317 are exposed, thereby forming the interlayer dielectric layer 329. In this embodiment, the interlayer dielectric layer 329 is also located on the surface of the contact layer 328 and the surface of the modified region 327.

[0165] The interlayer dielectric layer 329 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0166] In other embodiments, the planarization process may cause the first dummy gate to be thinned.

[0167] In this embodiment, the planarization process is a mechanochemical polishing process. During mechanochemical polishing, the larger the size of the polished area, the more likely it is to produce a "depression" defect. The deeper the "depression" defect, the more likely it is to be partially worn away. The first gate 315 has a dimension greater than 10 μm along the gate width direction, and the first dummy gate structure 318 has a dimension less than or equal to 2 μm along the gate width direction. During the planarization process, the material of the first hard mask layer 319 above the first dummy gate structure 318 has a higher wear resistance than the material of the interlayer dielectric layer 329, thus protecting the first dummy gate structure 318. Furthermore, due to the small size of the first dummy gate structure 318, "depression" defects are less likely to occur on the surface of the first dummy gate structure 318, thereby protecting the first gate 315 below it from being worn away. During the planarization process, the first dummy gate structure 318 may be thinned, but as long as a portion of the first dummy gate structure 318 remains, the first gate 315 will not be worn away.

[0168] Please refer to Figure 18 , the first dummy gate 316 is removed by etching, and a plurality of first trenches 330 are formed in the interlayer dielectric layer 329 ; the second dummy gate 317 is removed, and a second trench 331 is formed in the interlayer dielectric layer.

[0169] The method of etching and removing the first dummy gate 316 and the second dummy gate 317 includes one or both of dry etching and wet etching. In this embodiment, the method of etching and removing the first dummy gate 316 and the second dummy gate 317 is a wet etching process.

[0170] In this embodiment, the second gate dielectric layer 320 is exposed at the bottom of the first trench 330 ; and the third gate dielectric layer 323 is exposed at the bottom of the second trench 331 .

[0171] The solution used in the wet etching process includes tetramethylammonium hydroxide or potassium hydroxide solution. Thus, during the etching process for removing the first dummy gate 316 , the first dummy gate 316 can have a larger etching selectivity with respect to the interlayer dielectric layer 329 and the second gate dielectric layer 320 ; and during the etching process for removing the second dummy gate 316 , the second dummy gate 317 can have a larger etching selectivity with respect to the interlayer dielectric layer 329 and the third gate dielectric layer 323 .

[0172] Please refer to Figure 19 , a second gate 332 is filled in the first trench 330 ; while forming the second gate 332 , a third gate 333 is formed in the second trench 331 .

[0173] In this embodiment, the second gate structure 334 includes a second gate 332 and a second gate dielectric layer 320 located between the second gate 332 and the first gate 315. In other embodiments, the second gate structure includes a second gate but does not include a second gate dielectric layer.

[0174] In this embodiment, the third gate structure 336 includes a third gate 333 and a third gate dielectric layer 323 located on the third gate 333 and the second region 302. In other embodiments, the third gate structure includes a third gate but does not include a third gate dielectric layer.

[0175] A third gate material layer is formed on the surface of the interlayer dielectric layer 329, within the first trench 330, and within the second trench 331. The third gate material layer is planarized until the surface of the interlayer dielectric layer 329 is exposed, thereby forming the second gate 332 and the third gate 333. During the planarization process, the interlayer dielectric layer 329 may be thinned.

[0176] The process for planarizing the third gate material layer is a mechanical chemical polishing process.

[0177] The process of filling the first trench 330 and the second trench 331 with the second gate material layer includes an atomic layer deposition process or a physical vapor deposition process.

[0178] The second gate 332 and the third gate 333 are made of metal, such as copper, aluminum, or tungsten.

[0179] The size of the first gate 315 along the gate width direction is greater than 10 μm, and the size of the second gate 332 along the gate width direction is less than or equal to 2 μm.

[0180] The process for planarizing the second gate material layer includes a mechanical chemical polishing process. Due to the small size of the second gate 332, it is less likely to produce a "depression" defect in the second gate 332, thereby protecting the first gate 315 below it and preventing the first gate 315 from being worn away, thereby improving device performance.

[0181] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 19 , including: a substrate 300, the substrate including a first area 301 and a second area 302; a first gate 315 located on the first area 301; two or more second gate structures 334 located on part of the first gate 315, the second gate structure 334 including a second gate 332, the second gate 332 and the first gate 315 are made of different materials; a third gate structure 335 located on the second area 302, the third gate structure 335 including a third gate 333, the material of the third gate 333 including metal.

[0182] The resistivity of the material of the second gate 332 is lower than the resistivity of the material of the first gate 315 .

[0183] The material of the second gate 332 includes metal; the metal includes copper, aluminum or tungsten; the material of the first gate 315 includes polysilicon.

[0184] The first gate 315 has first doping ions therein; the first doping ions are N-type ions or P-type ions.

[0185] The semiconductor structure further includes a modified layer 327 located on the surface of the first gate 315 , and the modified layer 327 is located between the second gate structures 334 .

[0186] The material of the modified layer 327 includes metal silicide.

[0187] The semiconductor structure further includes first source and drain regions 325 located in the first region 301 on both sides of the first gate 315 , and second dopant ions are present in the first source and drain regions 325 .

[0188] The material of the first source / drain region 325 includes silicon carbide, and the second doping ions are N-type ions; the material of the first source / drain region 325 includes silicon germanium, and the second doping ions are P-type ions.

[0189] The third gate structure 335 further includes a third gate dielectric layer 323 located between the third gate 333 and the second region 302 .

[0190] The material of the third gate dielectric layer 323 includes a high-K dielectric material.

[0191] The third gate structure 335 further includes: an oxide layer located between the second region 302 and the third gate dielectric layer 323 ; and a metal compound layer located between the third gate dielectric layer 323 and the third gate 333 .

[0192] The semiconductor structure further includes: second source and drain regions 326 located in the second region 302 on both sides of the third gate structure 335; and third doping ions are present in the second source and drain regions 326 .

[0193] A contact layer 328 is located on the surfaces of the first source / drain region 325 and the second source / drain region 326 ; the material of the contact layer 328 is metal silicide.

[0194] The dimension of the second gate structure 334 along the gate width direction is less than or equal to 2 micrometers.

[0195] The semiconductor structure further includes a first gate dielectric layer 324 located between the first gate 315 and the first region 301 .

[0196] The material of the first gate dielectric layer 324 includes silicon oxide.

[0197] The semiconductor structure further includes a second gate dielectric layer 320 located between the second gate 332 and the first gate 315 .

[0198] The second gate dielectric layer 320 is made of a high-K dielectric material.

[0199] The semiconductor structure further includes: an oxide layer located between the first gate 315 and the second gate dielectric layer 320 ; and a metal compound layer located between the second gate dielectric layer 320 and the second gate 332 .

[0200] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region; a first gate located on the first region; Two or more second gate structures located on a portion of the first gate, the second gate structures including a second gate, the second gate being made of a different material than the first gate; a modified layer located on a surface of the first gate, wherein the modified layer is located between the second gate structures; A conductive plug is located on the surface of the modified layer.

2. The semiconductor structure according to claim 1, wherein The resistivity of a material of the second gate is lower than the resistivity of a material of the first gate.

3. The semiconductor structure according to claim 2, wherein: The material of the second gate includes metal; the metal includes copper, aluminum or tungsten; the material of the first gate includes polysilicon.

4. The semiconductor structure according to claim 3, wherein: The first gate has first doping ions therein; the first doping ions are N-type ions or P-type ions.

5. The semiconductor structure according to claim 1, wherein The material of the modified layer includes metal silicide.

6. The semiconductor structure according to claim 1, wherein Also includes: a first source and drain region located in the first region on both sides of the first gate; The first source and drain regions have second doping ions therein.

7. The semiconductor structure according to claim 1, wherein The substrate also includes a second region.

8. The semiconductor structure according to claim 7, wherein: Also includes: A third gate structure is located on the second region; the third gate structure includes a third gate, and the material of the third gate includes metal.

9. The semiconductor structure according to claim 8, wherein: The third gate structure further includes a third gate dielectric layer located between the third gate and the second region.

10. The semiconductor structure according to claim 9, wherein: The material of the third gate dielectric layer includes a high-K dielectric material.

11. The semiconductor structure according to claim 10, wherein: The third gate structure further includes: an oxide layer located between the second region and the third gate dielectric layer; and a metal compound layer located between the third gate dielectric layer and the third gate.

12. The semiconductor structure according to claim 8, wherein Also includes: Second source and drain regions are respectively located in the second region on both sides of the third gate structure; and third doping ions are present in the second source and drain regions.

13. The semiconductor structure according to claim 1, wherein: The dimension of the second gate structure along the gate width direction is less than or equal to 2 micrometers.

14. The semiconductor structure according to claim 1, wherein: Also includes: A first gate dielectric layer is located between the first gate and the first region.

15. The semiconductor structure according to claim 14, wherein: The material of the first gate dielectric layer includes silicon oxide.

16. The semiconductor structure according to claim 1, wherein Also includes: A second gate dielectric layer is located between the second gate and the first gate.

17. The semiconductor structure according to claim 16, wherein: The material of the second gate dielectric layer includes a high-K dielectric material.

18. The semiconductor structure according to claim 16, wherein: Also includes: an oxide layer located between the first gate and the second gate dielectric layer; A metal compound layer is located between the second gate dielectric layer and the second gate.

19. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; forming a first gate on the first region; forming two or more first dummy gate structures on the first gate, wherein the first dummy gate structures include a first dummy gate; forming a modified layer on the surface of the first gate, wherein the modified layer is located between the first dummy gate structures; After forming the modified layer, replacing the first dummy gate with a second gate to form two or more second gate structures on the first gate, wherein the second gate structures include a second gate, and the second gate and the first gate are made of different materials; A conductive plug is formed on the surface of the modified layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: The material of the first gate includes polysilicon.

21. The method for forming a semiconductor structure according to claim 19, wherein: Also includes: A first gate dielectric layer is formed between the first gate and the first region.

22. The method for forming a semiconductor structure according to claim 21, wherein: The material of the first gate dielectric layer includes silicon oxide.

23. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the first gate includes: forming a first gate layer on the first region; and patterning the first gate layer to form a first gate.

24. The method for forming a semiconductor structure according to claim 23, wherein: The method for forming the first gate further includes: doping first doping ions in the first gate layer; the first doping ions are N-type or P-type.

25. The method for forming a semiconductor structure according to claim 19, wherein: The material of the second gate includes metal.

26. The method for forming a semiconductor structure according to claim 19, wherein: The second gate structure further includes a second gate dielectric layer located between the second gate and the first gate.

27. The method for forming a semiconductor structure according to claim 26, wherein: The material of the second gate dielectric layer includes a high-K dielectric material.

28. The method for forming a semiconductor structure according to claim 27, wherein: The second gate structure further includes: an oxide layer located between the first gate and the second gate dielectric layer; and a metal compound layer located between the second gate dielectric layer and the second gate.

29. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the second gate structure also includes: forming an interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer is also located on the sidewall and surface of the first gate, and the sidewall of the first dummy gate, and the interlayer dielectric layer exposes the first dummy gate; etching and removing the first dummy gate, forming a plurality of first trenches in the interlayer dielectric layer; and filling the first trenches to form a second gate.

30. The method for forming a semiconductor structure according to claim 19, wherein: A first dummy gate structure is formed while forming the first gate; the method for forming the first gate and the first dummy gate structure includes: forming a first gate layer on the first region; etching part of the first gate layer to form the first gate and two or more first dummy gates on the first gate.

31. The method for forming a semiconductor structure according to claim 30, wherein: The method for forming the first dummy gate structure includes: forming a first gate layer on the first region, forming a first dummy gate layer on the surface of the first gate layer; patterning the first dummy gate layer and the first gate layer to form a first gate and two or more first dummy gates on the first gate.

32. The method for forming a semiconductor structure according to claim 31, wherein: The first dummy gate structure also includes: a first hard mask layer located on the first dummy gate; the method for forming the first dummy gate structure and the first gate also includes: forming the first hard mask layer on the first dummy gate layer; using the first hard mask layer as a mask, etching the first dummy gate layer until the surface of the first gate layer is exposed to form the first dummy gate; using the first hard mask layer as a mask, etching the first gate layer exposed by the first dummy gate until the surface of the first region is exposed to form the first gate.

33. The method for forming a semiconductor structure according to claim 32, wherein: The method for forming the first hard mask layer includes: forming an initial first hard mask layer on the surface of the first dummy gate layer, and etching the initial first hard mask layer until a portion of the surface of the first dummy gate layer is exposed.

34. The method for forming a semiconductor structure according to claim 19, wherein: After forming the first gate and before forming the second gate structure, the method further includes: forming first source and drain regions in the first regions on both sides of the first gate, wherein the first source and drain regions have second doping ions.

35. The method for forming a semiconductor structure according to claim 19, wherein: The material of the modified layer includes metal silicide; and the formation process of the modified layer includes a self-aligned metal silicide process.

36. The method for forming a semiconductor structure according to claim 29, wherein: The substrate further includes a second region; the forming method further includes: forming a third gate structure on a portion of the second region, the third gate structure including a third gate, and the material of the third gate is the same as that of the second gate.

37. The method for forming a semiconductor structure according to claim 36, wherein: The method for forming the third gate structure includes: forming a second trench in the interlayer dielectric layer on the second region; and forming a third gate in the second trench.

38. The method for forming a semiconductor structure according to claim 37, wherein: The method for forming the second trench includes: before forming the interlayer dielectric layer, forming a second dummy gate structure on the second region, the second dummy gate structure including a second dummy gate; the interlayer dielectric layer is also located on the sidewall of the second dummy gate structure and exposes the top surface of the second dummy gate structure; removing the second dummy gate and forming the second trench in the interlayer dielectric layer.

39. The method for forming a semiconductor structure according to claim 37, wherein: While forming the second gate, a third gate is formed in the second trench; the method for forming the second and third gates includes: forming a third gate material layer on the surface of the interlayer dielectric layer, in the first trench, and in the second trench; and flattening the third gate material layer until the surface of the interlayer dielectric layer is exposed to form the second and third gates.

40. The method for forming a semiconductor structure according to claim 39, wherein: The process for planarizing the third gate material layer is a mechanical chemical polishing process.

41. The method for forming a semiconductor structure according to claim 38, wherein: The method for forming the second dummy gate structure includes: forming a second dummy gate material layer in the second region, and patterning the second dummy gate material layer to form the second dummy gate.

42. The method for forming a semiconductor structure according to claim 38, wherein: The first dummy gate structure and the first gate are formed at the same time as the second dummy gate is formed; the method for forming the first dummy gate structure, the first gate and the second dummy gate includes: forming a first gate layer on the first region; forming a first dummy gate material layer on the first gate layer and the second region; forming a first hard mask material layer on the first dummy gate material layer; etching the first hard mask material layer until a portion of the first dummy gate layer on the first region and a portion of the second region is exposed to form an initial first hard mask layer; etching the first dummy gate material layer on the first region with the initial first hard mask layer until a surface of the first gate layer is exposed to form a first dummy gate layer on a portion of the first gate layer, A second dummy gate layer is formed on the second region; after forming the first dummy gate layer and the second dummy gate layer, a portion of the initial first hard mask layer is removed to expose a portion of the first dummy gate layer and a portion of the second dummy gate layer surface, thereby forming a first hard mask layer on the first region and a second hard mask layer on the second region, respectively; using the first hard mask layer as a mask, the first dummy gate layer is etched until a portion of the first gate layer surface is exposed to form the first dummy gate; using the first hard mask layer as a stencil, the first gate layer exposed by the first dummy gate layer is etched until the surface of the first region is exposed to form a first gate; using the second hard mask layer as a stencil, the second dummy gate layer is etched until the surface of the second region is exposed to form a second dummy gate.

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