Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first region; forming an initial first gate structure on the first region, the initial first gate structure comprising an initial first gate; forming at least one first gate opening in the initial first gate to form a first gate structure with the initial first gate structure and to form a first gate with the initial first gate; forming a second gate in the first gate opening, the material of the first gate and the material of the second gate being different, and the second gate material having different performance according to different integrated circuit performance requirements of the first gate structure, so as to adjust the performance of the first gate structure and to meet more integrated circuit design requirements.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacities, and more functions, integrated circuit chips are evolving towards higher device density and higher integration levels. Typically, a complete integrated circuit includes first-region devices and second-region devices integrated on the same semiconductor substrate. There is at least one first-region device, which is at least one input / output device. The second-region devices form the second region and are used to implement the main functions of the integrated circuit. The input / output devices provide corresponding input signals to the second-region devices or output corresponding signals from the second-region devices. The operating voltage of the input / output devices is not lower than the operating voltage of the second-region devices. Due to the difference in operating voltage between the first-region and second-region devices, the structures of the corresponding devices also differ.

[0003] As integrated circuit technology continues to advance to below the nanometer level, incompatibility issues may arise between integrated circuit design requirements and existing device processes. For example, the performance of existing devices may not meet the circuit design requirements. Therefore, it is necessary to continuously introduce new advanced processes to improve device performance. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a first region; a first gate structure located on the first region, the first gate structure including a first gate, the first gate having at least one first gate opening; and a second gate located within the first gate opening, the material of the second gate being different from the material of the first gate.

[0006] Optionally, the resistivity of the material of the second gate is lower than that of the material of the first gate.

[0007] Optionally, the material of the second gate is metal; the material of the first gate is polycrystalline silicon.

[0008] Optionally, the first gate contains a first doped ion, which is an N-type ion or a P-type ion.

[0009] Optionally, it also includes: a first source / drain region located in the substrate on both sides of the first gate structure.

[0010] Optionally, it may also include: a first contact layer located on the surface of the first source / drain region; the material of the first contact layer is a metal silicide layer.

[0011] Optionally, the substrate may further include a second region.

[0012] Optionally, it also includes a second gate structure located on the second region.

[0013] Optionally, the second gate structure includes a third gate, the material of which includes a metal.

[0014] Optionally, the second gate structure further includes a second gate dielectric layer located between the third gate and the substrate.

[0015] Optionally, the material of the second gate dielectric layer includes a high-k dielectric material.

[0016] Optionally, the second gate structure further includes: a silicon oxide layer located between the substrate and the second gate dielectric layer; and a titanium nitride layer located between the second gate dielectric layer and the third gate.

[0017] Optionally, it also includes: second source / drain regions located in the substrate on both sides of the second gate structure.

[0018] Optionally, it may also include: a second contact layer located on the surface of the second source / drain region; the material of the second contact layer is a metal silicide.

[0019] Optionally, the dimension of the first gate opening along the gate length direction is less than or equal to 2 micrometers.

[0020] Optionally, the depth of the first gate opening is less than the thickness of the first gate.

[0021] Optionally, the first gate structure further includes a first gate dielectric layer located between the first gate and the substrate.

[0022] Optionally, the material of the first gate dielectric layer includes silicon oxide.

[0023] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region; forming an initial first gate structure on the first region, the initial first gate structure including an initial first gate; forming at least one first gate opening in the initial first gate, forming a first gate structure with the initial first gate structure, and forming a first gate with the initial first gate; forming a second gate in the first gate opening, wherein the materials of the first gate and the second gate are different.

[0024] Optionally, the method for forming the initial first gate structure includes: forming an initial first gate layer on a first region; and patterning the initial first gate layer to form the initial first gate.

[0025] Optionally, the method for forming the initial first gate structure further includes: doping the initial first gate with a first dopant ion, wherein the first dopant ion is N-type or P-type.

[0026] Optionally, the method for forming the initial first gate structure further includes: forming a first gate dielectric layer between the initial first gate and the substrate; the material of the first gate dielectric layer includes silicon oxide.

[0027] Optionally, the initial first gate structure further includes a first hard mask layer located on the initial first gate.

[0028] Optionally, the method of patterning the initial first gate layer includes: forming a first hard mask material layer on the surface of the initial first gate layer; patterning the first hard mask material layer to form a first hard mask layer, the first hard mask layer exposing a portion of the surface of the initial first gate layer; using the first hard mask layer as a mask, etching the initial first gate layer until the substrate surface is exposed to form the initial first gate.

[0029] Optionally, it further includes: forming an interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer also being located on the sidewall surface of the initial first gate structure.

[0030] Optionally, the method for forming the first gate opening and the first gate includes: forming a patterned layer on the surface of the initial first gate, the patterned layer exposing a portion of the initial first gate surface; etching the initial first gate using the patterned layer as a mask to form the first gate and the first gate opening; and removing the patterned layer after forming the first gate opening.

[0031] Optionally, the method for forming the interlayer dielectric layer includes: forming an interlayer dielectric material film on the substrate and on the sidewalls and top surface of the initial first gate structure; planarizing the interlayer dielectric material film to form the interlayer dielectric layer.

[0032] Optionally, the method of forming the second gate includes: filling the first gate opening with a second gate material layer; planarizing the second gate material layer until the first gate surface is exposed to form the second gate.

[0033] Optionally, the planarization process is a mechanical-chemical grinding process.

[0034] Optionally, the second gate material is a metal.

[0035] Optionally, after forming the initial first gate structure and before forming the first gate opening, the method further includes: forming first source / drain regions in the first regions on both sides of the initial first gate structure.

[0036] Optionally, it further includes: forming a first contact layer on the surface of the first source / drain region; the material of the first contact layer is a metal silicide.

[0037] Optionally, it further includes: the substrate further includes a second region; a second gate structure is formed on a portion of the second region, the second gate structure including a third gate, the material of the third gate being the same as the material of the second gate.

[0038] Optionally, the method of forming the second gate structure includes: forming a second gate opening in an interlayer dielectric layer on the second region; and forming a third gate in the second gate opening.

[0039] Optionally, the method for forming the second gate opening includes: forming a dummy gate structure on the second region before forming the interlayer dielectric layer, the dummy gate structure including a dummy gate layer; the interlayer dielectric layer is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate layer; removing the dummy gate layer to form the second gate opening within the interlayer dielectric layer.

[0040] Optionally, while forming a second gate in the first gate opening, a third gate is formed in the second gate opening; the method for forming the second gate and the third gate includes: forming a second gate material layer on the surface of the interlayer dielectric layer, in the first gate opening, and in the second gate opening; planarizing the second gate material layer until the first gate surface is exposed, thereby forming the second gate and the third gate.

[0041] Optionally, the process for planarizing the gate material layer is a mechanical-chemical polishing process.

[0042] Optionally, the dummy gate structure and the initial first gate structure are formed simultaneously. The method for forming the dummy gate structure and the initial first gate structure includes: forming an initial first gate layer on a first region; forming an initial dummy gate layer on the initial first gate layer and on the second region; forming a second hard mask material layer on the initial dummy gate layer; etching the second hard mask material layer until a portion of the initial dummy gate layer on the first region is exposed, forming an initial second hard mask layer; etching the initial dummy gate layer in the first region with the initial second hard mask layer until the surface of the initial first gate layer is exposed, forming a transition mask layer on a portion of the initial first gate layer; after forming the transition mask layer, removing a portion of the initial second mask layer in the second region to expose a portion of the surface of the initial dummy gate layer in the second region, forming a second mask layer in the second region; etching the initial first gate layer and the initial dummy gate layer with the second mask layer and the transition mask layer until the substrate surface is exposed, forming the first gate and the dummy gate layer.

[0043] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0044] The semiconductor structure provided by the present invention includes a first gate structure located on the first region. The first gate structure includes a first gate, which has at least one first gate opening. A second gate is located within the first gate opening. Since the material of the second gate is different from that of the first gate, a second gate material with different properties can be selected according to the performance requirements of different integrated circuits for the first gate structure, thereby achieving the purpose of adjusting the performance of the first gate structure and thus meeting more integrated circuit design requirements.

[0045] Furthermore, the material of the second gate is metal, and the material of the first gate is polysilicon. Since the resistivity of metal is lower than that of polysilicon, the resistivity of the gate composed of the first gate and the second gate is reduced. Therefore, a low-resistivity polysilicon gate structure can be obtained without running a complex metal silicide process.

[0046] Furthermore, the second gate is made of metal, and the first gate is connected to the contact plug through the second gate. Since the resistivity of metal is lower than that of polysilicon, the gate structure formed by the first gate and the second gate has a low contact resistance with the contact plug. Therefore, it is not necessary to run a metal silicide process to form a low-resistance contact layer on the surface of the first gate, thus saving a process step.

[0047] Furthermore, the material of the first gate dielectric layer includes silicon oxide, thus the threshold voltage of the first gate structure is low.

[0048] The semiconductor structure formation method of the present invention involves forming at least one first gate opening within an initial first gate, forming a first gate structure with the initial first gate structure, forming a first gate with the initial first gate, and forming a second gate within the first gate opening. The materials of the first gate and the second gate are different. The performance of the gate formed by the first gate and the second gate can be changed by altering the number of openings, the opening size, and the properties of the second gate material filling the opening, thereby obtaining a more optimized gate structure performance.

[0049] Furthermore, the size of the first gate opening along the gate length direction is less than or equal to 2 micrometers. Therefore, the second gate size is small. When the second gate material is planarized by mechanical and chemical polishing process, it is not easy to produce "dimpled" defects, so as not to cause the second gate to be worn away. This further protects the first gate below the second gate, thereby improving the performance of the first gate structure in the first region.

[0050] Furthermore, the material of the second gate is metal, and the material of the first gate is polysilicon. Since the resistivity of metal is lower than that of polysilicon, the resistivity of the gate composed of the first gate and the second gate is reduced. Therefore, a low-resistivity polysilicon gate structure can be obtained without running a complex metal silicide process.

[0051] Furthermore, the second gate is made of metal, and the first gate is connected to the contact plug through the second gate. Since the resistivity of metal is lower than that of polysilicon, the gate structure formed by the first gate and the second gate has a low contact resistance with the contact plug. Therefore, it is not necessary to run a metal silicide process to form a low-resistance contact layer on the surface of the first gate, thus saving process steps.

[0052] Furthermore, the material of the first gate dielectric layer includes silicon oxide, thus the threshold voltage of the first gate structure is low. Attached Figure Description

[0053] Figure 1 This is a schematic cross-sectional view of a semiconductor structure.

[0054] Figures 2 to 8 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention;

[0055] Figures 9 to 16 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to another embodiment of the present invention. Detailed Implementation

[0056] As described in the background section, the performance of semiconductor structures formed in the prior art needs improvement. The following analysis will illustrate this with reference to a semiconductor structure.

[0057] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor.

[0058] Please refer to Figure 1 A substrate 100 is provided, and a polysilicon gate structure 101 is formed on a portion of the surface of the substrate 100. The polysilicon gate structure 101 includes a gate dielectric layer 102 located on the surface of the substrate 100 and a polysilicon gate 103 located on the surface of the gate dielectric layer 102.

[0059] In the above methods, the polysilicon gate, due to its high resistivity, is increasingly unable to meet the requirements of existing devices as semiconductors continue to develop. In another embodiment, a high dose of dopant is incorporated into the polysilicon gate to reduce the threshold voltage and resistivity of the gate structure, but the resistivity of the polysilicon gate remains high. As device feature sizes continue to shrink to submicron or even nanometer scales, the problem of high polysilicon gate resistivity becomes increasingly serious. To reduce the resistivity of the polysilicon gate, in yet another embodiment, a metal silicide process is used to form a layer of metal silicide on the surface of the polysilicon gate to reduce the resistance of the polysilicon gate structure.

[0060] To address the aforementioned issues, this invention provides a semiconductor structure and its formation method, in which a first gate structure is located on a first region. The first gate structure includes a first gate, at least one first gate opening within the first gate, and a second gate within the first gate opening. Since the material of the second gate differs from that of the first gate, a second gate material with different properties can be selected according to the performance requirements of different integrated circuits for the first gate structure, thereby achieving the purpose of adjusting the performance of the first gate structure. For example, selecting a second gate material with low resistivity can reduce the resistivity of the first gate structure without requiring complex metal silicide processes, thus meeting more integrated circuit design requirements.

[0061] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0062] Figures 2 to 8 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0063] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 including a first region 201.

[0064] In this embodiment, the substrate 200 further includes: a substrate 202, an isolation structure 203 located on the upper part of the substrate 200, and a deep well 204 located in the substrate 200. The isolation structure 203 is used to achieve electrical insulation between different semiconductor devices. The deep well 204 is used to isolate noise generated by external factors on devices subsequently formed on the substrate.

[0065] The substrate 202 is made of monocrystalline silicon, and the isolation structure 203 is made of silicon oxide.

[0066] In this embodiment, the deep well 204 is an N-type well, and its formation method includes: implanting phosphorus ions into the substrate along a direction perpendicular to the substrate 200, with an implantation energy of 10 kEV to 3000 kEV and an implantation dose of 10 12 cm -2 ~10 14 cm -2 This forms the deep well 204. In other embodiments, the deep well is formed by implanting boron ions into the substrate to form a P-type well.

[0067] Please refer to Figure 3 An initial first gate structure 205 is formed on the first region 201, the initial first gate structure 205 including an initial first gate 207.

[0068] In this embodiment, the initial first gate structure 205 further includes a first gate dielectric layer 206 and a first hard mask layer 208. In other embodiments, the initial first gate structure includes a first gate dielectric layer and an initial first gate, and the initial first gate structure does not include a first hard mask layer.

[0069] The material of the first gate dielectric layer 206 includes silicon oxide.

[0070] The initial first gate 207 material comprises polycrystalline silicon.

[0071] In this embodiment, the initial first gate 207 also contains a first doped ion, which is either N-type or P-type. The doping method for the doped ion includes ion implantation. The first doped ion can adjust the threshold voltage of the subsequently formed semiconductor device and reduce the gate resistivity of polysilicon.

[0072] The method for forming the initial first gate structure 205 includes: forming an initial first gate layer on a first region 201; and patterning the initial first gate layer to form the initial first gate 207.

[0073] In this embodiment, the method of patterning the initial first gate layer includes: forming a first hard mask material layer on the surface of the initial first gate layer; patterning the first hard mask material layer to form a first hard mask layer 208, wherein the first hard mask layer 208 exposes a portion of the surface of the initial first gate layer; using the first hard mask layer 208 as a mask, etching the initial first gate layer until the surface of the substrate 200 is exposed to form the initial first gate 207.

[0074] In this embodiment, before forming the initial first gate layer, a first gate dielectric material layer is formed on the surface of the first region 201; after etching the initial first gate layer, the first gate dielectric material layer is etched to form the first gate dielectric layer 206.

[0075] The material of the first hard mask layer 208 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0076] Please refer to Figure 4 First source / drain regions 209 are formed in the first regions 201 on both sides of the initial first gate structure 205.

[0077] The initial first gate structure 205 is located at the bottom and forms a channel between the first source and drain regions 209, and the direction of the gate length refers to the direction of the channel length.

[0078] Please refer to Figure 5 A first contact layer 210 is formed on the surface of the first source / drain region 209.

[0079] The material of the first contact layer 210 is a metal silicide.

[0080] The method for forming the first contact layer 210 includes: forming a protective layer on the surface of the initial first gate structure 205; forming a metal silicide layer on the surface of the first source / drain region 209 using a self-aligned silicide process to form the first contact layer 210; and removing the protective layer after forming the first contact layer 210.

[0081] The first contact layer 210 is located on the surface of the first source / drain region 208, and its resistivity is lower than that of the first source / drain region 208, thereby reducing the contact resistance between the first source / drain region 209 of the device and the subsequently formed contact plug, and improving the performance of the device.

[0082] Please refer to Figure 6 An interlayer dielectric layer 211 is formed on the surface of the substrate 200, and the interlayer dielectric layer 211 is also located on the initial first gate structure 205 (e.g., Figure 5 (As shown) Sidewall surface.

[0083] In this embodiment, the interlayer dielectric layer 211 exposes the top surface of the initial first gate 207. In other embodiments, the interlayer dielectric layer 211 does not expose the top surface of the initial first gate 207.

[0084] The interlayer dielectric layer 211 is used to isolate metal interconnects and devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field-effect transistors when metal spans different regions.

[0085] The material of the interlayer dielectric layer 211 includes silicon oxide.

[0086] The method for forming the interlayer dielectric layer 211 includes: depositing an interlayer dielectric material layer on the surface of the substrate 200, the surface of the first contact layer 210, and the sidewall surface of the initial first gate structure 205 using a chemical vapor deposition process; and planarizing the interlayer dielectric material layer using a chemical mechanical polishing process until the top surface of the initial first gate 207 is exposed.

[0087] Please refer to Figure 7 At least one first gate opening 212 is formed on the surface of the initial first gate 207, so that the initial first gate structure 205 (as shown in the figure) is used. Figure 5 As shown) forms a first gate structure 213, and with the initial first gate 207 (as shown) Figure 5 As shown, the first gate 214 is formed.

[0088] The method for forming the first gate opening 212 and the first gate 214 includes: forming a patterned layer on the surface of the initial first gate 207, the patterned layer exposing a portion of the surface of the initial first gate 207; etching the initial first gate 207 using the patterned layer as a mask to form the first gate 214 and the first gate opening 212; and removing the patterned layer after forming the first gate opening 212.

[0089] The depth of the first gate opening 212 is less than the thickness of the first gate 214. A portion of the initial first gate 207 is retained at the bottom and sidewalls of the first gate opening 212 to form the first gate 214.

[0090] In this embodiment, the number of first gate openings 212 is two. In other embodiments, the number of first gate openings is not limited to two.

[0091] In this embodiment, the dimension of the first gate opening 212 along the gate length direction is less than or equal to 2 micrometers. In other embodiments, the dimension of the first gate opening 212 is not limited.

[0092] Subsequently, a second gate material will be filled into the first gate opening 212 to form a second gate.

[0093] Please refer to Figure 8 In the first gate opening 212 (e.g. Figure 7 A second gate 215 is formed inside (as shown), and the materials of the first gate and the second gate are different.

[0094] The method of forming the second gate 215 includes: filling the first gate opening 212 with a second gate material layer; planarizing the second gate material layer until the surface of the first gate 214 is exposed to form the second gate 215.

[0095] The process of filling the first gate opening 212 with a second gate material layer includes atomic layer deposition, physical vapor deposition, or electroplating. In this embodiment, the process of filling the first gate opening 212 with a second gate material layer is atomic layer deposition.

[0096] The process for planarizing the second gate material layer includes a mechanical-chemical polishing process.

[0097] The material of the second gate 215 includes metals, such as copper, aluminum or tungsten.

[0098] Because the resistivity of the second gate material is lower than that of the first gate material, the gate composed of the first gate 214 and the second gate 215 has a lower resistivity. The size of the first gate 214, the first gate opening 212, and the material properties of the second gate 215 collectively determine the performance of the gate composed of the first gate and the second gate. A gate with a target resistivity can be obtained by adjusting the size of the first gate opening 212 and the material properties of the second gate 215.

[0099] Subsequently, a contact plug is formed on the second gate. Since the resistivity of the second gate material is lower than that of the first gate material, it is not necessary to run a metal silicide process, which reduces the contact resistance between the first gate 214 and the contact plug, saving process steps.

[0100] The process for filling the gate material includes atomic layer deposition. This atomic layer deposition process has excellent step coverage, ensuring that the first gate opening 212 is well filled.

[0101] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 8The system includes: a substrate 200, the substrate including a first region 201; a first gate structure 213 located on the first region 201, the first gate structure 213 including a first gate 214, the first gate 214 having at least one first gate opening 212 (e.g., ...). Figure 7 (as shown); a second gate 215 is located within the first gate opening 212, and the material of the second gate 215 is different from the material of the first gate 214.

[0102] The resistivity of the material of the second gate 215 is lower than that of the material of the first gate.

[0103] The second gate 215 is made of metal; the first gate is made of polysilicon.

[0104] The first gate 214 contains a first doped ion, which is an N-type ion or a P-type ion.

[0105] The semiconductor structure further includes a first source / drain region 209 located in the substrate on both sides of the first gate structure 213.

[0106] The semiconductor structure further includes: a first contact layer 210 located on the surface of the first source / drain region 209; the material of the first contact layer 210 is a metal silicide layer.

[0107] The depth of the first gate opening 212 is less than the thickness of the first gate 214.

[0108] The first gate structure 213 further includes a first gate dielectric layer 206 located between the first gate 214 and the substrate 200.

[0109] The material of the first gate dielectric layer 206 is silicon oxide.

[0110] Figures 9 to 16 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to another embodiment of the present invention.

[0111] Please refer to Figure 9 A substrate 300 is provided, the substrate including a first region 301 and a second region 302.

[0112] In this embodiment, the first region 301 is used to form a first region device; the second region 302 is used to form a second region device.

[0113] The substrate 300 further includes a base 303 and an insulating isolation structure 305 located on the upper part of the substrate 300. The isolation structure is used to achieve electrical insulation between different semiconductor devices. The material of the base 303 includes single-crystal silicon, and the material of the isolation structure 305 includes silicon oxide.

[0114] In this embodiment, the deep well 304 is an N-type well, and its formation method includes: implanting phosphorus ions into the substrate along a direction perpendicular to the substrate 300, with an implantation energy of 10 kEV to 3000 kEV and an implantation dose of 10 12 cm -2 ~10 14 cm -2 This forms the deep well 304. In other embodiments, the deep well is formed by implanting boron ions into the substrate to form a P-type well.

[0115] In this embodiment, an initial first gate structure is subsequently formed on the first region 301, the initial first gate structure including a first gate; a dummy gate structure is formed on the second region 302, the dummy gate structure including a dummy gate layer. The formation process of the initial first gate structure and the dummy gate structure is as follows: Figures 10 to 12 As shown.

[0116] Please refer to Figure 10 An initial first gate layer 306 is formed on the first region 301; an initial dummy gate layer 307 is formed on the initial first gate layer 306 and on the second region 302; and a second hard mask material layer 401 is formed on the initial dummy gate 307.

[0117] In this embodiment, the thickness of the initial dummy gate layer 307 is less than or equal to the thickness of the initial first gate layer 306, which facilitates the subsequent synchronous etching to form the dummy gate structure and the initial first gate structure.

[0118] The material of the second hard mask material layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. The second hard mask material layer 401 is used to form the initial second hard mask layer.

[0119] The initial first gate layer 306 is made of polysilicon. The initial first gate layer 306 is used for the subsequent formation of the first gate.

[0120] The initial first gate layer 306 contains first doped ions, which are N-type or P-type ions. The doping method for the first doped ions includes ion implantation. The first doped ions can adjust the threshold voltage of the subsequently formed semiconductor structure and reduce the resistivity of the first gate.

[0121] The method for forming the initial first gate layer 306 includes: forming a first gate material layer (not shown in the figure) on the surface of the substrate 300, patterning the first gate material layer, exposing the surface of the second region 302, and forming the initial first gate layer 306.

[0122] In this embodiment, the method further includes: forming an initial first hard mask layer 310 on the surface of the first gate material layer, wherein the initial first hard mask layer 310 exposes the first gate material layer on the second region 302; etching the first gate material layer with the initial first hard mask layer 310 as a mask until the surface of the second region 302 is exposed, thereby forming the initial first gate layer 306.

[0123] In this embodiment, the method further includes: forming a first gate dielectric material layer (not shown in the figure) on the surface of the substrate 300 before forming the first gate material layer; etching the first gate dielectric material layer after etching the first gate material layer to form the initial first gate dielectric layer 309.

[0124] The initial dummy gate layer 307 is made of silicon. The initial dummy gate layer 307 is used for a subsequently formed dummy gate, which is then used to form a third gate.

[0125] In this embodiment, the method further includes forming an initial second gate dielectric layer 311 on the surfaces of the initial first hard mask layer 310 and the second region 302 before forming the initial dummy gate layer 307.

[0126] The initial first gate dielectric layer 309 is made of silicon oxide. The initial first gate dielectric layer 309 is used for the subsequent formation of the first gate dielectric layer.

[0127] The initial first hard mask layer 310 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. The initial first hard mask layer 310 is used for the subsequent formation of the first hard mask layer.

[0128] The initial second gate dielectric layer 311 is made of a high-k dielectric material. This initial second gate dielectric layer 311 is used to subsequently form the second gate dielectric layer. The high-k dielectric material has a dielectric constant greater than 25 and includes HfO2. The second gate dielectric layer can significantly reduce the quantum tunneling effect of the dielectric layer, thereby effectively improving gate leakage current and its resulting power consumption. In other embodiments, an oxide layer is located between the surface of the second region and the initial second gate dielectric layer. The oxide layer is made of silicon oxynitride, and its purpose is to improve the interface states between the high-k dielectric material and the substrate silicon. In other embodiments, a titanium nitride layer is located between the initial second gate dielectric layer and the initial dummy gate. This titanium nitride layer is used to adjust the threshold voltage of the subsequently formed device.

[0129] In this embodiment, the initial first gate dielectric layer 310 and the initial second gate dielectric layer 311 are formed by etching in two separate steps, and different materials are used. The initial first gate dielectric layer is an oxide layer, so the threshold voltage of the subsequently formed first gate is relatively low. If the initial first gate dielectric layer and the initial second gate dielectric layer are formed simultaneously using the same material, such as using a high-k dielectric material as the gate dielectric layer, the threshold voltage of the first gate will be high, which cannot meet the requirements of the device.

[0130] Please refer to Figure 11 The second hard mask material layer 401 is etched until the initial dummy gate layer 307 on a portion of the first region 301 is exposed, forming an initial second hard mask layer 308; the initial dummy gate layer 307 on the first region 301 is etched with the initial second hard mask layer 308 (e.g., ...). Figure 10 As shown), a transition mask layer 312 is formed on a portion of the initial first gate layer 306 until the surface of the initial first gate layer 306 is exposed.

[0131] In this embodiment, the transition mask layer 312 includes a first hard mask layer 313, which is formed by etching the initial first hard mask layer 310. After the transition mask layer 312 is formed, since the thickness of the initial dummy gate layer 307 is less than or equal to the thickness of the initial first gate layer 306, the surface of the initial first gate layer 306 and the surface of the initial second hard mask layer 308 are approximately on the same plane. This facilitates the synchronization of the subsequent etching processes to form the dummy gate structure and the first gate structure, eliminating the need for two separate etching operations.

[0132] Please refer to Figure 12 After the formation of the transition mask layer 312 (e.g.) Figure 11 As shown), remove a portion of the initial second mask layer 308 on the second region 302 (as shown). Figure 11 As shown), this exposes a portion of the initial dummy gate layer 307 of the second region 302 (as shown). Figure 10 On the surface shown, a second hard mask layer 314 is formed on the second region 302; the second hard mask layer 314 and the transition mask layer 312 (as shown) Figure 10 As shown) is the mask etching of the initial first gate layer 306 (as shown). Figure 11 The initial dummy gate layer 307 on the second region 302 (as shown) is formed until the surface of the substrate 300 is exposed, thus forming the first gate 315 and the dummy gate layer 316.

[0133] In this embodiment, the initial first gate structure 317 further includes a first gate dielectric layer 318 located between the first region 301 and the first gate 315; the dummy gate structure 319 further includes a second gate dielectric layer 320 located between the second region 302 and the dummy gate layer 316.

[0134] In this embodiment, the initial first gate structure 317 further includes a first hard mask layer located on the initial first gate; the dummy gate structure 319 further includes a second hard mask layer 314 located on the dummy gate layer 316.

[0135] In this embodiment, it further includes: removing a portion of the initial dummy gate layer 307 on the transition mask layer 312 to expose the surface of the first mask layer 313.

[0136] In this embodiment, the initial first gate layer 306 is etched using the transition mask layer 312 as a mask. In other embodiments, after exposing the surface of the first mask layer 313, the initial first gate layer 306 is etched using the first mask layer 313 as a mask.

[0137] In this embodiment, the initial first gate dielectric layer 309 is etched to form a first gate dielectric layer 318; the second gate dielectric material layer 311 is etched to form a second gate dielectric layer 320.

[0138] Please refer to Figure 13 A first source / drain region 321 is formed in the first region 301 on both sides of the initial first gate structure 317; a second source / drain region 322 is formed in the second region 302 on both sides of the dummy gate structure 319; a first contact layer 323 is formed on the surface of the first source / drain region 321; and a second contact layer 400 is formed on the surface of the second source / drain region 322.

[0139] The region between the first source and drain regions 321 and located below the initial first gate structure 317 forms the channel of the first region device, and the direction of the gate length refers to the direction of the channel length.

[0140] The region between the first source and drain regions 321 and located below the second pseudo-gate structure 319 forms the channel of the second region device, and the direction of the gate length refers to the direction of the channel length.

[0141] The first contact layer 323 is made of metal silicide; the second contact layer 400 is made of metal silicide.

[0142] The first contact layer 323 has a lower resistance, which can reduce the contact resistance between the first source / drain region 321 and the subsequently formed conductive plug; the second contact layer 400 has a lower resistance, which can reduce the contact resistance between the second source / drain region 322 and the subsequently formed conductive plug.

[0143] The formation process of the first contact layer 323 includes a self-aligned siliconization process; the formation process of the second contact layer 400 also includes a self-aligned siliconization process. In this embodiment, the first contact layer 323 and the second contact layer 400 are completed simultaneously in the same process, saving production costs.

[0144] Please refer to Figure 14 An interlayer dielectric layer 324 is formed on the surface of the substrate 300, and the interlayer dielectric layer 324 is located on the initial first gate structure 317 (e.g., Figure 13 The sidewall (as shown) is also located on the sidewall of the dummy gate structure 319 and exposes the top surface of the dummy gate layer 316.

[0145] This embodiment also includes: removing the first mask layer 313 and the second mask layer 314.

[0146] The interlayer dielectric layer 324 is used to isolate metal interconnects and devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field-effect transistors when metal spans different regions.

[0147] The material of the interlayer dielectric layer 324 includes silicon oxide.

[0148] The method for forming the interlayer dielectric layer 324 includes: on the substrate 300, the initial first gate structure 317 (such as...) Figure 13 The sidewalls and top surface of the pseudo-gate structure 319 (as shown) Figure 13 An interlayer dielectric material film is formed on the sidewalls and top surface of the dummy gate 316 (as shown); the interlayer dielectric material film is planarized until the upper surface of the dummy gate 316 is exposed, forming the interlayer dielectric layer 324.

[0149] The process for planarizing the interlayer dielectric material film includes a mechanical-chemical polishing process.

[0150] Please refer to Figure 15 At least one first gate opening 325 is formed within the initial first gate 315, and a first gate 326 is formed with the initial first gate 315, with the initial first gate structure 317 (as shown in the figure). Figure 13 (As shown) A first gate structure 327 is formed; the dummy gate layer 316 is removed, and a second gate opening 328 is formed in the interlayer dielectric layer 324.

[0151] The process of the first gate opening 325 includes a dry etching process.

[0152] The first gate opening 325 has a dimension of less than or equal to 2 micrometers along the gate length direction. Subsequently, a second gate material will be filled into the first gate opening 325 to form a second gate. When the second gate material is planarized using a mechanical chemical polishing process, due to the small size of the second gate, it is not easy to generate "dent" defects, thus preventing the second gate from being worn away. This further protects the first gate 326 below the second gate, thereby improving the performance of the first gate structure on the first region.

[0153] The number of first gate openings is greater than one. In this embodiment, the number of first gate openings 325 is two; in other embodiments, the number of first gate openings is not limited to two.

[0154] The parameters of the etching process include: the first etching gas includes hydrogen bromide and chlorine; the power of the etching machine is 100 watts to 1000 watts; the gas pressure in the etching chamber is 2 mTorr to 20 mTorr; the flow rate of hydrogen bromide is 10 mL / min to 500 mL / min; and the flow rate of chlorine is 10 mL / min to 500 mL / min.

[0155] The etching process for removing the dummy gate layer 316 includes one or both of dry etching and wet etching processes.

[0156] The method of etching away the dummy gate layer 316 includes etching the dummy gate layer 316 until the second gate dielectric layer 320 is exposed.

[0157] In this embodiment, to reduce process steps and save costs, the first gate opening 325 and the second gate opening 328 are formed simultaneously, and the initial first gate 315 and the removal of the dummy gate layer 316 are completed in one dry etching process. In other embodiments, the first gate opening 325 and the second gate opening 328 are not formed simultaneously. In another embodiment, the first gate opening 325 is formed using a dry etching process, while the second gate opening 328 is formed using a wet etching process.

[0158] In this embodiment, the thickness of the initial dummy gate layer 307 is less than or equal to the thickness of the initial first gate layer 306. Therefore, the thickness of the dummy gate layer 316 is less than or equal to the thickness of the initial first gate layer 315. Furthermore, while the dummy gate layer 316 is removed, the first gate opening 325 is formed within the initial first gate layer 315. The depth of the first gate opening 325 is less than the thickness of the initial first gate layer 315, without etching to the first gate dielectric layer 318.

[0159] Please refer to Figure 16A second gate material layer is formed on the surface of the interlayer dielectric layer 324, inside the first gate opening 325, and inside the second gate opening 328; the second gate material layer is planarized until the surface of the first gate 326 is exposed, forming the second gate 329 and the third gate 330.

[0160] In this embodiment, the second gate structure 331 includes a third gate 330 and a second gate dielectric layer 320.

[0161] The second gate material is a metal, such as copper, aluminum, or tungsten. The resistivity of the second gate material is lower than that of the first gate material. Therefore, the first gate region composed of the first gate 326 and the second gate 329 has a lower resistivity, and a gate with lower resistivity can be obtained without forming a metal silicide layer on the surface of the first gate 326 through a metal silicide process.

[0162] The first gate 326 has a dimension greater than 10 micrometers along the gate length direction, and the third gate 330 has a dimension less than or equal to 2 micrometers along the gate length direction.

[0163] The planarization process is a mechanochemical polishing process. During mechanochemical polishing, large-sized patterns are prone to over-polishing, resulting in "recessed" defects in the central portion. Since the first gate 326 is much larger than the third gate 330, it is prone to "recessed" defects. The wider the first gate 326, the deeper the "recessed" defects, sometimes exceeding its thickness. Because a portion of the upper layer of the first gate 326 is replaced by the second gate material, the size of the gate material region on top of the first gate 326 becomes smaller. The number and size of the first gate openings 325 determine the size of the gate material exposed on the surface of the first gate 326. A smaller size reduces the likelihood of "recessed" defects on the surface of the first gate 326, further suppressing the wear-off of the polysilicon gate material layer and thus improving device performance.

[0164] Furthermore, if the first gate 326 requires a metal silicide process to reduce its resistivity, the surfaces of the metal silicide layers of both the third gate 330 and the first gate 326 will be exposed during the planarization process. This would result in the third gate 330 being contaminated by the metal silicide, thereby reducing device performance. The technical solution described in this invention eliminates the need for the first gate 326 to undergo a metal silicide process, thus avoiding the adverse effects on device performance caused by contamination of the third gate 330 during the planarization process.

[0165] The process for filling the second gate material is atomic layer deposition. This atomic layer deposition process has excellent step coverage, ensuring that the first gate opening 325 and the second gate opening 328 are well filled.

[0166] Accordingly, another embodiment of the present invention also provides a semiconductor structure formed by the above-described forming method. Please refer to [the original text]. Figure 16 The system includes: a substrate 300, the substrate including a first region 301 and a second region 301; a first gate structure 327 located on the first region 301, the first gate structure 327 including a first gate 326, the first gate 326 having at least one first gate opening 325 (e.g., ...). Figure 15 (as shown); a second gate 329 is located within the first gate opening 325, the material of the second gate being different from that of the first gate; a second gate structure 331 is located on the second region 302.

[0167] The resistivity of the material of the second gate 329 is lower than that of the material of the first gate 326.

[0168] The second gate 329 is made of metal; the first gate 326 is made of polysilicon.

[0169] The first gate 326 contains a first doped ion, which is an N-type ion or a P-type ion.

[0170] The semiconductor structure further includes a first source / drain region 321 located in the substrate 300 on both sides of the first gate structure 327.

[0171] The semiconductor structure further includes: a first contact layer 323 located on the surface of the first source / drain region 321; the material of the first contact layer 323 is a metal silicide layer.

[0172] The second gate structure 331 includes a third gate 330, the material of which includes metal.

[0173] The second gate structure 331 further includes a second gate dielectric layer 320 located between the third gate 330 and the substrate 300.

[0174] The material of the second gate dielectric layer 320 includes a high-k dielectric material.

[0175] The second gate structure 331 further includes: a silicon oxide layer located between the substrate 300 and the second gate dielectric layer 320; and a titanium nitride layer located between the second gate dielectric layer 320 and the third gate 330.

[0176] The semiconductor structure further includes: second source / drain regions 322 located in the substrate 300 on both sides of the second gate structure 331.

[0177] The semiconductor structure further includes: a second contact layer 400 on the surface of the second source / drain region 322; the material of the second contact layer 400 is a metal silicide layer.

[0178] The first gate opening 325 has a dimension of less than or equal to 2 micrometers along the gate length direction.

[0179] The depth of the first gate opening 325 is less than the thickness of the first gate 319.

[0180] The first gate structure 327 further includes a first gate dielectric layer 318 located between the first gate 326 and the substrate 200.

[0181] The material of the first gate dielectric layer 318 includes silicon oxide.

[0182] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first region and a second region; A first gate structure located on the first region, the first gate structure including a first gate, the first gate having at least one first gate opening, the first gate having a dimension greater than 10 micrometers along the gate length direction, and the first gate opening having a dimension less than or equal to 2 micrometers along the gate length direction; A second gate is located within the first gate opening, and the material of the second gate is different from that of the first gate. A second gate structure located on the second region, the second gate structure including a third gate, the material of the third gate being the same as that of the second gate, the dimension of the third gate along the gate length direction being less than or equal to 2 micrometers.

2. The semiconductor structure as described in claim 1, characterized in that, The resistivity of the material of the second gate is lower than that of the material of the first gate.

3. The semiconductor structure as described in claim 2, characterized in that, The second gate is made of metal; the first gate is made of polycrystalline silicon.

4. The semiconductor structure as described in claim 3, characterized in that, The first gate contains a first doped ion, which is an N-type ion or a P-type ion.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first source / drain regions are located in the substrate on both sides of the first gate structure.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: The first contact layer is located on the surface of the first source / drain region; The material of the first contact layer is a metal silicide layer.

7. The semiconductor structure as described in claim 1, characterized in that... The material of the third gate includes metal.

8. The semiconductor structure as described in claim 7, characterized in that, The second gate structure further includes a second gate dielectric layer located between the third gate and the substrate.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the second gate dielectric layer includes a high-k dielectric material.

10. The semiconductor structure as described in claim 9, characterized in that, The second gate structure further includes: a silicon oxide layer located between the substrate and the second gate dielectric layer; and a titanium nitride layer located between the second gate dielectric layer and the third gate.

11. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: The second source and drain regions are located in the substrates on both sides of the second gate structure.

12. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: The second contact layer is located on the surface of the second source / drain region; The material of the second contact layer is a metal silicide.

13. The semiconductor structure as claimed in claim 1, characterized in that, The depth of the first gate opening is less than the thickness of the first gate.

14. The semiconductor structure as claimed in claim 1, characterized in that, The first gate structure further includes a first gate dielectric layer located between the first gate and the substrate.

15. The semiconductor structure as described in claim 14, characterized in that, The material of the first gate dielectric layer includes silicon oxide.

16. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; An initial first gate structure is formed on the first region, the initial first gate structure including an initial first gate; An interlayer dielectric layer is formed on the surface of the substrate, and the interlayer dielectric layer is also located on the sidewall surface of the initial first gate structure. At least one first gate opening is formed in the initial first gate, a first gate structure is formed with the initial first gate structure, and a first gate is formed with the initial first gate, wherein the dimension of the first gate along the gate length direction is greater than 10 micrometers, and the dimension of the first gate opening along the gate length direction is less than or equal to 2 micrometers. A second gate opening is formed within the interlayer dielectric layer on the second region; A second gate is formed within the first gate opening, and the materials of the first gate and the second gate are different. A third gate is formed within the second gate opening to form a second gate structure on a portion of the second region. The second gate structure includes the third gate, the material of which is the same as that of the second gate, and the dimension of the third gate along the gate length direction is less than or equal to 2 micrometers.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming an initial first gate structure includes: forming an initial first gate layer on a first region; and patterning the initial first gate layer to form the initial first gate.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the initial first gate structure further includes: doping the initial first gate with a first dopant ion, wherein the first dopant ion is N-type or P-type.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, The initial first gate structure further includes: forming a first gate dielectric layer between the initial first gate and the substrate; the material of the first gate dielectric layer includes silicon oxide.

20. The method for forming a semiconductor structure as described in claim 17, characterized in that, The initial first gate structure further includes a first hard mask layer located on the initial first gate.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The method of patterning the initial first gate layer includes: forming a first hard mask material layer on the surface of the initial first gate layer; patterning the first hard mask material layer to form a first hard mask layer, the first hard mask layer exposing a portion of the surface of the initial first gate layer; using the first hard mask layer as a mask, etching the initial first gate layer until the surface of the substrate is exposed to form the initial first gate.

22. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the first gate opening and the first gate includes: forming a patterned layer on the surface of the initial first gate, the patterned layer exposing a portion of the initial first gate surface; etching the initial first gate using the patterned layer as a mask to form the first gate and the first gate opening; and removing the patterned layer after forming the first gate opening.

23. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the interlayer dielectric layer includes: forming an interlayer dielectric material film on the substrate and on the sidewalls and top surface of the initial first gate structure; planarizing the interlayer dielectric material film to form the interlayer dielectric layer.

24. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second gate includes: filling the first gate opening with a second gate material layer; planarizing the second gate material layer until the first gate surface is exposed, thereby forming the second gate.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, The planarization process is a mechanical-chemical grinding process.

26. The method for forming a semiconductor structure as described in claim 24, characterized in that, The second gate material is a metal.

27. The method for forming a semiconductor structure as described in claim 16, characterized in that, After forming the initial first gate structure and before forming the first gate opening, the method further includes: forming first source / drain regions in the first regions on both sides of the initial first gate structure.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, Also includes: A first contact layer is formed on the surface of the first source / drain region; The material of the first contact layer is a metal silicide.

29. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second gate opening includes: forming a dummy gate structure on the second region before forming the interlayer dielectric layer, the dummy gate structure including a dummy gate layer; the interlayer dielectric layer is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate layer; removing the dummy gate layer to form the second gate opening within the interlayer dielectric layer.

30. The method for forming a semiconductor structure as described in claim 16, characterized in that, While forming a second gate within the first gate opening, a third gate is formed within the second gate opening; the method for forming the second gate and the third gate includes: forming a second gate material layer on the surface of the interlayer dielectric layer, within the first gate opening, and within the second gate opening; planarizing the second gate material layer until the first gate surface is exposed, thereby forming the second gate and the third gate.

31. The method for forming a semiconductor structure as described in claim 30, characterized in that, The process for planarizing the gate material layer is a mechanical-chemical polishing process.

32. The method for forming a semiconductor structure as described in claim 29, characterized in that, The dummy gate structure and the initial first gate structure are formed simultaneously. The method for forming the dummy gate structure and the initial first gate structure includes: forming an initial first gate layer on a first region; forming an initial dummy gate layer on the initial first gate layer and on the second region; forming a second hard mask material layer on the initial dummy gate layer; etching the second hard mask material layer until a portion of the initial dummy gate layer on the first region is exposed, forming an initial second hard mask layer; etching the initial dummy gate layer in the first region with the initial second hard mask layer until the surface of the initial first gate layer is exposed, forming a transition mask layer on a portion of the initial first gate layer; after forming the transition mask layer, removing a portion of the initial second mask layer in the second region to expose a portion of the surface of the initial dummy gate layer in the second region, forming a second mask layer on the second region; etching the initial first gate layer and the initial dummy gate layer with the second mask layer and the transition mask layer as masks until the substrate surface is exposed, forming the first gate and the dummy gate layer.

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