Configurable nonlinear filter for digital predistortion

Abstract

The present disclosure relates to configurable nonlinear filters for digital predistortion. Some embodiments herein describe a radio frequency communication system that may include a transmitter that outputs a radio frequency (RF) transmit signal, the transmitter including a digital predistortion system (DPD) that predistorts the RF transmit signal. The DPD system may include a configurable nonlinear filter having multiple rows, such as a Laguerre filter, wherein at least one row operates with a configurable decimation ratio. The DPD system may also include a decimation filter and a cross switch coupled between the decimation filters.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 198,530, filed on October 26, 2020, entitled “CONFIGURABLE NON-LINEAR FILTERFOR DIGITAL PRE-DISTORTION,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The disclosed technology relates generally to radio transceivers and, more particularly, to digital predistortion (DPD) techniques that compensate for charge trapping effects in power amplifiers. Background Art

[0004] Radio transceivers can be used in a variety of radio frequency (RF) communication systems. For example, a transceiver can be included in a base station or mobile device to send and receive signals associated with a variety of communication standards, including, for example, cellular and / or wireless local area network (WLAN) standards. Transceivers can also be used in radar systems, instrumentation, industrial electronics, military electronics, laptop computers, digital radios, and / or other electronic devices.

[0005] The RF communication system may also include a power amplifier for amplifying the RF transmission signal from the transceiver to a power level suitable for wireless transmission. There are various types of power amplifiers, including those utilizing silicon (Si) based devices, gallium arsenide (GaAs) based devices, indium phosphide (InP) based devices, silicon carbide (SiC) based devices, and gallium nitride (GaN) based devices. Various types of power amplifiers may provide different advantages in terms of cost, performance, and / or operating frequency. For example, while silicon-based power amplifiers generally offer lower manufacturing costs, some silicon-based power amplifiers are inferior to their compound semiconductor counterparts in terms of certain performance indicators.

[0006] Devices used in power amplifiers, such as field effect transistors (FETs) or bipolar transistors, can exhibit various transient non-ideal device characteristics. For example, FETs can trap charge during operation, which can temporarily change device characteristics such as effective threshold voltage and / or drain current. Hardware and / or software solutions are required to compensate for transient non-ideal behaviors, including those caused by charge trapping associated with power amplifier transistors. Summary of the invention

[0007] The present disclosure relates to digital predistortion (DPD) systems, and in particular to DPD systems including a configurable nonlinear matrix for accounting for charge trapping effects in power amplifiers. In certain embodiments, a DPD system is provided that uses a configurable nonlinear filter to provide flexibility to address charge trapping effects in power amplifiers. For example, the DPD system may include a nonlinear filter (e.g., a Laguerre filter) in which input digital transmission data is extracted using multiple extraction ratios and selectively provided to the nonlinear filter (e.g., using a cross switch) and in which the rows themselves have configurable coefficients. Thus, the nonlinear filter operates with configurable rows, columns, time constants, and extractions to provide flexibility to address charge trapping effects over a time range from a few microseconds to a few milliseconds.

[0008] The DPD system works with multiple decimated captures and / or multiple non-decimated samples, where decimation can be performed after capturing the transmit data stream and the power amplifier (PA) output data stream, and correcting the sample and sub-sample time alignment between the 2 streams.

[0009] Some embodiments may include a radio frequency (RF) communication system including: a transmitter configured to output an RF transmit signal; and a power amplifier configured to amplify the RF transmit signal. In addition, the transmitter includes a digital predistortion (DPD) system configured to predistort the RF transmit signal, the DPD system including a configurable nonlinear filter having a plurality of rows, wherein at least one row operates with a configurable decimation ratio.

[0010] In some embodiments, the DPD system includes a plurality of decimation filters, and a crossbar switch coupled between the plurality of decimation filters and the plurality of rows of the configurable nonlinear filter.

[0011] In some embodiments, at least a portion of the plurality of decimation filters have individually controllable decimation ratios.

[0012] In some embodiments, the configurable nonlinear filter operates with a plurality of different time constants.

[0013] In some implementations, the configurable nonlinear filter compensates for charge trapping effects of the power amplifier.

[0014] In some embodiments, the configurable nonlinear filter is a Laguerre filter.

[0015] In some embodiments, the Laguerre filter operates with a programmable number of filter stages corresponding to matrix columns.

[0016] In some embodiments, the plurality of coefficients of the plurality of rows are programmable.

[0017] In some embodiments, the configurable nonlinear filter further includes: a set of input decimation filters configured to selectively reduce an operating rate of the nonlinear filter.

[0018] In some embodiments, the configurable nonlinear filter further includes: a set of output interpolation filters configured to compensate for the reduced operating rate provided by the set of input decimation filters.

[0019] In some embodiments, the configurable nonlinear filter includes two or more rows of a shared infinite impulse response (IIR) filter.

[0020] In some implementations, all rows of configurable nonlinear filters share an IIR filter.

[0021] In some implementations, the IIR filter includes a transposed pipeline structure having a floating memory stage.

[0022] In some embodiments, the configurable non-linear filter further includes a first plurality of look-up tables (LUTs) configured to provide data to a plurality of rows of the configurable non-linear filter.

[0023] In some embodiments, the first plurality of LUTs are configured to provide piecewise linear interpolation of a nonlinear transfer function.

[0024] In some embodiments, the configurable nonlinear filter further includes a second plurality of LUTs configured to process data output from the plurality of rows.

[0025] In some embodiments, the DPD system further includes a GMP circuit that operates in conjunction with the configurable nonlinear filter to provide DPD.

[0026] In some embodiments, the configurable nonlinear filter is rate matched to the GMP circuit.

[0027] In some embodiments, the GMP circuit operates on a data stream and the configurable non-linear filter operates on an earlier version of the data stream.

[0028] Some embodiments may include a transmitter of an RF communication system, the transmitter comprising: a digital transmit circuit configured to generate an in-phase (I) transmit signal and a quadrature-phase (Q) transmit signal, wherein the digital transmit circuit includes a digital predistortion (DPD) system configured to predistort the I transmit signal and the Q transmit signal to compensate for downstream power amplifier nonlinearities, wherein the digital predistortion system includes a nonlinear filter having multiple rows, at least one row operating with a configurable decimation ratio.

[0029] In some embodiments, the DPD system includes a plurality of decimation filters, and a crossbar switch coupled between the plurality of decimation filters and the plurality of rows of the configurable nonlinear filter.

[0030] In some embodiments, at least a portion of the plurality of decimation filters have individually controllable decimation ratios.

[0031] In some embodiments, the configurable nonlinear filter operates with a plurality of different time constants.

[0032] In some embodiments, a configurable nonlinear filter compensates for charge trapping effects.

[0033] In some embodiments, the configurable nonlinear filter is a Laguerre filter.

[0034] In some embodiments, the Laguerre filter operates with a programmable number of filter stages corresponding to matrix columns.

[0035] In some embodiments, the plurality of coefficients of the plurality of rows are programmable.

[0036] In some embodiments, the configurable nonlinear filter further includes: a set of input decimation filters configured to selectively reduce an operating rate of the nonlinear filter.

[0037] In some embodiments, the configurable nonlinear filter further includes: a set of output interpolation filters configured to compensate for the reduced operating rate provided by the set of input decimation filters.

[0038] In some embodiments, the configurable nonlinear filter includes two or more rows of a shared infinite impulse response (IIR) filter.

[0039] In some implementations, all rows of configurable nonlinear filters share an IIR filter.

[0040] In some implementations, the IIR filter includes a transposed pipeline structure having a floating memory stage.

[0041] In some embodiments, the configurable non-linear filter further includes a first plurality of look-up tables (LUTs) configured to provide data to a plurality of rows of the configurable non-linear filter.

[0042] In some embodiments, the first plurality of LUTs are configured to provide piecewise linear interpolation of a nonlinear transfer function.

[0043] In some embodiments, the configurable nonlinear filter further includes a second plurality of LUTs configured to process data output from the plurality of rows.

[0044] In some embodiments, the DPD system further includes a GMP circuit that operates in conjunction with the configurable nonlinear filter to provide DPD.

[0045] In some embodiments, the configurable nonlinear filter is rate matched to the GMP circuit.

[0046] In some embodiments, the GMP circuit operates on a data stream and the configurable non-linear filter operates on an earlier version of the data stream.

[0047] Some embodiments describe a method of digital predistortion in an RF communication system. The method includes: generating an in-phase (I) transmit signal and a quadrature-phase (Q) transmit signal; predistorting the I transmit signal and the Q transmit signal using a digital predistortion (DPD) system to compensate for nonlinearity of a power amplifier; and configuring a decimation ratio of at least one row of nonlinear filters of the digital predistortion system. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1A is a schematic diagram of one embodiment of a radio frequency (RF) communication system.

[0049] Figure 1B is a set of graphs depicting an example of power amplifier linearization using digital predistortion (DPD).

[0050] Figure 1C is a graph of an example of output power versus input power for a power amplifier.

[0051] Figure 2A is a schematic diagram of another embodiment of an RF communication system.

[0052] Figure 2B is a schematic diagram of another embodiment of an RF communication system.

[0053] Figure 3 is a schematic diagram of another embodiment of an RF communication system in which a nonlinear Laguerre filter circuit is used to correct low frequency noise and a generalized memory polynomial (GMP) circuit is used to correct high frequency noise.

[0054] Figure 4A Illustrated is an example architecture for identifying initial conditions for Laguerre executor training.

[0055] Figure 4C The signal flow is shown for two HR filters 352, 354 (where X represents a multiplier) connected in series with floating memory according to some embodiments.

[0056] Figure 4B The signal flow for two IIR filters 352, 354 (where X represents a multiplier) in series is illustrated in accordance with some embodiments.

[0057] Figure 5 is a schematic diagram of a configurable nonlinear filter according to one embodiment.

[0058] Figure 6 is a schematic diagram of one embodiment of a Laguerre infinite impulse response (IIR) filter matrix.

[0059] Fig. 7A yes Figure 6 A schematic diagram of one embodiment of an IIR transposed structure of a Laguerre filter matrix.

[0060] Figure 7B yes Figure 6 Schematic diagram of one embodiment of a transposed pipelined IIR structure of a Laguerre filter matrix.

[0061] Figure 8 is a diagram depicting one embodiment of capture of extraction data for adaptation. DETAILED DESCRIPTION

[0062] The following detailed description of the embodiments presents various descriptions of specific embodiments of the present invention. However, the present invention can be implemented in many different ways. In this specification, reference is made to the accompanying drawings in which the same reference numerals may represent the same or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it should be understood that some embodiments may include more elements than a subset of the elements shown in the accompanying drawings and / or the accompanying drawings. In addition, some embodiments may combine any suitable combination of features from two or more accompanying drawings.

[0063] As described above, devices for power amplifiers can be based on a variety of different semiconductor material systems. For example, some power semiconductor devices are based on silicon technology, such as Si-based laterally diffused metal oxide semiconductor (LDMOS) devices, which can provide cost advantages over other types of power semiconductor devices. For certain applications, such as those requiring relatively high frequencies (e.g., in excess of 4 GHz), relatively high powers (e.g., in excess of 100 W), and / or relatively high power efficiency, compound semiconductor-based power semiconductor devices (e.g., GaN-based power amplifiers) can be used as a higher performance alternative. GaN-based power amplifiers have certain advantages over other technologies (e.g., silicon-based technologies), including improvements in efficiency and frequency range (e.g., higher unity-gain cutoff frequency or f T ) and other advantages.

[0064] While demand for high-performance power amplifiers based on compound semiconductors such as GaN has been steadily rising, their implementation has been limited to relatively low-volume applications, such as military / aerospace. Limited implementation is due in part to manufacturing costs, which are currently significantly higher than silicon-based technologies.

[0065] In addition to cost considerations, certain technical improvements are also needed in compound semiconductor based power semiconductor devices. One such improvement is associated with reducing charge trapping and / or mitigating the effects of charge trapping that have been observed in power amplifiers. A variety of adverse effects of charge trapping have been observed, including but not limited to transconductance frequency dispersion, current collapse of DC drain characteristics, gate hysteresis transients, drain hysteresis transients, and / or limited microwave power output.

[0066] Digital predistortion (DPD) systems operate by manipulating a baseband representation of a communication signal. For example, digital compensation may be applied to the in-phase (I) and quadrature-phase (Q) components of a baseband signal using a lookup table (LUT) and / or multipliers to create a predistorted signal at baseband. When the predistorted signal is upconverted to radio frequency (RF), the added predistortion components allow the downstream power amplifier to output an RF waveform that is closer to the intended linear upconversion of the original baseband signal.

[0067] The present disclosure relates to DPD systems, and more particularly to DPD systems including a configurable nonlinear matrix for accounting for charge trapping effects of a power amplifier.

[0068] In certain embodiments, a DPD system is provided that uses a configurable nonlinear filter to provide flexibility to address charge trapping effects in a power amplifier. For example, the DPD system may include a nonlinear filter (e.g., a Laguerre filter) in which input digital transmission data is decimated using multiple decimation ratios and selectively provided to different rows of the nonlinear filter (e.g., using a crossbar switch) and in which the rows themselves have configurable coefficients. Thus, the nonlinear filter provides flexibility with configurable rows, time constants, and decimation operations to address charge trapping effects over a time range from a few microseconds to a few milliseconds.

[0069] The DPD system works with multiple decimated captures and / or multiple non-decimated samples, where decimation can be performed after capturing the transmit data stream and the power amplifier (PA) output data stream and correcting the sample and sub-sample time alignment between the two streams.

[0070] Example of an RF communication system using a DPD circuit

[0071] Figure 1Ais a schematic diagram of an embodiment of an RF communication system 10. The RF communication system 10 includes a transceiver 1, a front-end system 2, and an antenna 3. The transceiver 1 includes a DPD circuit 4 and an input power directional coupler 6, and the front-end system 2 includes a power amplifier 5 and an output power directional coupler 7.

[0072] For clarity, only certain components of the transceiver 1 and the front-end system 2 are depicted. However, the transceiver 1 and the front-end system 2 may include additional components. In addition, other configurations of input power detection and output power detection are also possible, including but not limited to configurations in which the input power detection is performed on the front-end system 2.

[0073] like Figure 1A As shown, the transceiver 1 provides an RF transmit signal TX to a front-end system 2. In addition, the RF transmit signal TX is amplified by a power amplifier 5 to generate an amplified transmit signal for an antenna 3.

[0074] In this example, the input power directional coupler 6 provides a local observation of the input power of the power amplifier. In addition, the output power directional coupler 7 is used to generate an observation signal OBS indicating the output power of the power amplifier. Therefore, the transceiver 1 operates using observation data indicating the input power and output power of the power amplifier. Although one example of an observation circuit for input power and output power is described, observation can be performed in other ways.

[0075] In the illustrated embodiment, the transceiver 1 generates an RF transmit signal TX with predistortion provided by a DPD circuit 4. The DPD circuit 4 may be implemented with a configurable nonlinear matrix according to one or more features of the present disclosure.

[0076] Figure 1B is a set of graphs 120, 140, 160 depicting an example of power amplifier linearization using DPD. The graphs include Figure 1A A first graph 120 of the output signal of the DPD circuit 4 versus the input signal. The graph also includes Figure 1A A second graph 140 of the output signal of the power amplifier 5 versus the input signal. The graph also includes Figure 1A The output signal of the combination of the DPD circuit 4 and the power amplifier 5 is a third graph of the signal 160 .

[0077] like Figure 1B As shown, DPD operates to provide pre-emphasis that compensates for power amplifier nonlinearities. For example, DPD can be performed on a complex envelope at baseband to provide a curve fit to an inverse model of the power amplifier. For example, a sum of polynomials can be fit to a desired envelope shape that compensates for power amplifier nonlinearities.

[0078] Figure 1CFIG. 1 is an example of a graph 180 of output power versus input power of a power amplifier. Graph 180 shows the output power of a power amplifier with and without DPD. Figure 1A Example performance of power amplifier 5. Figure 1C As shown, when DPD is used, the power amplifier 5 can be operated at a higher input power without gain compression.

[0079] Example RF communication system uses observation data to train the DPD circuit

[0080] Figure 2A is a schematic diagram of another embodiment of an RF communication system 60. The RF communication system 60 includes a transceiver 51, a front-end system 12, and an antenna 13.

[0081] like Figure 2A As shown, the transceiver 51 provides an RF transmission signal TX to the front-end system 12, and receives an observation signal OBS from the front-end system 12. Figure 2A Not shown, additional signals may be transmitted between the transceiver 51 and the front-end system 12, such as receive signals, control signals, additional transmit signals, and / or additional observation signals.

[0082] In the illustrated embodiment, the transceiver 51 includes a digital transmit circuit 52, an I path digital-to-analog converter (DAC) 23a, a Q path DAC 23b, an I path mixer 24a, a Q path mixer 24b, a variable gain amplifier (VGA) 25, a directional coupler 26, a LO 27, and an observation receiver 29. The digital transmit circuit 52 includes a DPD circuit 53.

[0083] Although one example of a transceiver with DPD is shown, the teachings herein are applicable to transceivers implemented in a variety of ways. Thus, other implementations are possible.

[0084] In the illustrated embodiment, the digital transmit circuit 52 generates a pair of orthogonal signals, corresponding to a digital I signal and a digital Q signal. The digital I signal and the digital Q signal are generated by a DPD. The DPD circuit 53 may include a configurable nonlinear filter implemented according to any embodiment herein.

[0085] In the illustrated embodiment, the I-path DAC 23a converts the digital I signal from the digital transmission circuit 22 into a differential analog I signal. The I-path mixer 24a receives the I clock signal from the LO 27, and the I-path mixer 24a uses the signal to up-convert the differential analog I signal. The Q-path DAC 23b converts the digital Q signal from the digital transmission circuit 22 into a differential analog Q signal. In the absence of quadrature error, the analog I signal and the analog Q signal have a phase separation of 90 degrees and can be used as a complex representation of the signal to be transmitted. The Q-path mixer 24b receives the Q clock signal from the LO 27, and the Q-path mixer 24b uses the Q clock signal to up-convert the differential analog Q signal. The output of the I-path mixer 24a and the output of the Q-path mixer 24b are combined to produce a differential up-converted signal, which is amplified by the VGA 25 to produce the RF transmission signal TX. In this example, the I clock signal and the Q clock signal are differential.

[0086] like Figure 2A As shown, the observation receiver 29 processes the local observation signal from the directional coupler 26 and the observation signal OBS from the front-end system 12 to generate observation data provided to the digital transmission circuit 52. The observation data can be used to train the DPD circuit 53. The observation data can also be used for a variety of other functions, such as transmission power control.

[0087] In the illustrated embodiment, I path mixer 24a and Q path mixer 24b are analog mixers that mix analog I and Q signals.

[0088] Figure 2B is a schematic diagram of another embodiment of an RF communication system 70. The RF communication system 70 includes a transceiver 61, a front-end system 12, and an antenna 13.

[0089] In the illustrated embodiment, transceiver 61 includes digital transmit circuitry 52 (including DPD circuitry 53 ), digital mixer 42 , RF digital-to-analog converter (DAC) 45 , VGA 25 , directional coupler 26 , LO 27 , and observation receiver 29 .

[0090] and Figure 2A 60 compared to the RF communication system, Figure 2B The RF communication system 70 is implemented to perform mixing before analog-to-digital conversion. Figure 2A 60 compared to the RF communication system, Figure 2B The RF communication system 70 uses the digital mixer 42.

[0091] In the illustrated embodiment, the digital mixer 42 receives a digital I signal and a digital Q signal from a digital transmit circuit 52. The digital I signal and the digital Q signal are generated using DPD. The DPD circuit 53 may include a configurable nonlinear filter implemented according to any embodiment herein. The digital mixer 52 also receives an I clock signal and a Q clock signal from the LO 27. In addition, the digital mixer 52 outputs a digital representation of the up-converted transmit signal, which is processed by the RF ADC 43 to generate an analog up-converted transmit signal (differential in this example). The analog up-converted transmit signal is amplified by the VGA 25 to produce the RF transmit signal TX.

[0092] In some embodiments, the digital mixer 42 is used to calculate ((I*LO_I)-(Q*LO_Q)), where I is the digital I signal, Q is the digital Q signal, LO_I is the I clock signal, and LO_Q is the Q clock signal.

[0093] In the illustrated embodiment, the transceiver can process signals of various frequencies, including not only RF signals between 30 MHz and 7 GHz, but also higher frequency signals, such as X-band (approximately 7 GHz to 12 GHz), K-band, and u frequency band (about 12GHz to 18GHz), K band (about 18GHz to 27GHz), K a The present invention relates to signals in the RF band (approximately 27 GHz to 40 GHz), the V band (approximately 40 GHz to 75 GHz), and / or the W band (approximately 75 GHz to 110 GHz). Thus, the teachings herein are applicable to a variety of RF communication systems, including microwave systems.

[0094] Example of an RF Communication System Using a Laguerre Filter

[0095] Figure 3 is a schematic diagram of another embodiment of an RF communication system 300, wherein a nonlinear Laguerre filter circuit 310 is used to correct low frequency noise and a generalized memory polynomial (GMP) circuit 312 is used to correct high frequency noise. The RF communication system 300 can correct for charge trapping effects and broadband distortion of a power amplifier.

[0096] Figure 3 RF communication system 300 is illustrated, which includes a first nonlinear filter network for correcting narrowband distortion (in this example, a nonlinear Laguerre filter circuit 310) and a second nonlinear filter network for correcting wideband distortion (in this example, a GMP circuit 312) according to some embodiments. RF communication system 300 may include actuator 302, power amplifier 304 (in this example, including FETs, such as GaN FETs), least squares module 306, and feedback actuator 308.

[0097] In the illustrated embodiment, the actuator 302 may include a first nonlinear filter network 310 configured to compensate for narrowband distortion of the power amplifier, such as frequencies from 10kHz to 0.1Hz. The first nonlinear filter network 310 may include a plurality of nonlinear filters, such as infinite impulse response (IIR) filters. In this embodiment, the IIR filters may be used together as Laguerre filters. The first nonlinear filter network 310 may include a cascade or chain of IIR filters. In some embodiments, the first filter is a low pass filter, and the subsequent filters in the IIR filter chain are all pass filters. In some embodiments, the filters of the first nonlinear filter network 310 are orthogonal to each other. The use of IIR filters enables the system to use long time constants to resolve narrowband charge trap effects. It is not known that Laguerre filters are used to correct narrowband charge trapping effects. The nonlinear filter may be implemented according to any embodiment herein.

[0098] In some embodiments, the second nonlinear filter network 312 can be configured to compensate for the broadband distortion of the power amplifier. The second nonlinear filter network 312 can include multiple nonlinear filters, such as a finite impulse response (FIR) filter. The FIR filter can be used together as a general memory polynomial (GMP) filter or a GMP circuit. In some embodiments, the second nonlinear filter network 312 may include a digital predistortion (DPD) system and / or a DPD filter network that compensates for broadband distortion. The GMP circuit can be configured to compensate for the high frequency noise of the power amplifier. Although an example with a GMP circuit is shown, other implementations are also possible, including but not limited to the implementation of the filter implementation Volterra series.

[0099] In some embodiments, the input signal x is fed into a first nonlinear filter network 310 to produce a signal that compensates for narrowband distortion. The same input signal can be fed into a second nonlinear filter network 312 to compensate for wideband distortion. The combination of the outputs of the first nonlinear filter network 310 and the second nonlinear filter network 312 is added by an adder 314. The output of the adder 314 is fed into the power amplifier 304. In some embodiments, the input signal x corresponds to a digital data stream (e.g., in-phase (I) and quadrature (Q) data) provided by a baseband processor.

[0100] Although shown as being provided directly to power amplifier 304, the output of adder 314 may correspond to an RF transmit signal that is provided to the input of power amplifier 304 by one or more digital-to-analog converters (DACs), one or more mixers, one or more variable gain amplifiers (VGAs), and / or other circuits to generate an RF transmit signal.

[0101] In some embodiments, the output and input of the power amplifier 304 are also used to fit an inverse model, such as a feedback actuator 308. The feedback actuator can be used to train an actuator for applying DPD. The output of the power amplifier 304 can be fed into another first nonlinear filter network 318 and another second nonlinear filter network 316. In some embodiments, the input power and / or output power of the power amplifier 304 is captured by a directional coupler and then processed by an observation receiver to generate a digital representation of the observed power.

[0102] Continue to refer Figure 3 , the adder 320 adds the outputs of the other first nonlinear filter network 318 and the other second nonlinear filter network 316. Then, in this embodiment, the input of the power amplifier 304 is subtracted from the output of the adder 320 through another adder 322. The output of the other adder 322 is processed by the least squares module 306. The output of the least squares module 306 is used by the other second nonlinear filter network 316.

[0103] In some embodiments, the feedback actuator can include a first nonlinear filter network, such as a Laguerre filter, and a second nonlinear filter network, such as a GMP filter.

[0104] In some embodiments, the first nonlinear filter network is arranged in parallel with the second nonlinear filter network. In the illustrated embodiment, the nonlinear filter and the GMP circuit are arranged in parallel. In other embodiments, the first nonlinear filter network is arranged in series with the second nonlinear filter network. The first nonlinear filter network is arranged after the second nonlinear filter network, wherein the second nonlinear filter network adapts to high frequency distortion and the first nonlinear filter network adapts to low frequency charge trapping distortion.

[0105] In the illustrated embodiment, the power amplifier 304 amplifies an RF signal having a carrier frequency. In addition, the narrowband distortion corrected by the first nonlinear filter network 310 (e.g., a Laguerre filter) may correspond to a limited bandwidth around the carrier frequency and distortion occurring on a long time scale associated with charge trapping dynamics. For example, the bandwidth BW near the carrier frequency may be inversely proportional to the time constant τ (BW∝1 / τ), so the charge trapping effect is associated with a long time constant and a narrow bandwidth. This narrowband distortion is also referred to herein as the low-frequency noise of the power amplifier.

[0106] In the illustrated embodiment, the broadband distortion corrected by the second nonlinear filter network 312 (e.g., GMP filter) may include nonlinearities in the power amplifier (non-charge trap nonlinearities) that occur on a shorter time scale than narrowband distortion. Therefore, the time constant associated with this nonlinearity is small and the corresponding bandwidth is wide. This broadband distortion is also referred to herein as high-frequency noise of the power amplifier.

[0107] Figure 4A An example architecture 400 for constructing a Laguerre filter matrix using 1 row and 3 columns of Laguerre filters is illustrated. The first filter in each row may include a low pass filter, while the other filters in the same row may all be low pass filters. All filters are IIR filters. The transfer function of these IIR filters is

[0108]

[0109] L0 is a low-pass filter and L1 is an all-pass filter (τ delay).

[0110] "tau" is the time constant and Fs is the sampling rate at which the Laguerre structure operates.

[0111] Figure 4B The signal flow of 2 IIR filters 352, 354 (where X represents a multiplier) in series is shown according to some embodiments. The first filter 352 in the lower figure is L0, where b01 = 0; therefore the multiplier disappears.

[0112] Figure 4C The signal flow of two IIR filters 352, 354 (where X represents a multiplier) in series with floating memory according to some embodiments is illustrated. In order to reuse multipliers and adders across clock cycles for IIR calculations, the system can implement floating memory elements mem1 472 and mem2 474 that remember the output of each IIR filter and use it as the input of the next IIR filter in the next clock cycle.

[0113] Although certain embodiments herein are described in the context of Laguerre filters, the teachings herein are applicable to other implementations of nonlinear filters.

[0114] Example Architecture of a Configurable Nonlinear Filter

[0115] Figure 5 is a schematic diagram of a configurable nonlinear filter 500 according to one embodiment. In this example, the configurable nonlinear filter is implemented using a Laguerre filter configuration.

[0116] In the illustrated embodiment, Figure 5The configurable nonlinear filter 500 provides flexibility in accounting for charge trapping effects in a power amplifier.

[0117] In the illustrated embodiment, the configurable nonlinear filter 500 includes a multiplexer 502 that receives various signals (in this example, including input signals, intermediate signals, and output signals) captured from a signal path via a crest factor reduction (CFR) circuit, explained in more detail below. In some embodiments, the configurable nonlinear filter 500 receives not only the output of the CFR circuit, but also the input of the CFR circuit and / or the intermediate signal of the CFR circuit. The output of the CFR circuit can be a signal obtained from the output of the CFR circuit before the signal is sent to the GMP executor.

[0118] In the embodiment shown, the Laguerre filter operates on amplitude, so the filter can be used as Figure 5 The CORDIC engine 506 shown operates with an amplitude extractor. In some implementations, the CORDIC 506 engine operates using only adders and no multipliers, thereby simplifying the hardware implementation. Although an embodiment using a CORDIC 506 is described, other implementations are possible. The CORDIC engine 506 provides a signal amplitude representing the signal envelope.

[0119] In the illustrated embodiment, a set of first order cascaded integrator comb (CIC) decimation filters 512A, 512B, 512C, 512D are included to reduce the operating rate of the Laguerre filter matrix. A variety of decimation ratios are supported. In some embodiments, an integrate and dump filter is included to eliminate the comb structure in the CIC. The decimation filters 512A, 512B, 512C, 512D can perform decimation in parallel. ZZ

[0120] In the illustrated embodiment, data is decimated using multiple decimation ratios and selectively provided to different rows of the nonlinear filter (using crossbar switch 516 in this example) and wherein the rows themselves have configurable coefficients. Thus, the nonlinear filter operates with configurable rows, columns, time constants, and decimation to provide flexibility to address charge trapping effects over a time range spanning from a few microseconds to a few milliseconds.

[0121] In the illustrated embodiment, the four decimation filters 512A, 512B, 512C, 512D each have a different decimation ratio. Therefore, four copies of the same input signal can be decimated with different decimation ratios.

[0122] In the illustrated embodiment, delay management can also be used to match the CT DPD data path with the GMP data path. For example, since the CIC decimation filters 512A, 512B, 512C, 512D are included in Figure 5In an embodiment of the present invention, the CT DPD data path may have a higher group delay than the GMP path. Although more delay may be intentionally introduced in the GMP path, such delay is undesirable.

[0123] To avoid the negative effects of GMP path delays, the input to the nonlinear filter data path can be tapped from an "early" point. Thus, rather than providing the same input data stream to the configurable nonlinear filter 500 and the GMP circuit, the configurable nonlinear filter 500 can operate using earlier data. For example, a crest factor reduction (CFR) circuit and one or more half-band filters can be used to process the data stream provided to the GMP circuit, and the nonlinear filter can receive data before the CFR circuit and / or the half-band filter.

[0124] To balance the overall delay, the delay can be spread between the decimation rate and the input rate and the final output rate. In addition, by delaying at the decimation rate, the delay line cost is reduced. For example, since 1 delay unit at the decimation rate (input rate is N) is equal to N delay units at the input rate, the delay line is reduced by a factor of N. The configurable nonlinear filter 500 can apply delays before and / or after signal decimation. For example, fine delays 510A, 510B, 510C, 510D (fine delay 510) can be applied before decimation, and coarse delays 514A, 514B, 514C, 514D (coarse delay 514) can be applied after decimation.

[0125] like Figure 5 As shown, a crossbar switch 516 is included to route any CIC decimation filter to any row of the Laguerre filter matrix. Thus, the crossbar switch facilitates routing data associated with a particular decimation rate to 1 row or multiple rows (time constants). Since the rows have configurable coefficients, they can operate at different time constants, thus providing flexibility for a variety of decimation ratios and time constants. In the illustrated example, there are eight Laguerre filter banks. The crossbar switch 516 determines which of the four signals will be processed by the eight corresponding Laguerre filters. Thus, the system can evaluate different models spanning different time constants, reducing the load on calibrating the system for a specific power amplifier. Another advantage is that while a given temperature will exhibit a specific time constant as charge trapping is reactivated, due to the multiple time constant span, the system does not need to track the time constant changes of the power amplifier to ambient air.

[0126] Continue to refer Figure 5 , at the input power level (kLUT 518A, 518B, 518C - collectively referred to as kLUT 518 - at Figure 5A nonlinear transfer function with a lookup table in FIG. 1 is implemented using an interpolating LUT. For example, each row in a Laguerre matrix may include an interpolating LUT.

[0127] In some implementations, the transfer function can be decomposed into K uniformly spaced piecewise linear regions. However, K non-uniformly spaced piecewise linear regions can also be used to improve local linearity and provide more piecewise regions for highly nonlinear regions.

[0128] In the illustrated embodiment, the LUT can be used to store the (x, y) coordinates of each piecewise linear region as well as the slope. In addition, the actual output is obtained by linear interpolation between two consecutive LUT values. In some implementations, the slope is calculated offline and stored in the LUT when the LUT contents are calculated. In other implementations, the slope is calculated dynamically in hardware.

[0129] In the illustrated embodiment, the LUT can be implemented in a variety of ways, for example, a K-deep LUT to store the y coordinates of each region. K can have any suitable value, including but not limited to 2. b This makes LUT address decoding simple (b MSbits input).

[0130] Continue to refer Figure 5 , the interpolation LUT is also used for the nonlinear transfer function in the Laguerre IIR output stage ( Figure 5 Fbox 524A, 524B, 524C, 524D, 524E, 524F, 524G, 524H in. Figure 5 In the example of , N LUTs are used, but only one LUT needs to be accessed in a given input cycle. Therefore, a single monolithic memory cell can be used for storage instead of N memory cells, saving area and power. In other embodiments, a non-Laguerre nonlinear filter can be used instead of a Laguerre filter.

[0131] In the illustrated embodiment, the output of the kLUT is input into Laguerre IIR filters 552A, 552B, 552C, 552D, 552E, 552F, 552G, 552H. As shown in the example below, there are eight Laguerre filter groups. Each of the eight Laguerre filter groups includes a Laguerre filter and Fboxes. For example, the first Laguerre filter group may include Laguerre IIR filters 552A, 552B, 552C, 552D and Fboxes 524A, 524B, 524C, 524D. The fourth Laguerre filter group may include Laguerre IIR filters 552E, 552F, 552G, 552H and Fboxes 524E, 524F, 524G, 524H. In this example, 32 IIR filters are used. As shown in the example below, Figure 5 As shown, Fbox accumulators 530A, 530B are used to sum the Fbox outputs in each row. Fboxes can calculate the nonlinearity of the Laguerre filter output, which is the actual actuator function of the nonlinear gate correction.

[0132] In the illustrated embodiment, first-order CIC interpolators 532A, 532B are included at the output to reverse the effects of CIC decimation at the input. Thus, CIC interpolators 532A, 532B cancel decimation of the signal by interpolating the signal at a rate before decimation occurs. Use of first-order CIC interpolators 532A, 532B allows simple sample repetition, thus low cost and little or no performance degradation. However, other implementations are also possible. The outputs of CIC interpolators 532A, 532B may be added via adder 534 to produce a Laguerre filter output.

[0133] In some embodiments, a second order CIC interpolator (linear interpolator 538) is used to change the input rate to match the CTDPD data path rate (eg, which may be 1x or 2x or 4x the input rate).

[0134] In the illustrated embodiment, a filter matrix including a run-time configurable row / column structure of Laguerre IIR filters is provided. The filter matrix operates at a decimation rate of the input rate / N and provides up to "N" IIR filters and "N" F-boxes in a row plus column structure. N can be any suitable value, including, for example, between 2 and 128, or more specifically between 16 and 64 (e.g., 32). Although example values ​​of N are provided, other implementations are possible.

[0135] Continue to refer Figure 5 , Figure 5The output of the nonlinear filter can be combined with the GMP circuit (see, for example) by the adder 544. Figure 3 In combination, the rate of the nonlinear filter can be matched to the rate of the regular data path through the GMP circuit, which may be a higher rate due to the insertion of the filter in the main data path. Figure 5 The path of the configurable nonlinear filter 500 shown is also referred to herein as the CT DPD data path. For flexibility, the system may include a programmable scaling control 536 to obtain a Laguerre output. The system may include a fine delay element 540 to match the residual delay between the GMP and Laguerre paths. The system may include a delay 528 on the CT input data to compensate for the delay on the Laguerre path before the data reaches the final complex multiplier. The system may include a selector 520 that selects which decimation filter (or decimation ratio) the CT DPD adaptive algorithm uses. The adaptive algorithm processes 1 decimation rate and the rows connected to the decimation rate in a serial manner at a time. The system may include a capture buffer 526 to capture the decimated LG path data, baseband TX data, and ORX data. The content is used for the adaptive algorithm, which fine-tunes the fLUT / fBox content and provides linearization. The system may include a DPD input port 508.

[0136] Laguerre IIR filter matrix example

[0137] Figure 6 is a schematic diagram of one embodiment of a Laguerre infinite impulse response (IIR) filter matrix 600 . Fig. 7A yes Figure 6 Schematic diagram of one embodiment of an IIR transposed structure 700 of a Laguerre filter matrix. Figure 7B is used for Figure 6 Schematic diagram of one embodiment of a transposed pipelined IIR structure 750 of a Laguerre filter matrix. Figure 6-7B The filter matrix structure of can be included in the configurable nonlinear filter, for example Figure 5 Configurable nonlinear filter.

[0138] Continue to refer Figures 5 to 7B In some embodiments, each IIR filter is calculated in 1 input clock cycle, thereby using 1 HW IIR unit to calculate N IIR filters in 1 decimation cycle. This reduces the area requirement of the Laguerre filter matrix by N.

[0139] In some implementations, the rows and columns are programmable. In some implementations, the total active columns among all active rows may be limited (eg, not exceeding "N").

[0140] In some embodiments, each IIR is first order and the output is a function of the current and previous inputs and the previous output. Thus, the output of each IIR stage is remembered and used to update the state variables and calculate the output of the next state for the next cycle.

[0141] In some embodiments, the Laguerre infinite impulse response (IIR) filter matrix 600 may include multiple stages (1 to N) 602A, 602B, 602N. Each stage 602A, 602B, 602N may include multiple (1 to M) nonlinear filters, such as Laguerre IIR filters. Each (or at least some) of the 1 to M filters may include a first nonlinear low-pass filter (LPF) 604A, 604B, 604N, and may include one or more nonlinear all-pass filters 606A, 608A, 606B, 608B, 606N, 608N. For each stage 602A, 602B, 602N, the LPF and possibly one or more all-pass filters may be arranged in series. The LPF filter may receive a signal, process the signal through the LPF, output the signal to a series of all-pass filters, and then process the signal through the all-pass filters. In some embodiments, the filters of the first nonlinear filter network are orthogonal to each other. For example, an LPF may allow signals with frequencies below a certain cutoff frequency to pass through the LPF, and a subsequent all-pass filter may allow the signal to pass through with only phase modification with no or little effect on the amplitude.

[0142] Nonlinear function F(v kl ) can include v kl The memory polynomial expansion of , for example,

[0143] In some embodiments, stages 602A, 602B, 602N (e.g., 1 to M filters, each stage may include an LPF and possibly one or more all-pass filters) are arranged in parallel with each other. In some embodiments, each of the 1 to M filters includes a correction element, which is further described in detail herein. Each of the stages 602A, 602B, 602N may consider different time constants because charge trap distortion may occur in multiple responses across various time scales.

[0144] In some embodiments, a complex baseband signal is received from a digital upconverter (x), which may include an in-phase and quadrature phase (I / Q) signal. The system generates an envelope of the signal by determining an absolute signal of the complex baseband signal via an absolute value block. For example, a coordinate rotation digital computation (CORDIC) circuit may be used to process the digital I and digital Q data to generate a digital envelope. The absolute value block outputs the envelope of the signal.

[0145] In some embodiments, the system propagates the output of the absolute value block to multiple correction elements. The multiple correction elements introduce nonlinearity to the signal. For example, the multiple correction elements can adopt exponentiation of the output of the absolute value block. The first correction element can adopt the 1 exponentiation of the output of the absolute value block. The second correction element can adopt the 2 exponentiation of the output of the absolute value block. N correction elements can adopt N exponentiations of the output of the absolute value block. Thus, the correction elements adopt nonlinear powers of the envelope.

[0146] In some embodiments, the outputs of 1 to N correction elements are propagated to corresponding 1 to N nonlinear filters 602A, 602B, 602N, such as 1 to N Laguerre filters. The first filter 604A, 604B, 604N may include a low pass filter, while the remaining filters 606A, 606B, 606N, 608A, 608B, 608N may include all pass filters. The following is a digital representation of a low pass filter (LPF) and an all pass filter (BPF).

[0147] Level 0: LPF,

[0148] Level 1-L: BPF,

[0149]

[0150] a1 is the filter coefficient, F s is the sampling rate (e.g., in the range of 100MHz), and τ is the time constant of the charge trap effect (e.g., microseconds, milliseconds). The time constant can be determined by looking at the charge trap effect of the power amplifier. Then, the a1 filter coefficient can be determined.

[0151] In some embodiments, the outputs of 1 to N nonlinear filters 256A, 256B, 256N are added via an adder to generate a low-frequency gain term g. lag The low frequency gain term g lag Indicates the narrowband frequency correction gain.

[0152] In some embodiments, the low frequency gain term g lag Multiplying the complex baseband signal input through the multiplier generates a correction signal to correct the charge trapping effect u lag .

[0153] In some embodiments, the first nonlinear network and / or the second nonlinear network are at least partially implemented in software (e.g., implemented by a digital signal processor as an all-digital solution). In some embodiments, the first nonlinear network and / or the second nonlinear network are at least partially implemented in firmware.

[0154] like Fig. 7A As shown in the embodiment 700 of , the entire Laguerre IIR matrix 702 is calculated with x[n] as input and uses three multipliers 706, 708, 712 and two adders 710, 716. The Laguerre IIR matrix 702 outputs y1, which is the input of the next loop. The next loop uses the same multipliers 722, 718, 730 and adders 724, 728 to determine y2. In addition, as Figure 7B As shown, a transposed pipeline structure 750 with a floating memory stage may be used. Then for the third cycle (unseeded), y2 will become the new input to the Laguerre IIR matrix, and the same multipliers and adders will be used with y2 as the new input. Thus, the multipliers and adders are reused across time to calculate each cycle of 1 IIR. In some embodiments, except Fig. 7A In addition to the delays 714, 726, mem1 768 and mem2 772 float in space from one stage to the next across time (cycles).

[0155] exist Figure 7B In the example, input x is stored in mem2 756, and multipliers 760, 758, 770 are used to determine y1, which is used as input for the next cycle, where multipliers 776, 774, 786 and adders 778, 782 are used to calculate y2. The transposed pipeline IIR structure (only 1 multiplication and 1 cycle addition) is suitable for high frequency operation. In addition, if there is a clock that is M times faster than the input clock, M*N IIRs, Fboxes can be calculated or an input clock that is M times slower can be supported.

[0156] In some embodiments, the filter matrix is ​​implemented by arbitration. For example, IIR hardware resource arbitration between different row requestors can be used.

[0157] This arbitration can be beneficial because different rows can run at different decimation ratios and their decimation stages can be asynchronous with respect to each other, and in some implementations only one IIR hardware unit is provided to be shared across time.

[0158] In some embodiments, round-robin arbitration is used. For example, the first row "r" is granted the IIR resource for that row number; once completed, if it requests access to the IIR resource, the "r+1" row is involved; otherwise, r+2, ...

[0159] This approach is advantageous because a row cannot request a resource earlier than N cycles, where N is the decimation ratio. For example, in one implementation where N=32, the limiting case is that 7 rows request access in the same cycle, and their requests are queued to be granted; and in the very next cycle, row 8 requests access. If each row has 4 columns (4 IIRs), then 28 cycles will pass before row 8 accesses the IIR resource. It will still complete in cycles 29-32, and can only request access in cycle 33, since the minimum decimation ratio is 32.

[0160] Example timing diagram for data extraction

[0161] Figure 8 810 is a diagram depicting one embodiment of capture of decimated data for adaptation. In graph 800, the system first determines the IIR state variables to determine the current state of the IRR (first pulse of graph 810). Then, when the current state of the IIR is known, the system can begin to calculate the next output given a new input (second pulse of graph 810). Thus, the system captures samples, i.e., inputs from the next decimation cycle. The captured inputs can include the input of the Laguerre filter, the output of the power amplifier, such as graph 840. Graph 830 includes the CFR output modulated by the Laguerre filter. The decimated data capture is captured in cycles, as shown in graph 820.

[0162] In some embodiments, for a given decimation ratio across multiple time constants, adaptation is performed in software. For example, by controlling the IIR coefficients, each time constant can be handled by a given row of the Laguerre matrix. The IIR coefficients determine the time constant (and vice versa).

[0163] In the illustrated embodiment, the adaptation process attempts to obtain an estimated model of the power amplifier to which DPD is applied.

[0164] In certain embodiments herein, the decimated Laguerre output and the downsampled nonlinear filter data path signal in the model are used to construct a power amplifier model. The power amplifier output is also downsampled and processed by the observation receiver.

[0165] To produce the decimated Laguerre output in the model, the current state of the IIR filter in the actuator and the successive decimated input samples in the actuator are needed to construct the IIR output at a specific point in time. The decimated input samples can be captured simultaneously for multiple time constants (rows) along with the downsampled main nonlinear filter data path. In some implementations, the decimation and downsampling frequency and phase are programmable to allow flexibility.

[0166] In some implementations, only one decimated Laguerre input is used to capture all lines (time constant), which helps reduce capture buffer space.

[0167] in conclusion

[0168] In the above, it should be understood that any feature of any one embodiment may be combined with or substituted for any other feature of any other embodiment.

[0169] Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, etc. Examples of electronic devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, cameras such as camcorders, digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, peripheral devices, clocks, etc. In addition, electronic devices may include unfinished products.

[0170] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprises," "comprising," "containing," "having," etc. should be construed to have an inclusive rather than an exclusive or exhaustive meaning; that is, in the sense of "including but not limited to."

[0171] The foregoing description may refer to an element or feature as being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" refers to a direct or indirect connection of an element / feature to another element / feature, and is not necessarily a mechanical connection. Similarly, unless otherwise expressly stated, "coupling" refers to a direct or indirect coupling of an element / feature to another element / feature, and is not necessarily a mechanical coupling. Therefore, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intermediate elements, devices, features, or components may exist in actual embodiments (assuming that the functionality of the depicted circuit is not adversely affected). In addition, the words "herein", "above", "below", and words of similar meaning used in this application refer to the entirety of this application, rather than to any particular part of this application. Where the context permits, the words used in the above detailed description in the singular or plural may also include the plural or singular, respectively. The word "or" refers to a list containing two or more items, and the word covers all the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0172] Furthermore, conditional language used herein, such as "may," "might," "for example," and the like, unless specifically stated otherwise or otherwise understood in the context of use, is generally intended to convey that some embodiments include and other embodiments do not include certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require features, elements, and / or states or whether such features, elements, and / or states are included or will be performed in any particular embodiment.

[0173] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms; in addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and may delete, move, add, subdivide, combine, and / or modify some elements. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments. The various features and processes described above may be implemented independently of one another, or may be combined in various ways. All possible combinations and subcombinations of the features of the present disclosure are intended to fall within the scope of the present disclosure.

Claims

1. A radio frequency (RF) communication system, comprising: A transmitter configured to output an RF transmission signal; and a power amplifier configured to amplify the RF transmit signal, wherein the transmitter comprises a digital predistortion (DPD) system configured to predistort the RF transmit signal, the DPD system comprising a configurable nonlinear filter having a plurality of rows, wherein at least one row operates with a configurable decimation ratio; and Wherein, the configurable nonlinear filter compensates for the charge trapping effect of the power amplifier.

2. The RF communication system according to claim 1, wherein: The DPD system includes a plurality of decimation filters and a crossbar switch coupled between the plurality of decimation filters and the plurality of rows of the configurable non-linear filter.

3. The RF communication system according to claim 2, wherein: At least a portion of the plurality of decimation filters have individually controllable decimation ratios.

4. The RF communication system according to claim 1, wherein: The configurable nonlinear filter operates with a plurality of different time constants.

5. The RF communication system according to claim 1, wherein: The configurable nonlinear filter is a Laguerre filter.

6. The RF communication system according to claim 5, wherein: The Laguerre filter operates with a programmable number of filter stages corresponding to the columns of the matrix.

7. The RF communication system according to claim 1, wherein: The plurality of coefficients of the plurality of rows are programmable.

8. The RF communication system according to claim 1, wherein: The configurable nonlinear filter also includes: a set of input decimation filters configured to selectively reduce the operating rate of the configurable nonlinear filter; and a set of output interpolation filters configured to compensate for the reduced operating rate provided by the set of input decimation filters.

9. The RF communication system according to claim 1, wherein: The configurable nonlinear filter includes two or more rows of a shared infinite impulse response (IIR) filter.

10. The RF communication system according to claim 9, wherein: The IIR filter includes a transposed pipeline structure with a floating memory stage.

11. The RF communication system according to claim 1, wherein: The configurable non-linear filter further comprises a first plurality of look-up tables (LUTs) configured to provide data to a plurality of rows of the configurable non-linear filter.

12. The RF communication system of claim 11, wherein the first plurality of LUTs are configured to provide piecewise linear interpolation of a nonlinear transfer function.

13. The RF communication system according to claim 11, wherein: The configurable non-linear filter also includes a second plurality of LUTs configured to process data output from the plurality of rows.

14. The RF communication system according to claim 1, wherein: The DPD system also includes a generalized memory polynomial (GMP) circuit that operates in conjunction with the configurable nonlinear filter to provide DPD.

15. The RF communication system of claim 14, wherein: The configurable nonlinear filter is rate matched to the GMP circuit.

16. The RF communication system of claim 14, wherein: The GMP circuit operates on a data stream and the configurable non-linear filter operates on an earlier version of the data stream.

17. A transmitter of an RF communication system, the transmitter comprising: A digital transmission circuit is configured to generate an in-phase I transmission signal and a quadrature-phase Q transmission signal, The digital transmission circuit includes a digital predistortion DPD system, which is configured to predistort the I transmission signal and the Q transmission signal to compensate for the nonlinearity of a downstream power amplifier. wherein the digital predistortion system comprises a configurable nonlinear filter having a plurality of rows, wherein at least one row operates with a configurable decimation ratio; and Wherein, the configurable nonlinear filter compensates for the charge trapping effect of the power amplifier.

18. The transmitter according to claim 17, wherein: The DPD system includes a plurality of decimation filters and a crossbar switch coupled between the plurality of decimation filters and the plurality of rows of the configurable non-linear filter.

19. The transmitter according to claim 17, wherein: The configurable nonlinear filter operates with a plurality of different time constants.

20. The transmitter of claim 17, wherein: The configurable nonlinear filter is a Laguerre filter.

21. A method for digital predistortion in an RF communication system, the method comprising: Generate an in-phase I transmit signal and a quadrature-phase Q transmit signal; Predistorting the I transmit signal and the Q transmit signal using a digital predistortion DPD system to compensate for nonlinearity of a power amplifier; and Configuring a decimation ratio of at least one row of a configurable nonlinear filter of the digital predistortion (DPD) system; Wherein, the configurable nonlinear filter compensates for the charge trapping effect of the power amplifier.

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