Operation Clock Generation Device and Reference Clock Gating Circuit

Abstract

An operating clock generating device and a reference clock gating circuit. The gating circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter that counts according to the trigger of the external clock to generate a first clock number; a second counter that counts according to the trigger of the low-speed clock of a crystal oscillator to generate a second clock number, wherein the frequency of the low-speed clock is lower than the frequency of the external clock; and a determination circuit that, when the second clock number reaches a preset number, determines whether the ratio of the first clock number to the second clock number satisfies a preset condition, and generates a gating signal accordingly. If the gating signal indicates that the ratio satisfies the preset condition, the gating component receives the external clock and outputs the external clock as the reference clock; if the gating signal indicates that the ratio does not satisfy the preset condition, the gating component does not output the external clock.

Description

Technical Field

[0001] The present invention relates to a clock circuit, and more particularly to an operating clock generating device and a reference clock gating circuit. Background Art

[0002] As Figure 1 shown, the phase-locked loop (PLL) 110 of the internal PCIe physical layer circuit of a general system-on-chip (SoC) based on the high-speed peripheral component interface (PCIe) standard relies on a reference clock (REFCLK) provided by an external platform 120 (e.g., the motherboard of a general personal computer) to generate a high-speed and stable multiplied clock (pclk) as the operating clock. However, the reference clock provided by the external platform is unstable in some cases (e.g., when the SoC is just powered on, or when the SoC returns from a low-power mode to a normal mode), and it takes some time to provide an ideal reference clock. Therefore, if the SoC directly uses the unstable reference clock to generate a multiplied clock as the operating clock in these cases, the operating clock will cause the SoC to malfunction and may cause harm to the SoC.

[0003] SoCs based on other interface standards (e.g., Serial Advanced Technology Attachment (SATA)) also encounter similar problems. Summary of the Invention

[0004] One object of the present disclosure is to provide an operating clock generating device and a reference clock gating circuit that can output a reliable reference clock.

[0005] An embodiment of the operating clock generation device of the present disclosure includes a reference clock gating circuit and an operating clock generation circuit. The reference clock gating circuit is used to perform a detection operation to output a reference clock according to an external clock, where the external clock is derived from an external clock source, and the operating clock generation device and the external clock source are not included in the same chip. The reference clock gating circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter for counting according to the trigger of the external clock to generate a first clock number; a second counter for counting according to the trigger of a low-speed clock to generate a second clock number, where the frequency of the low-speed clock is lower than that of the external clock, and the low-speed clock is derived from a crystal oscillator; and a determination circuit for determining whether the ratio of the first clock number to the second clock number satisfies a preset condition after the second clock number reaches a preset number or a multiple of the preset number, and generating a gating signal accordingly. The gating component is used to receive the external clock and output the external clock as the reference clock when the detection operation is performed and the gating signal indicates that the ratio satisfies the preset condition; the gating component is further used to not output the reference clock when the detection operation is performed and the gating signal indicates that the ratio does not satisfy the preset condition. The operating clock generation circuit is coupled to the gating component and is used to receive the reference clock and generate an operating clock accordingly.

[0006] An embodiment of the reference clock gating circuit of the present disclosure is used to perform a detection operation to output a reference clock according to an external clock, where the external clock is derived from an external clock source, and the reference clock gating circuit and the external clock source are not included in the same chip. The reference clock gating circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter for counting according to the trigger of the external clock to generate a first clock number; a second counter for counting according to the trigger of a low-speed clock to generate a second clock number, where the frequency of the low-speed clock is lower than that of the external clock, and the low-speed clock is derived from a crystal oscillator; and a determination circuit for determining whether the ratio of the first clock number to the second clock number satisfies a preset condition after the second clock number reaches a preset number or a multiple of the preset number, and generating a gating signal accordingly. The gating component is used to receive the external clock and output the external clock as the reference clock when the detection operation is performed and the gating signal indicates that the ratio satisfies the preset condition; the gating component is further used to not output the reference clock when the detection operation is performed and the gating signal indicates that the ratio does not satisfy the preset condition.

[0007] Regarding the features, actual operations and effects of the present invention, the preferred embodiments will be described in detail below with reference to the accompanying drawings. Description of the Drawings

[0008] Figure 1 A phase-locked loop of a system-on-chip (SoC) generates a doubled-frequency clock based on an external reference clock;

[0009] Figure 2 An embodiment of the operating clock generation device of the present disclosure is shown;

[0010] Figure 3 Shown is Figure 2 an embodiment of the reference clock gating circuit of

[0011] Figure 4 Shown is Figure 3 an embodiment of the detection circuit of

[0012] Figure 5 Shown is Figure 4 an embodiment of the decision circuit of

[0013] Figure 6 Shown is Figure 4 another embodiment of the decision circuit of Detailed Description of the Invention

[0014] The present disclosure discloses an operating clock generation device and a reference clock gating circuit, which can verify whether an external clock is reliable, and output the external clock as a reference clock when the external clock is reliable.

[0015] Figure 2 An embodiment of the operating clock generation device of the present disclosure is shown. Figure 2 The operating clock generation device 200 of EXT comprises a reference clock gating circuit 210 and an operating clock generation circuit 220. The reference clock gating circuit 210 is used to perform a detection operation to detect an external clock (CLK REF ), and thus output the external clock as a reference clock (CLK OP ) when the result of the detection operation indicates that the external clock is reliable, where the external clock is derived from an external clock source, and the operating clock generation device 200 and the external clock source are not included in the same chip (e.g., a system-on-chip (SoC)). The operating clock generation circuit 220 (e.g., a known or self-developed phase-locked loop) is coupled to the reference clock gating circuit 210 and is used to receive the reference clock to generate an operating clock (CLK

[0016] Figure 3 Shown is Figure 2 an embodiment of the reference clock gating circuit 210 of Figure 3As shown, the reference clock gating circuit 210 includes a detection circuit 310 and a gating component 320. The detection circuit 310 is used to perform the detection operation according to a low-speed clock (CLK XTAL ) to generate a gating signal (SW CTRL ) to indicate whether the external clock is reliable. The gating component 320 (e.g., a switch) is used to receive the external clock and output the external clock as the reference clock when the detection operation is performed and the gating signal indicates that the external clock is reliable (e.g., the gating signal is at a high level); the gating component 320 is also used to not output the reference clock when the detection operation is performed and the gating signal indicates that the external clock is not reliable (e.g., the gating signal is at a low level). When the detection operation is not performed, the gating component 320 receives the external clock and outputs the external clock as the reference clock; at this time, the gating signal can be maintained at the same level (e.g., high level) to keep the gating component 320 conducting.

[0017] Figure 4 shows Figure 3 an embodiment of the detection circuit 310 shown. As Figure 4 shown, the detection circuit 310 includes a first counter 410, a second counter 420, and a decision circuit 430. The first counter 410 can be a known or self-developed counter, which is used to count according to the trigger of the external clock to generate a first clock number (C1). The second counter 420 can be a known or self-developed counter, which is used to count according to the trigger of the low-speed clock to generate a second clock number (C2). The frequency of the low-speed clock (e.g., 25 MHz) is lower than the frequency of the external clock (e.g., 100 MHz), and the low-speed clock is derived from a crystal oscillator (e.g., a known or self-developed crystal oscillator such as a quartz oscillator) (not shown), so it is quite accurate. The crystal oscillator can be included in the reference clock gating circuit 210 or located outside the reference clock gating circuit 210. It should be noted that since the low-speed clock is quite reliable; therefore, the second clock number can be used as a reference benchmark for the decision circuit 430 to make a decision.

[0018] Please refer to Figure 4 . The decision circuit 430 is used to judge the ratio of the first clock number to the second clock number after the second clock number reaches a preset number or a multiple of the preset number, and determine whether it meets a preset condition (e.g., or ) and generate the gate control signal accordingly. When the gate control signal indicates that the ratio meets the preset condition, the gate control component 320 receives the external clock and outputs the external clock as the reference clock; when the gate control signal indicates that the ratio does not meet the preset condition, the gate control component 320 does not output the reference clock.

[0019] Figure 5 Shows an embodiment of the determination circuit 430. As Figure 5 shown, the determination circuit 430 includes a digital comparator 510, a calculation circuit 520, and a judgment circuit 530. The digital comparator 510 is used to compare the number of the second clocks with the preset number / the multiple of the preset number to generate a comparison result (S COMP ) indicating whether the number of the second clocks reaches the preset number / the multiple of the preset number. If the time point when the number of the second clocks reaches the preset number / the multiple of the preset number is a target time point, the calculation circuit 520 is used to calculate the ratio of the number of the first clocks at the target time point to the number of the second clocks at the target time point after the comparison result indicates that the number of the second clocks reaches the preset number / the multiple of the preset number (S RATIO ). The judgment circuit 530 is used to judge whether the ratio meets the preset condition. For example, when the preset condition is a preset value (e.g., ), the judgment circuit 530 includes a comparator (not shown) to compare the ratio with the preset value to generate a comparison result (i.e., the gate control signal SW CTRL ) indicating whether the ratio is equal to the preset value. Another example is that when the preset condition is a preset range (e.g., a range determined by a low threshold and a high threshold), the judgment circuit 530 includes at least one comparator (not shown) to compare the ratio with the preset range to generate at least one comparison result indicating whether the ratio falls within the preset range.

[0020] Figure 6 Shows another embodiment of the determination circuit 430. As Figure 6As shown, the decision circuit 430 includes a digital comparator 610 and a judgment circuit 620. The digital comparator 610 is used to compare the second clock number with the preset number / multiples of the preset number to generate a comparison result indicating whether the second clock number reaches the preset number / multiples of the preset number. If the time point when the second clock number reaches the preset number / multiples of the preset number is a target time point, the judgment circuit 530 is used to judge whether the first clock number at the target time point meets the preset condition after the comparison result indicates that the second clock number reaches the preset number / multiples of the preset number; since the second clock number is the preset number / multiples of the preset number at this time, the above judgment as a whole is equivalent to judging whether the ratio of the first clock number to the second clock number meets the preset condition. In an exemplary operation, The preset condition is a preset range between a low threshold 395 and a high threshold 405; when the second clock number is equal to the preset number 100, the ideal first clock number is 4×100 = 400; the judgment circuit 620 includes at least one comparator (not shown) that can compare the first clock number (e.g., 397) at the target time point, the low threshold and the high threshold to generate at least one comparison result (e.g., low threshold 395 < first clock number 397 < high threshold 405) indicating whether the first clock number falls within the preset range.

[0021] In an exemplary operation, when the ratio of the first clock number to the second clock number does not meet the preset condition, the decision circuit 430 generates a control signal to cause the reference clock gating circuit 210 to re - execute the detection operation; for example, when the ratio of the first clock number to the second clock number does not meet the preset condition, the decision circuit 430 generates the control signal (e.g., a reset signal at a high level) to reset the first counter 410 and the second counter 420, so as to cause the reference clock gating circuit 210 to re - execute the detection operation. In an exemplary operation, when the ratio of the first clock number to the second clock number does not meet the preset condition, the decision circuit 430 generates a control signal (e.g., a reset signal at a low level) to cause the reference clock gating circuit 210 to continue to execute the detection operation; for example, when the ratio of the first clock number to the second clock number does not meet the preset condition, the decision circuit 430 generates the control signal to allow the first counter 410 and the second counter 420 to continue counting, so as to cause the reference clock gating circuit 210 to continue to execute the detection operation; theoretically, since the external clock will gradually tend to be stable, the ratio of the first clock number to the second clock number will gradually decrease, and this ratio will eventually meet the preset condition.

[0022] Please refer to Figures 2 to 6. In one example, the foregoing external clock source and the operation clock generating device 200 are disposed on the same main board (e.g., the main board of a general computer). In one example, the frequency of the external clock (e.g., 100 MHz) is higher than twice the frequency of the low-speed clock (e.g., 25 MHz) and lower than the frequency of the operation clock (e.g., 2.5 GHz); however, the above conditions are not limitations for the implementation of the present invention. As long as the low-speed clock is more accurate than the external clock, such a clock relationship is applicable to the present invention. In one example, the reference clock gating circuit 210 performs the detection operation according to at least one of the following conditions: the operation clock generating device 200 is in a power-on initial stage; a fixed detection period; and a preset trigger event. The above preset trigger event is, for example: the system / operation clock generating device 200 including the external clock source is restarted; the voltage fluctuation of the system / operation clock generating device 200 including the external clock source reaches a preset level; or the integrated circuit including the operation clock generating device 200 returns from a low-power mode to a normal mode. In one example, when the result of the detection operation indicates that the external clock changes from reliable to unreliable, the reference clock gating circuit 210 disables / resets the operation clock generating circuit 220 using a signal (e.g., the gating signal), and when the result of the detection operation indicates that the external clock changes from unreliable to reliable, enables the operation clock generating circuit 220 using the signal.

[0023] It should be noted that Figure 2 the reference clock gating circuit 210 can be implemented independently to output a reliable reference clock; the reference clock gating circuit 210 can also be combined with other known or self-developed operation clock generating circuits to generate an operation clock. It should also be noted that, on the premise of being possible to implement, those of ordinary skill in the art can selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement the combination of some or all of the technical features in multiple of the foregoing embodiments, thereby increasing the flexibility when implementing the present invention.

[0024] In summary, the present invention can verify whether an external clock is reliable, and output the external clock as a reference clock when the external clock is reliable.

[0025] Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to what is defined by the scope of the claims in this specification.

[0026]

Symbol Description

[0027] 110: Phase-locked loop

[0028] 120: External platform

[0029] REFCLK: Reference clock

[0030] pclk: Multiplied clock

[0031] 200: Operation clock generation device

[0032] 210: Reference clock gating circuit

[0033] 220: Operation clock generation circuit

[0034] CLK EXT : External clock

[0035] CLK REF : Reference clock

[0036] CLK OP : Operation clock

[0037] 310: Detection circuit

[0038] 320: Gating component

[0039] CLK XTRL : Low-speed clock

[0040] SW CTRL : Gating signal

[0041] 410: First counter

[0042] 420: Second counter

[0043] 430: Decision circuit

[0044] C1: First clock number

[0045] C2: Second clock number

[0046] 510: Digital comparator

[0047] 520: Calculation circuit

[0048] 530: Judgment circuit

[0049] S COMP : Comparison result

[0050] S RATIO : Ratio of C1 to C2

[0051] 610: Digital comparator

[0052] 620: Judgment circuit.

Claims

1. An operating clock generating device, comprising: A reference clock gating circuit for performing a detection operation to output a reference clock based on an external clock, wherein the external clock is derived from an external clock source, and the operating clock generating device and the external clock source are not included in the same chip. The reference clock gating circuit includes: A detection circuit, including: A first counter for counting based on the trigger of the external clock to generate a first clock number; A second counter, which is used to count according to the trigger of a low-speed clock to generate a second clock number, wherein the frequency of the low-speed clock is lower than the frequency of the external clock, and the low-speed clock is derived from a crystal oscillator; And A decision circuit for determining whether the ratio of the first clock number to the second clock number satisfies a preset condition after the second clock number reaches a preset number or a multiple of the preset number, and generating a gating signal accordingly; And A gating component for receiving the external clock and outputting the external clock as the reference clock when the gating signal indicates that the ratio satisfies the preset condition during the execution of the detection operation. The gating component is further configured not to output the reference clock when the gating signal indicates that the ratio does not satisfy the preset condition during the execution of the detection operation; and An operating clock generating circuit coupled to the gating component for receiving the reference clock and generating an operating clock accordingly.

2. A reference clock gating circuit for performing a detection operation to output a reference clock based on an external clock, wherein the external clock is derived from an external clock source, and the reference clock gating circuit and the external clock source are not included in the same chip. The reference clock gating circuit includes: A detection circuit, including: A first counter for counting based on the trigger of the external clock to generate a first clock number; A second counter, which is used to count according to the triggering of a low-speed clock to generate a second clock number, wherein the frequency of the low-speed clock is lower than the frequency of the external clock, and the low-speed clock is derived from a crystal oscillator; And A decision circuit for determining whether the ratio of the first clock number to the second clock number satisfies a preset condition after the second clock number reaches a preset number or a multiple of the preset number, and generating a gating signal accordingly; And A gating component for receiving the external clock and outputting the external clock as the reference clock when the gating signal indicates that the ratio satisfies the preset condition during the execution of the detection operation. The gating component is further configured not to output the reference clock when the gating signal indicates that the ratio does not satisfy the preset condition during the execution of the detection operation.

3. The reference clock gating circuit according to claim 2, wherein the frequency of the external clock is higher than the frequency of the low-speed clock and lower than the frequency of the operating clock.

4. The reference clock gating circuit according to claim 2, further comprising: the crystal oscillator.

5. The reference clock gating circuit according to claim 2, wherein the preset condition includes at least one of the following conditions: the ratio is equal to a preset value; the ratio falls within a preset ratio range; and when the time point when the second clock number reaches a preset number or a multiple of the preset number is a target time point, the first clock number at the target time point falls within a preset number range.

6. The reference clock gating circuit as claimed in claim 2, wherein the reference clock gating circuit performs the detection operation according to at least one of the following conditions: the reference clock gating circuit is in a power-on initial stage; a fixed detection period; and a preset trigger event.

7. The reference clock gating circuit as claimed in claim 2, wherein when the detection operation is not performed, the gating component receives the external clock and outputs the external clock as the reference clock.

8. The reference clock gating circuit as claimed in claim 2, wherein when the ratio of the number of the first clocks to the number of the second clocks does not meet the preset condition, the decision circuit generates a control signal to cause the reference clock gating circuit to re-perform the detection operation.

9. The reference clock gating circuit as claimed in claim 8, wherein when the ratio of the number of the first clocks to the number of the second clocks does not meet the preset condition, the decision circuit generates the control signal to reset the first counter and the second counter, so as to cause the reference clock gating circuit to re-perform the detection operation.

10. The reference clock gating circuit as claimed in claim 2, wherein when the ratio of the number of the first clocks to the number of the second clocks does not meet the preset condition, the decision circuit generates a control signal to cause the reference clock gating circuit to continue performing the detection operation.

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