Dual-loop phase-locked loop

Abstract

The present disclosure provides a dual-loop phase-locked loop, which comprises a voltage-controlled oscillator, a frequency discriminator and phase discriminator, a first charge pump and a first loop filter located between the two on an integral path, and a second charge pump and a second loop filter located between the two on a proportional path, wherein the second loop filter comprises a voltage generator for receiving an input voltage and generating a bias voltage according to a sweep slope change, and a filter circuit for adjusting the potential of its input node according to the bias voltage to maintain the potential of the output voltage of the loop filter on the proportional path during the sweep process of the dual-loop phase-locked loop, so that different initial voltages can be applied to the input node of the loop filter on the proportional path according to the sweep slope requirement, and after the initial voltage is applied to the loop filter on the proportional path, the system parameters can be accurately controlled, and the stability, reliability and related performance parameters of the dual-loop phase-locked loop are greatly improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electronic circuits, in particular to a double-loop phase-locked loop. BACKGROUND

[0002] In the application of integrated circuits, the clock system is an important module of chip design, and is realized by using a phase-locked loop circuit to meet different clock needs of the system.

[0003] In the related art, the frequency locking of a frequency synthesis phase-locked loop is realized by a single loop, which is sequentially connected by a frequency discriminator, a charge pump, a loop filter, a voltage-controlled oscillator, a pre-frequency divider and a frequency divider. First, the voltage-controlled oscillator generates an oscillation signal with a certain frequency through self-oscillation, and the signal enters the frequency discriminator after being processed by the pre-frequency divider and the frequency divider, and the frequency difference and phase difference signals are compared with the reference frequency and enter the charge pump. The charge pump determines the intake current or pump current according to the frequency difference and phase difference, and converts the current into a voltage value. The output voltage of the charge pump is filtered by the loop filter and enters the voltage-controlled oscillator, and the value of the variable capacitor in the voltage-controlled oscillator is adjusted to change the frequency of the oscillation signal. In fact, the entire loop first locks the frequency of the signal generated by the voltage-controlled oscillator in the required frequency band according to the frequency difference, and then gradually approaches the reference frequency through the output signal frequency of the frequency divider to lock the oscillation frequency at the required frequency point.

[0004] In this traditional phase-locked loop, the variable capacitor of the voltage-controlled oscillator covers a very limited frequency range, which is completely unsuitable for wideband applications such as ZigBee systems. If a variable capacitor array is used for frequency band selection, the control signal of the capacitor array and the frequency band need to be in a one-to-one correspondence, i.e. a certain digital control value is set in advance to correspond to a certain frequency band, and when the oscillation signal of the frequency band is needed, the manually input digital code control word is set to make the oscillation frequency in the frequency band, and then the loop frequency is fine-tuned to finally lock the signal at a certain oscillation frequency in the frequency band. However, due to process deviation, voltage variation and temperature drift, the frequency signal generated by the actual voltage-controlled oscillator circuit is far different from the predetermined value, and the one-to-one correspondence between the variable capacitor array control word and the frequency band will have a large deviation. To lock the required oscillation frequency, more loop cycles are needed to approach the frequency, greatly prolonging the frequency locking time of the phase-locked loop.

[0005] On this basis, an improved double-loop phase-locked loop is proposed as Figure 1As shown, the double-loop phase-locked loop 100 including the integral path 120 and the proportional path 130, when sweeping, the output voltage of the loop filter 122 on the integral path 120 will change according to the output frequency, and the output voltage of the loop filter 132 on the proportional path 130 is ideally unchanged, but in the actual circuit, on the one hand, due to the input phase difference of the phase detector 110 not being 0 during the sweeping process, the output voltage of the loop filter 132 on the proportional path 130 will change, deviating from its expected value, and this deviation will change the loop parameters of the double-loop phase-locked loop 100, thereby deteriorating the overall performance of the phase-locked loop and even causing the phase-locked loop to lose lock.

[0006] On the other hand, the loop filter 132 on the proportional path 130 in the current double-loop phase-locked loop 100 generally adopts a differential virtual ground connection mode, as shown in Figure 2 The virtual ground potential is connected to the connection node of the series-connected resistor R1 and resistor R2. This connection mode cannot avoid the phenomenon that the output voltage of the loop filter 132 on the proportional path 130 deviates from the expected value during the sweeping process. SUMMARY

[0007] In order to solve the above technical problems, the present disclosure provides a double-loop phase-locked loop.

[0008] The present disclosure provides a double-loop phase-locked loop, which comprises:

[0009] A voltage-controlled oscillator having a power terminal and a control terminal for generating a high-frequency clock signal;

[0010] A phase detector for detecting a phase difference between a phase of the high-frequency clock signal and a phase of a reference signal, and generating an integral signal representing an integral value of the phase difference and a proportional signal representing a current value of the phase difference;

[0011] A first charge pump and a first loop filter located on an integral path between the voltage-controlled oscillator and the phase detector, for receiving the integral signal and supplying an adjusted integral signal to the power terminal of the voltage-controlled oscillator;

[0012] A second charge pump and a second loop filter located on a proportional path between the voltage-controlled oscillator and the phase detector, for receiving the proportional signal and supplying an adjusted proportional signal to the control terminal of the voltage-controlled oscillator;

[0013] The second loop filter comprises:

[0014] A voltage generator for receiving an input voltage and generating a bias voltage according to a sweeping slope change; and

[0015] a filter circuit for obtaining the bias voltage at an input node thereof and adjusting a potential of the input node according to the bias voltage to maintain a potential of an output voltage of a loop filter in a proportional path during a frequency sweeping process of the dual-loop phase-locked loop,

[0016] The voltage-controlled oscillator generates a high-frequency clock signal having an oscillation frequency controlled by both the adjusted integral signal and the proportional signal, such that a phase of the high-frequency clock signal is locked to a phase of the reference signal.

[0017] Preferably, the aforementioned dual-loop phase-locked loop further comprises:

[0018] a frequency divider coupled between the voltage-controlled oscillator and the frequency discriminator for dividing the high-frequency clock signal to obtain a low-frequency signal,

[0019] wherein the frequency discriminator detects a phase difference by comparing a phase of the low-frequency signal with a phase of the reference signal.

[0020] Preferably, the aforementioned loop filter further comprises:

[0021] a gain amplifier connected between an output of the voltage generator and the input node of the filter circuit for gain amplifying the bias voltage.

[0022] Preferably, the input node of the aforementioned second loop filter comprises a first input node and a second input node, and the aforementioned filter circuit comprises:

[0023] a first resistor and a third resistor connected in series between the first input node and a first output node;

[0024] a second resistor and a fourth resistor connected in series between the second input node and a second output node, the first output node and the second output node being configured to provide the output voltage;

[0025] a first capacitor having a first end connected to a connection node of the first resistor and the third resistor and a second end connected to a connection node of the second resistor and the fourth resistor;

[0026] a second capacitor having a first end connected to the first output node and a second end connected to the second output node.

[0027] Preferably, the aforementioned voltage generator comprises:

[0028] a switched resistor network having a plurality of fifth resistors connected in series between a power supply terminal and a ground terminal, and each connection node between any two adjacent fifth resistors being connected with a switch element,

[0029] The two switch elements are connected to the first input node and the second input node respectively to provide the bias voltage.

[0030] Preferably, the bias voltage is a voltage value that makes the output voltage of the loop filter in the proportional path zero when the dual-loop phase-locked loop switches from the lock mode to the frequency sweep mode and works at a predetermined frequency sweep slope.

[0031] Preferably, the first loop filter comprises:

[0032] a third capacitor and a sixth resistor, the first end of the third capacitor and the first end of the sixth resistor are connected to the third output node of the first charge pump, the second end of the third capacitor is grounded, and the second end of the sixth resistor is connected to the power terminal;

[0033] a fourth capacitor and a seventh resistor, the second end of the fourth capacitor and the first end of the seventh resistor are connected to the ground, the first end of the fourth capacitor is connected to the power terminal, and the second end of the seventh resistor is connected to the fourth output node of the first charge pump.

[0034] Preferably, the first output node and the second output node of the second loop filter are used to provide an output voltage to the control terminal.

[0035] Preferably, the bias voltage in the second loop filter is proportional to the frequency sweep slope and is proportional to the output current of the first charge pump in the proportional path.

[0036] The dual-loop phase-locked loop provided by the present disclosure has a proportional path and an integral path coupled between the phase detector and the voltage-controlled oscillator, wherein the loop filter in the proportional path comprises a voltage generator for receiving an input voltage and generating a bias voltage according to a frequency sweep slope, and a filter circuit for obtaining the bias voltage through its input node and adjusting the potential of the input node according to the bias voltage to maintain the potential of the output voltage of the loop filter in the proportional path during the frequency sweep process of the dual-loop phase-locked loop, so that different initial voltages can be applied to the input node of the loop filter in the proportional path according to the frequency sweep slope requirement, and after the initial voltage is applied to the loop filter in the proportional path, the system parameters can be accurately controlled, which greatly improves the stability, reliability and related performance parameters of the dual-loop phase-locked loop. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown;

[0039] Figure 2 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown Figure 1 A structure diagram of a loop filter in the double-loop phase-locked loop shown is shown;

[0040] Figure 3 A circuit structure diagram of a double-loop phase-locked loop provided by an embodiment of the present disclosure is shown;

[0041] Figure 4 A structure diagram of a second loop filter in the double-loop phase-locked loop shown is shown; Figure 3 A structure diagram of a second loop filter in the double-loop phase-locked loop shown is shown;

[0042] Figure 5 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown Figure 4 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown

[0043] Figure 6 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown Figure 3 A circuit structure diagram of a double-loop phase-locked loop in the prior art is shown DETAILED DESCRIPTION

[0044] For the purpose of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the drawings, which are described below. It will be appreciated that the present disclosure can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0046] In a wireless transceiver, a phase-locked loop (PLL) is generally used to synthesize a variable local oscillator signal from a reference signal source, such as a crystal oscillator, which has a stable output with low phase noise. The PLL produces an output signal that is phase-locked to the reference signal. Typically, the desired output radio frequency is higher than the reference frequency from a suitable reference source. An important characteristic of a PLL when used as a local oscillator is its selectivity of communication channels, i.e., the gap between its output channels or its resolution.

[0047] The earliest and simplest type is an integer-N PLL single loop in which the output signal is fed back to the phase comparator of the PLL through a divider with an integer division ratio N. Typically, the comparison signal is derived by a reference divider with an integer division ratio R. The selection of the output channel is equal to the comparison frequency. This type of PLL is well developed and has a sufficiently low power consumption for battery applications. However, when the division ratios R and N are set to provide a high output frequency with a narrow selection of the communication channel, this simple type of PLL suffers from phase noise problems.

[0048] Another very important type of PLL is the fractional-N PLL, which has the same structure as the integer-N PLL except that the division ratio of the feedback divider is an integer plus a rational fraction. The selection of the communication channel of the output signal is therefore also a rational fraction of the comparison frequency. However, it is difficult to implement a fractional-N PLL for low noise and low power. A high performance fractional-N PLL requires high complexity, consumes a large area of silicon and is not easily integrated with other low noise systems on the same module.

[0049] Improvements to the single loop PLL can be obtained by using a dual loop PLL which combines two phase locked loops.

[0050] The loop filter (for example, the loop filter on the proportional path 130) 132 in the conventional dual loop phase locked loop architecture 100. When the dual loop phase locked loop 100 is sweeping, the output voltage of the loop filter 122 on the integral path 120 will change according to the output frequency, and the output voltage of the loop filter 132 on the proportional path 130 ideally remains unchanged, but in actual circuits, due to the fact that the input phase difference of the frequency discriminator and phase detector 110 is not 0 during the sweeping process, and the loop filter 132 on the proportional path 130 in the current dual loop phase locked loop 100 is connected in a differential virtual ground manner, which cannot avoid the fact that the output voltage of the loop filter 132 on the proportional path 130 will change during the sweeping process, deviating from its expected value. This deviation causes the loop parameters of the dual loop phase locked loop 100 to change, thereby degrading the overall performance of the phase locked loop and even causing the phase locked loop to lose lock, affecting the performance of the phase locked loop.

[0051] Based on this, the dual loop phase locked loop (PLL) in the embodiments of the present disclosure is proposed to effectively compensate for the voltage deviation defects in the above, so that the phase locked loop maintains the expected system parameters under different sweeping slope requirements, so that the dual loop phase locked loop can adapt to different application requirements.

[0052] In the following, the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 3A circuit structure diagram of a double-loop phase-locked loop is shown, Figure 4 A double-loop phase-locked loop is shown for Figure 3 A structure diagram of a second loop filter in the double-loop phase-locked loop is shown, Figure 5 A structure diagram of a second loop filter in the double-loop phase-locked loop is shown, Figure 4 A circuit structure diagram of a voltage generator in the second loop filter is shown, Figure 6 A circuit structure diagram of a voltage generator in the second loop filter is shown, Figure 3 A circuit structure diagram of a first loop filter in the double-loop phase-locked loop is shown.

[0054] Referring to Figure 3 The double-loop phase-locked loop 200 can be used to synthesize a local oscillation signal for a radio frequency transceiver, such as a mobile phone. In the embodiment, the double-loop phase-locked loop 200 comprises at least a phase-frequency detector 210, an integral path 230, a proportional path 220 and a voltage-controlled oscillator 240.

[0055] The voltage-controlled oscillator 240 has a power terminal b and a control terminal a, and is used to generate a high frequency clock signal fout;

[0056] The phase-frequency detector 210 is used to detect a phase difference φ between a phase of the high frequency clock signal fout and a phase of a reference signal fref, and to generate an integral signal representing an integral value of the phase difference φ and a proportional signal representing a current value of the phase difference φ;

[0057] The integral path 230 comprises a first charge pump 231 and a first loop filter 232, and is used to receive the integral signal and to supply an adjusted integral signal Vco1 to the power terminal b of the voltage-controlled oscillator 240;

[0058] The proportional path 220 comprises a second charge pump 221 and a second loop filter 222, and is used to receive the proportional signal and to supply an adjusted proportional signal Vco2 to the control terminal a of the voltage-controlled oscillator 240,

[0059] The second loop filter 222 is used to receive an input voltage VDD and to generate a bias voltage Vdiff according to a sweep slope variation, and to adjust a potential of an input node of the second loop filter 222 according to the bias voltage Vdiff, so as to maintain a potential of an output voltage (i.e. the proportional signal Vco2) of the second loop filter 222 during a sweep process of the double-loop phase-locked loop 200,

[0060] The aforementioned voltage controlled oscillator 240 generates a high frequency clock signal fout having an oscillation frequency controlled by both the adjusted integral signal Vco1 and the adjusted proportional signal Vco2, such that the phase of the high frequency clock signal fout is locked to the phase of the aforementioned reference signal fref.

[0061] In the present embodiment, the voltage controlled oscillator (VCO) 240 generates a high frequency clock signal fout based on at least two controllable parameters, such as Vco1 and Vco2 controlled separately based on a proportional signal and an integral signal. And based on which the parameters adjust the frequency of the high frequency clock signal fout.

[0062] The frequency of the high frequency clock signal fout provided by the voltage controlled oscillator 240 is a function of the control voltage. In addition, the VCO has another controllable parameter. When the VCO has a ring oscillator topology comprising a series connection of delay cells, for example, the number of delay cells, the size of the delay cells, the value of the load capacitance of the delay cells, the current through the delay cells, etc. can be used to control the frequency of the oscillation signal OUT. The proportional signal and the integral signal are used separately, for example, to adjust the control voltage and the size of the delay cells.

[0063] In another embodiment, the voltage controlled oscillator 240 can be implemented as an inductance-capacitance (LC) type oscillator. The frequency of the LC type oscillator depends on the inductance and the capacitance of the LC type oscillator. In one example, the capacitance of the LC type oscillator is collectively determined by at least one variable capacitor and a capacitor bank. The variable capacitor has a voltage controlled capacitor, and the capacitor bank has a plurality of capacitors optionally included in the LC type oscillator. The proportional signal and the integral signal are used separately, for example, to control the capacitance of the variable capacitor and the number of selected capacitors in the capacitor bank.

[0064] Further, in the present embodiment, the aforementioned dual-loop phase-locked loop 200 further comprises:

[0065] a frequency divider 250 coupled between the aforementioned voltage controlled oscillator 240 and the frequency / phase discriminator 210 for dividing the aforementioned high frequency clock signal fout to obtain a low frequency signal fb, wherein the aforementioned frequency / phase discriminator 210 detects the aforementioned phase difference φ by comparing the phase of the low frequency signal fb with the phase of the aforementioned reference signal fref. In a frequency sweeping system, the frequency sweeping of the output frequency is usually achieved by changing the input frequency dividing ratio N (N is an integer) of the frequency divider 250.

[0066] In the present embodiment, the phase-frequency detector 210 receives the divided low frequency signal fb and the reference signal fref, and generates a pair of signals (a first control signal UP and a second control signal DN) with variable pulse width. The pulse width varies based on the phase difference φ between the divided low frequency signal fb and the reference signal fref. For example, when the divided low frequency signal fb leads the reference signal fref with a positive phase difference, the second control signal DN has a wider pulse width proportional to the positive phase difference; when the divided low frequency signal fb lags behind the reference signal fref with a positive phase difference, the first control signal UP has a wider pulse width proportional to the positive phase difference.

[0067] Further, in the present embodiment, the aforementioned dual-loop phase-locked loop 200 can further comprise an external crystal oscillator 201 for providing the reference (frequency) signal fref.

[0068] Further, with reference to Figure 4 In the present embodiment, the aforementioned second loop filter 222 comprises a voltage generator 2221 for receiving an input voltage VDD and generating a bias voltage Vdiff according to a sweep slope variation, a gain amplifier 2222 connected between the output of the voltage generator 2221 and the input nodes (A1 and A2) of the filter circuit 2223 for gain amplifying the aforementioned bias voltage Vdiff, and a filter circuit 2223 for obtaining the bias voltage Vdiff through its input nodes (A1 and A2) and adjusting the potential of the aforementioned input nodes (A1 and A2) according to the bias voltage Vdiff, so as to maintain the potential of the output voltage Vco2 of the second loop filter 222 on the proportional path 220 during the sweep process of the dual-loop phase-locked loop 200.

[0069] Further, in the present embodiment, the input nodes of the aforementioned second loop filter 222 comprise a first input node A1 and a second input node A2, and the filter circuit 2223 comprises a first resistor R1 and a third resistor R3, a second resistor R2 and a fourth resistor R4, and a first capacitor C1 and a second capacitor C2,

[0070] The first resistor R1 and the third resistor R3 are connected in series between a first input node A1 and a first output node, the second resistor R2 and the fourth resistor R4 are connected in series between a second input node A2 and a second output node, the first output node and the second output node are used to provide the output voltage Vco2, a first end of the first capacitor C1 is connected to a connection node of the first resistor R1 and the third resistor R3, a second end of the first capacitor C1 is connected to a connection node of the second resistor R2 and the fourth resistor R4, a first end of the second capacitor C2 is connected to the first output node, and a second end of the second capacitor C2 is connected to the second output node.

[0071] In combination Figure 3 And Figure 4 In the embodiment, a connection node of the first resistor R1 and the third resistor R3 in the second loop filter 222 is connected to a fifth output node of the second charge pump 221, a connection node of the second resistor R2 and the fourth resistor R4 is connected to a sixth output node of the second charge pump 221, and the first output node and the second output node of the second loop filter 222 are used to provide the output voltage Vco2 to the control terminal a.

[0072] With reference to Figure 5 In the embodiment, the voltage generator 2221 comprises:

[0073] a switched resistor network, the switched resistor network has a plurality of fifth resistors R5 connected in series between a power supply terminal and a ground terminal, and a switch element is connected between any adjacent two fifth resistors R5,

[0074] In the frequency sweeping process, the two switch elements are connected to the first input node A1 and the second input node A2 respectively to provide the bias voltage Vdiff.

[0075] Further, in the embodiment, the bias voltage Vdiff has a voltage value that makes the output voltage Vco2 of the second loop filter 222 in the proportional path 220 zero when the dual-loop phase-locked loop 200 is switched from the locked mode to the frequency sweeping mode and works at a predetermined frequency sweeping slope.

[0076] Further, with reference to Figure 6 In the embodiment, the first loop filter 232 comprises a third capacitor C3 and a sixth resistor R6, and a fourth capacitor C4 and a seventh resistor R7,

[0077] The first end of the third capacitor C3 and the first end of the sixth resistor R6 are commonly connected to the third output node of the first charge pump 231, the second end of the third capacitor C3 is grounded, and the second end of the sixth resistor R6 is connected to the aforementioned power terminal b; the second end of the fourth capacitor C4 and the first end of the seventh resistor R7 are commonly connected to the ground, the first end of the fourth capacitor C4 is connected to the aforementioned power terminal b, and the second end of the seventh resistor R7 is connected to the fourth output node of the first charge pump 231.

[0078] Specifically, in combination with the foregoing description, the second loop filter 222 for the dual-loop phase-locked loop 200 provided by the embodiment of the present disclosure adds an additional bias circuit to the loop filter architecture on a conventional proportional path, splits node A into two nodes A1 and A2, and node A1 and node A2 are equipotential points in the conventional mode. The embodiment of the present disclosure utilizes a voltage generator 2221 to generate two bias voltages with a difference of Vdiff, and the bias voltages are pushed through a unit gain amplifier 2222 (unit gain buffer). The bias voltage Vdiff is an expected voltage known according to the frequency sweep slope and the characteristics of the phase-locked loop system, and the value is determined by the following steps:

[0079] Method one:

[0080] 1) Fix the potential of the node (A1 / A2) in the second loop filter 222 on the proportional path 220 in the dual-loop phase-locked loop 200 to 0, and make the entire dual-loop phase-locked loop 200 work in the locked mode;

[0081] 2) On the basis of step 1, make the dual-loop phase-locked loop 200 enter the frequency sweep mode, and the frequency sweep slope is set according to the current working environment requirement;

[0082] 3) In the frequency sweep mode, the second charge pump 131 on the proportional path 130 of the conventional dual-loop phase-locked loop 100 has an output voltage offset, and the offset voltage Vdiff output by the second charge pump 131 on the proportional path 130 is measured;

[0083] 4) The voltage generator 2221 controls the output voltage difference to be Vdiff, and the bias voltage between the first input node A1 and the second input node A2 is set to -Vdiff, so that the offset voltage on the proportional path 220 is the same as in the locked mode, which is 0;

[0084] 5) By repeating steps 1) to 4) above, the required input voltage size under different frequency sweep slopes can be obtained, so that the dual-loop phase-locked loop 200 can adapt to different application requirements.

[0085] Method two:

[0086] In combination with the above Figure 4 As shown in the circuit structure of the second loop filter 222, the principle can be known by analysis:

[0087] The frequency-sweeping phase difference φ (1)

[0088] And

[0089] The bias voltage Vdiff (2)

[0090] Wherein, The frequency-sweeping slope is (Framp) / (∆T), C3 represents the capacitance size of the first loop filter 232 on the integral path 230, R1 represents the resistance size of the second loop filter 222 on the proportional path 220, Icp1 represents the output current size of the second charge pump 221 on the proportional path 220, and Kvco represents the parameter of the voltage-controlled oscillator 240.

[0091] 1) According to formula (1), the phase difference φ generated by the double-loop phase-locked loop 200 during frequency sweeping is related to the following parameters: the frequency-sweeping slope ((Framp) / (∆T)), the capacitance C3 of the first loop filter 232 on the integral path 230, the resistance size of the second loop filter 222 on the proportional path 220, the output current Icp1 of the second charge pump 221 on the proportional path 220, and the parameter Kvco of the voltage-controlled oscillator 240;

[0092] 2) According to formula (2), the size of the bias voltage Vdiff in the aforementioned second loop filter 222 is proportional to the frequency-sweeping slope, and is proportional to the output current of the second charge pump 221 on the proportional path 220. According to the relationship between the phase difference φ and the bias voltage Vdiff, the size of the bias voltage Vdiff can be adjusted by adjusting the position of the gating switch in the voltage generator 2221 (the number of the fifth resistors R5 in series), so as to compensate for the offset phase;

[0093] 3) After the phase compensation, the offset voltage Vdiff will be zero, so that the same locking state as in the traditional (locking) mode is achieved in the frequency-sweeping mode;

[0094] 4) By repeating steps 1)-3) above, the size of the voltage generator 2221 (i.e. the bias voltage Vdiff) required for different frequency-sweeping slopes can be obtained, so that the double-loop phase-locked loop 200 can adapt to different application requirements.

[0095] Therefore, the system parameters of the double-loop phase-locked loop 200 provided by the embodiments of the present disclosure can be precisely controlled, thereby greatly improving the stability and reliability of the phase-locked loop.

[0096] The prior art solution adopts a virtual ground connection at node A in the loop filter 132 on the proportional path 130, which cannot accurately control the loop output voltage in the actual frequency sweep state, resulting in parameter deviation in the design of the subsequent circuit and the entire system, leading to deterioration of system performance. After the initial voltage (i.e., bias voltage Vdiff) is applied to the second loop filter 222 on the proportional path 220, the system parameters can be accurately controlled, greatly improving the stability, reliability, and related performance parameters of the double-loop phase-locked loop 200.

[0097] In summary, in the double-loop phase-locked loop 200 provided by the embodiments of the present disclosure, the second loop filter 222 on the proportional path 220 can receive the input voltage VDD using the voltage generator 2221 and generate a bias voltage Vdiff according to the sweep slope change; and the bias voltage Vdiff is obtained through the input nodes (A1 and A2) of the filter circuit 2223, and the potential of the aforementioned input nodes A1 and A2 is adjusted according to the bias voltage Vdiff, so as to maintain the potential of the output voltage Vco2 of the second loop filter 222 on the proportional path 220 of the double-loop phase-locked loop 200 during the sweep process. Thus, different initial voltages can be applied to the input nodes of the second loop filter 222 on the proportional path 220 according to the sweep slope requirement, so that the system parameters can be accurately controlled, and the stability and reliability of the double-loop phase-locked loop 200 are greatly improved.

[0098] It should be noted that in the description of the present disclosure, it is understood that the terms "upper", "lower", "inner", etc. indicate the orientation or positional relationship, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0099] In addition, in this document, the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0100] Finally, it should be noted that the above-mentioned embodiments are merely intended for the purpose of illustration, and are not intended to limit the implementation modes. Based on the above description, those skilled in the art can further make other variations or changes in the form of different embodiments. Here, it is not necessary or possible to enumerate all the implementation modes. The obvious variations or changes derived therefrom are still within the protection scope of the disclosure.

Claims

1. A dual-loop phase-locked loop, characterized in that: include: a voltage-controlled oscillator having a power supply terminal and a control terminal for generating a high-frequency clock signal; a phase frequency detector for detecting a phase difference between the phase of the high-frequency clock signal and the phase of a reference signal, and generating an integral signal representing an integral value of the phase difference and a proportional signal representing a current value of the phase difference; a first charge pump and a first loop filter located on an integration path between the voltage controlled oscillator and the phase frequency detector, for receiving the integration signal and supplying a conditioned integration signal to a power supply terminal of the voltage controlled oscillator; as well as a second charge pump and a second loop filter located on a proportional path between the voltage controlled oscillator and the phase frequency detector, for receiving the proportional signal and supplying an adjusted proportional signal to a control terminal of the voltage controlled oscillator, Wherein, the second loop filter comprises: A voltage generator, configured to receive an input voltage and generate a bias voltage according to a sweep slope; a filter circuit, configured to obtain the bias voltage through its input node and adjust the potential of the input node according to the bias voltage to maintain the potential of the output voltage of the second loop filter located on the proportional path during the frequency sweep of the dual-loop phase-locked loop; The voltage controlled oscillator generates a high frequency clock signal having an oscillation frequency controlled by both the adjusted integral signal and the proportional signal, such that a phase of the high frequency clock signal is locked to a phase of the reference signal; The dual-loop phase-locked loop further includes: a frequency divider coupled between the voltage-controlled oscillator and the phase frequency detector, configured to divide the high-frequency clock signal to obtain a low-frequency signal, wherein the phase frequency detector detects the phase difference by comparing the phase of the low-frequency signal with the phase of the reference signal; a gain amplifier connected between the output terminal of the voltage generator and the input node of the filter circuit, and configured to perform gain amplification on the bias voltage; The input nodes of the second loop filter include a first input node and a second input node, and the filtering circuit includes: a first resistor and a third resistor, wherein the first resistor and the third resistor are connected in series between the first input node and the first output node; a second resistor and a fourth resistor, wherein the second resistor and the fourth resistor are connected in series between the second input node and a second output node, and the first output node and the second output node are used to provide the output voltage; a first capacitor, wherein a first end of the first capacitor is connected to a connection node between the first resistor and the third resistor, and a second end of the first capacitor is connected to a connection node between the second resistor and the fourth resistor; A second capacitor, wherein a first end of the second capacitor is connected to the first output node, and a second end of the second capacitor is connected to the second output node.

2. The dual-loop phase-locked loop according to claim 1, wherein: The voltage generator comprises: A switch resistor network, wherein the switch resistor network comprises a plurality of fifth resistors sequentially connected in series between the power supply terminal and the ground, and a connection node between any two adjacent fifth resistors is connected to a switch element, During the frequency sweep process of the dual-loop phase-locked loop, the two switching elements that are sequentially enabled are connected to the first input node and the second input node respectively to provide the bias voltage.

3. The dual-loop phase-locked loop according to claim 2, wherein: The magnitude of the bias voltage is a voltage value that causes the offset voltage of the output voltage of the loop filter located on the proportional path to become zero when the dual-loop phase-locked loop switches from the locking mode to the sweep mode and operates at a predetermined sweep slope.

4. The dual-loop phase-locked loop according to claim 3, wherein: The first loop filter comprises: a third capacitor and a sixth resistor, wherein a first end of the third capacitor and a first end of the sixth resistor are commonly connected to the third output node of the first charge pump, a second end of the third capacitor is grounded, and a second end of the sixth resistor is connected to the power terminal; A fourth capacitor and a seventh resistor, wherein the second end of the fourth capacitor and the first end of the seventh resistor are commonly connected to the ground, the first end of the fourth capacitor is connected to the power supply terminal, and the second end of the seventh resistor is connected to the fourth output node of the first charge pump.

5. The dual-loop phase-locked loop according to claim 4, wherein: A connection node between the first resistor and the third resistor in the second loop filter is connected to a fifth output node of the second charge pump, a connection node between the second resistor and the fourth resistor is connected to a sixth output node of the second charge pump, and the first output node and the second output node of the second loop filter are used to provide the output voltage to the control terminal.

6. The dual-loop phase-locked loop according to claim 5, wherein: The magnitude of the bias voltage in the second loop filter is proportional to the frequency sweep slope and proportional to the output current of the first charge pump on the proportional path.

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