A system and method for suppressing sampling jitter of an analog-to-digital converter

Abstract

The present invention provides a system and method for suppressing sampling jitter of an analog-to-digital converter. In the present invention, a pilot signal generated inside a phase measurement processing terminal is combined with a signal to be measured and then enters a digital phase-locked loop through ADC sampling to measure and suppress aperture jitter noise in the ADC sampling process in real time; a clock sideband modulation signal generated inside the phase measurement processing terminal is used to generate a clock sideband beat signal in a two-way carrier phase measurement system to measure and suppress sampling clock jitter noise in the ADC sampling process in real time; by combining the measurement data of the aperture jitter noise and the measurement data of the sampling clock jitter noise, a data processing flow is given to completely eliminate the sampling jitter noise in the ADC sampling process.

Description

Technical Field

[0001] The present invention belongs to the field of satellite navigation, and relates to a system and method for suppressing the sampling jitter of an analog-to-digital converter (ADC). Background Art

[0002] In the precise inter-satellite laser measurement, the optical carrier phase measurement of a two-satellite formation can achieve inter-satellite displacement measurement with nanometer-level accuracy and realize the precise inversion of the Earth's time-varying gravity field, which has important application value in the national defense field. At the phase measurement processing terminal, the accuracy of the optical carrier phase measurement is mainly limited by the ADC sampling jitter.

[0003] Specifically, the limiting factors of the optical carrier phase measurement accuracy are as follows:

[0004] (1) The sampling jitter noise of the analog-to-digital converter (ADC) in the phase measurement system;

[0005] (2) Thermal noise;

[0006] (3) Dynamic stress error.

[0007] Among them, the thermal noise is mainly determined by the input signal carrier-to-noise ratio and the filter parameters of the digital phase-locked loop. In the case of high laser carrier-to-noise ratio (for example, greater than 100 dB-Hz), the filter bandwidth can be converged to the Hz level through the step-by-step tracking method in the algorithm, so the influence of thermal noise can be ignored. The dynamic stress error can be eliminated by means of a low-order frequency-locked loop assisting a high-order phase-locked loop.

[0008] The ADC sampling jitter noise is the bottleneck factor restricting the optical carrier phase measurement accuracy. The ADC sampling jitter noise is composed of the aperture jitter noise and the sampling clock jitter noise of the ADC. The aperture jitter noise is caused by the non-ideality of the ADC device itself and is approximately white noise. The sampling clock jitter noise is introduced by the clock driving the ADC to work, that is, the frequency noise of the ADC working clock will cause time jitter of the ADC at the sampling points.

[0009] When the ADC device and the working clock remain unchanged, the ADC sampling jitter noise is proportional to the input signal frequency.

[0010] In the test of the phase measurement system, when a single-carrier signal with a high input carrier-to-noise ratio is input, the phase noise output by the phase measurement system can be considered to be mainly contributed by the ADC sampling jitter, that is, the superposition of two types of noise: aperture jitter and sampling clock jitter. Further, when the input signal is homologous with the ADC clock and the sampling clock jitter can be ignored, the phase noise output by the phase measurement system is mainly contributed by the aperture jitter.

[0011] In the precise inter-satellite laser measurement, the ADC sampling jitter noise is the main problem to be overcome for achieving high-precision optical carrier phase measurement. Currently, the aperture jitter noise of ADC devices is in the ps level and it is difficult to further optimize. The short-term frequency stability of the ultra-stable crystal oscillator used as the ADC sampling clock is between 10 -12 and 10 -13 , and it is also difficult to further optimize under the limitations of size and power consumption.

[0012] The literature Auxiliary functions of the LISA laser link:ranging,clock noisetransfer and data communication,Classical and Quantum Gravity,2011,28(9):094008 and Time-delay interferometry and clock-noise calibration,Physical ReviewD,2018,98(4):042003 introduce the technical route of suppressing the sampling clock jitter by using clock sideband modulation in the time-delay interferometry data combination in the mission of three-satellite formation for space gravitational wave detection. The method introduced in this article is only applicable to the three-satellite formation system for space gravitational wave detection, and suppresses the sampling clock jitter noise term in the time-delay interferometry data combination, without considering the method of directly suppressing the sampling clock jitter noise in a more general two-way carrier phase measurement system. Summary of the Invention

[0013] The technical problem solved by the present invention: The present invention proposes a system and method for suppressing the sampling jitter of an analog-to-digital converter, which can measure and compensate the aperture jitter and sampling clock jitter noise of the ADC in real time, and break through the key technology of high-precision optical carrier phase measurement.

[0014] The technical solution adopted by the present invention: A system for suppressing the sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system. The two-way carrier phase measurement system includes Satellite 1 (i.e., the first satellite) and Satellite 2 (i.e., the second satellite). Satellite 1 emits a laser beam, which reaches Satellite 2 and interferes with the local oscillator laser of Satellite 2 to measure the phase value of the carrier beat frequency signal Satellite 2 emits a laser beam, which reaches Satellite 1. The local oscillator light of Satellite 1 interferes with the laser beam from Satellite 2 to measure the phase value of the carrier beat frequency signal

[0015] The system for suppressing the sampling jitter of the analog-to-digital converter is provided in both Satellite 1 and Satellite 2;

[0016] The system for suppressing the sampling jitter of an analog-to-digital converter includes a frequency synthesizer unit, an electro-optic phase modulator, and a digital signal processing unit;

[0017] In satellite 1, a ultra-stable crystal oscillator provides a reference frequency for the frequency synthesizer unit. The frequency synthesizer unit generates a sampling clock signal, an FPGA operating clock signal, a pilot signal, and a sideband modulation signal through a phase-locked frequency multiplication circuit, sends the sampling clock signal to the ADC, sends the FPGA operating clock signal to the digital signal processing unit, and outputs the pilot signal to the combiner; among them, the frequency of the sampling clock is f s ; the frequency of the pilot signal is f 1,P ; the waveform of the sideband modulation signal is a sine wave, and the frequency is ν 1,SB ;

[0018] The sideband modulation signal generated by the frequency synthesizer unit is loaded on the electro-optic phase modulator, so that first-order sideband signals are generated on both sides of the optical carrier; the laser frequency of satellite 1 is ν1, and the first-order sideband frequency is v1±v 1,SB ;

[0019] The digital signal processing unit includes a digital filter and a phase-locked loop; the photodetector generates a carrier beat signal and a sideband beat signal, among which, the frequency f 1,carr = v1 - v2; the frequency f 1,SB of the sideband beat signal = (v1 - v2) - (v 1,SB - v 2,SB ), ν2 is the laser frequency of satellite 2, ν 2,SB is the clock sideband modulation signal frequency set by satellite 2. After the carrier beat signal and the sideband beat signal pass through the combiner, a pilot signal with a frequency of f 1,P is added. After the signal output by the combiner passes through the ADC, a digital signal is output; after the digital signal passes through the digital filter and the phase-locked loop, three groups of phase measurement value sequences are obtained respectively, including: the phase measurement value of the pilot signal the phase measurement value of the carrier beat signal the phase measurement value of the sideband beat signal

[0020] In satellite 2, a ultra-stable crystal oscillator provides a reference frequency for the frequency synthesizer unit. The frequency synthesizer unit generates a sampling clock signal, an FPGA operating clock signal, a pilot signal, and a sideband modulation signal through a phase-locked frequency multiplication circuit, sends the sampling clock signal to the ADC, sends the FPGA operating clock signal to the digital signal processing unit, and outputs the pilot signal to the combiner; among them, the frequency of the sampling clock is f s ; the frequency of the pilot signal is f 2,P ; the waveform of the sideband modulation signal is a sine wave, and the frequency is ν 2,SB; The sideband modulation signal generated by the frequency synthesis unit is loaded onto the electro-optic phase modulator, causing first-order sideband signals to be generated on both sides of the optical carrier; the laser frequency of satellite 2 is ν2, and the first-order sideband frequency is v2 ± v 2,SB ;

[0021] The digital signal processing unit includes a digital filter and a phase-locked loop; the photodetector generates a carrier beat signal and a sideband beat signal. Among them, the frequency f 2,car r of the carrier beat signal = v1 - v2; the frequency f 2,SB of the sideband beat signal = (v1 - v2) - (v 1,SB - v 2,SB ); The carrier beat signal and the sideband beat signal are added with a pilot signal of frequency f 2,P after passing through a combiner. The signal output by the combiner is output as a digital signal after passing through an ADC; the digital signal passes through a digital filter and a phase-locked loop to obtain two groups of phase measurement value sequences, including: the phase measurement value of the pilot signal the phase measurement value of the carrier beat signal

[0022] The two satellites transmit the phase measurement value sequence and the corresponding carrier frequency value to the ground, eliminating the dual-star ADC aperture jitter noise and sampling clock jitter noise in the original phase measurement value combination, and outputting a signal

[0023]

[0024] Among them, D τ is the time delay operator, and there is D τ F(t) = F(t - τ), where F(t) is a function of time t, and τ is the inter-satellite link time delay of the two satellites obtained through the GNSS subsystem.

[0025] A method for suppressing the sampling jitter of an analog-to-digital converter using the above system includes the following steps:

[0026] Step 1: Each of the two satellites performs optical carrier phase measurement to obtain the carrier beat signal phase measurement value sequence and and the corresponding carrier frequency values f 1,carr and f 2,carr , and use the GNSS subsystem for time synchronization and satellite orbit determination during the carrier phase measurement;

[0027] Step 2: Satellite 1 performs pilot signal measurement to obtain the pilot signal phase measurement value sequence of satellite 1

[0028] Step 3: Satellite 2 performs pilot signal measurement to obtain the pilot signal phase measurement value sequence of satellite 2

[0029] Step 4: Satellite 1 measures the sideband beat frequency signal below the carrier frequency to obtain a sequence of measured phase values of the sideband beat frequency signal and the corresponding frequency value f 1,SB ;

[0030] Step 5: The two satellites transmit the sequence of measured phase values and the corresponding carrier frequency values to the ground, eliminate the dual-star ADC aperture jitter noise and sampling clock jitter noise in the original combination of measured phase values, and the two-way optical carrier phase measurement system outputs a signal

[0031]

[0032] where D τ is the time delay operator, and there is D τ F(t) = F(t - τ), where F(t) is a function of time t, and τ is the inter-satellite link delay of the two satellites obtained through the GNSS subsystem

[0033] The advantages of the present invention compared with the prior art are as follows:

[0034] (1) The ADC sampling jitter noise consists of two types of noise: aperture jitter and sampling clock jitter. The present invention proposes an implementation scheme for eliminating ADC aperture jitter and sampling clock jitter in a dual-star formation system, completely eliminating the ADC sampling jitter noise in carrier phase measurement

[0035] (2) In the present invention, the sampling clock, pilot signal, and clock sideband modulation signal are designed with the same source, generated by the same frequency synthesis unit receiving the internal reference clock signal, and have the same background noise, which can better eliminate the ADC sampling jitter noise and reduce the influence of sampling clock jitter on eliminating aperture noise of the pilot signal

[0036] (3) The present invention uses the pilot signal generated inside the phase measurement terminal to be combined with the signal to be measured and then enters the digital phase-locked loop through ADC sampling to measure and suppress the aperture jitter noise in the ADC sampling process in real time

[0037] (4) The present invention uses the clock sideband modulation signal generated inside the phase measurement terminal to generate a clock sideband beat frequency signal in the two-way carrier phase measurement system to measure and suppress the sampling clock jitter noise in the ADC sampling process in real time

[0038] (5) The present invention combines the measurement data of aperture jitter noise and the measurement data of sampling clock jitter noise to give a data processing flow, completely eliminating the sampling jitter noise in the ADC sampling process Description of the Drawings

[0039] Figure 1 It is a schematic diagram of a two-way carrier phase measurement system

[0040] Figure 2 It is the system composition diagram for suppressing ADC sampling jitter in Satellite 1;

[0041] Figure 3 It is the system composition diagram for suppressing ADC sampling jitter in Satellite 2;

[0042] Figure 4 It is the data processing flow chart of the present invention. Detailed implementation manners

[0043] The present invention will be described with reference to the accompanying drawings.

[0044] Embodiment

[0045] 1) System for suppressing ADC sampling jitter

[0046] The technical solution of the present invention is to use the clock sideband modulation signal to measure the ADC sampling clock jitter noise in real time, use the pilot signal to measure the ADC aperture jitter in real time, and eliminate the sampling clock jitter and aperture jitter in the data processing of the two-satellite formation two-way carrier phase measurement. Figure 1 It is a schematic diagram of the two-way carrier phase measurement system. Satellite 1 emits a laser beam, which reaches Satellite 2 and interferes with the local oscillator laser of Satellite 2 to measure the phase value of the carrier beat frequency signal Similarly, the local oscillator light of Satellite 1 interferes with the laser from Satellite 2 to measure the phase value of the carrier beat frequency signal Through the linear combination of the two-satellite phase measurement values, the two-satellite displacement information and Doppler frequency shift information can be characterized, providing scientific signal observation values for realizing the inversion of the Earth's time-varying gravity field.

[0047] Taking the spaceborne ultra-stable crystal oscillator as the reference frequency source, the ADC sampling clock, FPGA working clock, pilot signal and sideband modulation signal are output through the frequency synthesis unit. The purpose of generating the pilot signal is to measure the ADC aperture jitter in real time, and the purpose of generating the sideband modulation signal is to measure the ADC sampling clock jitter in real time. The system composition of suppressing ADC sampling jitter in a two-way optical carrier phase measurement system of the present invention is as shown in Figure 2 and Figure 3 shown, mainly including a frequency synthesis unit, an electro-optic phase modulator (EOM) and a digital signal processing unit.

[0048] In Satellite 1, the system composition for suppressing ADC sampling jitter is as follows:

[0049] a) Frequency synthesis unit:

[0050] The ultra-stable crystal oscillator provides the reference frequency for the frequency synthesis unit. The frequency synthesis unit generates four types of signals through the phase-locked frequency multiplication circuit: 1. Sampling clock, with a frequency of f s ; 2. FPGA working clock; 3. Pilot signal, with a frequency of f1,P ; 4. The sideband modulation signal has a sine waveform and a frequency of ν. 1,SB . The frequency of the pilot signal is f 1,P is slightly higher than the intermediate frequency signal frequency to be measured. The sideband modulation signal is about 2 GHz to amplify the sampling clock jitter noise and improve the noise measurement accuracy.

[0051] b) Electro-optic phase modulator (EOM):

[0052] The sideband modulation signal generated by the frequency synthesis unit is loaded onto the EOM, causing first-order sideband signals to be generated on both sides of the optical carrier. The laser frequency of Satellite 1 is ν1, and the first-order sideband frequency is v1 ± v 1,SB . The modulation depth is set to 0.45 rad, consuming approximately 10% of the carrier power.

[0053] c) Digital signal processing unit:

[0054] Since both satellites have sideband modulation signals, at the photodetector, there are: 1. The carrier beat signal f 1,carr , where f 1,carr = v1 - v2; 2. The sideband beat signal f 1,SB , where f 1,SB = (v1 - v2) - (v 1,SB - v 2,SB ), and the other sideband beat signal (v1 - v2) + (v 1,SB - v 2,SB ) is ignored here. After passing through the combiner, a pilot signal with a frequency of f 1,P is also added. Therefore, there are three types of signals in the digital signal after passing through the ADC. After passing through appropriate digital filters and phase-locked loops, three groups of phase measurement value sequences are obtained at time t: the phase measurement value of the pilot signal the phase measurement value of the carrier beat signal the phase measurement value of the sideband beat signal

[0055] In Satellite 2, the system for suppressing ADC sampling jitter consists of the following:

[0056] d) Frequency synthesis unit:

[0057] The ultra-stable crystal oscillator provides a reference frequency for the frequency synthesis unit. The frequency synthesis unit generates four types of signals through a phase-locked frequency multiplication circuit: 1. The sampling clock with a frequency of f s ; 2. The FPGA working clock; 3. The pilot signal with a frequency of f 2,P ; 4. The sideband modulation signal has a sine waveform and a frequency of ν 2,SB . The frequency of the pilot signal is f 2,PSlightly higher than the intermediate frequency signal frequency to be measured. The sideband modulation signal is about 2 GHz to amplify the sampling clock jitter noise and improve the noise measurement accuracy.

[0058] e) Electro-optic phase modulator (EOM):

[0059] The sideband modulation signal generated by the frequency synthesis unit is loaded on the EOM, causing first-order sideband signals to be generated on both sides of the optical carrier. The laser frequency of satellite 2 is ν2, and the first-order sideband frequency is v2 ± v 2,SB . The modulation depth is set to 0.45 rad, consuming approximately 10% of the carrier power.

[0060] f) Digital signal processing unit:

[0061] Since both satellites have sideband modulation signals, at the photodetector, there are: 1. Carrier beat frequency signal f 2,carr , with f 2,carr = v1 - v2; 2. Sideband beat frequency signal f 2,SB , with f 2,SB = (v1 - v2) - (v 1,SB - v 2,SB ), and here we ignore the other sideband beat frequency signal (v1 - v2) + (v 1,SB - v 2,SB ). After the combiner, a pilot signal with a frequency of f 2,P is also added. Therefore, the digital signal after ADC has two types of signals. After passing through an appropriate digital filter and phase-locked loop, two groups of phase measurement value sequences are obtained at time t: the phase measurement value of the pilot signal and the phase measurement value of the carrier beat frequency signal

[0062] 2) Subtract the ADC aperture jitter noise in satellite 1

[0063] As Figure 2 shown, according to the phase measurement value of the pilot signal , the phase noise of the pilot signal can be obtained as:

[0064]

[0065] Among them, f 1,P is the nominal frequency of the pilot signal of satellite 1. Since the pilot signal and the ADC sampling clock are of the same source, the sampling clock jitter noise can be ignored. Therefore is the aperture jitter of the pilot signal passing through the ADC. The aperture jitter noise converted to the carrier beat frequency signal is:

[0066]

[0067] Subtract the aperture jitter noise from the phase measurement value of the carrier beat frequency signal in satellite 1:

[0068]

[0069] Deduct the aperture jitter noise from the phase measurement value of the sideband beat frequency signal of satellite 1:

[0070]

[0071] 3) Deduct the ADC aperture jitter noise in satellite 2

[0072] As Figure 3 shown, according to the phase measurement value of the pilot signal the phase noise of the pilot signal can be obtained as:

[0073]

[0074] where f 2,P is the nominal frequency of the pilot signal of satellite 2. Since the pilot signal and the ADC sampling clock are of the same origin, the sampling clock jitter noise can be ignored. Therefore is the aperture jitter of the pilot signal passing through the ADC. The aperture jitter noise converted to the carrier beat frequency signal is:

[0075]

[0076] Deduct the aperture jitter noise from the phase measurement value of the carrier beat frequency signal of satellite 2:

[0077]

[0078] 4) Deduct the ADC sampling clock jitter noise

[0079] Since the sideband modulation signal and the sampling clock are of the same origin, let the phase noise of the sideband modulation signal be q1, then the sampling clock phase noise is q1f s / ν 1,SB , and the ADC sampling clock jitter noise of the carrier signal is q1f 1,carr / ν 1,SB .

[0080] In the two-way carrier phase measurement system, the phase measurement value of the carrier beat frequency signal of satellite 1 is:

[0081]

[0082] where p1(t) is the phase noise of the local oscillator laser of satellite 1, p2(t - τ) is the phase noise of the laser of satellite 2, and τ is the time delay of the inter-satellite link. The sampling clock jitter noise is not considered here for the time being.

[0083] The phase measurement value of the carrier beat frequency signal at satellite 2 is:

[0084]

[0085] For the convenience of writing and calculation, the time-delay operator D is introduced. τ , we have p i (t - τ) = D τ p i (t) = p i,τ and

[0086] By performing the following linear combination on the phase measurement values of the double stars:

[0087]

[0088] From equations (8) and (9), we can obtain:

[0089]

[0090] This is the output measurement value of the double-star formation carrier phase measurement system.

[0091] Further considering the ADC sampling clock jitter noise of the phase measurement system, we have:

[0092]

[0093] where a1 = f 1,carr / ν 1,SB , a2 = f 1,carr / ν 2,SB , q1 is the clock phase noise of satellite 1 with frequency ν 1,SB , q2 is the clock phase noise of satellite 2 with frequency ν 2,SB . Here, f 1,carr = v1 - v2, ν1 is the laser frequency of satellite 1, ν2 is the laser frequency of satellite 2. Without loss of generality, it is assumed that the laser frequency ν1 of satellite 1 is higher than the laser frequency ν2 of satellite 2.

[0094] Therefore, we have:

[0095]

[0096] At satellite 1 and satellite 2, to extract the clock noise terms of the double stars, the clock signals with frequencies ν 1,SB and ν 2,SB are respectively modulated onto the laser links to form first-order clock sidebands, namely v1 ± v 1,SB and v2 ± v 2,SB . When the frequency difference between ν 1,SB and ν 2,SB is small, the photodetector will receive the beat frequency signal between the first-order sidebands of the double-star lasers, and the beat frequency is f 1,carr +(v 1,SB -v 2,SB ) and f1,carr -(v 1,SB -v 2,SB )。 The former is defined as the upper sideband beat frequency signal, and the latter is defined as the lower sideband beat frequency signal, which are located on the right and left sides of the carrier signal f 1,carr respectively in the frequency spectrum.

[0097] Consider the phase measurement value of the lower sideband beat frequency signal at satellite 1 here:

[0098]

[0099] Among them, due to the change in the frequency of the signal to be measured, the coefficient of the clock noise q1(t) becomes b1 = f 1,SB / ν 1,SB , where f 1,SB = f 1,carr -(v 1,SB -v 2,SB ).

[0100] Further, by subtracting the phase measurement value of the carrier at satellite 1 from the phase measurement value of the clock sideband beat frequency signal at satellite 1, we can obtain:

[0101]

[0102] Define the measurement value:

[0103]

[0104] Obviously, by subtracting the phase measurement value of the carrier beat frequency signal from the phase measurement value of the clock sideband beat frequency signal, the dual-star clock noise term can be extracted, that is:

[0105]

[0106] Therefore, by subtracting the corresponding noise term in equation (13), the suppression of the sampling clock jitter noise can be achieved, that is:

[0107]

[0108] 5) Data processing for suppressing sampling jitter

[0109] The comprehensive implementation method for suppressing ADC aperture jitter and clock phase noise is:

[0110]

[0111] Among them, is the output value of the bidirectional optical carrier phase measurement system after comprehensively suppressing aperture jitter and sampling clock jitter. D τ is the time delay operator, and there is D τF(t) = F(t - τ), where F(t) is a function of time t and τ is the time delay of the inter-satellite link between the two satellites.

[0112] Equation (19) shows that three additional sets of phase measurement values are required to suppress the ADC sampling jitter in a two-way optical carrier phase measurement system:

[0113] ① The phase measurement value of the pilot signal of Satellite 1

[0114] ② The phase measurement value of the pilot signal of Satellite 2

[0115] ③ The phase measurement value of the sideband beat signal of Satellite 1

[0116] Combined with Figure 2 and Figure 3 , under the guidance of Equation (19), the suppression of the ADC sampling clock jitter in two-way optical carrier phase measurement can be achieved.

[0117] For example, Figure 4 , the main implementation steps of a method for suppressing the sampling jitter of an analog-to-digital converter according to the present invention are as follows:

[0118] Step 1: Each of the two satellites performs optical carrier phase measurement to obtain a sequence of phase measurement values and and the corresponding carrier frequency values f 1,carr and f 2,carr , and necessary two-satellite time synchronization and satellite orbit determination are performed using the GNSS subsystem in the carrier phase measurement;

[0119] Step 2: Satellite 1 performs pilot signal measurement to obtain a sequence of phase measurement values

[0120] Step 3: Satellite 2 performs pilot signal measurement to obtain a sequence of phase measurement values

[0121] Step 4: Satellite 1 measures the sideband beat signal below the carrier frequency to obtain a sequence of phase measurement values and the corresponding frequency value f 1,SB ;

[0122] Step 5: The two satellites transmit the sequence of phase measurement values and the corresponding carrier frequency values to the ground for the following combination:

[0123]

[0124] The aperture jitter noise and sampling clock jitter noise of the two-satellite ADC in the original phase measurement value combination can be eliminated. Among them, D τ is the time delay operator, and there is D τF(t) = F(t - τ), where F(t) is a function of time t, and τ is the inter-satellite link delay obtained through the GNSS subsystem. f 1,P and f 2,P are the pilot frequency values set by Satellite 1 and Satellite 2, and ν 2,SB is the clock sideband modulation signal frequency set by Satellite 2.

[0125] The parts not detailed in the present invention are well-known technologies to those skilled in the art.

Claims

1. A system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system, characterized in that: The system for suppressing the sampling jitter of the analog-to-digital converter is provided in both the first satellite and the second satellite; The system for suppressing the sampling jitter of the analog-to-digital converter includes a frequency synthesis unit, an electro-optic phase modulator, and a digital signal processing unit; In the first satellite, the ultra-stable crystal oscillator provides a reference frequency for the frequency synthesis unit. The frequency synthesis unit generates a sampling clock signal, an FPGA working clock signal, a pilot signal, and a sideband modulation signal, sends the sampling clock signal to the ADC, sends the FPGA working clock signal to the digital signal processing unit, and outputs the pilot signal to the combiner; The sideband modulation signal generated by the frequency synthesis unit is loaded on the electro-optic phase modulator, so that first-order sideband signals are generated on both sides of the optical carrier; The digital signal processing unit includes a digital filter and a phase-locked loop; The photodetector generates a carrier beat signal and a sideband beat signal. After passing through a combiner, the carrier beat signal and the sideband beat signal are added with a pilot signal having a frequency of f 1,P . After the signal output by the combiner passes through an ADC, a digital signal is output; After passing through a digital filter and a phase-locked loop, three groups of phase measurement value sequences are obtained from the digital signal, including: the phase measurement value of the pilot signal the phase measurement value of the carrier beat signal the phase measurement value of the sideband beat signal In the second satellite, the ultra-stable crystal oscillator provides a reference frequency for the frequency synthesis unit. The frequency synthesis unit generates a sampling clock signal, an FPGA working clock signal, a pilot signal, and a sideband modulation signal. It sends the sampling clock signal to the ADC, sends the FPGA working clock signal to the digital signal processing unit, and outputs the pilot signal to the combiner. The sideband modulation signal generated by the frequency synthesis unit is loaded onto the electro-optic phase modulator, causing first-order sideband signals to be generated on both sides of the optical carrier. The digital signal processing unit includes a digital filter and a phase-locked loop. The photodetector generates a carrier beat signal and a sideband beat signal. After passing through the combiner, the carrier beat signal and the sideband beat signal are increased by a pilot signal with a frequency of f 2,P . The signal output by the combiner is output as a digital signal after passing through the ADC. After passing through the digital filter and the phase-locked loop, two groups of phase measurement value sequences are obtained, including: the phase measurement value of the pilot signal the phase measurement value of the carrier beat signal The double stars transmit the phase measurement value sequence and the corresponding carrier frequency value to the ground, eliminate the double-star ADC aperture jitter noise and sampling clock jitter noise in the original phase measurement value combination, and output the signal 2. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 1, characterized in that: The two-way carrier phase measurement system includes a first satellite and a second satellite. The first satellite emits a beam of laser, which reaches the second satellite and interferes with the local oscillator laser of the second satellite to measure the phase value of the carrier beat frequency signal. The second satellite emits a beam of laser, which reaches the first satellite. The local oscillator light of the first satellite interferes with the laser from the second satellite to measure the phase value of the carrier beat frequency signal.

3. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 2, characterized in that: In the first satellite, among the sampling clock signal, FPGA working clock signal, pilot signal, and sideband modulation signal generated by the frequency synthesis unit, the frequency of the sampling clock is f s , the frequency of the pilot signal is f 1,P , the waveform of the sideband modulation signal is a sine wave, and the frequency is ν 1,SB ; the sideband modulation signal generated by the frequency synthesis unit is loaded on the electro-optic phase modulator, so that the frequencies of the first-order sideband signals generated on both sides of the optical carrier are v1 ± v 1,SB , where ν1 is the laser frequency of the first satellite.

4. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 3, characterized in that: In the first satellite, the frequency f of the carrier beat signal generated by the photodetector 1,carr = v1 - v2, and the frequency f of the sideband beat signal 1,SB = (v1 - v2) - (v 1,SB - v 2,SB ), ν2 is the laser frequency of the second satellite, and ν 2,SB is the clock sideband modulation signal frequency set by the second satellite.

5. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 4, characterized in that: In the second satellite, among the sampling clock signal, FPGA working clock signal, pilot signal, and sideband modulation signal generated by the frequency synthesis unit, the frequency of the sampling clock is f s , the frequency of the pilot signal is f 2,P , the waveform of the sideband modulation signal is a sine wave, and the frequency is ν 2,SB ; the sideband modulation signal generated by the frequency synthesis unit is loaded onto the electro-optic phase modulator, so that the frequencies of the first-order sideband signals generated on both sides of the optical carrier are v2 ± v 2,SB .

6. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 5, characterized in that: In the second satellite, the frequency f of the carrier beat signal generated by the photodetector 2,carr = v1 - v2, and the frequency f of the sideband beat signal 2,SB = (v1 - v2) - (v 1,SB - v 2,SB ).

7. The system for suppressing sampling jitter of an analog-to-digital converter in a two-way carrier phase measurement system according to claim 6, characterized in that: The double stars transmit the phase measurement value sequence and the corresponding carrier frequency value to the ground, eliminate the double-star ADC aperture jitter noise and sampling clock jitter noise in the original phase measurement value combination, and output the signal Among them, D τ is the time delay operator, and there is D τ F(t) = F(t - τ), where F(t) is a function of time t, and τ is the inter-satellite link delay of the double stars obtained through the GNSS subsystem.

8. A method of using the system for suppressing sampling jitter of an analog-to-digital converter according to any one of claims 1 to 7, characterized in that, The steps are as follows: Step 1: Each of the two satellites performs optical carrier phase measurement to obtain a sequence of phase measurement values of the carrier beat signal and and the corresponding carrier frequency values f 1,carr and f 2,carr , and in the carrier phase measurement, the GNSS subsystem is used for time synchronization between the two satellites and satellite orbit determination; Step 2: The first satellite performs pilot signal measurement to obtain the pilot signal phase measurement value sequence of the first satellite Step 3: The second satellite performs pilot signal measurement to obtain the pilot signal phase measurement value sequence of the second satellite Step 4: The first satellite measures the sideband beat frequency signal below the carrier frequency to obtain a sequence of measured phase values of the sideband beat frequency signal and the corresponding frequency value f 1,SB ; Step 5: The dual satellites transmit the phase measurement value sequence and the corresponding carrier frequency values to the ground, eliminate the dual-satellite ADC aperture jitter noise and sampling clock jitter noise in the original phase measurement value combination, and the bidirectional optical carrier phase measurement system outputs a signal Among them, D τ is the time delay operator, and there is D τ F(t) = F(t - τ), where F(t) is a function of time t, and τ is the inter-satellite link time delay of the double stars obtained through the GNSS subsystem.

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