Semiconductor device, memory device, and method of forming the same

Abstract

In some aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implant region, and a distance between the first doped region and the second doped region is equal to or greater than 0.6 μm.

Description

BACKGROUND

[0001] The present disclosure relates to semiconductor devices, memory devices, and methods of manufacturing the same.

[0002] Integrated circuit isolation, such as local oxidation of silicon (LOCOS), deep trench isolation, and shallow trench isolation (STI, also known as buried oxide isolation technology), is a part of an integrated circuit that separates circuit components and prevents current leakage between adjacent circuit components. For advanced complementary metal oxide semiconductor (CMOS) processes, isolation trenches, especially STI, play an important role in providing isolation between active regions of transistors. SUMMARY

[0003] In one aspect, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, two second doped regions formed in the substrate, and a first gate structure formed between the two second doped regions.

[0004] In another aspect, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. The peripheral circuit includes a high voltage (HV) circuit. The HV circuit includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, two second doped regions formed in the substrate, and a first gate structure formed between the two second doped regions.

[0005] In yet another aspect, a method for forming a semiconductor device includes forming a sacrificial first trench isolation in a substrate, etching back the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, forming a mask layer having an aperture over the first recess and the first trench isolation, ion implantation through the aperture to form a first doped region below the first trench isolation, forming two second doped regions in the substrate, and forming a first gate structure on the substrate and between the two second doped regions.

[0006] In yet another aspect, a method for forming a semiconductor device includes forming a sacrificial first trench isolation in a substrate, and forming a second trench isolation surrounding a portion of the substrate; etching back the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, and etching back the second trench isolation to form a second recess in the second trench isolation; forming a mask layer having an aperture over the first recess and the first trench isolation; ion implantation through the aperture to form a first doped region under the first trench isolation; forming two second doped regions in the substrate; and forming a first gate structure on the substrate and between the two second doped regions and a second gate structure over the portion of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] Figure 1A A schematic diagram showing a cross-section of an exemplary memory device is shown in accordance with some aspects of the present disclosure.

[0009] Figure 1B A schematic diagram showing a cross-section of another exemplary memory device is shown in accordance with some aspects of the present disclosure.

[0010] Figure 2 A schematic circuit diagram of an exemplary memory device including a peripheral circuit having a page buffer is shown in accordance with some aspects of the present disclosure.

[0011] Figure 3 A block diagram of a peripheral circuit provided with various voltages is shown in accordance with some aspects of the present disclosure.

[0012] Figure 4A A plan view of a semiconductor device is shown in accordance with some aspects of the present disclosure.

[0013] Figure 4B An enlarged plan view of a semiconductor device is shown in Figure 4A

[0014] Figure 4C A side view of a cross-section of a semiconductor device is shown in Figure 4A

[0015] A side view of a cross-section of a semiconductor device is shown in accordance with some aspects of the present disclosure. Figure 4D

[0016] Figure 4E ​​A perspective view of a 3D transistor of a semiconductor device is shown in accordance with some aspects of the present disclosure.

[0017] Figure 4F and Figure 4G A side view of two cross-sections of a 3D transistor is shown in accordance with some aspects of the present disclosure. Figure 4E

[0018] Figures 5A-5F A fabrication process for forming a semiconductor device is shown in accordance with some aspects of the present disclosure.

[0019] Figures 6A-6J A fabrication process for forming a semiconductor device is shown in accordance with some aspects of the present disclosure.

[0020] Figure 7 A flowchart of a method for forming an exemplary semiconductor device is shown in accordance with some aspects of the present disclosure.

[0021] Figure 8 A flowchart of a method for forming an exemplary semiconductor device is shown in accordance with some aspects of the present disclosure.

[0022] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Moreover, the present disclosure can be employed in various other applications, including, for example, those not specifically described herein. Accordingly, the function and structure features described herein can be combined, adjusted, and modified in various ways, and such combinations, adjustments, and modifications are considered to be within the scope of the present disclosure.

[0024] In general, terminology can be understood at least in part from usage in context. For example, terms, such as "one or more" as used herein, can be understood as in some contexts including one without necessarily excluding additional, in some contexts excluding one, in some contexts, including one, and, in some contexts, excluding one or in yet other contexts including one, excluding one, including one or more, excluding one or more, and so forth, as appropriate. Similarly, the terms "a" and "an," as used herein, can be understood to mean one or more, depending at least in part on the context in which the terms are used. Further, the term "based on" can be understood as not necessarily intended to refer to a set of conditions that must be satisfied to a certain degree of accuracy but instead can allow for circumstances in which, for example, the set of conditions is not satisfied and certain desired results nevertheless occur.

[0025] ​It should be readily understood that the terms "on," "over," and "above" in the present disclosure are to be interpreted in the broadest possible way, such that "on" means not only "directly on" but also "on with intervening features or layers therebetween," and "over" or "above" means not only "over" or "above" but also "it is over" or "it is above" (i.e., directly on) with no intervening features or layers therebetween.

[0026] Furthermore, to facilitate description, spatially relative terms, such as "under", "below", "lower", "over", "upper", and the like, can be used herein for describing an element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0027] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0028] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over an entire underlying or overlying structure, or can have a extent less than the underlying or overlying structure. Furthermore, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect via contacts are formed) and one or more dielectric layers.

[0029] In 3D NAND memory devices, string drivers are most commonly used and are one of the most important circuits configured to control an array of 3D NAND memory strings. Specifically, more stacked arrays of memory cells require more peripheral circuits to operate multiple semiconductor devices (e.g., memory devices), thereby requiring more high-voltage transistors for the string drivers in the peripheral circuits. One of the reasons for high-voltage transistor failure is electrical breakdown. For example, during programming of a memory cell, a high-voltage transistor of a string driver can hold a bias of more than 25 volts (V). In addition, adjacent high-voltage transistors can have a voltage difference of 25 V from each other. Although there can be a shallow trench isolation (STI) for each high-voltage transistor to be separated and isolated, the breakdown voltage requirement is significantly increased. In addition, during erasing of a memory cell, a high-voltage transistor can hold another bias of more than 24 V from array coupling. These high voltages during operation can cause electrical breakdown of the high-voltage transistor. As the array stack increases, the breakdown voltage requirement also increases. Although the STI can provide isolation for adjacent transistors or other semiconductor devices, the limited chip area limits the increase in width and depth of the STI, thereby limiting the further increase in breakdown voltage.

[0030] One of the bottlenecks of the breakdown voltage (i.e., the breakdown path) is the space between the heavily doped n-well (also known as n-plus (NP) region) of the high-voltage transistor and the STI. In some embodiments, a p-well (also known as a field light doping (FLD) region) is further formed under the STI to provide additional breakdown voltage. This space between the NP and the FLD becomes a critical point for the breakdown voltage of the high-voltage transistor. If the space can be expanded, the breakdown voltage can be increased.

[0031] To address one or more of the foregoing concerns, the present disclosure introduces a solution in which the STI is thinned by removing an upper portion of the STI and a mask layer, which can be a photoresist layer, is provided to cover the thinned STI and ion implantation is performed through an aperture of the mask layer and through the thinned STI to form an FLD region under the thinned STI, thereby reducing the width of the FLD region and thus increasing the breakdown voltage of the high-voltage transistor. In addition, in some embodiments, some steps of the method of forming the FLD region can be configured to form a 3D transistor and a high-voltage transistor in the same process, which significantly simplifies the manufacturing process and reduces the cost of each process.

[0032] It should be noted that the disclosure uses exemplary 3D transistors and exemplary high voltage transistors to illustrate how the disclosed trench isolation can be formed in the same process for these transistors. Any semiconductor device having other types of 3D transistors or high voltage transistors with similar characteristics can also be implemented using the disclosed method with appropriate modifications.

[0033] Figure 1A A schematic diagram of a cross-section of a memory device 100 is shown in accordance with some aspects of the disclosure. The memory device 100 represents an example of a bonded chip. The components of the memory device 100 (e.g., the memory cell array and the peripheral circuitry) can be formed on different substrates, respectively, and then combined to form the bonded chip. The memory device 100 can include a first semiconductor structure 102 that contains an array of memory cells (memory cell array). In some implementations, the memory cell array includes an array of NAND flash memory cells. For ease of description, the memory cell array in the present disclosure can be described using a NAND flash memory cell array as an example. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and can include any other suitable type of memory cell array, such as a dynamic random access memory (DRAM) cell array, a static random access memory (SRAM) cell array, a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, just to name a few, or any combination thereof.

[0034] The first semiconductor structure 102 can be a NAND flash memory device in which the memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into fingers, which are in turn organized into blocks, with each NAND memory cell electrically connected to a separate line called a bit line (BL). All of the cells in a NAND memory cell that have the same vertical position can be electrically connected by a word line (WL) through a control gate. In some implementations, a plane contains a certain number of blocks that are electrically connected by the same bit line. The first semiconductor structure 102 can include one or more planes, and the peripheral circuitry needed to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104.

[0035] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each 2D NAND memory cell including a floating-gate transistor. According to some embodiments, the array of 2D NAND memory cells includes multiple 2D NAND memory strings, each 2D NAND memory string including multiple memory cells connected in series (similar to NAND gates) (e.g., 32 to 128 memory cells) and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (taking a 2D form). In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each 3D NAND memory string extending vertically (taking a 3D form) above the substrate through a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / tiers in the memory stack), a 3D NAND memory string typically includes 32 to 256 NAND memory cells, each NAND memory cell including a floating-gate transistor or a charge-trapping transistor.

[0036] like Figure 1A As shown, the memory device 100 may further include a second semiconductor structure 104, which includes peripheral circuitry for the memory cell array of the first semiconductor structure 102. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for assisting in the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders or column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or voltage generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). For example, the peripheral circuitry may include 3D transistors and high-voltage transistors according to some embodiments of this disclosure.

[0037] like Figure 1AAs shown, the memory device 100 also includes a bonding interface 106 vertically positioned between the first semiconductor structure 102 and the second semiconductor structure 104. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be fabricated separately (and in some embodiments, in parallel) such that a thermal budget of fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not constitute a limitation on the process of fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104. Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through the bonding interface 106 to form direct, short distance (e.g., micron scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, as opposed to long distance (e.g., millimeter or centimeter scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface delays and enabling high speed I / O throughput at reduced power consumption. Data transfers between the array of memory cells in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 can be performed through the interconnects (e.g., bonding contacts) spanning the bonding interface 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, chip size can be reduced and memory cell density can be increased.

[0038] It should be appreciated that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Figure 1B A schematic diagram of a cross-section of another exemplary memory device 101 according to some embodiments is shown. As with the memory device 100 of Figure 1A Unlike the memory device 100 of Figure 1BIn memory device 101, first semiconductor structure 102, which includes an array of memory cells, is located above second semiconductor structure 104, which includes peripheral circuitry. Nonetheless, according to some embodiments, bonding interface 106 is formed vertically between first semiconductor structure 102 and second semiconductor structure 104 in memory device 101, and first semiconductor structure 102 and second semiconductor structure 104 are bonded vertically through bonding (e.g., hybrid bonding). Hybrid bonding (also known as "metal / dielectric hybrid bonding") is a direct bonding technique (e.g., forming a bond between surfaces without using an intervening layer such as solder or adhesive), and can achieve both metal-metal (e.g., Cu to Cu) bonding and dielectric-dielectric (e.g., Si02to Si02) bonding simultaneously. Data transfer between the array of memory cells in first semiconductor structure 102 and the peripheral circuitry in second semiconductor structure 104 can be performed through interconnects (e.g., bonding contacts) across bonding interface 106.

[0039] Figure 2 A schematic circuit diagram of a memory device 200 including peripheral circuitry is shown in accordance with some aspects of the present disclosure. Memory device 200 can include an array of memory cells 201 and peripheral circuitry 202 coupled to array of memory cells 201. Memory devices 100 and 101 can be examples of memory device 200, where array of memory cells 201 and peripheral circuitry 202 can be contained in first semiconductor structure 102 and second semiconductor structure 104, respectively. Array of memory cells 201 can be a NAND flash array of memory cells, where memory cells 206 are provided in the form of an array of 3D NAND memory strings 208, each 3D NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 can hold a continuous analog value (e.g., voltage or charge) that depends on the number of electrons captured within a region of memory cell 206. Each memory cell 206 can be a floating gate type of memory cell that includes a floating gate transistor, or can be a charge trap type of memory cell that includes a charge trapping transistor.

[0040] In some implementations, each memory cell 206 is a single-level cell (SLC) flash memory having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell 206 is a multi-level cell (MLC) flash memory capable of storing two memory states. In some implementations, each memory cell 206 may be a triple-level cell (TLC) or a quad-level cell (QLC). Each MLC can be programmed to present a range of possible nominal memory values. In one example, if each MLC stores two bits of data, then the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used for the erase state.

[0041] like Figure 2 As shown, each 3D NAND memory string 208 may include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end, such that the SSG transistor 210 and DSG transistor 212 can be configured to activate the selected 3D NAND memory string 208 (column of the array) via its source and drain ends during read and program operations. In some embodiments, the sources of the SSG transistors 210 of the 3D NAND memory strings 208 in the same block 204 are coupled to, for example, ground via the same source line (SL) 214 (e.g., a common SL). In some embodiments, the drains of the DSG transistors 212 of the 3D NAND memory strings 208 in the same block 204 are coupled to a page buffer (not shown) in peripheral circuitry 202. According to some embodiments, the DSG transistor 212 of each 3D NAND memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each 3D NAND memory string 208 is configured to be selected or unselected by applying a selection voltage (e.g., higher than the threshold voltage of the DSG transistor 212) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the SSG transistor 210) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0042] like Figure 2 As shown, the 3D NAND memory string 208 can be organized into multiple blocks 204, each of which may have a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a row 220 of memory cells 206, which is a basic data unit for program and read operations. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 in the corresponding row 220 and gate lines coupling the control gates.

[0043] Peripheral circuitry 202 can be coupled to memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, peripheral circuitry 202 can include any suitable circuitry to facilitate the operation of memory cell array 201. For example, peripheral circuitry 202 can read target memory cell 206 of memory cell array 201 by applying a read voltage signal to word line 218 containing data to be read and sensing whether target memory cell 206 on word line 218 has been switched. Furthermore, peripheral circuitry 202 can write / program target memory cell 206 of memory cell array 201 by applying a write voltage signal to word line 218 containing data to be written. Additionally, the peripheral circuitry 202 is configured to select or deselect each 3D NAND memory string 208 by applying a selection voltage (e.g., higher than the threshold voltage of the DSG transistor 212) or a deselect voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the SSG transistor 210) or a deselect voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215. The peripheral circuitry 202 may include various types of peripheral circuitry formed using CMOS technology. For example, the peripheral circuitry may include 3D transistors and high-voltage transistors according to some embodiments of this disclosure.

[0044] Unlike logic devices, memory devices (e.g., 3D NAND flash memory) require a wide range of voltages to supply to the memory's peripheral circuitry. These voltages include higher voltages (e.g., 3.3V or higher) that are unsuitable for logic devices (e.g., microprocessors) particularly using advanced CMOS technology nodes (e.g., sub-22nm), but are necessary for memory operation. Figure 3A block diagram of a peripheral circuit provided with various voltages is shown in accordance with some aspects of the present disclosure. In some implementations, the peripheral circuit (e.g., peripheral circuit 202 in memory device 200 in Figure 2 Figure 2 The peripheral circuit (e.g., peripheral circuit 202 in memory device 200 in

[0045] ​In some embodiments, the LLV source 301 is configured to provide a voltage between 0.9V and 2.0V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, 1.25V, 1.3V, 1.35V, 1.4V, 1.45V, 1.5V, 1.55V, 1.6V, 1.65V, 1.7V, 1.75V, 1.8V, 1.85V, 1.9V, 1.95V, any range defined by any one of these values as a lower limit, or within any range defined by any two of these values). In one example, the voltage is 1.2V. In some embodiments, the LV source 303 is configured to provide a voltage between 2V and 3.3V (e.g., 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range defined by any one of these values as a lower limit, or within any range defined by any two of these values). In one example, the voltage is 3.3V. In some embodiments, the HV source 305 is configured to provide a voltage greater than 3.3V. In one example, the voltage is between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range defined by any one of these values as a lower limit, or within any range defined by any two of these values). It should be understood that the voltage ranges described above with respect to the HV source 305, the LV source 303, and the LLV source 301 are for illustrative purposes only and are non-limiting, as any other appropriate voltage ranges can be provided by the HV source 305, the LV source 303, and the LLV source 301. However, the voltage levels provided by at least the LV source 303 and the HV source 305 (e.g., 2V and higher) can not be suitable for 3D transistors (e.g., fin field effect transistors, also referred to as FinFETs) in logic devices using advanced CMOS technology nodes (e.g., sub-22nm).

[0046] Memory peripheral circuits (e.g., peripheral circuits 202) can be classified as LLV circuits 302, LV circuits 304, and HV circuits 306 coupled to LLV source 301, LV source 303, and HV source 305, respectively, based on their applicable voltage levels (Vddi, Vdd2, or Vdd3). In some implementations, HV circuits 306 include one or more drivers coupled to a memory cell array (e.g., memory cell array 201) through word lines, bit lines, SSG lines, DSG lines, source lines, etc., and are configured to drive the memory cell array by applying voltages at appropriate levels to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuits 306 can be voltage-tolerant in a range between, for example, 5V and 30V. In one example, HV circuits 306 can include word line drivers (not shown) that apply a program voltage (Vprog) or pass voltage (Vpass) in a range between, for example, 5V and 30V to a word line during a program operation. In another example, HV circuits 306 can include bit line drivers (not shown) that apply an erase voltage (Veras) in a range between, for example, 5V and 30V to a bit line during an erase operation. In some implementations, LV circuits 304 include page buffers (not shown) configured to buffer data read from or to be programmed to the memory cell array. For example, a voltage of, for example, 3.3V can be provided to the page buffers by LV source 303. In some implementations, LLV circuits 302 include I / O circuits (not shown) configured to interface the memory cell array with a memory controller. For example, a voltage of, for example, 1.2V can be provided to the I / O circuits by LLV source 301.

[0047] At least one of the LLV circuit 302, the LV circuit 304, or the HV circuit 306 can include the 3D transistor disclosed herein. In some implementations, each of the LLV circuit 302, the LV circuit 304, and the HV circuit 306 includes the 3D transistor. In one example, the LLV circuit 302 can be capable of withstanding voltages in a range of, for example, between 0.9 V and 2 V. In one example, the LV circuit 304 can be capable of withstanding voltages in a range of, for example, between 2 V and 3.3 V. In some implementations, each of the LLV circuit 302 and the LV circuit 304 includes the 3D transistor, while the HV circuit 306 includes a planar circuit. Further, the LLV circuit 302, the LV circuit 304, or the HV circuit 306 can be implemented as a peripheral circuit with the 3D transistor and / or the planar transistor in any suitable combination disclosed herein. In some implementations, the 3D transistor can provide much better control of the channel and prevent leakage current between the source and the drain when the gate is off. In addition, the 3D transistor can reduce chip area and power consumption.

[0048] To address the challenges described above, a semiconductor device 400 is provided in accordance with some aspects of the present disclosure. For example, the semiconductor device 400 can be included in the HV circuit 306 in Figure 3 As shown in a plan view of the semiconductor device 400, one or more HV transistors 401 are formed on a substrate 421 in Figure 4A The HV transistors 401 can be separated or partitioned in the y-direction and / or the x-direction by one or more trench isolations 411 and one or more first doped regions 413. It should be noted that in the following, the x-axis, the y-axis, and the z-axis in the figures show the spatial relationship of the components therein. For example, the substrate 421 includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally in the x-direction (lateral direction or width direction). As used herein, when the substrate of a semiconductor device is located in the lowest plane of the semiconductor device in the z-direction (vertical direction or thickness direction), is a component (e.g., layer or device) of the semiconductor device “on,” “above,” or “below” another component (e.g., layer or device) determined with respect to the substrate in the z-direction. The same concept will be employed throughout the present disclosure to describe the spatial relationship.

[0049] The trench isolation 411 is formed in and extends in the substrate 421 and is configured to prevent current leakage between adjacent transistors or other semiconductor devices (e.g., adjacent HV transistors 401).

[0050] The first doped region 413 comprises a p-type doped material. In other words, the first doped region 413 is doped with any suitable p-type dopant, such as boron (B) or gallium (Ga). In some embodiments, the first doped region 413 is formed beneath the trench isolation 411 and is configured to provide high resistance and block leakage paths. For example, the surface doping concentration of the first doped region 413 may be 1 x 10⁻⁶. 16 Up to 1x10 19 cm -3 For example, the surface doping concentration of the first doped region 413 can be 1 x 10⁻⁶. 16 2x10 16 3x10 16 4x10 16 5x10 16 6x10 16 7x10 16 8x10 16 9x10 16 1x10 17 2x10 17 3x10 17 4x10 17 5x10 17 6x10 17 7x10 17 8x10 17 9x10 17 1x10 18 2x10 18 3x10 18 4x10 18 5x10 18 6x10 18 7x10 18 8x10 18 9x10 18 Or 1x10 19 cm -3 In some embodiments, the first doped region 413 is an ion implantation region.

[0051] HV transistor 401 may include one or more gate structures 403 formed between two of the one or more second doped regions 405. In some embodiments, HV transistor 401 may have two gates and three n-wells, such as Figure 4AThe two gate fingers are electrically connected and connected to a gate pad. The second doped region 405 includes an n-type doped material. In other words, the second doped region 405 is doped with any suitable n-type dopant, such as phosphorus (P) or arsenic (As). In some embodiments, the two second doped regions 405 are configured to be n-wells of the HV transistor 401. For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 19 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. -3 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 17 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 18 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. 19 For example, the surface doping concentration of the second doped region 405 can be 1 x 1018to 1 x 1020cm-3. -3 .

[0052] The HV transistor 401 can also include a third doped region 404 formed below the second doped region 405 and the gate structure 403. The third doped region 404 includes a p-type doped material. In other words, the third doped region 404 is doped with any suitable p-type dopant, such as boron (B) or gallium (Ga). In some embodiments, the third doped region 404 is configured to be a p-well of the HV transistor 401. For example, the surface doping concentration of the third doped region 404 can be 1 x 1018to 1 x 1020cm-3. 16 For example, the surface doping concentration of the third doped region 404 can be 1 x 1018to 1 x 1020cm-3. 19 For example, the surface doping concentration of the third doped region 404 can be 1 x 1018to 1 x 1020cm-3. -3For example, the surface doping concentration of the third doped region 404 can be 1 x 10⁻⁶. 16 2x10 16 3x10 16 4x10 16 5x10 16 6x10 16 7x10 16 8x10 16 9x10 16 1x10 17 2x10 17 3x10 17 4x10 17 5x10 17 6x10 17 7x10 17 8x10 17 9x10 17 1x10 18 2x10 18 3x10 18 4x10 18 5x10 18 6x10 18 7x10 18 8x10 18 9x10 18 Or 1x10 19 cm -3 In some embodiments, the third doped region 404 is formed by providing a p-doped substrate and bonding the p-doped substrate to the substrate 421. Based on the fact that the second doped region 405 is the n-well of the HV transistor 401 and the third doped region 404 is the p-well of the HV transistor 401, when the HV transistor 401 is in the "on" state (i.e., a forward voltage is applied), it exhibits resistive behavior between the drain and source terminals. In other words, it allows current flow when the n-well and p-well are forward biased. Moreover, when the HV transistor 401 is in the "off" state (i.e., a reverse voltage is applied), the HV transistor 401 is equivalent to a PN diode or PIN diode. In other words, when the n-well and p-well are reverse biased, the space charge region extends primarily on one of the doped sides (i.e., the n-well side). This PN junction in the "off" state can remain reverse biased between the drain and source terminals, acting as an insulator and disallowing current flow. This PN junction structure is particularly capable of withstanding high breakdown voltages.

[0053] As mentioned above, although the HV transistor 401 can maintain a high breakdown voltage, trench isolation may become a bottleneck to improving the breakdown voltage. Figure 4B Some aspects of this disclosure are shown. Figure 4Aenlarged plan view of a semiconductor device in a semiconductor-on-insulator (SOI) structure. As shown, the semiconductor device includes a substrate 421, an HV transistor 401 formed on the substrate 421, a first trench isolation 411 formed alongside the HV transistor 401 and configured to block a leakage path between the HV transistor 401 and an adjacent transistor, and a first doped region 413 formed below the first trench isolation 411. The semiconductor device can also include an interlayer dielectric (ILD) 4119 formed above the substrate 421 and covering a top surface of the HV transistor 401 and the first trench isolation 411. Figure 4B As shown, when a high reverse bias is applied to the HV transistor 401, a space between the n-well (i.e., NP) region and the trench isolation (i.e., STI) and the first doped region (i.e., FLD) thereunder creates a high electric field. The distance of this space is a key point for the breakdown voltage. Specifically, the longer the distance, the higher the breakdown voltage that the HV transistor can withstand. Since the width of the n-well of the HV transistor 401 cannot be modified easily due to the limited chip area, other solutions can be needed to increase the distance. Moreover, conventional photolithography techniques can not be able to achieve a width of the FLD region that is less than 0.4 pm or a distance between the NP region and the FLD region that is greater than 0.6 pm, the disclosed techniques according to some aspects of the present disclosure provide a manufacturing method that improves such limitations. Thus, it is informed that using the method according to the present disclosure, the distance between the NP region and the FLD region can be greater than 0.6 pm, such as 0.6-0.8 pm, for example, 0.61 pm, 0.62 pm, 0.63 pm, 0.64 pm, 0.65 pm, 0.66 pm, 0.67 pm, 0.68 pm, 0.69 pm, 0.70 pm, 0.71 pm, 0.72 pm, 0.73 pm, 0.74 pm, 0.75 pm, 0.76 pm, 0.77 pm, 0.78 pm, 0.79 pm, or 0.80 pm. In some embodiments, the distance between the NP region and the STI can be greater than 0.4 pm, such as 0.4-0.6 pm, for example, 0.41 pm, 0.42 pm, 0.43 pm, 0.44 pm, 0.45 pm, 0.46 pm, 0.47 pm, 0.48 pm, 0.49 pm, 0.50 pm, 0.51 pm, 0.52 pm, 0.53 pm, 0.54 pm, 0.55 pm, 0.56 pm, 0.57 pm, 0.58 pm, 0.59 pm, or 0.60 pm.

[0054] Figure 4C shows a side view of a cross-section of a semiconductor device 400 along the AA plane in FIG. 4A, according to some aspects of the present disclosure. As shown, the semiconductor device 400 includes a substrate 421, an HV transistor 401 formed on the substrate 421, a first trench isolation 411 formed alongside the HV transistor 401 and configured to block a leakage path between the HV transistor 401 and an adjacent transistor, and a first doped region 413 formed below the first trench isolation 411. The semiconductor device 400 can also include an interlayer dielectric (ILD) 4119 formed above the substrate 421 and covering a top surface of the HV transistor 401 and the first trench isolation 411. Figure 4A Figure 4C As shown, the semiconductor device 400 includes a substrate 421, an HV transistor 401 formed on the substrate 421, a first trench isolation 411 formed alongside the HV transistor 401 and configured to block a leakage path between the HV transistor 401 and an adjacent transistor, and a first doped region 413 formed below the first trench isolation 411. The semiconductor device 400 can also include an interlayer dielectric (ILD) 4119 formed above the substrate 421 and covering a top surface of the HV transistor 401 and the first trench isolation 411.

[0055] ​The HV transistor 401 can include a third doped region 404 formed in the substrate 421 and extending into the substrate 421 in the z-direction, a second doped region 405 formed in the third doped region 404 of the substrate 421, and a first gate structure 408 formed on the substrate 421 and extending vertically (i.e., in the z-direction) and laterally (i.e., in the y-direction) between two second doped regions 405. The first gate structure 408 includes a first gate dielectric 407 formed on the third doped region 404 of the substrate 421 and a first gate electrode 409 formed on the first gate dielectric 407. The HV transistor 401 can also include a first electrode 425 formed on and electrically connected to the respective second doped region 405 and a second electrode 427 formed on and electrically connected to the first gate electrode 409.

[0056] The substrate 421 can include silicon (e.g., single-crystalline silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other appropriate material. In some embodiments, the substrate 421 includes a Si substrate. The first gate dielectric 407 can include any appropriate dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the first gate dielectric 407 includes silicon oxide (i.e., gate oxide). The first gate electrode 409 can include any appropriate conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. In some embodiments, the first gate electrode 409 includes doped polysilicon (i.e., gate poly). The interlayer dielectric 4119 can include any appropriate dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the interlayer dielectric 4119 includes silicon oxide. The first electrode 425 and the second electrode 427 can include any appropriate conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. In some embodiments, the first electrode 425 and the second electrode 427 include tungsten.

[0057] A first trench isolation 411 is formed, and extends vertically (i.e., in the z-direction) into the substrate 421, and is also formed next to the HV transistor 401 to isolate the HV transistor 401 from adjacent transistors and prevent leakage paths. The trench isolation (e.g., the first trench isolation 411) can be a shallow trench isolation (STI). These STIs can be formed in or on the substrate 421 and located between adjacent transistors or other semiconductor devices to reduce current leakage. The trench isolation (e.g., the first trench isolation 411) can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric with a dielectric constant or k-value higher than silicon nitride (k > 7). In some embodiments, the material of the first trench isolation 411 includes silicon oxide. In some embodiments, the first trench isolation 411 can be a thinned trench isolation. In other words, the top surface of the thinned isolation trench 411 is lower than the top surface of the substrate 421.

[0058] A first doped region 413 is formed below the first trench isolation 411 and has a width equal to or less than 0.2 pm in the lateral direction (e.g., in the y-direction). Also, as shown, the distance dl between the second doped region 405 and the first doped region 413 in the lateral direction (e.g., in the y-direction) is equal to or greater than 0.6 pm, or even greater than 0.7 pm. The reduced width of the first doped region 413 and the increased distance between the second doped region 405 and the first doped region 413 can significantly improve the breakdown voltage of the HV transistor 401. It should be noted that the distances herein refer to the closest portion of a region to the closest portion of another region. Figure 4C

[0059] Figure 4D A side view of a cross-section of another semiconductor device 420 is shown, in accordance with some aspects of the present disclosure. The semiconductor device 420 is similar to the semiconductor device 400, except for a 3D transistor 430 formed on the substrate 421. For ease of description, other components in the semiconductor device 420 that are the same as those in the semiconductor device 400 can be referred to by the same reference numbers as in the semiconductor device 400. As shown, the semiconductor device 420 can include the 3D transistor 430 formed on the substrate 421. According to some embodiments of the present disclosure, the 3D transistor 430 can be included in the LLV circuit 302 or the LV circuit 304. It should be noted that although the 3D transistor 430 is shown as a vertical transistor, the 3D transistor 430 can also be a lateral transistor. Figure 4C Figure 4D Figure 4D ​​​The 3D transistor 430 is shown in the zy plane and is arranged side by side with the HV transistor 401 and the first trench isolation 411, but it is not necessary to arrange the 3D transistor 430 in this manner. For example, the 3D transistor 430 may be rotated 90 degrees or be in other orientations, or the 3D transistor 430 may be arranged at the far end of the substrate 421 or even on another substrate 421 in the same wafer (not shown).

[0060] 3D transistor 430 can also be used in Figures 4E-4G As shown in the image. It is possible to... Figure 4D and Figures 4E-4G Let's discuss it together. For example... Figure 4E As shown, the 3D transistor 430 may include a 3D semiconductor body 446 having a source 4461, a drain 4462, and an active region 4463 formed between the source 4461 and the drain 4462. The 3D semiconductor body 446 is partially formed in a second recess 436 extending through the second trench isolation 431 in the z-direction. In other words, at least a portion of the 3D semiconductor body 446 (i.e., the bottom portion of the 3D semiconductor body 446) is surrounded by the second trench isolation 431. In some embodiments, the 3D transistor 430 further includes a gate structure 435 in contact with a portion 433 of the substrate (e.g., corresponding to the active region 4463). The gate structure 435 may include a second gate dielectric 437 and a second gate electrode 439 formed on the second gate dielectric 437. The portion 433 of the substrate is surrounded by the source 4461 and the drain 4462 in the x-direction and by the second trench isolation 431 in the y-direction. The 3D semiconductor body 446 extends at least partially above the top surface of the substrate 421, thereby exposing not only the top surface of the 3D semiconductor body 446 but also both side surfaces of the 3D semiconductor body 446. For example... Figure 4EAs shown, for example, the 3D semiconductor body 446 can take a 3D structure (also referred to as a "fin") to expose three of its faces. Also, the 3D semiconductor body 446 can extend through the second trench isolation 431 and can be at least partially surrounded by the second trench isolation 431 on both sides in the y-direction. In some embodiments, the 3D semiconductor body 446 is formed from the substrate 421. In some embodiments, the 3D semiconductor body 446 includes single crystalline silicon. The source 4461 and the drain 4462 can be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). In plan view, the source 4461 and the drain 4462 can be separated by the gate structure 435. That is, according to some embodiments, in plan view, the gate structure 435 is formed between the source 4461 and the drain 4462. When a gate voltage applied to the second gate electrode 439 of the gate structure 435 is higher than a threshold voltage of the 3D transistor 430, a channel of the 3D transistor 430 in the substrate 421 can be formed laterally under the gate structure 435 between the source 4461 and the drain 4462. As Figure 4E As shown, the gate structure 435 can be located over and in contact with a portion 433 of the substrate (i.e., an active region 4463) in which a channel can be formed. In other words, according to some embodiments, the gate structure 435 is in contact with three faces of the active region 4463 (i.e., in a top plane of the portion 433 of the substrate and two side planes of the portion 433 of the substrate). Also, the portion 433 of the substrate is surrounded by the gate structure 435 in the y-direction and by the source 4461 and the drain 4462 on the other two sides in the x-direction. It should be understood that, although not shown in Figures 4E-4G the 3D transistor 430 can include additional components, such as a well and a spacer.

[0061] The second gate dielectric 437 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the second gate dielectric 437 includes silicon oxide (i.e., a gate oxide). The second gate electrode 439 can include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. In some embodiments, the second gate electrode 439 includes doped polysilicon (i.e., gate polysilicon).

[0062] A second trench isolation 431 is formed, and the second trench isolation 431 extends vertically (i.e., in the z-direction) into the substrate 421. The second trench isolation 431 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material comprises any dielectric with a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, the material of the second trench isolation 431 comprises silicon oxide. In some embodiments, the depth of the second recess 436 is substantially the same as the depth between the top surface of the substrate 421 and the top surface of the thinned trench isolation 411.

[0063] Figures 5A-5F The present disclosure illustrates some aspects of forming a semiconductor device 500 (corresponding to...) Figure 4C The manufacturing process of semiconductor devices (400) in China. Figure 7 Examples of semiconductor devices (corresponding to) are shown in accordance with some aspects of this disclosure. Figure 4C The flowchart of method 700 (using semiconductor device 400) is provided. It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figures 5A-5F and Figure 7 The different execution sequences shown will affect Figures 5A-5F and Figure 7 Describe them together.

[0064] refer to Figure 7 Method 700 begins with operation 702, in which a sacrificial first trench isolation is formed in the substrate. For example, as... Figure 5A As shown, on substrate 521 (corresponding to Figure 4CA sacrificial first trench isolation 5111 is formed in substrate 521. In some embodiments, the sacrificial first trench isolation 5111 may be STI and is formed in substrate 521, for example, using wet / dry etching and thin film deposition of silicon oxide. The top surface of the sacrificial first trench isolation 5111 may be planarized, for example, using chemical mechanical polishing (CMP). The sacrificial first trench isolation 5111 may divide substrate 521 into multiple regions, in which multiple transistors may be formed respectively. In some embodiments, the sacrificial first trench isolation 5111 is formed by etching substrate 521 to form a first trench recess (not shown). After forming the first trench recess, an oxide layer (not shown) is deposited covering substrate 521 and located in the first trench recess. Next, the oxide layer covering substrate 521 is removed, leaving the oxide layer in the first trench recess to form the sacrificial first trench isolation 5111. In some embodiments, removing the oxide layer covering the substrate 521 includes applying CMP to the oxide layer to remove the oxide layer covering the substrate 521.

[0065] As mentioned above, in order to form the FLD region under trench isolation, a mask layer with a hole pattern should be provided to form the FLD region. However, due to the critical dimension (CD) of the hole pattern forming the mask layer (e.g., the minimum diameter of the hole is approximately 0.36 μm), the width of the FLD region cannot be less than 0.4 μm. Therefore, the process for manufacturing trench isolation and the FLD region in this disclosure provides a solution to this challenge.

[0066] Method 700 proceeds to operation 704, such as... Figure 7 As shown, in this operation, the first trench isolation is etched back to form a first depression and a first trench isolation. For example, as... Figure 5B As shown, the sacrificial first trench isolation 5111 is etched back using photolithography and wet / dry etching to form a first recess 5113 and the first trench isolation 511. The first recess 5113 is formed on the first trench isolation 511. In some embodiments, the first trench isolation 511 is as follows: Figure 4C Thinning of the trench isolation 411.

[0067] Next, method 700 proceeds to operation 706, such as... Figure 7 As shown, in this operation, a mask layer with holes is formed over the first recess and the first trench isolation. For example, as Figure 5CAs shown, a mask layer 5115 having an aperture 5117 is formed over the first recess 5113 and the first trench isolation 511. In some embodiments, the mask layer 5115 includes a photoresist layer. The mask layer 5115 having the aperture 5117 is configured for ion implantation of the FLD region under the first trench isolation 511 as discussed above. Also, because the thickness of the first trench isolation 511 is reduced, a lower power is needed for ion implantation to form the FLD region. Therefore, the thickness of the mask layer 5115 in the first recess 5113 and the size (e.g., critical dimension) of the aperture 5117 can also be reduced. It should be noted that the size (e.g., critical dimension) of the aperture 5117 is reduced because when the mask layer 5115 (e.g., photoresist material) is formed in the recess (e.g., first recess 5113), the remaining mask after being subjected to ultraviolet exposure and development can have a smaller pattern than expected. In addition, by using the thinned first trench isolation 511, the energy of the ion implantation that penetrates the STI is reduced, thereby reducing the thickness of the mask layer 5115 that is compatible with the energy of the ion implantation. For example, to penetrate a 0.5 μm STI to form the FLD region, a 5 μm photoresist layer is needed to have an energy of 210 keV, such that the minimum critical dimension of the aperture is limited to 0.36 μm. By using the thinned first trench isolation 511, because the STI is thinned to, for example, 0.3 μm, the energy of the ion implantation can be reduced to 180 keV for a 3 μm photoresist layer, such that the minimum critical dimension of the aperture is reduced to 0.2 μm or less. With the reduced aperture size, the thinned mask layer, and the thinned trench isolation, not only does the ion implantation to form the FLD region allow a lower power, but also the width of the FLD region is reduced to a limit that is not achievable by existing photolithography technology.

[0068] Next, the method 700 proceeds to operation 708, in which a first doped region is formed under the first trench isolation by ion implantation, as shown in FIG. 5B. For example, the first doped region 513 having a reduced width is formed by ion implantation through the aperture 5117 of the mask layer 5115 and through the first trench isolation 511, as shown in FIG. 5B. The width of the first doped region 513 can be equal to or less than 0.2 μm. The first doped region 513 can be doped with any suitable p-type dopant (e.g., B or Ga). The power of the ion implantation can be, for example, 150 to 270 keV. In some embodiments, the mask layer 5115 can be stripped after the ion implantation. Figure 7 Figure 5C Next, the method 700 proceeds to operation 710, in which two second doped regions are formed in the substrate, as shown in FIG. 5C. For example, the two second doped regions 515 are formed by ion implantation through the aperture 5117 of the mask layer 5115 and through the first trench isolation 511, as shown in FIG. 5C. The two second doped regions 515 can be doped with any suitable n-type dopant (e.g., P or As). The power of the ion implantation can be, for example, 150 to 270 keV. In some embodiments, the mask layer 5115 can be stripped after the ion implantation.

[0069] Next, the method 700 proceeds to operation 710, in which two second doped regions are formed in the substrate, as shown in FIG. 5C. For example, the two second doped regions 515 are formed by ion implantation through the aperture 5117 of the mask layer 5115 and through the first trench isolation 511, as shown in FIG. 5C. The two second doped regions 515 can be doped with any suitable n-type dopant (e.g., P or As). The power of the ion implantation can be, for example, 150 to 270 keV. In some embodiments, the mask layer 5115 can be stripped after the ion implantation. Figure 7 Figure 5D ​​As shown, two second doped regions 505 are formed in the substrate 521 by any suitable doping technique (e.g., ion implantation). The second doped regions 505 can be doped with any suitable n-type dopant (e.g., P or Ar). In some embodiments, the two second doped regions 505 are formed in the third doped region 504 of the substrate 521. The third doped region 504 can be formed in the substrate 521 by any suitable doping technique (e.g., ion implantation). The third doped region 504 can be doped with any suitable p-type dopant (e.g., B or Ga).

[0070] Next, the method 700 proceeds to operation 712, in which a first gate structure is formed on the substrate and between the two second doped regions, as shown in FIG. 5B. For example, a first gate structure 508 is formed on the third doped region 504 of the substrate 521 and between the two second doped regions 505, as shown in FIG. 5B. The first gate structure 508 includes a first gate dielectric 507 formed on the third doped region 504 of the substrate 521 and a first gate electrode 509 formed on the first gate dielectric 507. The HV transistor 501 (corresponding to the HV transistor 401 in FIG. 4B) is then formed. Figure 7 Figure 5D Next, the method 700 proceeds to operation 714, in which an interlayer dielectric is formed on the substrate covering the HV transistor and the first trench isolation and filling the first recess, as shown in FIG. 5C. For example, an interlayer dielectric 510 is formed on the substrate 521 covering the HV transistor 501 and the first trench isolation 511 and filling the first recess 512, as shown in FIG. 5C. Figure 4C

[0071] Next, the method 700 proceeds to operation 714, in which an interlayer dielectric is formed on the substrate covering the HV transistor and the first trench isolation and filling the first recess, as shown in FIG. 5C. For example, an interlayer dielectric 510 is formed on the substrate 521 covering the HV transistor 501 and the first trench isolation 511 and filling the first recess 512, as shown in FIG. 5C. Figure 7 Figure 5E ​​​As shown, an interlayer dielectric 5119 is formed on substrate 521, covering the HV transistor 501 and the first trench isolation 511 and filling the first recess 5113. In some embodiments, the interlayer dielectric 5119 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the interlayer dielectric 5119 may include the same material as the first trench isolation 511. The interlayer dielectric 5119 can be deposited using one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Furthermore, after forming the interlayer dielectric 5119, as... Figure 5F As shown, wet / dry etching can be applied to the interlayer dielectric 5119 to form a contact hole 526 extending through the interlayer dielectric 5119 in the z-direction, thereby exposing the second doped region 505 and the first gate electrode 509. Then, the contact hole 526 is filled with electrode material to form a... Figure 4C The first electrode 425 and the second electrode 427 are in the middle.

[0072] Figures 6A-6F This illustration shows some aspects of forming a semiconductor device 600 (corresponding to...) Figure 4D The manufacturing process of semiconductor device 420 in the middle. Figure 8 Examples of semiconductor devices (corresponding to) are shown in accordance with some aspects of this disclosure. Figure 4D The flowchart illustrates method 800 using semiconductor device 420. It should be understood that the operations shown in method 800 are not exhaustive, and any other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figures 6A-6F and Figure 8 The different execution sequences shown will affect Figures 6A-6F and Figure 8 Describe them together.

[0073] refer to Figure 8 Method 800 begins with operation 802, in which a sacrificial first trench isolation is formed in the substrate, and a second trench isolation is formed in the substrate surrounding a portion of the substrate. For example, as... Figure 6A As shown, on substrate 621 (corresponding to Figure 4DA sacrificial first trench isolation 6111 is formed in substrate 621. In some embodiments, the sacrificial first trench isolation 6111 and the second trench isolation 631 may be STI and formed in substrate 621, for example, using wet / dry etching and thin film deposition of silicon oxide. The top surfaces of the sacrificial first trench isolation 6111 and the second trench isolation 631 may be planarized, for example, using chemical mechanical polishing (CMP). In some embodiments, the sacrificial first trench isolation 6111 may divide substrate 621 into multiple regions, in which multiple transistors may be formed respectively. A second trench isolation 631 surrounding a portion 633 of the substrate is formed in substrate 621. The portion 633 of the substrate is defined by the second trench isolation 631 and may be the active region of a 3D transistor, as will be discussed later.

[0074] In some embodiments, forming a sacrificial first trench isolation (e.g., 6111) in a substrate (e.g., 621) includes etching the substrate to form a first trench recess (not shown). Next, a first oxide layer (not shown) is formed covering the substrate and located within the first trench recess. Then, the first oxide layer covering the substrate is removed, leaving the first oxide layer in the first trench recess to form the sacrificial first trench isolation. In some embodiments, forming a second trench isolation (e.g., 631) in a substrate surrounding a protrusion (e.g., a portion of the substrate) includes etching the substrate to form a second trench recess (not shown) surrounding the protrusion. Next, a second oxide layer is formed covering the protrusion and located within the second trench recess. Then, the second oxide layer covering the protrusion is removed, leaving the second oxide layer in the second trench recess to form the second trench isolation.

[0075] In one implementation, such as Figure 6G As shown, the second trench is isolated (e.g., Figure 6G Etching is performed on 631) to form a second recess in the second trench isolation (e.g., Figure 6G 636) includes etching a second trench isolation to expose the substrate (e.g., Figure 6G The top surface of (621) in the middle. The second recess (e.g., Figure 6G 636) is at least partially surrounded by a second trench (e.g., 631), such as Figure 6G As shown. Subsequently, source electrodes can be formed on both sides of portion 433 of the substrate (e.g., corresponding to...). Figure 4E of Figure 6H The source (4461) and drain (e.g., corresponding to the source ... in the middle. Figure 4E of Figure 6H The drain in the middle is 4462). Then a 3D semiconductor body is formed (i.e., corresponding to...). Figure 4E of Figure 6H3D semiconductor body 446). It should be noted that the gate structure (e.g., Figure 6G and Figure 6H 435 and 635 in the text can be formed before or after the formation of the second depression.

[0076] In another implementation, such as Figure 6I and Figure 6J As shown, the second trench is etched for isolation (e.g., corresponding to...). Figure 4E of Figure 6J 431) to form a second recess in the second trench isolation (e.g., Figure 6J 6313) includes the sacrificial second trench isolation (e.g., Figure 6I The 6311 in the middle is etched back to expose the 3D semiconductor host (i.e., Figure 6J The sidewalls of the 3D semiconductor body 446 in the middle, thereby forming a thinned second trench isolation (e.g., Figure 6J (431 in the text). In some implementations, the second trench is sacrificed for isolation (e.g., Figure 6I 6313) from the portion of the substrate (e.g., Figure 6I The same height as 633) is etched back to the portion 433 below the substrate height, such as Figure 6J The second trench isolation 431 is shown in the diagram. It should be noted that the gate structure (e.g., Figure 6I and Figure 6J 435 and 635 in the text can be formed before or after the formation of the second depression.

[0077] As mentioned above, in order to form an FLD region under trench isolation, a mask layer with a hole pattern should be provided to form the FLD region. However, due to the critical size (CD) of the hole pattern forming the mask layer (e.g., the minimum diameter of the hole is about 0.36 μm), the width of the FLD region cannot be less than 0.4 μm. Therefore, the process for manufacturing trench isolation and FLD regions in this disclosure provides a solution to this challenge.

[0078] Method 800 proceeds to operation 804, such as... Figure 8 As shown, in this operation, the first sacrificial trench isolation is etched back to form a first recess and a first trench isolation, and the second trench isolation is also etched back to form a second recess in the second trench isolation. For example, as Figure 6B As shown, photolithography and wet / dry etching are used to isolate the sacrificial first trench (i.e., as...). Figure 6A The first recess 6113 is formed on the first trench isolation 611 by etching back the 6111 (in the middle) to form a first recess 6113 and a first trench isolation 611. In some embodiments, the first trench isolation 611 is as follows:Figure 4D The thinned trench isolation 411 is shown. In the same etch process, the second trench isolation 631 is etched back to form a second recess 636 (although the second recess 636 is not shown in cross-section in FIG. 6B, it can be shown as the second recess 436 in FIG. 4B). In some embodiments, the depth of the first recess 6113 is the same or similar to the depth of the second recess 636 because they are formed in the same etch process. Figure 6B Figure 4E In some embodiments, the depth of the first recess 6113 is the same or similar to the depth of the second recess 636 because they are formed in the same etch process.

[0079] Next, the method 800 proceeds to operation 806, in which a mask layer with an aperture is formed over the first recess and the first trench isolation, as shown in FIG. 6C. Figure 8 Figure 6C In some embodiments, the mask layer 6115 includes a photoresist layer. The mask layer 6115 with the aperture 6117 is configured for ion implantation of the FLD region (i.e., the first doped region 613) under the first trench isolation 611 as discussed above. Also, because the thickness of the first trench isolation 611 is reduced, the thickness of the mask layer 6115 and the size of the aperture 6117 are also reduced. With the reduced aperture size, the thinned mask layer, and the thinned trench isolation, not only does the ion implantation to form the FLD region allow for lower power, but also the width of the FLD region is reduced to a limit that is not achievable with existing photolithography technology.

[0080] Next, the method 800 proceeds to operation 808, in which a first doped region is formed under the first trench isolation by ion implantation, as shown in FIG. 6D. Figure 8 Figure 6C In some embodiments, the mask layer 6115 can be stripped after the ion implantation. The first doped region 613 can be doped with any appropriate p-type dopant (e.g., B or Ga). The power of the ion implantation can be, for example, 150 to 270 keV. In some embodiments, the mask layer 6115 can be stripped after the ion implantation.

[0081] Next, the method 800 proceeds to operation 810, in which two second doped regions are formed in the substrate, as shown in FIG. 6E. Figure 8 Figure 6D ​​​​As shown, two second doped regions 605 are formed in substrate 621 using any suitable doping technique (e.g., ion implantation). The second doped regions 605 can be doped with any suitable n-type dopant (e.g., P or Ar). In some embodiments, the two second doped regions 605 are formed in a third doped region 604 in substrate 621. The third doped region 604 can be formed in substrate 621 using any suitable doping technique (e.g., ion implantation). The third doped region 604 can be doped with any suitable p-type dopant (e.g., B or Ga).

[0082] Next, method 800 proceeds to operation 812, as follows: Figure 8 As shown, in this operation, a first gate structure is formed on the substrate and between two second doped regions, and a second gate structure is formed on a portion of the substrate. For example, as... Figure 6D As shown, a first gate structure 608 is formed on the third doped region 604 of the substrate 621 and between the two second doped regions 605. The first gate structure 608 includes a first gate dielectric 607 formed on the third doped region 604 of the substrate 621 and a first gate electrode 609 formed on the first gate dielectric 607. An HV transistor 601 (corresponding to...) is then formed. Figure 4D (HV transistor 401 in the example). In some embodiments, the formation of the first gate structure can be interchanged with the formation of two second doped regions. In other words, a first gate structure 608 is formed on a substrate 621, and then two second doped regions 605 are formed on both sides of the first gate structure 608. In some embodiments, the second doped regions 605 are n-wells of the HV transistor 601, and the third doped region 604 is a p-well of the HV transistor 601. After this process, the lateral (e.g., y-direction) distance between the nearest (i.e., shortest distance) second doped region 605 and the first doped region 613 can be equal to or greater than 0.6 μm, or even greater than 0.7 μm. The increased distance between the nearest second doped region 605 and the first doped region 613 can significantly improve the breakdown voltage of the HV transistor 601. During the same deposition process, a second gate structure 635 is formed on a portion 633 of the substrate. The second gate structure 635 includes a second gate dielectric 637 formed on a portion 633 of the substrate and a second gate electrode 639 formed on the second gate dielectric 637. In some embodiments, the formation of the second gate dielectric 637 on the portion 633 of the substrate and the formation of the first gate dielectric 607 on the third doped region 604 of the substrate 621 are performed in the same deposition process. In some embodiments, the formation of the second gate electrode 639 on the second gate dielectric 637 and the formation of the first gate electrode 609 on the first gate dielectric 607 are performed in the same deposition process. A 3D transistor 630 (corresponding to...) is then formed. Figure 4D(3D transistor 430 in the middle). Specifically, it can be used Figures 4E-4G The detailed formation of the 3D transistor 630 is described. This is achieved by forming a transistor with a source (i.e., Figure 4E The source (4461) and drain (i.e., Figure 4E The 3D semiconductor body (i.e., the drain 4462) and the active region (i.e., the active region 4463) formed between the source and drain. Figure 4E The 3D semiconductor body 446 is used to form the 3D transistor 630. The 3D semiconductor body (i.e., Figure 4E The 3D semiconductor body 446 is formed on the second trench isolation 631 extending in the z-direction (corresponding to Figure 4E The second groove isolation 431) in the second recess 636 (such as Figure 6B In other words, at least a portion of the 3D semiconductor body (i.e., such as...) Figure 4E The bottom portion of the 3D semiconductor body 446 is surrounded by a second trench isolation 631. The 3D transistor 630 also includes a gate structure 635 that contacts a portion 633 of the substrate. The portion 633 of the substrate (corresponding to...) Figure 4E and Figure 4G The portion 433 of the substrate in the x direction is the source (i.e., Figure 4E The source (4461) and drain (i.e., Figure 4E The drain (4462) is surrounded by a second trench isolation (631) in the y direction. The 3D semiconductor body (i.e., Figure 4E The 3D semiconductor body 446 extends at least partially above the top surface of the substrate 621, thereby exposing not only the 3D semiconductor body (i.e., Figure 4E The top surface of the 3D semiconductor body 446 is exposed, as are the two side surfaces of the 3D semiconductor body. It should be noted that, although as in Figure 6D The 3D transistor 630 is shown in the zy plane and is arranged side by side with the HV transistor 601 and the first trench isolation 611, but it is not necessary to arrange the 3D transistor 630 in this manner. For example, the 3D transistor 630 may be rotated 90 degrees or be in other orientations, or the 3D transistor 630 may be arranged at the far end of the substrate 621 or even on another substrate (not shown) in the same wafer (not shown).

[0083] Next, method 800 proceeds to operation 814, as follows: Figure 8 As shown, in this operation, an HV transistor, a first trench isolation layer, and a 3D transistor are formed on a substrate, and the interlayer dielectric of the first recess is filled. For example, as... Figure 6EAs shown, an interlayer dielectric 6119 is formed over the substrate 621 covering the HV transistor 601, the first trench isolation 611, and the 3D transistor 630 and filling the first recess 6113. The interlayer dielectric 6119 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the interlayer dielectric 6119 can include the same material as the first trench isolation 611. The interlayer dielectric 6119 can be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Further, after forming the interlayer dielectric 6119, a wet / dry etch can be applied to the interlayer dielectric 6119 to form a contact hole 626 extending through the interlayer dielectric 6119 in the z-direction, thereby exposing the second doped region 605 and the first gate electrode 609. The contact hole 626 is then filled with an electrode material to form the first electrode 425 and the second electrode 427 in FIG. 4B, as described above. Figure 6F As shown, an interlayer dielectric 6119 is formed over the substrate 621 covering the HV transistor 601, the first trench isolation 611, and the 3D transistor 630 and filling the first recess 6113. The interlayer dielectric 6119 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the interlayer dielectric 6119 can include the same material as the first trench isolation 611. The interlayer dielectric 6119 can be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Further, after forming the interlayer dielectric 6119, a wet / dry etch can be applied to the interlayer dielectric 6119 to form a contact hole 626 extending through the interlayer dielectric 6119 in the z-direction, thereby exposing the second doped region 605 and the first gate electrode 609. The contact hole 626 is then filled with an electrode material to form the first electrode 425 and the second electrode 427 in FIG. 4B, as described above. Figure 4D As shown, an interlayer dielectric 6119 is formed over the substrate 621 covering the HV transistor 601, the first trench isolation 611, and the 3D transistor 630 and filling the first recess 6113. The interlayer dielectric 6119 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the interlayer dielectric 6119 can include the same material as the first trench isolation 611. The interlayer dielectric 6119 can be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Further, after forming the interlayer dielectric 6119, a wet / dry etch can be applied to the interlayer dielectric 6119 to form a contact hole 626 extending through the interlayer dielectric 6119 in the z-direction, thereby exposing the second doped region 605 and the first gate electrode 609. The contact hole 626 is then filled with an electrode material to form the first electrode 425 and the second electrode 427 in FIG. 4B, as described above.

[0084] According to one aspect of the disclosure, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion-implanted region, and a distance between the first doped region and the second doped region is equal to or greater than 0.6 pm.

[0085] In some embodiments, the second doped region is a drain region or a source region of a transistor.

[0086] In some embodiments, a top surface of the first trench isolation is lower than a top surface of the substrate.

[0087] In some embodiments, a width of the first doped region is equal to or less than 0.2 pm.

[0088] In some embodiments, the first gate structure includes a first gate dielectric and a first gate electrode formed on the first gate dielectric.

[0089] In some embodiments, the first gate electrode includes polysilicon.

[0090] In some embodiments, the first doped region and the second doped region have different doping types.

[0091] In some embodiments, the first doped region is doped with a p-type dopant. The second doped region is doped with an n-type dopant.

[0092] In some embodiments, the semiconductor device further includes a second trench isolation in the substrate and surrounding a portion of the substrate, a three-dimensional (3D) semiconductor body partially formed in the second trench isolation, and a second gate structure in contact with a plurality of faces of the 3D semiconductor body. The second gate structure includes a second gate dielectric and a second gate electrode formed on the second gate dielectric.

[0093] According to another aspect, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. The peripheral circuit includes a first circuit. The first circuit includes a semiconductor device. The semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed under the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implantation region, and a distance between the first doped region and the second doped region is equal to or greater than 0.6 pm.

[0094] In some embodiments, the first circuit is capable of withstanding a voltage in a range of 5V to 30V.

[0095] In some embodiments, the array of memory cells includes an array of 3D NAND memory strings.

[0096] In some embodiments, the peripheral circuit further includes a second circuit, the second circuit including a 3D transistor.

[0097] In some embodiments, the second circuit is capable of withstanding a voltage in a range of 0.9V to 2V.

[0098] According to yet another aspect, a method for forming a semiconductor device includes forming a sacrificial first trench isolation in a substrate, etching back the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, where the first recess is formed on the first trench isolation, forming a mask layer having an aperture over the first recess and the first trench isolation, ion implanting through the aperture to form a first doped region under the first trench isolation, and forming a second doped region in the substrate.

[0099] In some embodiments, the method further includes forming a first gate structure on the substrate and adjacent to the second doped region.

[0100] In some embodiments, a first portion of the mask layer is formed in the first recess, and a second portion of the mask layer is formed on the substrate.

[0101] In some embodiments, the first portion of the mask layer in the first recess is thinner than the second portion of the mask layer on the substrate.

[0102] In some embodiments, the method further includes forming an interlayer dielectric to fill the first recess.

[0103] In some embodiments, ion implantation via the hole to form the first doped region under the first trench isolation includes ion implanting a p-type dopant in the substrate.

[0104] In some embodiments, forming the sacrificial first trench isolation in the substrate includes: etching the substrate to form a first trench recess; forming an oxide layer covering the substrate and located in the first trench recess; and removing the oxide layer covering the substrate and leaving the oxide layer in the first trench recess to form the sacrificial first trench isolation.

[0105] In some embodiments, removing the oxide layer covering the substrate includes applying a chemical polishing process (CMP) to the oxide layer to remove the oxide layer covering the substrate.

[0106] According to yet another aspect, a method for forming a semiconductor device includes: forming a sacrificial first trench isolation in a substrate, and forming a second trench isolation surrounding a protrusion on the substrate; etching the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, and etching the second trench isolation to form a second recess in the second trench isolation; forming a mask layer having a hole over the first recess and the first trench isolation; ion implantation via the hole to form a first doped region under the first trench isolation; forming a second doped region in the substrate; and forming a first gate structure on the substrate and adjacent to the second doped region and a second gate structure on the protrusion on the substrate.

[0107] In some embodiments, the protrusion on the substrate is a portion of the substrate.

[0108] In some embodiments, forming the sacrificial first trench isolation in the substrate includes: etching the substrate to form a first trench recess; forming a first oxide layer covering the substrate and located in the first trench recess; and removing the first oxide layer covering the substrate and leaving the first oxide layer in the first trench recess to form the sacrificial first trench isolation.

[0109] In some embodiments, forming the second trench isolation surrounding the protrusion on the substrate includes: etching the substrate to form a second trench recess surrounding the protrusion; forming a second oxide layer covering the protrusion and located in the second trench recess; and removing the second oxide layer covering the protrusion and leaving the second oxide layer in the second trench recess to form the second trench isolation.

[0110] In some embodiments, removing the second oxide layer covering the protrusion includes applying a chemical polishing process (CMP) to the second oxide layer to remove the oxide layer covering the substrate.

[0111] In some embodiments, etching the second trench isolation to form the second recess in the second trench isolation includes etching the second trench isolation to expose the substrate. The second recess is at least partially surrounded by the second trench isolation.

[0112] In some embodiments, etching the second trench isolation to form the second recess in the second trench isolation includes etching back the second trench isolation to form a thinned second trench isolation.

[0113] In some embodiments, the method further includes forming an interlayer dielectric to fill the first recess.

[0114] In some embodiments, the method further includes forming a third doped region in the substrate. The second doped region is formed in the third doped region.

[0115] In some embodiments, forming the first gate structure further includes forming a first gate dielectric on the substrate and forming a first gate electrode on the first gate dielectric. Also, forming the second gate structure further includes forming a second gate dielectric on the substrate and forming a second gate electrode on the second gate dielectric.

[0116] In some embodiments, the first recess and the second recess have the same depth.

[0117] The foregoing description of specific implementations and / or embodiments are presented for the purpose of clarity and description. Such approaches were developed and tested for the applications described. However, such implementations and / or embodiments can be readily modified and / or combined for use with a variety of applications. Thus, the foregoing description of specific implementations and / or embodiments should not be construed as limiting, but simply as descriptive. Modifications and / or combinations can readily occur to those skilled in the art, and such modifications and / or combinations are properly within the scope of the disclosure.

[0118] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: a substrate; a first trench isolation in the substrate; a first doped region formed under the first trench isolation; a second doped region formed in the substrate; and a first gate structure formed adjacent to the second doped region, wherein the first doped region is an ion implant region, and a distance between adjacent ones of the first doped regions and respective adjacent second doped regions is equal to or greater than 0.6 pm. the second doped region is a drain region or a source region of a transistor.

2. The semiconductor device of claim 1, wherein, a top surface of the first trench isolation is lower than a top surface of the substrate.

3. The semiconductor device according to claim 1 or 2, wherein a width of the first doped region is equal to or less than 0.2 pm.

4. The semiconductor device according to claim 1 or 2, wherein the first gate structure includes a first gate dielectric and a first gate electrode formed on the first gate dielectric.

5. The semiconductor device according to claim 1 or 2, wherein the first gate electrode includes polysilicon.

6. The semiconductor device of claim 5, wherein, the first doped region and the second doped region have different doping types.

7. The semiconductor device according to claim 1 or 2, wherein the first doped region is doped with p-type dopants, wherein the second doped region is doped with n-type dopants.

8. The semiconductor device of claim 7, wherein, 9. The semiconductor device of claim 1 or 2, further comprising: a second trench isolation in the substrate and surrounding a portion of the substrate; a three-dimensional (3D) semiconductor body formed partially in the second trench isolation; and a second gate structure in contact with multiple faces of the 3D semiconductor body, wherein the second gate structure includes a second gate dielectric and a second gate electrode formed on the second gate dielectric.

10. A memory device comprising: an array of memory cells; and a peripheral circuit coupled to the array of memory cells, the peripheral circuit comprising: a first circuit, the first circuit comprising: a semiconductor device, the semiconductor device comprising: a substrate; a first trench isolation in the substrate; a first doped region formed under the first trench isolation; a second doped region formed in the substrate; and a first gate structure formed adjacent to the second doped region, wherein the first doped region is an ion implant region, and a distance between adjacent ones of the first doped regions and respective adjacent second doped regions is equal to or greater than 0.6 pm. the first circuit is capable of withstanding voltages in a range of 5V to 30V. the array of memory cells comprises an array of 3D NAND memory strings.

11. The memory device of claim 10, wherein, the peripheral circuit further comprises a second circuit, the second circuit comprising 3D transistors.

12. The memory device of claim 10 or 11, wherein, the second circuit is capable of withstanding voltages in a range of 0.9V to 2V.

13. The memory device of claim 10 or 11, wherein, 15. A method for forming a semiconductor device, comprising:

14. The memory device of claim 13, wherein, forming a sacrificial first trench isolation in a substrate; etching back the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, wherein the first recess is formed on the first trench isolation; forming a mask layer having apertures over the first recess and the first trench isolation; performing ion implantation through the apertures to form a first doped region under the first trench isolation; and forming a second doped region in the substrate, ​ ​ wherein a distance between adjacent ones of the first doped regions and respective adjacent ones of the second doped regions is equal to or greater than 0.6 pm.

16. The method of claim 15, further comprising: forming a first gate structure on the substrate and adjacent to the second doped regions.

17. The method of claim 15 or 16, wherein, a first portion of the mask layer is formed in the first recess, and a second portion of the mask layer is formed on the substrate.

18. The method of claim 17, wherein, the first portion of the mask layer in the first recess is thinner than the second portion of the mask layer on the substrate.

19. The method of claim 15 or 16, further comprising: forming an interlayer dielectric to fill the first recess.

20. The method of claim 15 or 16, wherein, implanting ions to form the first doped regions under the first trench isolation via the holes comprises implanting p-type dopants in the substrate.

21. The method of claim 15 or 16, wherein, forming the sacrificial first trench isolation in the substrate comprises: etching the substrate to form a first trench recess; forming an oxide layer covering the substrate and located in the first trench recess; and removing the oxide layer covering the substrate and leaving the oxide layer in the first trench recess to form the sacrificial first trench isolation.

22. The method of claim 21, wherein, removing the oxide layer covering the substrate comprises: applying a chemical polishing process (CMP) to the oxide layer to remove the oxide layer covering the substrate.

23. A method for forming a semiconductor device, comprising: forming a sacrificial first trench isolation in a substrate, and forming a second trench isolation surrounding a protrusion on the substrate; etching the sacrificial first trench isolation to form a first recess and a first trench isolation in the substrate, and etching the second trench isolation to form a second recess in the second trench isolation; forming a mask layer having holes over the first recess and the first trench isolation; implanting ions to form first doped regions under the first trench isolation via the holes; forming second doped regions in the substrate; and forming a first gate structure on the substrate and adjacent to the second doped regions and forming a second gate structure over the protrusion on the substrate, wherein a distance between adjacent ones of the first doped regions and respective adjacent ones of the second doped regions is equal to or greater than 0.6 pm.

24. The method of claim 23, wherein, the protrusion on the substrate is a portion of the substrate.

25. The method of claim 23 or 24, wherein, forming the sacrificial first trench isolation in the substrate comprises: etching the substrate to form a first trench recess; forming a first oxide layer covering the substrate and located in the first trench recess; and removing the first oxide layer covering the substrate and leaving the first oxide layer in the first trench recess to form the sacrificial first trench isolation.

26. The method of claim 23 or 24, wherein, forming the second trench isolation surrounding the protrusion on the substrate comprises: etching the substrate to form a second trench recess surrounding the protrusion; forming a second oxide layer covering the protrusion and located in the second trench recess; and removing the second oxide layer covering the protrusion and leaving the second oxide layer in the second trench recess to form the second trench isolation. removing a second oxide layer covering the protruding portions and leaving a second oxide layer in the second trench recess to form the second trench isolation.

27. The method of claim 26, wherein, removing a second oxide layer covering the protruding portions includes: applying a chemical polishing process (CMP) to the second oxide layer to remove the oxide layer covering the substrate.

28. The method of claim 23 or 24, wherein, etching the second trench isolation to form the second recess in the second trench isolation includes: etching the second trench isolation to expose the substrate, wherein the second recess is at least partially surrounded by the second trench isolation.

29. The method of claim 23 or 24, wherein, etching the second trench isolation to form the second recess in the second trench isolation includes: etching back the second trench isolation to form a thinned second trench isolation.

30. The method of claim 23 or 24, further comprising: forming an interlayer dielectric to fill the first recess.

31. The method of claim 23 or 24, further comprising: forming a third doped region in the substrate, wherein the second doped region is formed in the third doped region.

32. The method of claim 23 or 24, wherein forming the first gate structure further comprises: forming a first gate dielectric on the substrate and a first gate electrode on the first gate dielectric, and wherein forming the second gate structure further comprises: forming a second gate dielectric on the substrate and a second gate electrode on the second gate dielectric.

33. The method of claim 23 or 24, wherein, the first recess and the second recess have the same depth.

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