LED precursor comprising strain-relaxed structure

Abstract

A Light Emitting Diode (LED) precursor and a method of forming the LED precursor are provided. The LED precursor includes a first semiconductor layer and a monolithic LED structure provided on a growth surface of the first semiconductor layer. The first semiconductor layer includes a Group III-nitride. The first semiconductor layer includes a mesa structure extending from a major surface of the first semiconductor layer to define the growth surface, the growth surface including a bulk semiconductor surface and a mesa surface. The first semiconductor layer includes a first semiconductor sublayer and a strain-relaxed sublayer, the first semiconductor sublayer including a Group III-nitride having a first in-plane lattice constant. The strain-relaxed sublayer includes a Group III-nitride provided across the first semiconductor sublayer, wherein the strain-relaxed sublayer provides the mesa surface of the mesa structure such that the mesa surface has a second in-plane lattice constant, the second in-plane lattice constant being greater than the first in-plane lattice constant. The monolithic LED structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, wherein the monolithic LED structure includes a plurality of Group III-nitride layers. The monolithic LED structure has a first monolithic LED structure portion provided on the mesa surface, and a second monolithic LED structure portion surrounding the first monolithic LED structure portion and having a sidewall surface that is tilted with respect to the mesa surface.

Description

Technical Field

[0001] This disclosure relates to group III-nitride semiconductors. More specifically, this disclosure relates to light-emitting diodes (LEDs) that include group III-nitride semiconductors. Background Technology

[0002] Micro LED arrays are typically defined as LED arrays with a size of 100 × 100 μm² or smaller. They are self-emissive micro-displays / projectors suitable for a variety of devices, such as smartwatches, head-up displays, head-up displays, camcorders, viewfinders, multi-point excitation sources, and micro-projectors.

[0003] In many applications, there is a demand for a miniature display / projector capable of outputting light within a specific wavelength range. For example, in many color displays, it is common to provide each pixel with the ability to output a combination of red, green, and blue light.

[0004] One known form of micro-LED array comprises multiple LEDs formed of group III-nitrides. Group III-nitride LEDs are inorganic semiconductor LEDs containing GaN and its alloys with InN and AlN in the active light-emitting regions. Group III-nitride LEDs can be driven at significantly higher current densities and emit higher light power densities than conventional large-area LEDs, such as organic light-emitting diodes (OLEDs) where the light-emitting layer is an organic compound. Therefore, higher brightness (luminance) is defined as the amount of light emitted per unit area of ​​the light source in a given direction, making micro-LEDs suitable for applications that require or benefit from high brightness. For example, applications benefiting from high brightness may include displays in high-brightness environments or include projectors. Furthermore, group III-nitride micro-LEDs have relatively high luminous efficacy, expressed in lumens per watt (lm / W), compared to other conventional large-area LEDs. The relatively high luminous efficacy of group III-nitride micro-LED arrays reduces power consumption compared to other light sources and makes micro-LEDs particularly suitable for portable devices.

[0005] One method for forming micro-LEDs, particularly micro-LED arrays, from group III nitrides is selective area growth (SAG), as described, for example, in US-B-7,087,932. In SAG, a mask is patterned on a buffer layer. The material in the mask is such that, under the growth conditions, no additional material grows directly on the mask, but only within apertures that expose portions of the underlying buffer layer surface. Another notable feature of group III nitride selective area growth along the

[0001] direction is that, depending on growth parameters such as growth temperature, pressure, and V / III ratio, the perimeter of the growth portion of the c-plane semiconductor defined by the opening region of the patterned mask acquires a facet inclined relative to the (0001) plane (also called the c-plane). The inclined facets are typically oriented along the {110 1} or {110 2} plane of the wurtzite crystal and exhibit a reduced polarization field compared to the c-plane surface (semi-polar surface).

[0006] A known type of group III nitride LED utilizes an In-Ga-N alloy system to define multiple quantum wells in the active region of the LED. Typically, GaN and In are provided. x Ga 1-x Alternating layers of N are used to define the quantum well. For blue LEDs, the mole fraction of indium, X, is typically <0.2. Increasing In... x Ga 1-x The amount of indium doped in the N-layer increases the depth of the potential well, thereby increasing the wavelength of the light emitted by the LED.

[0007] However, it is well known that increasing the indium molar fraction X to above 0.2 to provide native green and red LEDs significantly reduces LED efficiency. One of the fundamental problems is that indium doping efficiency is low if indium is deposited on relaxed or compressively strained GaN. High In fraction layers typically require low growth temperatures and are prone to phase separation, which adversely affects IQE (e.g., JOURNAL OF APPLIED PHYSICS 123, 160901 (2018)).

[0008] "InGaN lattice constant engineering via growth on (In,Ga)N / GaN nanostripe arrays," Keller S. et al., Semicond. Sci. Technol., vol. 30, (2015), discloses the growth of planar (In,Ga)N layers on nanostripe arrays composed of InGaN / GaN multiple quantum wells. The nanostripe arrays exhibit elastic relaxation perpendicular to the stripe direction after patterning, leading to a lattice constant on (In,Ga)N / GaN nanostripe arrays. ┴The lattice constant is greater than that of the GaN substrate.

[0009] US-B-8,492,244 discloses a method for forming islands of strain-relaxed material layers on an intermediate substrate, relaxing the strained material islands at least partially by a first heat treatment, and transferring the strained material islands to a target substrate.

[0010] One object of the present invention is to provide an improved method for forming an LED precursor, and an improved LED precursor that solves at least one problem associated with prior art methods and arrays, or at least provides a commercially useful alternative thereto. Summary of the Invention

[0011] The inventors have recognized that the SAG method is highly dependent on the geometry of the layer / device to be manufactured. Therefore, performing the same SAG manufacturing process on substrates with different mask geometries can lead to undesirable local variations in doping distribution and layer composition due to localized variations in aperture size. Furthermore, the doping distribution and layer composition may also vary on different substrates due to different layouts. That is, the doping distribution / alloy composition of each layer of an LED device formed by SAG may depend on the geometry of the device. Therefore, even minor variations in the geometry of the device or array of devices may require recalibrating the SAG process for each layer of the device.

[0012] Furthermore, the inventors have realized that during the SAG process, material from the mask layer can be incorporated into the deposited structure. For example, elements within the mask layer may diffuse into the material grown by SAG during manufacturing, resulting in undesirable doping of the grown LED structure. In particular, a mask layer comprising Si or O (e.g., SiNx, SiO2) can provide a source of Si or O dopant for group III-nitride layers grown via SAG.

[0013] According to a first aspect of the present invention, a method for forming a light-emitting diode (LED) precursor is provided. The method includes:

[0014] (a) Forming a first semiconductor layer on a substrate, wherein forming the first semiconductor layer includes:

[0015] A first semiconductor sublayer comprising a group III-nitride having a first in-plane lattice constant is formed on the surface of the substrate; and

[0016] A strain sublayer is formed on the side of the first semiconductor sublayer opposite to the substrate, comprising a group III-nitride on the first semiconductor sublayer, wherein the strain sublayer at the interface between the strain sublayer and the first semiconductor sublayer is under compressive strain, such that at the interface...

[0017] The in-plane lattice constant of the strainor layer is the first in-plane lattice constant;

[0018] (b) Selectively removing a portion of the first semiconductor layer to expose the surface of the host semiconductor layer of the first semiconductor layer such that the first semiconductor layer defines a mesa structure extending from the surface of the host semiconductor layer;

[0019] (c) The strain sublayer is heated to a strain relaxation temperature, wherein the strain sublayer is relaxed by plastic deformation to form a strain relaxation sublayer, wherein the mesa structure has a mesa surface formed by a portion of the strain relaxation sublayer, and the mesa surface has a second in-plane lattice constant that is greater than the first in-plane lattice constant.

[0020] (d) A monolithic LED structure is formed on the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the main semiconductor surface, the monolithic LED structure comprising a plurality of group III-nitride layers, the monolithic LED structure having:

[0021] The first monolithic LED structure portion is provided above the surface of the platform; and

[0022] The second monolithic LED structure portion surrounds the first monolithic LED structure portion and has a sidewall surface that is inclined relative to the table surface.

[0023] In the SAG method, a monolithic LED structure can be grown on the exposed portion of the buffer layer. The monolithic LED structure is not grown on the portion of the buffer layer covered by the mask layer. In the first aspect of the method, the monolithic LED structure is overgrown on the growth surface of the first semiconductor layer without a mask layer. Therefore, the method for manufacturing the monolithic LED structure is a maskless overgrowing method.

[0024] The method of the first aspect allows for the formation of a monolithic LED structure on a growth surface in the absence of a mask layer. Therefore, the method of the first aspect reduces or eliminates problems associated with material recycling and mask layer contamination.

[0025] The mesa structure, forming part of the growth surface, helps define the geometry of the monolithic LED structure. Therefore, unlike known SAG methods, no mask layer is needed to define the apertures for the selective growth of the monolithic LED structure. Instead, the monolithic LED structure is grown above the growth surface to cover the mesa structure. By covering the mesa structure, the resulting monolithic LED structure has a first portion and a second portion, the first portion being substantially flat and covering the mesa surface, and the second portion surrounding the mesa surface and having sloping sidewalls similar to those of monolithic LED structures grown using SAG methods known in the art.

[0026] Importantly, the mesa surface is formed from a portion of the strain-relaxed surface of the strain-relaxed sublayer. By incorporating the strain-relaxed sublayer into the first semiconductor layer, the mesa surface can be configured for the growth of a monolithic LED structure with a higher In content active layer. That is, the in-plane lattice constant of the mesa surface can be provided to reduce the lattice mismatch between the mesa surface and the monolithic LED structure.

[0027] Furthermore, the method of the first aspect involves forming multiple layers of the monolithic LED structure on the growth surface, including the mesa surface and the host semiconductor surface. The multiple layers of the monolithic LED structure can be formed using a manufacturing process similar to SAG. However, in the method of the first aspect, the multiple layers of the monolithic LED structure are formed across the entire growth surface (i.e., there is no mask layer). Therefore, the formation of the multiple layers of the monolithic LED structure is less sensitive to changes in the geometry of the LED precursor to be formed. Thus, the method of forming the LED precursor can reduce or eliminate the calibration process that may need to be performed each time the geometry of the device is changed in order to form the multiple layers of the monolithic LED precursor.

[0028] It should be understood that the method of the first aspect yields a monolithic LED structure having a substantially flat upper surface surrounded by inclined sidewalls. Therefore, the monolithic LED structure can have a substantially trapezoidal cross-section. Such a trapezoidal cross-section can have increased light extraction efficiency because the inclined sidewalls of the trapezoidal cross-section can direct a larger proportion of light to the light-emitting surface of the LED precursor.

[0029] Furthermore, the method of the first aspect involves the formation of multiple layers of the monolithic LED structure across the mesa surface and the surface of the host semiconductor layer. The multiple layers of the monolithic LED structure can be formed using a manufacturing process similar to SAG. However, in the method of the first aspect, the multiple layers of the monolithic LED structure are formed across the entire growth surface (i.e., there is no mask layer). Therefore, the formation of the multiple layers of the monolithic LED structure is less sensitive to changes in the geometry of the LED precursor to be formed. Thus, the method of forming the LED precursor can reduce or eliminate the calibration process that may need to be performed each time the geometry of the device is changed in order to form the multiple layers of the monolithic LED precursor.

[0030] Specifically, in the method of the first aspect, the geometry of the LED precursor may be influenced by the geometry of the formed mesa structure. For example, when forming an LED precursor with a trapezoidal cross-section, the height and surface area of ​​the mesa structure can be varied to control the required height and surface area of ​​the formed LED precursor. Therefore, the aspect ratio of the formed LED precursor can be adjusted using the selective removal step. Subsequent steps where the monolithic LED structure is deposited on the mesa structure can remain constant, independent of the LED precursor's aspect ratio. Conversely, in the SAG process, a change in the aspect ratio of the trapezoidal cross-section of the LED structure may require recalibrating one or more of the deposition steps.

[0031] Regarding the term "precursor" in LED precursor, it should be noted that the described LED precursor does not necessarily include electrical contacts for the LED to allow light emission, nor does it necessarily include associated circuitry. Of course, the method of forming the LED precursor of the first aspect does not preclude the addition of additional electrical contacts and associated circuitry. Thus, the term precursor as used in this disclosure is intended to include the final product (i.e., LED, LED array, etc.).

[0032] In some embodiments, the step of selectively removing a portion of the first semiconductor layer includes removing a portion of the strainor layer through the entire thickness of the strainor layer and removing a corresponding portion of the first semiconductor sublayer, such that the surface of the host semiconductor layer is formed in the first semiconductor sublayer. In some embodiments, the step of selectively removing a portion of the first semiconductor layer includes removing a portion of the strainor layer partially through the thickness of the strainor layer (i.e., not removing a portion of the first semiconductor sublayer). Therefore, it should be understood that in some embodiments, the surface of the host semiconductor layer may be provided by the strainor layer, and in other embodiments by the first semiconductor sublayer.

[0033] The strain sublayer can be provided in various different forms to form the strain relaxation surface having a desired in-plane lattice constant. The strain sublayer can be configured to provide an interface between a first semiconductor sublayer having the first in-plane lattice constant and the monolithic LED structure (particularly the active region of the monolithic LED structure) having a higher in-plane lattice constant. In some embodiments, the strain sublayer includes In... X Ga 1-X N, where 0 < X ​​≤ 1. For example, in some embodiments, the first semiconductor sublayer comprises GaN having a first in-plane lattice constant, and the strain sublayer comprises In. X Ga 1-X N, wherein the increased In content of the strainor layer increases the in-plane lattice constant relative to the GaN layer.

[0034] In some embodiments, the strain sublayer is provided as a monolayer with a uniform composition (e.g., a single In). X Ga 1-X (N layers). That is to say, In X Ga 1-X The composition of the N sublayer is substantially the same throughout the entire sublayer.

[0035] In some embodiments, the strain layer comprises multiple layers, including a first strain layer comprising GaN and a strain layer comprising In. X Ga 1-X The second strain layers of N alternate, where 0 < X ​​≤ 1.

[0036] In some embodiments, the In content (X) of the strainor layer varies (e.g., increases or decreases) in the thickness direction. For example, in some embodiments, the In content (X) of the strainor layer varies in the thickness direction, decreasing in the thickness direction away from the first semiconductor sublayer. For example, in some embodiments, the strainor layer may be In... X Ga 1-X A monolayer of N, wherein the composition (i.e., In content X) is graded in the thickness direction. In some embodiments, the strain sublayer comprises multiple layers, alternating between a first strain layer and a second strain layer, each of the second strain layers having a different In content (i.e., decreasing in the thickness direction away from the first semiconductor sublayer). By providing the strain sublayer with a higher In content to the first semiconductor layer, the formation of mismatch dislocations during the formation of the strain relaxation sublayer can be promoted in regions away from the strain relaxation surface. That is, maximum lattice mismatch is provided away from the growth surface of the first semiconductor layer, thereby reducing the impact of lattice mismatch (dislocations) on the electrical properties of the LED precursor.

[0037] In some embodiments, the monolithic LED structure includes a second semiconductor layer provided above the mesa surface and the body semiconductor layer surface of the first semiconductor layer. In some embodiments, the monolithic LED structure includes an active layer comprising a plurality of group III nitride layers provided on the second semiconductor layer. In some embodiments, the monolithic LED structure includes a p-type semiconductor layer comprising group III nitrides formed on the active layer. Importantly, each of the layers in the monolithic LED structure can be formed as a substantially continuous layer above the growth surface of the first semiconductor layer.

[0038] In some embodiments, the second semiconductor layer comprises GaN. In some embodiments, the second semiconductor layer comprises In. Y Ga 1-Y N, where 0 < Y ≤ 1. For example, in some embodiments, the second semiconductor layer includes In. Y Ga 1-Y N, where 0 < Y ≤ 0.15. In some embodiments, the second semiconductor layer may include an n-type dopant (i.e., the second semiconductor layer may be n-type doped).

[0039] In some embodiments, the active layer can be configured to output light with a wavelength of at least 500 nm. That is, the LED precursor can be configured to generate visible light with a wavelength that is substantially green or red.

[0040] In some embodiments, the active layer includes at least one In Z Ga 1-Z The quantum well layer comprises N, where 0 < Z ≤ 0.5. The In content of the quantum well layer (Z), and / or the thickness of the at least one quantum well layer, can be configured to provide a desired wavelength of light output by the LED. In some embodiments, the active layer comprises a plurality of quantum well layers, each separated by a GaN layer. In particular, in some embodiments, the quantum well layer comprises In. Z Ga 1-Z N, where 0.2≤Z≤0.5.

[0041] In some embodiments, the quantum well layer may have a third in-plane lattice constant that is at least equal to the second in-plane lattice constant. Therefore, the strain-relaxed surface provides an intermediate surface on which the second semiconductor layer with reduced lattice mismatch and the active region may be formed.

[0042] In some embodiments, a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the body semiconductor surface, the barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface.

[0043] It should be understood that, unlike SAG technology, the monolithic LED structure is grown across the growth surface, including across the surface of the host semiconductor layer. To confine charge carriers within a portion of the monolithic LED structure defined by the mesa structure, a potential barrier is provided in the p-type layer of the monolithic LED structure. The p-type layer is provided between the first portion of the p-type semiconductor layer covering the mesa surface and the second portion of the p-type semiconductor layer covering the host semiconductor surface to restrict charge carriers flowing through the first portion of the p-type layer (i.e., confining charge carriers within the mesa structure).

[0044] In some embodiments, the step of forming the strain-relaxed sublayer includes a heat treatment step, wherein the strain-relaxed sublayer is heated (from room temperature) to a temperature of at least 800°C. By heating the strain-relaxed sublayer, dislocations can propagate through it because the strain-relaxed sublayer relaxes. This, in turn, reduces the strain in the strain-relaxed surface, thereby increasing the in-plane lattice constant of the strain-relaxed surface. Therefore, the heat treatment step can be used to control (increase) the lattice constant of the strain-relaxed surface.

[0045] According to a second aspect of this disclosure, a light-emitting diode (LED) precursor is provided. The LED precursor includes a first semiconductor layer and a monolithic LED structure. The first semiconductor layer includes a mesa structure extending from a main surface of the first semiconductor layer to define a growth surface, the growth surface including a host semiconductor surface and a mesa surface. The first semiconductor layer includes a first semiconductor sublayer and a strain relaxation sublayer. The first semiconductor sublayer includes a group III-nitride having a first in-plane lattice constant. The strain relaxation sublayer includes a group III-nitride provided across the first semiconductor sublayer, wherein the strain relaxation sublayer provides a mesa surface of the mesa structure, the mesa surface having a second in-plane lattice constant greater than the first in-plane lattice constant. The monolithic LED structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the host semiconductor surface. The monolithic LED structure includes a plurality of group III-nitride layers. The monolithic LED structure has a first monolithic LED structure portion and a second monolithic LED structure portion provided above the table surface, the second monolithic LED structure portion surrounding the first monolithic LED structure portion and having a sidewall surface inclined relative to the table surface.

[0046] The LED precursor according to the second aspect provides an LED precursor that can be formed by the method of the first aspect. Therefore, the LED precursor according to the second aspect can incorporate features corresponding to all the important features of the first aspect described above.

[0047] In some embodiments, the LED precursor includes a substrate on which the first semiconductor layer is provided. In some embodiments, the first semiconductor layer is not provided on the substrate. For example, the substrate can be removed from the first semiconductor layer to expose the surface of the first semiconductor layer on the side opposite to the monolithic LED structure.

[0048] According to a third aspect of this disclosure, a method for forming an LED array precursor is provided. The method includes:

[0049] (a) Forming a first semiconductor layer on a substrate, wherein forming the first semiconductor layer includes:

[0050] A first semiconductor sublayer comprising a group III-nitride having a first in-plane lattice constant is formed on the surface of the substrate; and

[0051] A strain sublayer comprising a group III-nitride is formed on the side of the first semiconductor sublayer opposite to the substrate, wherein the strain sublayer at the interface between the strain sublayer and the first semiconductor sublayer is under compressive strain such that the in-plane lattice constant of the strain sublayer at the interface is a first in-plane lattice constant; (b) a portion of the first semiconductor layer is selectively removed to expose the surface of the host semiconductor layer of the first semiconductor layer such that the first semiconductor layer defines a plurality of mesa structures, each mesa structure extending from the surface of the host semiconductor layer.

[0052] (c) The strain sublayer is heated to a strain relaxation temperature, wherein the strain sublayer is relaxed by plastic deformation to form a strain relaxation sublayer, wherein each mesa structure has a mesa surface formed by a portion of the strain relaxation sublayer, the mesa surface having a second in-plane lattice constant that is greater than the first in-plane lattice constant.

[0053] (d) A monolithic LED structure is formed on the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the main semiconductor surface, the monolithic LED structure comprising a plurality of group III-nitride layers, the monolithic LED structure having:

[0054] Multiple first monolithic LED structural portions, each first monolithic LED structural portion being provided above its respective mesa surface; and

[0055] Multiple second monolithic LED structural portions, each second monolithic LED structural portion surrounding the first monolithic LED structural portion and having sidewall surfaces inclined relative to their respective table surface.

[0056] The method according to the third aspect of this disclosure provides a method for forming a plurality of monolithic LED structures on a substrate, wherein each monolithic structure formed is similar to those monolithic structures formed by the method of the first aspect of this disclosure. Therefore, the method according to the third aspect may include all the important features of the first aspect as described above.

[0057] According to a fourth aspect of this disclosure, an LED array precursor is provided. The LED array precursor includes a first semiconductor layer and a monolithic LED array structure. The first semiconductor layer includes a plurality of mesa structures. Each mesa structure extends from a main surface of the first semiconductor layer to define a growth surface, the growth surface including a host semiconductor surface and a plurality of mesa surfaces. The first semiconductor layer includes a first semiconductor sublayer and a strain relaxation sublayer. The first semiconductor sublayer includes a group III-nitride having a first in-plane lattice constant. The strain relaxation sublayer includes a group III-nitride provided across the first semiconductor sublayer, wherein the strain relaxation sublayer provides a mesa surface for each mesa structure, the mesa surface having a second in-plane lattice constant greater than the first in-plane lattice constant. Each mesa structure has a mesa surface formed by a corresponding portion of the strain relaxation surface. The monolithic LED structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED structure covers each mesa surface and the host semiconductor surface. The monolithic LED structure includes a plurality of group III-nitride layers. The monolithic LED structure has multiple first monolithic LED structure portions and multiple second monolithic LED structure portions. Each first monolithic LED structure portion is provided above its respective table surface, and each second monolithic LED structure portion surrounds the first monolithic LED structure portion and has a sidewall surface that is inclined relative to its respective table surface.

[0058] In some embodiments, the LED precursor according to the first to fourth aspects of this disclosure, and the method for forming the LED array precursor therewith, can provide a micro-LED precursor and a micro-LED array precursor. The micro-LED array precursor is an array of micro-LED precursors. Each micro-LED precursor may have a size less than 100 μm × 100 μm. That is, at least the mesa portion of each micro-LED has a mesa surface with a size less than 100 μm × 100 μm. For example, in some embodiments, the mesa surface of the micro-LED precursor has a size less than 10... -8 m 2 Surface area. Attached Figure Description

[0059] The present disclosure will now be described in conjunction with the following non-limiting drawings. Further advantages of the present disclosure will be apparent when considered in conjunction with the drawings and with reference to the detailed description, wherein:

[0060] - Figure 1 A diagram illustrating intermediate steps of a method according to an embodiment of the present disclosure is shown, wherein a first semiconductor layer including a first semiconductor sublayer and a strained sublayer is provided;

[0061] - Figure 2 A diagram showing intermediate steps of a method according to an embodiment of the present disclosure is provided, wherein a first semiconductor layer including a mesa structure is provided;

[0062] - Figure 3 A diagram illustrating intermediate steps of a method according to an embodiment of the present disclosure is shown, wherein a first semiconductor layer having an overgrown second semiconductor layer is provided;

[0063] - Figure 4 A diagram of an LED precursor according to an embodiment of the present disclosure is shown, wherein a monolithic LED structure is provided on a first semiconductor layer;

[0064] - Figure 5 A diagram of an LED front-end according to an embodiment of the present disclosure is shown, wherein the strain layer includes a plurality of first strain layers and a plurality of second strain layers;

[0065] - Figure 6 A diagram of an LED front element according to an embodiment of the present disclosure is shown, wherein a mask layer is provided on... Figure 4 On the LED front;

[0066] - Figure 7 A diagram showing an LED precursor including a barrier according to an embodiment of the present disclosure is illustrated;

[0067] - Figure 8 A diagram showing intermediate steps of a method according to an embodiment of the present disclosure is provided, wherein an active layer of a monolithic LED structure is provided on a first semiconductor layer;

[0068] - Figure 9 A diagram of an LED precursor including a barrier according to another embodiment of the present disclosure is shown;

[0069] - Figure 10 a and Figure 10 b shows an SEM image of an example of a platform structure arranged in a square stacked array;

[0070] - Figure 10 c and Figure 10 Image d shows a SEM image of an overgrown monolithic LED array structure;

[0071] - Figure 11 SEM images of an overgrown monolithic LED array structure arranged in a hexagonal stacked array are shown. Detailed Implementation

[0072] According to one embodiment of this disclosure, a method for forming an LED precursor 1 is provided. Reference will now be made to... Figures 1 to 4 Describe a method for forming an LED precursor.

[0073] This specification pertains to the lattice constants of each layer of the LED precursor 1. Unless otherwise explicitly stated, the lattice constant of a layer should be understood as the in-plane lattice constant of that layer, rather than the lattice constant representing the dimension perpendicular to the layer (out-of-plane lattice constant).

[0074] like Figure 1 As shown, a substrate 10 can be provided for forming an LED precursor thereon. The substrate 10 can be any substrate 10 suitable for forming a group III-nitride electronic device. For example, the substrate 10 can be a sapphire substrate or a silicon substrate. The substrate may include one or more buffer layers configured to provide a substrate surface suitable for forming a group III-nitride layer.

[0075] A first semiconductor layer 20 is formed on the surface of a substrate. The first semiconductor layer 20 includes multiple layers. For example... Figure 1 As shown, the first semiconductor layer 20 includes a first semiconductor sublayer 21 and a strainor layer 22.

[0076] The first semiconductor sublayer 21 comprises a group III-nitride. In some embodiments, the first semiconductor sublayer may be n-type doped. In other embodiments, the semiconductor layer may not be intentionally doped. For example, in Figure 1 In this embodiment, the first semiconductor sublayer 21 comprises GaN. GaN can be n-type doped using suitable dopants such as Si or Ge. The first semiconductor sublayer 21 can be deposited using any suitable process for fabricating group III-nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The first semiconductor sublayer 21 has a first surface, which is the surface of the first semiconductor sublayer 21 on the side opposite to the substrate 10. A strain sublayer 22 is formed on the first surface of the first semiconductor sublayer 21. The first semiconductor sublayer 21 can be formed as a continuous sublayer across the surface of the substrate 10.

[0077] The first semiconductor sublayer 21 has a first in-plane lattice constant. The first semiconductor layer may have a wurtzite crystal structure. In some embodiments, the first semiconductor sublayer 21 may be formed on a substrate having a (0001) crystal plane provided on a surface parallel to the substrate 10. Therefore, for a first semiconductor sublayer having a first surface aligned with the (0001) crystal plane, the in-plane lattice constant may be a constant reflecting the a (or b) lattice constant.

[0078] like Figure 1 As shown, a strainor layer 22 is formed on a first surface of the first semiconductor sublayer 21. The strainor layer 22 comprises a group III nitride. The strainor layer 22 includes a strain surface on the side of the strainor layer 22 opposite to the substrate 10 (and the first semiconductor sublayer 21).

[0079] The strain sublayer 22 is formed with a coherent crystal structure that can be coherent with the first semiconductor sublayer 21. Thus, the interface between the first semiconductor sublayer 21 and the strain sublayer 22 can be a coherent interface. After a heat treatment step (discussed in more detail below), the strain sublayer 22 is relaxed to form a strain-relaxed sublayer 22a. The strain-relaxed sublayer 22a has a strain-relaxed surface 23 having a second in-plane lattice constant. The second in-plane lattice constant is greater than the first in-plane lattice constant of the first semiconductor sublayer 21. In some embodiments, similar to the first semiconductor sublayer 21, the strain-relaxed sublayer 22a can have a wurtzite crystal structure. In some embodiments, the strain-relaxed sublayer 22a can be formed on a substrate having a (0001) crystal plane provided parallel to the surface of the substrate 10. The strain-relaxed surface 23 can also be aligned with the (0001) crystal plane. Therefore, the in-plane lattice constant of the strain-relaxed surface 23 can be a constant reflecting the a-plane (or b-plane) lattice constant of the crystal structure.

[0080] The strain relaxation sublayer 22a (which is formed by the strain sublayer 22) can provide the strain relaxation surface 23 in a variety of ways.

[0081] In some embodiments, strainor layer 22 may be deposited as a single continuous layer. For example, strainor layer 22 may comprise a group III-nitride having a uniform composition. For example, strainor layer 22 may comprise In... X Ga 1－X N, where 0 < X ​​≤ 1. In some embodiments, strainer layer 22 may include In X Ga 1－X N, where 0 ≤ X ≤ 0.5, or where 0.1 ≤ X ≤ 0.4. Specifically, the strainor layer 22 can have a higher In content than the first semiconductor sublayer 21. For example, in Figure 1In one embodiment, the first semiconductor sublayer 21 comprises GaN. Therefore, the increased In content of the strain sublayer 22 relative to the first semiconductor sublayer 21 causes the strain relaxation sublayer 22a to relax to a second lattice constant, while the in-plane lattice constant of the strain relaxation surface 23 increases as desired.

[0082] In some embodiments, the strain sublayer 22 may be provided as a single continuous layer, wherein the composition of the strain sublayer 22 gradually varies over the entire thickness of the sublayer. For example, the strain sublayer 22 may include In X Ga 1－X N, wherein the In content (X) of the strain sublayer 22 increases or decreases, for example, in the thickness direction. For example, in some embodiments, the In content (X) of the strain relaxation sublayer decreases in the thickness direction away from the first semiconductor sublayer 21 (i.e., towards the strain surface 23). Thus, the strain sublayer 22 may be In X Ga 1－X A single sublayer of N, in which the composition (i.e., the In content X) is graded in the thickness direction.

[0083] In some embodiments, the strain sublayer 22 may be formed of multiple layers (i.e., sub-sublayers). The strain sublayer 22 may include multiple first strain layers, each having a third lattice constant, and multiple second strain layers, each having a fourth lattice constant. The first and second strain layers may be arranged alternately on top of each other to form the strain sublayer 22. Thus, each of the first and second strain layers may be formed as a continuous layer on top of each other. To provide a strain relaxation surface, the third and fourth lattice constants of the first and second strain layers are different. In some embodiments, the fourth lattice constant is greater than the third lattice constant.

[0084] For example, in one embodiment, the first strain layer may include GaN (i.e., the third lattice constant may be equal to the first lattice constant), and the second strain layer may include In. X Ga 1－X N, where 0 < X ​​≤ 1, 0 < X ​​≤ 0.5, or 0.1 ≤ X ≤ 0.4. The strain-relaxed surface may be provided by a first strain layer or a second strain layer. In other embodiments, the first strain layer may include In. X1 Ga 1-X1 N, where 0 < X1 ≤ 1, 0 < X1 ≤ 0.5, or 0.1 ≤ X1 ≤ 0.4 (i.e., the third lattice constant can be different from the first lattice constant), and the second strain layer may include In. X2 Ga 1-X2 N, where 0 < X2 ≤ 1, 0 < X2 ≤ 0.5, or 0.1 ≤ X2 ≤ 0.4.

[0085] In some embodiments, the composition of one or more of the first strain layer and the second strain layer may vary throughout the thickness of the strain relaxor layer. For example, the In content of the fourth strain layer may vary throughout the thickness of the strain relaxor layer 22.

[0086] Importantly, the compressive strain at the interface between the strain sublayer 22 and the first semiconductor sublayer 21 can lead to dislocation propagation when the strain sublayer 22 relaxes during heat treatment. By classifying the In content of the strain sublayer 22, the compressive strain can be higher at the interface and decrease towards the surface of the strain sublayer. Therefore, during relaxation, dislocations can preferentially propagate substantially in the in-plane direction rather than in the thickness direction. By providing the first semiconductor sublayer 21 with a strain-relaxed sublayer 22a having a higher In content, the formation of mismatched dislocations in the strain-relaxed sublayer 22a can be promoted in regions away from the strain-relaxed surface 23 (i.e., in regions with higher compressive strain). In other words, the formation of dislocations can be controlled to propagate in regions away from the growth surface 25 of the first semiconductor layer 20, thereby reducing the impact of lattice mismatch (dislocations) on the electrical properties of the LED precursor 1.

[0087] The strain layer 22 can be formed on the first semiconductor sublayer 21 by any growth method suitable for growing group III nitrides. The strain layer 22 can be formed as a continuous layer that substantially covers the entire main surface of the first semiconductor sublayer 21. The strain layer 22 can be deposited using any suitable process for fabricating group III nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0088] The growth surface 25 of the first semiconductor layer 20 can then be formed using a selective removal process. In this way, a portion of the first semiconductor layer 20 is selectively removed to form a mesa structure 24, such that the growth surface 25 of the first semiconductor layer 20 includes a host semiconductor layer surface 26 and a mesa surface 27.

[0089] For example, in Figure 2In this process, the growth surface 25 has been shaped using an etching process. During the etching process, a mask layer (not shown) defining the mesa can be deposited on the strained surface of the first semiconductor layer 20. The mask layer defining the mesa is configured to cover a portion of the first semiconductor layer 20, which is intended to form a mesa structure 24 having a mesa surface 27 with the growth surface 25. The uncovered portions of the first semiconductor layer 20 can then be selectively removed using an etchant. The etchant can etch away a portion of the first semiconductor layer 20 to expose the body semiconductor layer surface 26 of the first semiconductor layer 20. That is, the etchant may not completely etch through the entire thickness of the first semiconductor layer 20 to expose the underlying substrate 10. The mask layer defining the mesa can then be removed from the first semiconductor layer. By following the above process, the first semiconductor layer 20 can be shaped to provide a mesa structure 24, which is provided monolithically on the body semiconductor layer surface 26, for example as... Figure 2 As shown.

[0090] The mesa surface 27 is provided by a portion of the strainor layer 22 that has not been selectively removed. Therefore, after the selective removal step, the alignment of the portion of the strainor layer 22 forming the mesa surface 27 relative to the substrate 10 may remain unchanged. Thus, as... Figure 2 As shown, the mesa surface 27 may be parallel to the surface of the substrate 10. In some embodiments, the first semiconductor sublayer 21 is etched such that the host semiconductor surface 26 is also substantially parallel to the substrate 10. Therefore, the mesa surface 27 and the host semiconductor surface 26 of the first semiconductor layer 20 may both be substantially parallel to each other. In some embodiments, the mesa surface 27 and the host semiconductor surface 26 may be aligned with the (0001) plane of the group III-nitride forming the first semiconductor layer 20.

[0091] exist Figure 2 In the illustrated embodiment, the first semiconductor layer 20 is etched to expose the main semiconductor surface of the first semiconductor sublayer 21. Thus, the first semiconductor layer 20 is etched through the entire thickness of the strain gauge layer 22 and a portion of the thickness of the first semiconductor sublayer 21.

[0092] exist Figure 2 In the illustration, the mesa structure 24 has sidewalls that are substantially perpendicular to the host semiconductor surface 26 and the mesa surface 27. In other embodiments, the mesa structure 24 may be formed with inclined sidewalls. For example, different etchants can be used to control the shape of the sidewalls formed during the selective removal process.

[0093] After the formation of the first semiconductor layer 20, the strain layer 22 may undergo a heat treatment step. The heat treatment step may include heating the strain layer 22 to a temperature sufficient to cause plastic deformation of the strain layer 22. That is, the strain layer 22 is heated to a temperature at which thermal expansion of the strain relaxor layer 22a relative to the first semiconductor sublayer 21 causes plastic deformation of the strain layer 22. Plastic deformation of the strain layer 22 can lead to the formation of dislocations toward the interface between the strain layer 22 and the first semiconductor sublayer 21. For example, compressive stress present in the strain layer 22 during the heat treatment step can cause plastic deformation of the strain layer 22. Plastic deformation occurs through the propagation of mismatched dislocations substantially across the c-plane of the strain layer 22 (i.e., mismatched dislocations resulting from slippage in the c-plane) rather than in a direction transverse to the c-plane. The propagation of dislocations through the strain layer 22 alleviates at least some of the strain in the strain layer 22, thereby forming the strain relaxor layer 22a. Thus, the strain-relaxed sublayer 22b can be formed by the propagation of misfit dislocations rather than threading dislocations. Therefore, the heat treatment step can reduce the strain in the region of the mesa structure above the narrow band of dislocation propagation (i.e., the region of the mesa structure above the interface between the first semiconductor sublayer 21 and the strain-relaxed sublayer 22a). Therefore, the region above the dislocation band, including the strain-relaxed surface 23, can have reduced strain relative to the surface before the heat treatment step. This reduction in strain on the strain-relaxed surface 23 can increase its in-plane lattice constant. Further discussion on the propagation of misfit dislocations in the presence of mesa structures can be found at least in Mei et al., “Basal-plane slip in InGaN / GaN heterostructures in the presence of threading dislocations,” Applied Physics Letters, vol. 90, 2007, and Floro JA et al., “Misfit dislocation formation in the AlGaN / GaN heterointerface,” Journal of Applied Physics, Vol. 96, 2004.

[0094] The heat treatment step can be provided by any suitable method for annealing the material. For example, the heat treatment step can be provided by heating the strain relaxor layer 21 on the substrate 10 from room temperature to a first heat treatment temperature. The strain relaxor layer 21 can be held at the first heat treatment temperature for a first time period. The strain relaxor layer 21 can then be cooled back to room temperature. The heat treatment step can be performed in air, such as on a hot plate or in an oven. The heat treatment step can also be performed in a controlled atmosphere. In a controlled atmosphere, atmospheric compounds such as oxygen and water can be significantly reduced or completely eliminated. For example, the controlled atmosphere can be an NH3, Ag, or N2 atmosphere. In some embodiments, the heat treatment step can be performed in a controlled atmosphere containing N2 and NH3. Performing the heat treatment step in a controlled atmosphere can reduce or eliminate any undesirable chemical reactions that occur on the surface of the strain relaxor layer 22 during the heat treatment step.

[0095] In some embodiments, the heat treatment step may heat the strain relaxor layer 22 to a first heat treatment temperature of at least 500°C. In some embodiments, the first heat treatment temperature may be at least 800°C, 950°C, 1000°C, or 1050°C. The first time period may be at least 5 minutes. In some embodiments, the first time period may be at least 10 minutes, 20 minutes, 30 minutes, or 1 hour. For example, in some embodiments, the heat treatment step may include heating the strain relaxor layer to 800°C and holding the strain relaxor layer at that temperature for 1 hour, and then cooling it to room temperature. At higher first heat treatment temperatures, the first time period may be reduced (e.g., for a heat treatment temperature of 1050°C, the first time period is 5 minutes).

[0096] Importantly, when the strain relaxor layer 22a extends through a region of graded or variable composition, the heat treatment step can cause dislocations to propagate through regions of the strain relaxor layer with higher lattice mismatch at a lower heat treatment temperature than regions with lower lattice mismatch. Therefore, by providing a strain relaxor layer 22a with a graded or variable composition, dislocation propagation through the strain relaxor layer 22a can be further facilitated to occur in specific regions or bands of the strain relaxor layer 22. (The following is in conjunction with...) Figure 5 Let's discuss examples of this effect in more detail.

[0097] In some embodiments, the heat treatment step can be performed in situ after the formation of the first semiconductor layer 20. In other embodiments, the heat treatment step can be performed after the formation of the mesa structure 24. For example, in some embodiments, the heat treatment step can be performed in situ before the deposition of the second semiconductor layer 30.

[0098] Next, a monolithic LED structure can be formed on the growth surface 25 of the first semiconductor layer 20. The monolithic LED structure covers the mesa surface 27 and the body semiconductor layer surface 26. The monolithic LED structure includes multiple layers, each containing a group III nitride. In some embodiments, the group III nitride includes one or more of AlInGaN, AlGaN, InGaN, and GaN.

[0099] A monolithic LED structure refers to an LED structure that is formed as a single component. In other words, a monolithic LED structure is formed as a single component on a first semiconductor layer.

[0100] In one embodiment of this disclosure, such as Figure 3 As shown, the second semiconductor layer 30 can be deposited on the first semiconductor layer 20. The second semiconductor layer 30 is formed on the side of the first semiconductor layer 20 opposite to the substrate 10. In this way, the second semiconductor layer 30 forms the first layer of a plurality of layers in a monolithic LED structure.

[0101] The second semiconductor layer 30 can be formed on the growth surface 25 using any growth method suitable for growing group III nitrides. Figure 2 In this embodiment, the second semiconductor layer 30 is formed monolithically on the growth surface 25 (i.e., an overgrowth method). The second semiconductor layer 30 can be formed as a continuous layer that substantially covers the entire growth surface 25. The second semiconductor layer 30 can be deposited using any suitable process for fabricating group III-nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0102] The second semiconductor layer 30 includes a group III nitride. Figure 3 In this configuration, the second semiconductor layer 30 comprises GaN. The second semiconductor layer may be n-type doped. Suitable dopant, such as Si or Ge, can be used to n-type dope GaN. Figure 3 In this design, the second semiconductor layer 30 is not intentionally doped. Therefore, the second semiconductor layer 30 can be a (substantially) undoped layer. "Substantially undoped" can be understood as meaning that the group III-nitride layer does not contain any significant amount of dopant elements, while also understanding that some impurities may be present due to the manufacturing process. Therefore, a substantially undoped group III-nitride layer may not be intentionally doped. By forming the second semiconductor layer 30 from an undoped semiconductor, the flow of charge carriers through the LED can be more effectively confined within the mesa structure 24.

[0103] In some embodiments, the second semiconductor layer 30 may include In Y Ga 1-YN, where 0 < Y ≤ 1. For example, in some embodiments, the second semiconductor layer 30 includes In Y Ga 1-Y N, where 0 < Y ≤ 0.15. In some embodiments, the second semiconductor layer 30 may include an n-type dopant (i.e., the second semiconductor layer may be n-type doped). By incorporating In into the second semiconductor layer 30, the in-plane lattice constant of the second semiconductor layer 30 can be increased relative to the in-plane lattice constant of GaN. This increase can reduce the lattice mismatch between the second semiconductor layer 30 and the active layer 40. For example, in some embodiments where the active layer 40 is configured to output light with a wavelength of at least 620 nm, the second semiconductor layer 30 may include In. Y Ga 1-Y N, where 0.05≤Y≤0.15.

[0104] By growing a second semiconductor layer 30 on the first semiconductor layer 20, the second semiconductor layer 30 can have a crystal structure corresponding to the crystal structure of the first semiconductor layer 20. Specifically, the first portion 34 of the second semiconductor layer formed on the mesa surface 27 can have a crystal structure influenced by the in-plane lattice constant of the strain-relaxed surface 23 forming the mesa surface 27. For example, the second semiconductor layer 30 can also be grown with a similar crystal orientation when the mesa surface 27 of the first semiconductor layer 20 is aligned with the (0001) plane of a group III-nitride.

[0105] exist Figure 3 In one embodiment, a second semiconductor layer 30 is formed on the growth surface 25 to provide a sloping sidewall portion 38 extending between a first portion 34 of the second semiconductor layer on the mesa surface 27 of the first semiconductor layer and a second portion 36 of the second semiconductor layer on the body semiconductor surface 26 of the first semiconductor layer. Therefore, the second semiconductor layer 30 can be overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a Group III-nitride semiconductor layer including the second semiconductor layer mesa surface 37 and surrounded by the sloping sidewall portion 38. Effectively, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar having a regular trapezoidal cross-section perpendicular to the substrate, wherein the second semiconductor layer mesa surface 37 forms a substantially flat upper surface of the trapezoidal cross-section. The second semiconductor layer mesa surface 37 can be aligned with a plane parallel to the substrate surface on which the layers are formed.

[0106] A “regular trapezoidal cross-section” refers to a column whose top surface (covering the mesa surface 27) is narrower than its bottom surface (facing the main semiconductor surface 26), and which has a substantially flat top surface with sloping linear sides. This can result in a truncated cone shape, or more likely a truncated pyramid shape with three or more sides, typically six sides. The trapezoidal cross-section is formed by the mesa structure 24 of the first semiconductor layer, the first portion 34 of the second semiconductor layer, and the sloping sidewall portion 38 of the second semiconductor layer grown on the mesa structure 24. Thus, the regular trapezoidal cross-section extends above the second portion 36 of the second semiconductor layer in a continuous plane. The tapered side of the trapezoidal cross-section of the column is referred to herein as the sloping sidewall portion 38.

[0107] In some embodiments, each inclined sidewall portion 38 of each pillar has a substantially consistent angle (α) with the plane parallel to the first semiconductor layer. That is, the angle between the sidewall of the pillar and the plane parallel to the first semiconductor layer does not vary significantly. For example, the angle α is between 50° and 70°, more preferably between 58° and 64°, and most preferably about 62°.

[0108] Therefore, in some embodiments, the inclined sidewall portion 38 of the pillar may be inclined relative to the (0001) plane of the crystal structure of the first semiconductor layer 20. The inclined sidewall may typically be oriented along the {110 1} or {110 2} plane of the wurtzite crystal, exhibiting a reduced polarization field compared to the c-plane surface (semi-polar surface), similar to the structure generated by SAG.

[0109] In some embodiments, the pillars in the second semiconductor layer 30 are truncated hexagonal pyramids.

[0110] After the second semiconductor layer 30 is formed, a further monolithic LED structure layer can be formed on it. Figure 4 An example of an LED precursor is shown, in which... Figure 3 Further monolithic LED structure layers are formed on the intermediate structure.

[0111] like Figure 4 As shown, an active layer 40 can then be formed on the second semiconductor layer 30. The active layer 40 is configured as part of a monolithic LED structure to generate light of a first wavelength.

[0112] exist Figure 4 In some embodiments, the active layer 40 may include one or more quantum well layers (not shown). Thus, the active layer 40 may be a multi-quantum well layer. The quantum well layers within the active layer 40 may include group III-nitride semiconductors, preferably group III-nitride alloys comprising In. For example, in Figure 2 In some embodiments, the active layer 40 may include GaN and In. z Ga 1-zAlternating layers of N, where 0 < Z ≤ 1. Specifically, in some embodiments, the active layer may include In... z Ga 1-z N layers, where 0.2 ≤ Z ≤ 0.5. Thus, in some embodiments, the active layer 40 of the LED can be configured to output light with a wavelength of at least 540 nm. The thickness of the quantum well layer and the In content can be controlled to control the wavelength of the light generated by the active layer. The active layer 40 can be formed as a continuous layer covering most (e.g., all) of the exposed surface of the second semiconductor layer 30. The active layer 40 can be deposited using any suitable process for fabricating group III-nitride thin films, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0113] The active layer 40 may include a strain interface layer (not shown).

[0114] The deposition of the active layer 40 on the second semiconductor layer 30 can occur at a relatively high deposition rate on the first portion 35 of the second semiconductor layer on the mesa surface 27, and at a significantly lower deposition rate on the inclined sidewalls. This effect is caused by the different crystal planes aligning on the various surfaces, resulting in the active layer 40 being thicker above the mesa surface 27 than on the inclined sidewalls 35. This effect is described in more detail in GB1811190.6.

[0115] Then, further layers of the monolithic LED structure can be deposited on the active layer 40 on the side opposite to the second semiconductor layer 30. Figure 4 An example of forming a multi-layered monolithic LED structure is shown, wherein the multi-layered layers are formed on the growth surface 25 of the first semiconductor layer 20. All the multi-layered layers of the monolithic LED structure can be formed as continuous layers.

[0116] exist Figure 4 In one embodiment, an electron blocking layer 50 is provided on the active layer 40. The electron blocking layer 50 is provided on the side of the active layer 40 opposite to the side of the active layer 40 to which the second semiconductor layer 30 is provided. The electron blocking layer 50 comprises a group III-nitride. The electron blocking layer 50 may be formed as a continuous layer covering most (e.g., all) of the exposed surface of the active layer 40. The electron blocking layer 50 is configured to reduce the electron flow from the active layer 30 into the p-type semiconductor layer 60 of the monolithic LED structure. For example, in some embodiments, the electron blocking layer 50 may comprise Al. w Ga 1-w N, where 0 < w ≤ 1. Further details of a suitable electron blocking layer 50 can be found at least in APPLIED PHYSICS LETTERS 103, 061104 (2013).

[0117] like Figure 3 As shown, a p-type semiconductor layer 60 is provided above the active layer 40. The p-type semiconductor layer 60 is provided on the side of the electron blocking layer 50 opposite to the side where the active layer 40 is disposed. The p-type semiconductor layer 60 comprises a group III nitride. The p-type semiconductor layer 60 is doped with a suitable electron acceptor, such as Mg. The p-type semiconductor layer 60 can be formed as a continuous layer covering most (e.g., all) of the exposed surface of the active layer 40 (or the electron blocking layer 50, if present).

[0118] Therefore, the p-type semiconductor layer 60 may be provided with a first portion 64, which is substantially aligned with the mesa structure 24. That is, the surface of the first portion 67 of the p-type semiconductor layer is provided above the mesa surface 27 (i.e., the centers of the respective surfaces 27 and the centers of the respective 67 can be aligned). The p-type semiconductor layer 60 also includes a second portion 66, which covers at least a portion of the main semiconductor surface 26 remote from the mesa surface 24. Thus, a monolithic LED structure can generally be considered to have a first portion provided above the mesa surface 27 and a second portion covering at least a portion of the main semiconductor surface 26 remote from the mesa surface 27.

[0119] Figure 5 An embodiment of the LED front element 1 according to this disclosure is shown. (and) Figure 4 Similarly, in the embodiment, the LED precursor 1 includes a first semiconductor layer 20, a second semiconductor layer 30, an active layer 40, an electron blocking layer 50, and a p-type semiconductor layer 60. Therefore, these layers can be formed according to the method described above.

[0120] The first semiconductor layer 20 includes a first semiconductor sublayer 21 and a strain relaxation sublayer 22a. For example... Figure 5 As shown, the strain relaxation sublayer 22a comprises multiple layers. From the above discussion, it can be understood that... Figure 5 The strain relaxor layer 22a can be formed after the heat treatment step by a strain sublayer 22 comprising alternating first and second strain layers.

[0121] Figure 5 The strain relaxor layer 22a includes a plurality of first strain layers 101. The first strain layers 101 and second strain layers 102 are arranged alternately on top of each other. Thus, each of the first strain layers 101 and second strain layers 102 is formed as a continuous layer on top of each other.

[0122] exist Figure 5 In one embodiment, the first strain layer comprises GaN (i.e., the third lattice constant can be equal to the first lattice constant), and the second strain layer 102 comprises In. X Ga 1-XN, where 0 < X ​​≤ 1, 0 < X ​​≤ 0.5, or 0.1 ≤ X ≤ 0.4. The strain-relaxed surface can be provided by a first strain layer 101 or a second strain layer 102. Figure 5 In one embodiment, the strain relaxation surface 23 is provided by the first strain layer 101.

[0123] exist Figure 5 In one embodiment, the composition of the second strain layer 102 varies throughout the thickness of the strain relaxor layer 22a. Figure 5 In the embodiments, the first group of second strain layers 104 is provided with a first composition, and the second group of second strain layers 106 is provided with a second composition. The first and second compositions can be provided such that the in-plane lattice constant of the second group of second strain layers 106 is lower than the in-plane lattice constant of the first group of second strain layers 104. For example, in... Figure 5 In the embodiments, the first group of second strain layers 104 includes In X3 Ga 1-X3 N, where 0.1≤X3≤0.4, the second strain layer 106 of the second group includes In X3 Ga 1-X3 N, where 0 < X³ ≤ 0.15. Therefore, it should be understood that... Figure 5 The embodiments provide an example of a strain relaxor layer 22a (formed from strain relaxor layer 22) having graded components as described above.

[0124] Therefore, the first set of second strain layers 104 can provide a region of the mesa structure 24 where the strain is locally higher than the region of the mesa structure 24 where the second set of second strain layers 106 are provided. This can thus promote the formation of mismatched dislocations in the mesa structure region where the first set of second strain layers 104 are located. Figure 4 As shown, the first set of second strain layers is provided facing the first semiconductor sublayer 21 and away from the strain relaxation surface 23. Therefore, dislocations (caused by...) Figure 5 The dashed line D in the diagram indicates that the LED can propagate in the area of ​​the table structure that is far from the monolithic LED structure.

[0125] To improve charge carrier confinement in the active layer above the mesa surface 27 of the LED, a potential barrier can be formed between a first portion of the monolithic LED structure covering the mesa surface 27 and a second portion of the monolithic LED structure covering the host semiconductor surface 26, according to the method of this disclosure, wherein the barrier surrounds the first portion 64 of the p-type semiconductor layer covering the mesa surface 27. In other words, a potential barrier is provided between the upper contact surface of a generally flat surface with a regular trapezoidal shape and the layers formed above the host semiconductor surface 26 according to the method of this disclosure.

[0126] A method for forming such a barrier is schematically shown in Figure 3 and Figure 4middle. Figure 6 and Figure 7 The embodiments illustrate the manufacture of such Figure 4 The following are the further processing steps following the device shown.

[0127] exist Figure 6 In this process, a mask layer 70 is formed on the surface of the p-type semiconductor layer 60 on the side opposite to the electron blocking layer 50.

[0128] A mask layer 70 may be selectively provided on the p-type semiconductor layer 60. The mask layer 70 may be provided to define one or more vias. These vias may be configured to expose regions of the p-type semiconductor layer 60 to be selectively removed. For example, these vias may define a third portion 61 of the p-type semiconductor layer surrounding a first portion 64 of the p-type semiconductor layer covering a mesa structure. The third portion 61 of the p-type semiconductor layer may then be selectively removed, for example, by etching, to provide a barrier. Figure 6 In one embodiment, the third portion 61 of the p-type semiconductor layer is the inclined sidewall portion of the p-type semiconductor layer 60.

[0129] exist Figure 6 and 7 In one embodiment, an anisotropic etchant can be used to selectively remove the third portion 61 of the p-type semiconductor layer. An anisotropic etchant, such as KOH, can preferentially etch the tilted sidewall regions of the group III-nitride at a faster rate than a flat plane aligned parallel to the substrate (e.g., a surface aligned with the (0001) crystal plane). Therefore, a mask layer 70 can be provided to define a plurality of holes and the third portion 61 of the p-type semiconductor layer corresponding to the tilted sidewall regions of the p-type semiconductor layer 60, wherein the holes are aligned and expose the surface of the first portion 67 of the p-type semiconductor layer. The anisotropic etchant can then preferentially etch the p-type semiconductor layer 60 in the tilted sidewall regions at a significantly higher rate to remove the desired amount of material.

[0130] Figure 7 A schematic diagram of the LED precursor obtained after forming a potential barrier by selectively removing the third portion 61 of the p-type semiconductor layer is shown. Figure 7 As shown, the p-type semiconductor layer 60 is selectively removed through the thickness of this layer to expose the underlying layer. Figure 7(electron blocking layer 50 in the embodiment). Thus, the selective removal step forms a channel in the monolithic LED structure that surrounds the first portion 64 of the p-type semiconductor layer. Therefore, a potential barrier is formed in the p-type semiconductor layer 60 between the first portion 67 of the p-type semiconductor layer covering the mesa surface 27 and the second portion 66 of the p-type semiconductor layer covering the host semiconductor surface 26. This barrier is provided to increase the confinement of charge carriers in the portion of the active layer 40 covering the mesa structure 24 during operation.

[0131] In other embodiments of the method according to this disclosure, the depth of the selectively removed channel can be varied. For example, in some embodiments, the channel may extend only partially through the thickness of the third portion 61 of the p-type semiconductor layer. By reducing the thickness of the third portion of the p-type semiconductor layer 61, combined with the variation in the deposition rate of the monolithic LED structure on the aforementioned sidewall surface as described above, the remaining portion of the third portion 61 of the p-type semiconductor layer can present a significant resistance between the first portion 64 and the second portion 66 of the p-type semiconductor layer, thereby effectively providing a potential barrier. In other embodiments, the channel may extend at least partially through the thickness of one or more other layers of the monolithic LED structure.

[0132] Another method for forming this potential barrier is illustrated schematically. Figure 8 and Figure 9 middle.

[0133] Figure 8 An intermediate structure including a first semiconductor layer 20, a second semiconductor layer 30, and an active layer 40 is shown. Figure 8 The structure can be at least as described above regarding Figures 1 to 4 The methods and steps discussed are used to form the process.

[0134] In formation Figure 8 After the intermediate structure is formed, a p-type semiconductor layer 60 is formed on the active layer 40, such as... Figure 9 As shown. The p-type semiconductor layer 60 is formed on the side of the active layer 40 opposite to the second semiconducting layer 30. In some embodiments, an electron blocking layer 50 may be provided between the p-type semiconductor layer 60 and the active layer 40, such as... Figure 3 As shown.

[0135] exist Figure 9In this embodiment, the p-type semiconductor layer 60 comprises a Group III nitride, including Al. The p-type semiconductor layer 60 can be formed such that a higher concentration of Al is bonded to the sidewall portion 68 of the p-type semiconductor layer compared to the first portion 64 of the p-type semiconductor layer covering the mesa surface 27, thereby providing a potential barrier between the sidewall portion of the p-type semiconductor layer 68 and the first portion 64 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 68 and the first portion 64 of the p-type semiconductor layer can cause a bandgap change between the first portion 64 and the sidewall portion 68 greater than kTeV (i.e., greater than about 0.26eV) at room temperature.

[0136] For example, the sidewall portion of the p-type semiconductor layer 68 may include p-type Al x Ga 1-x N, where 2 ≤ x ≤ 50%, and the first portion 64 of the p-type semiconductor layer may include p-type Al y Ga 1-y N, where 1≤y≤15%.

[0137] As described above, the tilted sidewalls of the second semiconductor layer 30 cause variations in the deposition rate of group III nitrides, depending on whether the growth surface is tilted or substantially parallel to the substrate. For the growth of the p-type semiconductor layer 60, this difference in growth rate also affects Al bonding to the p-type semiconductor layer 60. Therefore, the tilted sidewall portion 68 can be formed using the same deposition process to have a higher Al content than the first portion 64. Consequently, the required barrier for limiting the current in the first portion 64 of the p-type semiconductor layer in the monolithic LED structure can be formed without any further patterning steps.

[0138] As mentioned above, an LED precursor with multiple layers can be provided.

[0139] The thickness of the first semiconductor layer 20 (in the direction perpendicular to the substrate surface) can be between 100 nm and 8 μm, and preferably between 3 μm and 5 μm. A portion of the first semiconductor layer 20 can be selectively removed to define a mesa structure, the height of which perpendicular to the host semiconductor surface 26 is at least 100 nm, 200 nm, 300 nm, or 500 nm. The mesa structure can have a height of no more than 4 μm. In some embodiments, the mesa structure can have a height between 1 μm and 2 μm. The height of the mesa structure can be the distance between the host semiconductor surface 26 and the mesa surface 27 in the direction perpendicular to the surfaces.

[0140] In some embodiments, the strainor layer 22 may have a thickness of at least 100 nm. In some embodiments, the strainor layer 22 may have a thickness approximately equal to the intended height of the mesa structure 24.

[0141] The second semiconductor layer 30 may have a thickness of at least 5 nm on the mesa surface 27 of the first semiconductor layer 20. The second semiconductor layer 30 may have a thickness of no more than 4 μm.

[0142] The thickness of the generally flat first portion 34 of the active layer 30 can be between 30 nm and 150 nm, and in some embodiments between 40 nm and 60 nm.

[0143] The thickness of the substantially flat first portion 44 of the electron blocking layer 50 can be between 5 nm and 50 nm, and in some embodiments between 20 nm and 40 nm. For example, in Figure 3 In some embodiments, the electron blocking layer can have a thickness of 33 nm. Due to variations in deposition rate, as described above, in the sidewall regions of the electron blocking layer 50, the electron blocking layer 50 can have a thickness of at least 0.5 nm up to approximately 25 nm. For example, in Figure 3 In one embodiment, the electron blocking layer 50 may have a thickness of about 7 nm in the sidewall region.

[0144] The substantially flat first portion 64 of the p-type semiconductor layer 60 may have a thickness of at least 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. The substantially flat first portion 64 of the p-type semiconductor layer 60 may have a thickness not exceeding 300 nm, 250 nm, or 200 nm. For example, in... Figure 3 In one embodiment, the generally flat first portion 64 of the p-type semiconductor layer 60 may have a thickness of about 100 nm.

[0145] According to embodiments of this disclosure, a light-emitting diode precursor 1 is provided. Figure 4 An embodiment of the LED precursor 1 according to the present disclosure is shown. Figure 4 The LED precursor includes a first semiconductor layer 20, a second semiconductor layer 30, an active layer 40, an electron blocking layer 50, and a p-type semiconductor layer 60.

[0146] like Figure 4 As shown, a first semiconductor layer 20 may be provided on a substrate 10. The substrate 10 may include sapphire, silicon, or SiC. The substrate 10 may include one or more buffer layers configured to provide a substrate surface suitable for forming a group III-nitride layer. Of course, in some embodiments, the LED precursor 1 may be fabricated according to the method described above, after which the substrate 10 may be removed. In some embodiments, the LED precursor 1 may be bonded to a backplane electronic substrate (not shown). The backplane electronic substrate may include circuitry and contacts configured to control and contact the LED precursor 1. In some embodiments, the backplane electronic substrate may be bonded to a p-type semiconductor layer 60.

[0147] like Figure 4 As shown, the first semiconductor layer 20 includes a mesa structure 24 extending from the main surface of the first semiconductor layer 20 to define a growth surface 25 including a host semiconductor surface 26 and a mesa surface 27. The main surface should be understood as the surface of the first semiconductor layer 20 that forms the majority of the total surface area of ​​the first semiconductor layer 20. For example, in... Figure 4 In this context, the main surface forming the growth surface 25 refers to the surface of the first semiconductor layer 20 on the side opposite to the substrate 10.

[0148] The mesa structure 24 can be considered as a pillar extending from the body semiconductor surface 26 of the first semiconductor layer 20. The mesa structure 24 is monolithically formed with the body semiconductor surface 26 of the first semiconductor layer 20, as described in the above method. The mesa structure 24 can be a pillar with any cross-sectional shape (i.e., the shape of the pillar when the first semiconductor layer 20 is viewed in a plan view). For example, the mesa structure 24 can be a pillar with a regular polygonal cross-section. In particular, the mesa structure 24 can be an elliptical (or circular) pillar, a rectangular pillar, or a hexagonal pillar. Figure 10 a shows an example of a plurality of mesa structures 24 of the first semiconductor layer 20, wherein each mesa structure 24 is a cylinder.

[0149] The first semiconductor layer 20 includes a first semiconductor sublayer 21 and a strain relaxation sublayer 22a. The formation and structure of the first semiconductor electronic layer 21 and the strain relaxation sublayer 22a have been discussed in detail above and will not be repeated here.

[0150] exist Figure 4 In one embodiment, the mesa structure 24 shown has sidewalls that are substantially perpendicular to the host semiconductor surface 26 and the mesa surface 27. In other embodiments, the mesa structure 24 may be formed with inclined sidewalls.

[0151] like Figure 4 As shown, a monolithic LED structure is provided on the growth surface 25 of the first semiconductor layer 20 such that the monolithic LED structure covers the mesa surface 27 and the main semiconductor surface 26.

[0152] As described above, the monolithic LED structure comprises multiple layers. Each layer is formed of a group III nitride. The monolithic LED structure includes a second semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 60. In some embodiments, the monolithic LED structure may further include an electron blocking layer 50.

[0153] As described above, a second semiconductor layer 30 is provided on the growth surface 25 to provide inclined sidewalls 38 extending between a first portion 34 of the second semiconductor layer on the mesa surface 27 of the first semiconductor layer and a second portion 36 of the second semiconductor layer on the body semiconductor surface 26 of the first semiconductor layer. Therefore, the second semiconductor layer 30 is overgrown on the mesa structure 24 of the first semiconductor layer 20 to provide a Group III-nitride semiconductor layer, which includes the first portion 34 and is surrounded by inclined sidewalls 33. Thus, the second semiconductor layer 30 can be overgrown on the mesa structure 24 to form a pillar with a regular trapezoidal cross-section perpendicular to the substrate, wherein the surface of the first portion 35 of the second semiconductor layer is substantially flat. The substantially flat surface of the first portion 35 can lie in a plane parallel to the substrate surface on which the layers are formed.

[0154] An active layer 40, an electron blocking layer 50 (if present), and a p-type semiconductor layer 60 can be provided on the second semiconductor layer 30 according to the method described above to form a monolithic LED structure. Examples of such a monolithic LED structure can also be found at least in... Figure 5 , Figure 6 , Figure 7 and Figure 9 I saw it in the middle.

[0155] To improve charge carrier confinement in the active layer above the mesa surface 27 of the LED, the LED precursor according to this disclosure may include a potential barrier between a first portion of the monolithic LED structure covering the mesa surface 27 and a second portion of the monolithic LED structure covering the host semiconductor surface 26, wherein the potential barrier surrounds the first portion of the p-type semiconductor layer covering the mesa surface 27. In other words, the method according to this disclosure provides a potential barrier between a generally flat surface of a regular trapezoidal shape and the layers formed above the host semiconductor surface 26.

[0156] like Figure 7 and Figure 9 As shown, a monolithic LED structure is formed such that a potential barrier is provided between a first portion 64 of a p-type semiconductor layer covering the mesa surface and a second portion 66 of a p-type semiconductor layer covering the body semiconductor surface, the barrier surrounding the first portion 64 of the p-type semiconductor layer covering the mesa surface. Figure 7 and Figure 9 The formation of the potential barrier in the embodiments has been discussed in detail above, so it will not be repeated here.

[0157] Therefore, an LED precursor according to an embodiment of the present disclosure can be provided.

[0158] According to another embodiment of this disclosure, a method for forming an LED array precursor can be provided.

[0159] According to this method, a first semiconductor layer 20 comprising a group III-nitride is formed on a substrate 10. On the side of the first semiconductor layer 20 opposite to the substrate 10, the first semiconductor layer 20 has a growth surface 25. Thus, the first semiconductor layer 20 can be formed with the aforementioned... Figures 1 to 9 The embodiments are formed using essentially the same method.

[0160] Next, portions of the first semiconductor layer 20 are selectively removed to form a plurality of mesa structures 24, such that the growth surface 25 of the first semiconductor layer 20 includes a plurality of mesa surfaces 27 and a host semiconductor layer surface 26. Therefore, this step of the method is substantially the same as the corresponding step in the method for forming an LED precursor, wherein a plurality of mesa structures 24 are formed.

[0161] Multiple mesa structures 24 can be regularly spaced on the substrate growth surface 25 of the first semiconductor layer 20. For example, each mesa structure can be provided as a hexagonal close-packed array or a square stacked array. Figure 10 Image a shows a scanning electron microscope (SEM) image of an exemplary layer, which includes a plurality of mesa structures similar to the first semiconductor layer 20 according to this disclosure. Figure 10 It is understood that multiple mesa structures 24 can be provided as part of the first semiconductor layer 20. Each mesa structure 24 can be a pillar with a cylindrical shape (circular cross-section). Figure 10 b shows Figure 10 A magnified view of one of the platform structures 24 shown in Figure a.

[0162] Then, a monolithic LED array structure is formed on the growth surface 25 of the first semiconductor layer 20, such that a first portion of the monolithic LED array structure covers the corresponding mesa surface 27 and a second portion of the monolithic LED array structure covers the host semiconductor surface 26. The monolithic LED array structure includes multiple layers. Each layer is formed of a group III nitride. The monolithic array structure may include a second semiconductor layer 30, an active layer 40 provided on the second semiconductor layer 30, and a p-type semiconductor layer 60 provided on the active layer 40. In some embodiments, the monolithic LED array structure may further include an electron blocking layer 50 provided between the active layer 40 and the second semiconductor layer 60.

[0163] A monolithic LED array structure refers to an LED array structure that is formed as a single component. In other words, a monolithic LED array structure is formed as a single component on a first semiconductor layer.

[0164] Each layer of the monolithic LED array structure can be provided using substantially the same process as the method described above for forming the LED precursor. It should be understood that substantially the same process used to form the monolithic LED array structure / monolithic LED structure can be used, regardless of the number or shape of the LEDs manufactured. Thus, the overgrowth method of this disclosure provides a method for forming an LED array precursor in which the main part of the manufacturing process is independent of the geometry of the LED array.

[0165] Figure 10 c and 10d show SEM images of multiple mesa structures with overgrown monolithic LED array structures. The monolithic LED array structure is formed on a surface similar to... Figure 10 On the multiple platform structures shown in figure a. Figure 10 a to Figure 10 In d, the platform structure is formed as a square stacked array pattern. Figure 11 SEM images of another array of mesa structures with an overgrown monolithic LED array structure are shown. Figure 11 In the middle, the platform structure is arranged in a hexagonal close-packed array pattern to provide the array structure shown.

[0166] A potential barrier can be provided between each first portion of the p-type semiconductor layer 64 covering each mesa surface 27 and the main portion of the p-type semiconductor layer 66 covering the main semiconductor surface 26. The barrier surrounds each first portion of the p-type semiconductor layer 64 covering the respective mesa surface 27.

[0167] To improve charge carrier confinement in the active layer 40 above each mesa surface 27 of each LED, a potential barrier is formed in each LED between a first portion of the monolithic LED structure covering the mesa surface 27 and a second portion of the monolithic LED structure covering the host semiconductor surface 26, wherein the barrier surrounds the first portion of the p-type semiconductor layer covering the mesa surface 27. That is, according to the method of this disclosure, a potential barrier is provided between the upper contact surface of each generally flat surface of a regular trapezoidal shape and the layers formed on the host semiconductor surface 26.

[0168] The potential barrier for each monolithic LED structure in an LED array can be formed in a variety of ways. For example, the potential barrier for each monolithic LED structure can be essentially as described above. Figure 7 As described or substantially as referenced above. Figure 9 The formation.

[0169] Similar to Figure 7 The structure shown can be formed by selectively removing a third portion 61 of the p-type semiconductor layer, which surrounds each first portion of the p-type semiconductor layer covering the mesa surface 64. Figure 7As shown, the thickness of the p-type semiconductor layer 60 extending through this layer is selectively removed to expose the underlying layer. Figure 7 (electron blocking layer 50 in the structure).

[0170] Similar to Figure 9 The structure in the diagram can be protected by providing a p-type semiconductor layer 60 containing a group III-nitride, including Al, to form a potential barrier. The p-type semiconductor layer 60 is provided such that a higher concentration of Al is bonded to the sidewall portion 63 of the p-type semiconductor layer compared to the first portion 64 of the p-type semiconductor layer covering the mesa surface 27, thus providing a potential barrier between the sidewall portion 63 and the first portion 64 of the p-type semiconductor layer. The difference in Al composition between the sidewall portion 63 and the first portion 64 of the p-type semiconductor layer allows the bandgap change to be greater than kTeV at room temperature (i.e., greater than about 0.26eV).

[0171] Therefore, a method for forming an LED array precursor is provided.

[0172] In yet another embodiment of this disclosure, an LED array precursor is provided.

[0173] The LED array precursor includes a first semiconductor layer 20 and a monolithic LED array structure.

[0174] The first semiconductor layer 20 includes a group III-nitride. For example... Figure 4 As shown, a first semiconductor layer 20 can be provided on a substrate 10. The substrate 10 may include sapphire, silicon, or SiC. The substrate 10 may include one or more buffer layers configured to provide a substrate surface suitable for forming a group III-nitride layer. Of course, in some embodiments, the LED array precursor can be fabricated according to the method described above, after which the substrate 10 can be removed. In some embodiments, the LED array precursor can be bonded to a backplane electronics substrate. The backplane electronics substrate may include circuitry and contacts configured to control and contact each LED of the LED array precursor. In some embodiments, the backplane electronics substrate can be bonded to a p-type semiconductor layer 60. Thus, the first semiconductor layer 20 can be provided substantially according to the method described above.

[0175] Similar to Figure 4 , Figure 5 , Figure 7 and Figure 9 As shown, the first semiconductor layer 20 includes a plurality of mesa structures 24 extending from the main surface of the first semiconductor layer to define a growth surface 25, the growth surface 25 including a main semiconductor surface 26 and a mesa surface 27. As described above, an example of a first semiconductor layer including a plurality of mesa structures 24 is shown in... Figure 10 As shown in a.

[0176] Similar to Figure 4 , Figure 5 , Figure 7 and Figure 9 In the embodiment shown, a monolithic LED array structure is provided on the growth surface 25 of the first semiconductor layer 20, such that the monolithic LED array structure covers the mesa surface 27 and the main semiconductor surface 26.

[0177] As described above, the monolithic LED array structure comprises multiple layers. Each layer is formed of a group III nitride. The monolithic LED array structure may include a second semiconductor layer 30, an active layer 40, an electron blocking layer 50, and a p-type semiconductor layer 60. Each layer of the monolithic LED array structure can be formed as a continuous layer. Therefore, each layer of the monolithic LED array structure can be provided in a manner similar to that described above.

[0178] To improve charge carrier confinement in the active layer above each mesa surface 27 of the LED array precursor, each LED precursor of the array includes a potential barrier between a first portion of each monolithic LED structure covering its respective mesa surface 27 and a second portion of each monolithic LED structure covering the host semiconductor surface 26, wherein the potential barrier surrounds the first portion of each p-type semiconductor layer covering its respective mesa surface 27. In other words, the method according to this disclosure provides a potential barrier between each substantially flat surface of a regular trapezoidal shape and the layers formed above the host semiconductor surface 26.

[0179] refer to Figure 7 and Figure 9 Each monolithic LED array structure is formed such that a barrier is provided between a first portion 64 of the p-type semiconductor layer covering the mesa surface and a second portion 66 of the p-type semiconductor layer covering the host semiconductor surface, the barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface 65.

[0180] refer to Figure 7 As described above, a potential barrier can be formed by selectively removing a third portion 61 of the p-type semiconductor layer, which surrounds the first portion of the p-type semiconductor layer covering the mesa surface 67. Figure 5 As shown, the p-type semiconductor layer 60 can be selectively removed through the thickness of this layer to expose the underlying layer. Figure 5 (electron blocking layer 50 in the embodiment).

[0181] refer to Figure 9A potential barrier can be formed by providing a p-type semiconductor layer 60 comprising an Al-containing group III-nitride. The p-type semiconductor layer 60 is provided such that a higher concentration of Al is bonded to each sidewall portion 63 of the p-type semiconductor layer 60 compared to each first portion 64 of the p-type semiconductor layer covering each mesa surface 27, thereby providing a potential barrier between each sidewall portion 63 and each first portion 67 of the p-type semiconductor layer for each LED precursor in the LED array precursor. The difference in Al composition between each sidewall portion 68 and each first portion 64 of the p-type semiconductor layer can result in a bandgap variation greater than kTeV at room temperature (i.e., greater than approximately 0.26eV).

[0182] For example, each sidewall portion 68 of the p-type semiconductor layer may include a p-type Al x Ga 1-x N, where 2 ≤ x ≤ 50%, and the mesa surface portion 65 of the p-type semiconductor layer may include p-type Al y Ga 1-y N, where 1≤y≤15%.

[0183] As described above, the tilted sidewalls of the second semiconductor layer 30 cause variations in the deposition rate of group III nitrides, depending on whether the growth surface is tilted or substantially parallel to the substrate. For the growth of the p-type semiconductor layer 60, the difference in growth rate also affects Al bonding into the p-type semiconductor layer 60. Therefore, the tilted sidewall portion 68 can be formed using the same deposition process to have a higher Al content than each of the first portions 64 of the p-type semiconductor layer. In this way, the necessary barrier for limiting the current in the mesa surface portion of the monolithic LED structure can be formed without any further patterning steps.

Claims

1. A method of forming a light emitting diode (LED) precursor, comprising: (a) forming a first semiconductor layer on a substrate, forming the first semiconductor layer comprising: forming a first semiconductor sub-layer comprising a Ill-nitride having a first in-plane lattice constant on a surface of the substrate; and forming a strained sub-layer comprising a Ill-nitride on the first semiconductor sub-layer on a side of the first semiconductor sub-layer opposite the substrate, wherein the strained sub-layer is under compressive strain at an interface between the strained sub-layer and the first semiconductor sub-layer such that an in-plane lattice constant of the strained sub-layer at the interface is the first in-plane lattice constant; (b) selectively removing a portion of the first semiconductor layer to expose a bulk semiconductor layer surface of the first semiconductor layer such that the first semiconductor layer defines a mesa structure extending from the bulk semiconductor layer surface; (c) heating the strained sub-layer to a strain relaxation temperature, wherein the strained sub-layer relaxes by plastic deformation to form a strain relaxed sub-layer, wherein the mesa structure has a mesa surface formed by a portion of the strain relaxed sub-layer, the mesa surface having a second in-plane lattice constant, the second in-plane lattice constant being greater than the first in-plane lattice constant; (d) forming a monolithic LED structure on the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the bulk semiconductor surface, the monolithic LED structure comprising a plurality of Ill-nitride layers, the monolithic LED structure having: a first monolithic LED structure portion provided over the mesa surface; and a second monolithic LED structure portion surrounding the first monolithic LED structure portion and having a sidewall surface that is tilted with respect to the mesa surface.

2. The method of claim 1, wherein, selectively removing a portion of the first semiconductor layer comprises removing a portion of the strained sub-layer and a corresponding portion of the first semiconductor sub-layer through an entire thickness of the strained sub-layer such that the bulk semiconductor layer surface is formed in the first semiconductor sub-layer.

3. The method of claim 1, wherein, The strain sublayer comprises In X Ga 1-X N, where 0 < X ≤ 1.

4. The method of claim 3, wherein, The strained sublayer includes a plurality of layers alternating between a first strained layer including GaN and a second strained layer including In X Ga 1-X N, where 0 < X < 1.

5. The method of claim 3, wherein, an In content X of the strained sub-layer decreases in a thickness direction away from the first semiconductor sub-layer.

6. The method of claim 1, wherein, the monolithic LED structure comprises: a second semiconductor layer provided over the mesa surface and the bulk semiconductor layer surface of the first semiconductor layer; an active layer comprising a plurality of Ill-nitride layers provided on the second semiconductor layer; a p-type semiconductor layer comprising a Ill-nitride formed on the active layer.

7. The method of claim 6, wherein, the second semiconductor layer comprises GaN or InYGai-YN, where 0 < Y < 1.

8. The method of claim 6, wherein, the active layer is configured to output light having a wavelength of at least 500 nm.

9. The method of claim 6, wherein, The active layer comprises at least one quantum well layer comprising In Z Ga 1-Z N having a third in-plane lattice constant which is at least equal to the second in-plane lattice constant, wherein 0 < Z < 1.

10. The method of claim 6, wherein a potential barrier is provided between a first portion of the p-type semiconductor layer covering the mesa surface and a second portion of the p-type semiconductor layer covering the bulk semiconductor surface, the potential barrier surrounding the first portion of the p-type semiconductor layer covering the mesa surface.

11. The method of any preceding claim, wherein, the strain relaxation temperature is at least 800 °C.

12. A light emitting diode (LED) precursor, comprising: A first semiconductor layer comprising a group III-nitride, the first semiconductor layer including a mesa structure extending from a main surface of the first semiconductor layer to define a growth surface, the growth surface including a host semiconductor surface and a mesa surface, wherein the first semiconductor layer comprises: A first semiconductor sublayer comprising a group III-nitride having a first in-plane lattice constant; and A strain-relaxed sublayer comprising a group III-nitride provided across the first semiconductor sublayer, wherein the strain-relaxed sublayer provides the mesa surface of the mesa structure, the mesa surface having a second in-plane lattice constant greater than the first in-plane lattice constant; and A monolithic LED structure has a growth surface of a first semiconductor layer such that the monolithic LED structure covers the mesa surface and the host semiconductor surface. The monolithic LED structure includes multiple group III-nitride layers and has the following characteristics: The first monolithic LED structure portion is provided above the surface of the platform; and The second monolithic LED structure portion surrounds the first monolithic LED structure portion and has a sidewall surface that is inclined relative to the table surface.

13. A method for forming an LED array precursor, comprising: (a) Forming a first semiconductor layer on a substrate, wherein forming the first semiconductor layer includes: A first semiconductor sublayer comprising a group III-nitride having a first in-plane lattice constant is formed on the surface of the substrate; and A strain sublayer comprising group III-nitride is formed on the side of the first semiconductor sublayer opposite to the substrate, wherein the strain sublayer at the interface between the strain sublayer and the first semiconductor sublayer is under compressive strain, such that the in-plane lattice constant of the strain sublayer at the interface is the first in-plane lattice constant. (b) Selectively removing a portion of the first semiconductor layer to expose the surface of the host semiconductor layer such that the first semiconductor layer defines a plurality of mesa structures, each mesa structure extending from the surface of the host semiconductor layer. (c) The strain sublayer is heated to a strain relaxation temperature, wherein the strain sublayer is relaxed by plastic deformation to form a strain relaxation sublayer, wherein each mesa structure has a mesa surface formed by a portion of the strain relaxation sublayer, the mesa surface having a second in-plane lattice constant, the second in-plane lattice constant being greater than the first in-plane lattice constant. (d) A monolithic LED structure is formed on the first semiconductor layer such that the monolithic LED structure covers the mesa surface and the main semiconductor surface, the monolithic LED structure comprising a plurality of group III-nitride layers, the monolithic LED structure having: Multiple first monolithic LED structural portions, each first monolithic LED structural portion being provided above its respective mesa surface; and Multiple second monolithic LED structural sections, each second monolithic LED structural section surrounding a first monolithic LED structural section and having sidewall surfaces inclined relative to their respective table surface.

14. An LED array precursor, comprising: A first semiconductor layer includes a plurality of mesa structures, each mesa structure extending from a main surface of the first semiconductor layer to define a growth surface, the growth surface including a main semiconductor surface and a plurality of mesa surfaces, wherein the first semiconductor layer includes: A first semiconductor sublayer comprising a group III-nitride having a first in-plane lattice constant; and A strain-relaxed sublayer comprising a group III-nitride provided across the first semiconductor sublayer, wherein the strain-relaxed sublayer provides the mesa surface for each mesa structure, the mesa surface having a second in-plane lattice constant greater than the first in-plane lattice constant; and A monolithic LED structure is provided on the growth surface of the first semiconductor layer such that the monolithic LED structure covers each mesa surface and the body semiconductor surface. The monolithic LED structure includes a plurality of group III-nitride layers and has the following characteristics: Multiple first monolithic LED structural portions, each first monolithic LED structural portion being provided above its respective mesa surface; and Multiple second monolithic LED structural sections, each second monolithic LED structural section surrounding a first monolithic LED structural section and having sidewall surfaces inclined relative to their respective table surface.

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