A wireless transceiver device with integrated common clock phase-locked loop

Abstract

The embodiment of the present application discloses a wireless transceiver. The device includes: a radio frequency receiver, a radio frequency transmitter, a first parallel-serial and serial-parallel converter, and a common clock phase-locked loop; wherein the radio frequency receiver, the radio frequency transmitter, the first parallel-serial and serial-parallel converter, and the common clock phase-locked loop are integrated in a radio frequency chip, the radio frequency receiver includes a down converter and an analog-to-digital converter, the radio frequency transmitter includes an up converter and a digital-to-analog converter, the first parallel-serial and serial-parallel converter is used to provide a digital interface with a baseband chip for the radio frequency chip; the common clock phase-locked loop is respectively coupled with the analog-to-digital converter, the digital-to-analog converter, and the first parallel-serial and serial-parallel converter, and is used to provide a clock signal for the analog-to-digital converter, the digital-to-analog converter, and the first parallel-serial and serial-parallel converter. The wireless transceiver can reduce the chip area and / or reduce the chip power consumption.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a wireless transceiver. Background Art

[0002] In wireless communication equipment, signal processing circuits can be divided into baseband (BB) signal processing circuits and radio frequency (RF) signal processing circuits. Baseband signals and RF signals have different frequency ranges and signal characteristics. Therefore, baseband signal processing circuits and RF signal processing circuits are often designed and manufactured separately. Since integrated circuit (IC) technology has become the mainstream circuit design and manufacturing process, baseband signal processing circuits can also be referred to as baseband integrated circuits (BBIC) or baseband chips, and RF signal processing circuits can also be referred to as radio frequency integrated circuits (RFIC) or RF chips.

[0003] Taking a mobile phone as an example, the RF chip and the baseband chip are usually two independently packaged chips in a mobile phone. The interface between the two chips is usually an analog interface, that is, the communication between the chips is based on the transmission of analog signals. Among them, the baseband chip has a built-in analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). Specifically, in the receiving direction, the analog RF signal is down-converted in the RF chip, the frequency is moved from the RF to the baseband, and the baseband analog signal is sent to the baseband chip, and analog-to-digital conversion, digital demodulation and decoding are implemented in the baseband chip. In the transmitting direction, the digital baseband signal is digitally encoded, modulated and converted into digital and analog in the baseband chip, and the baseband analog signal is sent to the RF chip, and the RF chip is up-converted, and the frequency is moved from the baseband to the RF to obtain an analog RF signal.

[0004] With the evolution of wireless communication technology, such as the commercialization of multiple input multiple output (MIMO) and carrier aggregation (CA), wireless communication devices need to integrate more and more receiving channels and transmitting channels, which will bring a large number of hardware connection requirements between RF chips and baseband chips. The need to integrate more input and output pins in the chip will make chip packaging design difficult on the one hand, and will also lead to a larger chip area and higher operating power consumption on the other hand. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a wireless transceiver to reduce chip area and / or reduce chip power consumption.

[0006] It should be understood that in the solution provided in the embodiment of the present application, the wireless transceiver can be a wireless communication device, or a part of a wireless communication device, such as an integrated circuit product such as a system chip or a communication chip. The wireless communication device can be a computer device that supports wireless communication functions.

[0007] Specifically, a wireless communication device can be a terminal such as a smartphone, or a wireless access network device such as a base station. Baseband chips are sometimes also called modems or baseband processing chips. RF chips are sometimes also called RF transceivers or RF processing chips. In physical implementation, a chip can be a chip with a separate package, or a bare die with input and output pins that is packaged in the same package or module with other dies or devices.

[0008] The wireless transceiver adopts a digital interface architecture. Compared with the traditional analog interface architecture, the radio frequency chip of the wireless transceiver integrates an analog-to-digital converter, a digital-to-analog converter, and a parallel-to-serial and serial-to-parallel converter. Therefore, the radio frequency chip and the baseband chip can communicate based on serial digital signals, reducing the large number of hardware wiring requirements brought by the traditional multi-channel multi-way parallel analog signals, thereby reducing the chip packaging area. In addition, since the analog-to-digital converter, the digital-to-analog converter, and the parallel-to-serial and serial-to-parallel converter each require their own clock signal, the wireless transceiver also integrates a common clock phase-locked loop, which can further reduce the chip area and reduce chip power consumption.

[0009] In a first aspect, an embodiment of the present invention provides a wireless transceiver device, including:

[0010] A radio frequency receiver, a radio frequency transmitter, a first parallel-to-serial and serial-to-parallel converter, and a common clock phase-locked loop;

[0011] The RF receiver, the RF transmitter, the first parallel-serial and serial-to-parallel converter, and the common clock phase-locked loop are integrated in a RF chip, the RF receiver includes a down-converter and an analog-to-digital converter, the RF transmitter includes an up-converter and a digital-to-analog converter, and the first parallel-serial and serial-to-parallel converter is used to provide a serial digital interface between the RF chip and a baseband chip;

[0012] The common clock phase-locked loop is coupled to the analog-to-digital converter, the digital-to-analog converter and the first parallel-to-serial and serial-to-parallel converter respectively, and is used to provide a common clock signal for the analog-to-digital converter, the digital-to-analog converter and the first parallel-to-serial and serial-to-parallel converter.

[0013] Since the analog-to-digital converter, the digital-to-analog converter and the parallel-to-serial and serial-to-parallel converters each require their own clock signal, a common clock phase-locked loop is also integrated in the wireless transceiver, which can further reduce the chip area and reduce the chip power consumption.

[0014] In combination with any of the above possible implementations, in a possible implementation, the wireless transceiver further includes a baseband chip, the baseband chip includes a second parallel-serial and serial-to-parallel converter, and the second parallel-serial and serial-to-parallel converter is used to provide a digital interface between the baseband chip and the radio frequency chip, so that the radio frequency chip and the baseband chip can communicate based on serial digital signals, reducing the large number of hardware wiring requirements brought by traditional multi-channel multi-path parallel analog signals, thereby reducing the chip packaging area.

[0015] In combination with any of the above possible implementations, in a possible implementation, the operating frequency of the serial digital interface between the first parallel-to-serial converter and the second parallel-to-serial converter adopts a customized digital interface protocol, and the rate of the digital signal transmitted by the differential signal line driven by the driver can be greater than 5,824Mbps or less than 1,248Mbps. After adopting the customized digital interface protocol, the rate of the digital signal transmitted by the differential signal line driven by the driver can be flexibly configured, reducing the selection restrictions on the frequency of the clock phase-locked loop. Based on the customized interface protocol, the serial data rate is no longer limited to the standard interface protocol, but can be flexibly determined according to the specific requirements of the system. The use of a customized digital interface transmission protocol can make the clock frequency selection of the parallel-to-serial converter (SerDes) less constrained and more flexible, so that it is easier to realize the multiplexing of the common clock signal with the DAC and ADC, reducing the difficulty and challenge of the design of the common clock phase-locked loop.

[0016] In combination with any of the above possible implementations, in one possible implementation, the common clock phase-locked loop includes a common phase-locked loop and a clock generator; the common phase-locked loop is used to generate a common clock signal; the clock generator is used to convert the common clock signal into multiple parallel clock signals, and output the multiple parallel clock signals to the analog-to-digital converter, the digital-to-analog converter and the first parallel-to-serial and serial-to-parallel converter respectively.

[0017] In an optional implementation, the clock generator may also include multiple parallel inverters for converting the input common clock signal into multiple outputs, and outputting the clock signals CLK_ADC, CLK_DAC and CLK_SDS to the ADC, DAC, SerDes, etc. in the RFIC. The isolation of each clock signal by the inverter can reduce the influence of the clock jitter of each module on the common clock phase-locked loop, as well as the mutual interference, and improve the stability of the clock signal.

[0018] In an optional implementation, the clock generator may include a clock divider, which is used to divide the common clock signal to generate a divided clock signal, and output the divided clock signal to the analog-to-digital converter, the digital-to-analog converter, or the first parallel-to-serial and serial-to-parallel converter. This not only achieves the isolation of the clock signals required by each module, which is equivalent to the effect of an inverter, but also further achieves the flexibility of the output clock signal, so that the frequencies of each clock signal can be different. Among them, in an optional implementation, the clock divider can be designed to be adjustable, and the clock divider includes a first divider, a second divider and a frequency divider selector; wherein the first divider and the second divider have different frequency division ratios, and the frequency divider selector is used to select the first divider or the second divider to divide the common clock signal. Thereby further improving the flexibility of the output frequency of the clock chip.

[0019] In an optional implementation, the common phase-locked loop may include a first sub-phase-locked loop, a second sub-phase-locked loop and a phase-locked loop selector; the phase-locked loop selector is used to select the first sub-phase-locked loop or the second sub-phase-locked loop to generate the common clock signal. Through the selection of the phase-locked loop selector, the speed of the rapid frequency switching of the common phase-locked loop can be improved, and the frequency coverage of the common phase-locked loop can also be improved.

[0020] In combination with any of the above possible implementations, in a possible implementation, the RF receiver includes multiple RF receiving channels, and the RF transmitter includes multiple RF transmitting channels; each of the RF receiving channels includes one of the analog-to-digital converters, and each of the RF transmitting channels includes one of the digital-to-analog converters.

[0021] Among them, the RF transmission channel and the RF receiving channel as well as the TL and RL of the SerDes can each include a corresponding local frequency divider. For example, each of the RF receiving channels can include a local analog-to-digital frequency divider, and the local analog-to-digital frequency divider in the RF receiving channel divides the signal output by the common clock phase-locked loop and provides it to the analog-to-digital converter in the RF receiving channel. After the local analog-to-digital frequency divider (DIVADC) is introduced into multiple RF receiving channels, the ADC of each RF receiving channel can be provided with the clock signal required by each RF receiving channel, so that each RF receiving channel can work in different bandwidth modes, increasing the flexibility of the RF receiver to receive multiple signals. Each of the RF transmission channels can also include a local digital-to-analog frequency divider, and the local digital-to-analog frequency divider in the RF transmission channel divides the signal output by the common clock phase-locked loop and provides it to the digital-to-analog converter in the RF transmission channel. After the local digital-to-analog frequency divider is introduced into multiple RF transmission channels, the DAC of the RF transmission channel can be provided with the clock signal required by each RF transmission channel, so that the RF transmission channel can work in different bandwidth modes, increasing the flexibility of multi-channel transmission signals. The TL and RL of SerDes can each include a local divider, which divides the signal output by the common clock phase-locked loop through the local divider to obtain the clock signal required by each channel, thereby increasing the flexibility of the clock signal required by the transmitting and receiving channels, so that each channel can operate in different bandwidth modes.

[0022] The multiple RF receiving channels may include a first RF receiving channel, a second RF receiving channel, a third RF receiving channel and a fourth RF receiving channel, the first RF receiving channel is used to receive a first carrier signal, the second RF receiving channel is used to receive a second carrier signal, the third RF receiving channel is used to receive a third carrier signal, and the fourth RF receiving channel is used to receive a fourth carrier signal; the multiple RF transmitting channels may include a first RF transmitting channel and a second RF transmitting channel; the first RF transmitting channel is used to transmit a fifth carrier signal, and the second RF transmitting channel is used to transmit a sixth carrier signal; the first carrier signal, the second carrier signal, the third carrier signal and the fourth carrier signal together constitute an inter-band downlink carrier aggregation; the fifth carrier signal and the sixth carrier signal together constitute an intra-band non-continuous uplink carrier aggregation or an inter-band uplink carrier aggregation. The first carrier signal and the first carrier signal may also be two non-continuous carriers in the same frequency band A, the third carrier signal may be a carrier of frequency band B, and the fourth carrier signal may be a carrier of frequency band C. Among them, the first carrier signal and the second carrier signal can also be two non-continuous carriers in the same frequency band A, and the third carrier signal and the fourth carrier signal can be two non-continuous carriers in the frequency band B. Further, the multiple RF receiving channels can also include a fifth RF receiving channel, a sixth RF receiving channel, and a seventh RF receiving channel. The fifth RF receiving channel is used to realize the reception and processing of the seventh carrier, the sixth RF receiving channel is used to realize the reception and processing of the eighth carrier signal, and the seventh RF receiving channel is used to realize the reception and processing of the ninth carrier signal; the seventh carrier signal, the eighth carrier signal and the ninth carrier signal have the same frequency band characteristics as the first carrier signal, and the seventh carrier signal, the eighth carrier signal, the ninth carrier signal and the first RF signal are received from different antennas, so that the seventh RF signal, the eighth RF signal and the ninth RF signal and the first RF signal constitute the reception of a 4X4 MIMO signal. The RF chip realizes the characteristics of CA+MIMO.

[0023] In combination with any of the above possible implementations, in one possible implementation, the RF receiving channel may include an in-phase receiving branch and an orthogonal receiving branch, and the in-phase receiving branch and the orthogonal receiving branch each include an analog-to-digital converter; the local analog-to-digital divider in the RF receiving channel is used to provide the same clock signal for the analog-to-digital converter in the in-phase receiving branch and the analog-to-digital converter in the orthogonal receiving branch in the RF receiving channel.

[0024] The RF transmission channel may include an in-phase transmission branch and an orthogonal transmission branch, and the in-phase transmission branch and the transmission and receiving branch each include a digital-to-analog converter; the local digital-to-analog divider in the RF transmission channel is used to provide the same clock signal for the digital-to-analog converter in the in-phase transmission branch and the digital-to-analog converter in the orthogonal transmission branch in the RF transmission channel.

[0025] In this way, an RF receiving channel or an RF transmitting channel only needs one local frequency divider to provide clock signals for the ADC or DAC of both IQ channels in the same RF transceiver channel, thereby further saving frequency divider resources and ensuring the consistency of the clock signals of the ADC or DAC of both IQ channels, and ensuring the consistency of the bandwidth processing of the two IQ channels.

[0026] In combination with any of the above possible implementations, in a possible implementation, the division ratio of the clock divider, the local modulus divider, the local modulus divider, and the local divider in the TL and RL of the SerDes can be a positive integer, or the sum of a positive integer and a simple decimal, and the simple decimal is a negative integer power of 2. Based on the above division ratio, the complexity of circuit implementation and implementation cost factors such as power consumption and area are reduced.

[0027] In combination with any of the foregoing possible implementations, in a possible implementation, the wireless transceiver device further includes:

[0028] A radio frequency front-end device, the radio frequency front-end device includes a low noise amplifier; the radio frequency front-end device is located between the radio frequency chip and the antenna; the radio frequency chip also includes a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor, the source of the PMOS is used to couple the power supply end, and the source of the NMOS is used to couple the ground end; the drain of the PMOS is coupled with the drain of the NMOS as an output end, which is used to couple the down converter; the gate of the PMOS is coupled with the gate of the NMOS as an input end, which is used to couple the low noise amplifier. The PMOS and the NMOS are used to achieve the transition between the LNA outside the radio frequency chip and the mixer inside the radio frequency chip. On the basis of the signal amplification by the low noise amplifier of the radio frequency front-end device, the gain of the radio frequency signal of the system can be further improved, and the flexibility of the system power control can be improved.

[0029] When the RF FEM integrates the PA, the transmitter in the RF chip can also integrate the transmit amplifier (TX_AMP) before the mixer to achieve the transition between the mixer and the off-chip PA. The receive amplifier (RX_AMP) and the transmit amplifier (TX_AMP) can further adjust the gain of the system's RF signal based on the off-chip RF FEM basic PA and improve the flexibility of the system's power control.

[0030] In combination with any of the above possible implementations, in a possible implementation, the RF chip may further include a local oscillator phase-locked loop for providing the local oscillator signal required for frequency conversion to the up-converter and / or the down-converter. Considering the huge difference in requirements and performance between the common clock phase-locked loop that provides clock signals for ADC, DAC, and SerDes and the phase-locked loop that provides local oscillator signals for the RF transceiver channel, from the perspective of system design, using a local oscillator phase-locked loop to provide local oscillator signals for the RF transceiver channel alone will make the system's clock signal design more efficient and performant.

[0031] Furthermore, the local oscillator phase-locked loop may further include a first local oscillator phase-locked loop (LO_PLL1) and a second local oscillator phase-locked loop (LO_PLL2). The first local oscillator phase-locked loop is used to provide a local oscillator signal for the downconverter of the RF receiving channel, and the second local oscillator phase-locked loop is used to provide a local oscillator signal for the upconverter of the RF transmitting channel. Furthermore, the first local oscillator phase-locked loop and the second local oscillator phase-locked loop are used to provide local oscillator signals for the mixer mix of the RF receiving channel and the RF transmitting channel, respectively. Different requirements of the RF transceiver channel for the phase-locked loop can be met, and the performance of the RF chip can be further optimized.

[0032] Furthermore, the reference signals of the common clock phase-locked loop, the first local oscillator phase-locked loop and the second local oscillator phase-locked loop can be provided by the same reference clock signal CLK_REF, and the reference signal CLK_REF can be input from the outside of the RF chip through the same RF chip pin, thereby reducing the control timing inside the chip and the synchronization error of the receiving and transmitting signals.

[0033] In combination with any of the above possible implementations, in a possible implementation, the wireless transceiver device further includes a power chip, the power chip is coupled to the radio frequency chip, the power chip supplies power to the radio frequency chip, and provides a reference clock signal for the common clock phase-locked loop. In this way, the clock reference signal provided by the power chip can coordinate the timing of the power chip and the radio frequency chip, synchronize the power on and off of the entire chipset, and optimize the function of the wireless transceiver device. The power chip can also be called a power management chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a wireless communication system provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of carrier configuration of a wireless communication system provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a deployment example of downlink inter-band carrier aggregation provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of a wireless transceiver device provided in an embodiment of the present application;

[0038] Figure 5A A schematic diagram of a SerDes structure provided in an embodiment of the present application;

[0039] Figure 5B A schematic diagram of receiving and sending signals based on a SerDes interface provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of a common clock phase-locked loop provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of another wireless transceiver device provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of a receiver architecture provided in an embodiment of the present application;

[0043] Fig. 9 A schematic diagram of a local frequency divider based on an orthogonal architecture provided in an embodiment of the present application;

[0044] Fig.10 A schematic diagram of a radio frequency receiver and a radio frequency transmitter provided in an embodiment of the present application;

[0045] Fig.11 A schematic diagram of a radio frequency chip provided in an embodiment of the present application;

[0046] Fig.12 A schematic diagram of a phase-locked loop provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] In wireless communication systems, devices can be divided into devices that provide wireless network services and devices that use wireless network services. Devices that provide wireless network services refer to those devices that make up the wireless communication network, which can be referred to as network equipment or network elements. Network equipment usually belongs to operators (such as China Mobile and Vodafone) or infrastructure providers (such as tower companies), and these manufacturers are responsible for operation or maintenance. Network equipment can be further divided into radio access network (RAN) equipment and core network (CN) equipment. Typical RAN equipment includes base stations (BS).

[0049] It should be understood that a base station may sometimes also be referred to as an access point (AP) or a transmission reception point (TRP). Specifically, a base station may be a generation Node B (gNB) in a 5G new radio (NR) system or an evolutionary Node B (eNB) in a 4G long term evolution (LTE) system. Depending on the physical form or transmission power of the base station, the base station may be divided into a macro base station or a micro base station. A micro base station is sometimes also referred to as a small base station or a small cell.

[0050] Devices that use wireless network services are usually located at the edge of the network and can be referred to as terminals. Terminals can establish connections with network devices and provide users with specific wireless communication services based on the services of network devices. It should be understood that due to the closer relationship between terminals and users, they are sometimes also referred to as user equipment (UE) or subscriber units (SU). In addition, compared to base stations that are usually placed in fixed locations, terminals often move with users and are sometimes referred to as mobile stations (MS). In addition, some network devices, such as relay nodes (RN) or wireless routers, are sometimes considered terminals because they have UE identities or belong to users.

[0051] Specifically, the terminal can be a mobile phone, a tablet computer, a laptop computer, a wearable device (such as a smart watch, a smart bracelet, a smart helmet, and smart glasses), and other devices with wireless access capabilities, such as smart cars, various Internet of Things (IOT) devices, including various smart home devices (such as smart meters and smart appliances) and smart city devices (such as security or monitoring equipment, smart road traffic facilities), etc.

[0052] For ease of description, this application will take a base station and a terminal as an example to describe in detail the technical solution of the embodiments of the present application.

[0053] Figure 1 A schematic diagram of the structure of a wireless communication system provided in an embodiment of the present application. Figure 1 As shown, the wireless communication system includes a terminal and a base station. According to the different transmission directions, the transmission link from the terminal to the base station is recorded as an uplink (UL), and the transmission link from the base station to the terminal is recorded as a downlink (DL). Similarly, data transmission in the uplink can be simply recorded as uplink data transmission or uplink transmission, and data transmission in the downlink can be simply recorded as downlink data transmission or downlink transmission.

[0054] In this wireless communication system, a base station can provide communication coverage for a specific geographical area through an integrated or external antenna device. One or more terminals located within the communication coverage of the base station can access the base station. A base station can manage one or more cells. Each cell has an identification, which is also called a cell identity (cell ID). From the perspective of wireless resources, a cell is a combination of downlink wireless resources and uplink wireless resources (optional) paired with it.

[0055] It should be understood that the wireless communication system may comply with the wireless communication standards of the third generation partnership project (3GPP), or may comply with other wireless communication standards, such as the wireless communication standards of the 802 series (such as 802.11, 802.15, or 802.20) of the Institute of Electrical and Electronics Engineers (IEEE). Figure 1Although only one base station and one terminal are shown in the figure, the wireless communication system may also include other numbers of terminals and base stations. In addition, the wireless communication system may also include other network devices, such as core network devices.

[0056] The terminal and the base station should be aware of the predefined configuration of the wireless communication system, including the radio access technology (RAT) supported by the system and the wireless resource configuration specified by the system, such as the basic configuration of the radio frequency band and carrier. The carrier is a frequency range that complies with the system regulations. This frequency range can be determined by the center frequency of the carrier (referred to as the carrier frequency) and the bandwidth of the carrier. These system predefined configurations can be part of the standard protocol of the wireless communication system, or determined through interaction between the terminal and the base station. The content of the relevant standard protocol may be pre-stored in the memory of the terminal and the base station, or embodied in the hardware circuit or software code of the terminal and the base station.

[0057] In the wireless communication system, the terminal and the base station support one or more of the same RAT, such as 5G NR, 4G LTE, or RAT of future evolution systems. Specifically, the terminal and the base station use the same air interface parameters, coding scheme, modulation scheme, etc., and communicate with each other based on the wireless resources specified by the system.

[0058] Figure 2 A schematic diagram of carrier configuration of a wireless communication system provided in an embodiment of the present application. In the wireless communication system, the base station configures two carrier sets for the terminal, which are respectively recorded as a first carrier set and a second carrier set. The first carrier set can be used for downlink carrier aggregation, and the second carrier set can be used for uplink carrier aggregation. The carriers included in the two carrier sets can be partially the same carriers or all the same carriers.

[0059] like Figure 2 As shown, the first carrier set includes 6 component carriers (CCs), which are denoted as CC 1 to CC 6. The second carrier set includes 4 component carriers, including CC 1 to CC 4. It should be understood that the number of CCs included in the first carrier set and the second carrier set is for illustrative purposes only. In the embodiment of the present application, the first carrier set and the second carrier set may also include other numbers of CCs. These CCs can be continuous or non-continuous in the frequency domain. Different CCs can be in the same frequency band, which can correspond to intra-band carrier aggregation (intra-band CA). Different CCs can also be in different frequency bands, which can correspond to inter-band carrier aggregation (inter-band CA).

[0060] Figure 3A schematic diagram of a deployment example of downlink inter-band carrier aggregation (DLCA) provided in an embodiment of the present application. As shown in the figure, the system allocates a carrier unit to the terminal in each of the three frequency bands Band1 (2110MHz-2170MHz), Band3 (1805MHz-1880MHz) and Band7 (2110MHz-2170MHz), which are CC0, CC1 and CC2 respectively. Assuming that the bandwidths of these three carrier units are 20MHz respectively, through the above inter-band carrier aggregation deployment, the terminal user can obtain a total of 60MHz of spectrum resources.

[0061] In order to support the above-mentioned inter-band carrier aggregation reception application, the terminal needs to have the ability to simultaneously receive multiple carrier components. Since multiple carrier components are located in different frequency bands, they are limited by the frequency bandwidth characteristics of the RF front-end device and the RF receiver circuit, and usually multiple parallel RF receiving channels are required to receive each carrier component respectively. Figure 3 Taking the carrier aggregation scenario of three frequency bands as an example, three RF receiving channels need to work simultaneously to receive three carrier units respectively. For carrier aggregation scenarios with more frequency bands, the number of channels of the RF receiver also needs to be increased accordingly. Similarly, in order to meet the transmission application that supports inter-band carrier aggregation, the wireless RF chip needs to have the ability to transmit multiple carrier units simultaneously, and multiple RF transmission channels also need to work simultaneously to transmit multiple carrier units respectively.

[0062] Another development trend of wireless communication is to use multi-antenna technology to improve communication performance, that is, to use MIMO technology to perform wireless transmission through multiple antennas at the same time, thereby improving the throughput of wireless communication. For wireless terminal devices that support MIMO technology, it is necessary to provide multiple antennas, as well as RF receivers and RF transmission channels corresponding to the number of antennas. For example, for a downlink 4×4 MIMO application scenario, on the mobile terminal side, even if there is only one carrier unit, it may be necessary to provide four receiving antennas and RF receiving channels corresponding to each antenna.

[0063] Figure 4 A schematic diagram of a wireless transceiver provided in an embodiment of the present application. It should be understood that Figure 4 Although the wireless transceiver in the figure only shows one RF receiving channel and one RF transmitting channel, the wireless transceiver in the embodiment of the present application is not limited to this. The wireless transceiver may also include two or more RF receiving channels and RF transmitting channels.

[0064] refer to Figure 4The wireless transceiver includes a radio frequency chip; the radio frequency chip includes a radio frequency receiver (RX10), a radio frequency transmitter (TX20), a common clock phase-locked loop (CLKPLL) and a serializer / deserializer (SerDes). The radio frequency receiver (RX10) may include a radio frequency receiving channel (RX101), the first radio frequency receiving channel (RX101) includes a down converter (Down_MIX) and an analog-to-digital converter (ADC), the down converter is used to perform down-conversion processing on the received radio frequency signal; the analog-to-digital converter is used to convert the down-converted signal into a digital signal.

[0065] The RF receiving channel may also include a receiving filter (RX_Filter), which is located between the down-converter and the digital-to-analog converter. The receiving filter filters the signal after the down-conversion processing by the down-converter and then provides it to the analog-to-digital converter, so as to suppress interference signals outside the receiving channel and improve the signal sensitivity of the receiving channel.

[0066] The radio frequency transmitter also includes a radio frequency transmission channel (TX 201), which includes a digital-to-analog converter (DAC) and a transmission mixer (TX_MIX), wherein the DAC is used to convert a received digital signal into an analog signal, and the transmission mixer performs up-conversion processing on the analog signal converted by the DAC and then transmits it;

[0067] The RF transmission channel may also include a transmission filter (TX_Filter), which is located between the transmission mixer and the digital-to-analog converter. The transmission filter filters the analog signal converted by the digital-to-analog converter and then provides it to the transmission mixer for up-conversion processing, so as to suppress out-of-band harmonics of the transmission channel.

[0068] The transmitting filter and the receiving filter may have a gain amplification function, and may amplify the signal gain while filtering the signal. The gain of the transmitting filter and the receiving filter may also be designed to be adjustable, so as to achieve flexible configuration of the signal gain.

[0069] The serial-serial converter (SerDes) is used to realize digital interface communication between the radio frequency chip and the external baseband chip. Due to the use of SerDes, the radio frequency chip can achieve a higher transmission rate with the same number of chip pins, thereby reducing the area of ​​the radio frequency chip.

[0070] The common clock phase-locked loop provides corresponding clock signals for the ADC, the DAC and the serial-to-serial converter (SerDes) interface. The clock signal CLK_ADC is provided for the ADC, the clock signal CLK_DAC is provided for the DAC, and the clock signal CLK_SDS is provided for the SerDes. By sharing the clock phase-locked loop, the number of phase-locked loops inside the RF chip can be reduced, thereby further reducing the area and power consumption of the RF chip. In addition, since the number of clock phase-locked loops is reduced, the mutual interference caused by the clock signal inside the system is also greatly reduced, further improving the performance of the RF chip.

[0071] Furthermore, the wireless transceiver may also include a baseband chip. A digital interface corresponding to the RF chip's serial-serial-to-parallel converter (SerDes) may also be integrated inside the baseband chip, that is, the baseband chip's serial-serial-to-parallel converter (SerDes). The pins of the SerDes in the baseband chip and the pins of the SerDes in the RF chip are coupled to each other in a one-to-one correspondence, and are used to realize the transmission of digital signals between the RF chip and the baseband chip. Due to the introduction of the SerDes, the signals between the RF chip and the baseband chip are on the same pin, which can greatly improve the communication rate of the chipset and further improve the channel bandwidth processed by the wireless transceiver.

[0072] Figure 5A A schematic diagram of a SerDes structure provided for an embodiment of the present application. Taking the SerDes inside the RF chip as an example, the SerDes includes multiple transmit channels (TL, Transmit Lane) and receive channels (RL, Receive Lane). The SerDes transmit channel (TL, Transmit Lane) of the RF chip serializes the received parallel data and sends it out, and the receive channel (RL, Receive Lane) receives the serially transmitted data and converts it into parallel data. The working mechanism of the SerDes in the BBIC is the same as that of the RF chip. The common phase-locked loop in the RFIC provides the required clock signal for each TL and RL.

[0073] Figure 5BA schematic diagram of receiving and sending signals based on a SerDes interface is provided for an embodiment of the present application. Specifically, in the direction of the RFIC receiving link, the (SerDes TL) transmitting channel in the RFIC obtains serial data after passing the received parallel data through a parallel to serial converter (P2S), and the serial data drives a group of differential signal lines (DS_P, DS_N) through a driver (DRV, Driver) and transmits it to the BBIC. On the BBIC side, the SerDes receiving channel (RL, Receive Lane) receives the serially transmitted data, performs clock data recovery (CDR, Clock Data Recovery), and after processing through a serial to parallel converter (S2P), the parallel data is obtained and then decoded and unpacked. In the direction of the RFIC transmitting link, the working mechanism of SerDes is similar to that of the receiving link, but the direction is reversed, that is, the data is transmitted from the BBIC to the RFIC. The common phase-locked loop in the RFIC provides the required clock signal CLK_SDS for the parallel-to-serial converter (P2S), and the BBIC provides the required clock signal CLK_BB for the CDR and S2P.

[0074] Furthermore, the data and command signal transmission between RFIC and BBIC through the serial-serial to serial-to-parallel converter (SerDes) interface can adopt a customized interface protocol instead of a standard interface protocol, such as the MIPI MPHY protocol, the JEDEC JESD204B protocol, the DDR protocol, etc. The use of a standard interface protocol facilitates the interconnection and intercommunication between RFIC and BBIC chips from different manufacturers. However, the above-mentioned various standard interface protocols have certain requirements for the serial data rate of SerDes, which limits the frequency of the SerDes working clock. Under the standard interface protocol, the rate of the serial digital signal output by the driver driving the differential signal line is fixed. For example, under MIPI MPHY, the rate of the digital signal transmitted by the differential signal line driven by the driver is only a limited number of specific rates between 1,248 to 5,824 Mbps, and the SerDes clock rate is generally equal to or half of the rate of the data signal, thereby correspondingly limiting the choice of the frequency of the common clock phase-locked loop. After adopting the customized digital interface protocol, the rate of the digital signal transmitted by the differential signal line driven by the driver can be greater than the flexible configuration, which can be greater than 5,824Mbps or less than 1,248Mbps, reducing the selection restrictions on the frequency of the clock phase-locked loop. Based on the customized interface protocol, the serial data rate is no longer limited by the standard interface protocol, but can be flexibly determined according to the specific requirements of the system. The use of a customized digital interface transmission protocol can make the clock frequency selection of the parallel-to-serial and serial-to-parallel converter (SerDes) less constrained and more flexible, making it easier to realize the multiplexing of clock signals with DAC and ADC, reducing the difficulty and challenges of clock phase-locked loop design.

[0075] Furthermore, one or more radio frequency front ends (RF FEM) may be further included between the RFIC and the antenna. The RF front end is located between the RFIC and the antenna, and is used to improve the quality of the received signal and the transmitted signal of the wireless transceiver. When the RF chip needs to integrate multiple receiving channels and transmitting channels, such as a RF chip that supports carrier aggregation or MIMO, the signal-to-noise ratio and transmission power of the transmission signals of multiple parallel receiving channels and transmitting channels need to meet higher design index requirements. Therefore, relying solely on the circuit integrated inside the RF chip itself will not be able to meet the design challenges of multiple channels. For cost and area considerations, the RF front end is not an ideal choice in wireless transceivers, especially mobile terminal chips, especially for low noise amplifiers (Low noise amplifier, LNA), which generally adopt an on-chip integrated solution. However, for multi-channel RF chips, the benefits brought by the RF front end solution will be greater than its cost and area disadvantages.

[0076] The RF front end of this embodiment may include an integrated low noise amplifier (LNA) module. The LNA module may include an LNA amplifier circuit to amplify the received antenna signal, thereby reducing the signal loss of the transmission path, thereby further improving the transmission quality of the signal from the antenna end to the RF chip. The RF front end of this embodiment may also include an integrated power amplifier (PA) module, which may include a PA power amplifier using a process that is more suitable for high power, such as a gallium arsenide (GaAs) process or a gallium nitride (GaN) process, and may further include a filter and a switch, thereby further achieving high-quality power amplification of the RF chip output signal, reducing inter-channel interference, thereby further improving the output power and quality of the RFIC's transmission signal, and further improving the system performance of the transmission system of the present invention.

[0077] The PA module and the LNA module can be integrated in different RF front-ends or the same RF front-end, and can be flexibly designed according to the specific design requirements of the system. Generally speaking, since the PA module and the LNA module respectively realize the functions of transmitting and receiving signals, in order to improve the isolation between the transmitter and the receiver, the PA module and the LNA module can be integrated in different RF front-end devices.

[0078] Furthermore, when the LNA is integrated in an off-chip RF FEM, the receiver in the RFIC may also integrate a receiving amplifier (RX_AMP) at the front end of the mixer to achieve the transition between the LNA outside the RF chip and the mixer inside the RF chip. The RX_AMP may include a simple amplifier circuit. For example, the simple amplifier circuit may be a P-channel metal oxide semiconductor transistor (PMOS) and an N-channel metal oxide semiconductor transistor (NMOS) connected in series, the source of the PMOS being used to couple the power supply signal, and the source of the NMOS being used to couple the ground (GND). The drain of the PMOS is coupled to the drain of the NMOS as an output terminal for coupling the down converter. The gates of the PMOS and the NMOS are used as input terminals for coupling the RF signal amplified by the off-chip LNA. Similar to the LNA, when the RF FEM integrates the PA, the transmitter in the RF chip may also integrate a transmitting amplifier (TX_AMP) before the mixer to achieve the transition between the mixer and the off-chip PA. Based on the RFFEM outside the chip, the receiving amplifier (RX_AMP) and the transmitting amplifier (TX_AMP) can further adjust the gain of the system's RF signal and improve the flexibility of the system's power control.

[0079] Furthermore, for application scenarios or systems that do not require high signal transmission performance, such as wireless hotspots (WIFI) or the Internet of Things (IOT) or some low-cost mobile phone terminals that do not require high communication quality, part or all of the LNA or PA can also be integrated in the RFIC to reduce the number of RF front-end components, thereby reducing the cost and area of ​​the wireless transceiver and improving its competitiveness.

[0080] Furthermore, the LNA and PA may share the same antenna to achieve transceiver duplex or frequency division duplex.

[0081] Furthermore, the RF chip in this embodiment can also integrate some digital sub-systems (DSS), such as digital front end (DFE) and interface unit (INTF). DFE includes a receiving digital front end and a transmitting processing front end. This part of the DFE mainly completes the conversion of the data sampling rate, as well as the calibration and compensation operations related to the non-ideal characteristics of the RF circuit, which can further improve the performance of the RF chip. INTF mainly performs encoding, packaging and other processing. The data processed by INTF is then sent to the serial-to-serial converter (SerDes) to further improve the reliability of transmission. The common clock phase-locked loop can also provide a clock signal CLK_DIG for the DFE and INTF, thereby further reducing the area and power consumption of the RF chip.

[0082] Furthermore, the clock signal of the SerDes in the RFIC can also come from an external BBIC chip. Compared with the solution of designing an independent SerDes phase-locked loop inside the RFIC, this SerDes clock signal solution can save clock resources, thereby reducing the area and power consumption of the RFIC. However, since the SerDes clock signal comes from an external chip, the frequency of the clock signal is limited, and the transmission rate of the signal between the RFIC and the BBIC chip is limited, so it cannot meet the transmission requirements of the RFIC and BBIC chips with higher speeds and more channels.

[0083] Furthermore, the common clock phase-locked loop in the RFIC requires a clock reference signal (Clock reference signal, CLK_REF) as a reference signal to generate an output clock signal. The wireless communication device may include a power management integrated circuit (PMIC). In addition to providing power for the RFIC and BBIC, the PMIC can also provide CLK_REF for the common clock phase-locked loop. The wireless communication device may also include an external clock source such as a crystal oscillator (Crystal) to provide CLK_REF for the common clock phase-locked loop. An oscillator, such as a resistor-capacitor (RC) oscillator, may also be integrated inside the RFIC to generate CLK_REF. Compared with other clock reference signal generation methods, the clock reference signal provided by the PMIC can coordinate the timing of the power management chip and the RF chip, synchronize the power on and off of the entire chipset, and optimize the function of the chipset.

[0084] This embodiment integrates the SerDes, DAC and ADC into the RFIC, realizes the digital interface communication between the RFIC and the BBIC, and improves the communication rate between the chips with the same number of pins. At the same time, this embodiment uses the same common clock phase-locked loop to provide clock signals for the ADC, DAC and SerDes integrated in the RFIC, realizes the multiplexing of the phase-locked loop, and reduces the area and power consumption of the entire RF chip.

[0085] Figure 6 A schematic diagram of a common clock phase-locked loop provided in an embodiment of the present application. Based on the above embodiment, the common clock phase-locked loop (CLKPLL) may further include a common phase-locked loop (PUB_PLL) and a clock generator (CLKGEN).

[0086] Specifically, the common phase-locked loop is used to output a common clock signal (PUB_CLK) to a clock generator. The clock generator can also perform one-way to multiple-way conversion on the common clock signal to generate corresponding clock signals CLK_ADC, CLK_DAC and CLK_SDS output to various modules such as ADC, DAC, SerDes, etc. in the RFIC.

[0087] For example, the clock generator can have a pass-through mode, outputting the same common clock signal directly to each module in the RFIC, such as ADC, DAC, SerDes, etc., as the corresponding clock signals CLK_ADC, CLK_DAC and CLK_SDS of each module. At this time, the clock signals required by each module are exactly the same.

[0088] The clock generator may also include multiple parallel inverters for converting the input common clock signal into multiple outputs, and outputting the clock signals CLK_ADC, CLK_DAC and CLK_SDS to the ADC, DAC, SerDes and other clock signals in the RFIC. The isolation of each clock signal by the inverter can reduce the influence of the clock jitter of each module on the common clock phase-locked loop, as well as the mutual interference, and improve the stability of the clock signal.

[0089] The clock generator CLKGEN may also include multiple clock dividers working in parallel. The clock generator CLKGEN divides the input common clock signal, and then outputs the clock signals CLK_ADC, CLK_DAC and CLK_SDS required by each module such as ADC, DAC, SerDes, etc. in the RFIC after the division. This not only achieves the isolation of the clock signals required by each module, which is equivalent to the effect of an inverter, but also further realizes the flexibility of the output clock signal, so that the frequencies of each clock signal can be different.

[0090] Specifically, taking a clock divider with four channels working in parallel as an example, the clock generator includes an ADC clock divider DADC, a DAC clock divider DDAC, a digital subsystem clock divider DDIG, and a serial-to-serial converter (SerDes) clock divider DSDS. It should be understood that Figure 6 Although CLKGEN in FIG. 1 shows only four parallel clock dividers, the present application is not limited thereto, and CLKGEN may also include other numbers of clock dividers other than four. Assume that the frequency of the common clock signal generated by the common phase-locked loop is f CLK_PLL .

[0091] Among them, DADC can generate the clock signal CLK_ADC required by the ADC on the RFIC. Assume that the frequency of CLK_ADC is f CLK_ADC , the division ratio of DADC is N DADC , then the following relationship exists:

[0092]

[0093] Among them, DDAC can generate the clock signal CLK_DAC required by the DAC on the RFIC. Assume that the frequency of CLK_DAC is f CLK_DAC , the division ratio of DDAC is N DDAC , then the following relationship exists:

[0094]

[0095] Among them, DDIG can generate the clock signal CLK_DIG required by multiple digital subsystems on RFIC. In the digital subsystem, the CLK_DIG signal is further converted from single-channel to multi-channel to provide the required clock signal for DFE and INTF in the digital subsystem.

[0096] Assume that the frequency of CLK_DAC is f CLK_DIG , the division ratio of DDIG is N DDIG , then the following relationship exists:

[0097]

[0098] Among them, DSDS can generate the clock signal CLK_SDS required by the SerDes on the RFIC. The clock signal CLK_SDS is sent to the SerDes and provided to the clock signals required by each transmitting channel (TL) and receiving channel (RL) in the SerDes. Assuming that the frequency of CLK_SDS is f CLK_SDS , the division ratio of DSDS is N DSDS , then the following relationship exists:

[0099]

[0100] In summary, the clock signals of different frequencies required by the ADC, DAC, digital subsystem, and serial-to-serial converter (SerDes) on the digital interface RFIC all come from the same common clock signal (PUB_CLK). The clock phase-locked loop CLKPLL uses CLK_REF as the reference clock, and the common phase-locked loop (PUB_PLL) generates a frequency of f CLK_PLL The common clock signal (PUB_CLK) is generated by the clock generator CLK_GEN for each specific clock divider to generate each required clock signal.

[0101] In summary, the clock signals required by the ADC, DAC, digital subsystem, and serial-to-serial converter (SerDes) can all come from the common clock signal (PUB_CLK).

[0102] Furthermore, the division ratio of each clock divider in CLKGEN often needs to be designed as a variable divider based on the clock frequency requirements of the ADC, DAC, digital subsystem, and serial-to-serial converter (SerDes), etc., adding the function of dynamic adjustable division ratio.

[0103] Specifically, the variable frequency divider may include a plurality of frequency dividers with different frequency division ratios connected in parallel and a frequency division selector. The frequency divider with a specific frequency division ratio is selected by the frequency division selector to realize the function of variable frequency division ratio of the frequency divider.

[0104] For example, a variable frequency divider may include a first frequency divider, a second frequency divider and a frequency division selector; the frequency division ratios of the first frequency divider and the second frequency divider are different; the first frequency divider and the second frequency divider are connected in parallel; the frequency division selector is used to select the first frequency divider or the second frequency divider to output the clock signal after the frequency division processing; thereby realizing the function of adjustable frequency division ratio of the variable frequency divider.

[0105] Among them, the frequency division selector can be a single-pole double-position switch, located at the input or output of the first frequency divider and the second frequency divider, and by switching the switch, the frequency division processing of the common clock signal by the first frequency divider or the second frequency divider is selected. The frequency division selector can also be two single-pole switches, respectively located at the input or output of the first frequency divider and the second frequency divider, and by switching the switch, the frequency division processing of the common clock signal by the first frequency divider or the second frequency divider is selected. The frequency division selector can also be a power supply controller, which realizes the frequency division processing of the common clock signal by the first frequency divider or the second frequency divider by adjusting the power supply selection of the first frequency divider and the second frequency divider.

[0106] Based on the variable frequency division ratio CLKGEN, the common phase-locked loop outputs a common clock signal (PUB_CLK) with a clock signal frequency f CLK_PLL It can be designed to be a fixed frequency, so as to avoid a module, such as ADC, affecting other modules, such as DAC or SerDes, from changing the working clock frequency. Each module can change its own working clock frequency by adjusting the division ratio of the corresponding clock divider in the clock generator CLKGEN.

[0107] With the help of the clock divider, the common clock signal (CLK_PUB) generated by the common phase-locked loop can be divided by different division ratios and provided to the DAC, ADC, SerDes and digital subsystems respectively, so that the DAC, ADC, SerDes and digital subsystems can have different clock frequencies. The introduction of the multi-way divider reduces the system's requirements for the common clock signal of the DAC, ADC, SerDes and digital subsystems, reduces the interdependence between these modules, and further improves the flexibility of system design.

[0108] The public phase-locked loop (PUB_PLL) can be an analog phase-locked loop or a digital phase-locked loop. Taking into account the different implementation methods of the phase-locked loop, the frequency range covered may be limited, and the frequency switching speed may also be limited. In order to further increase the performance and flexibility of the clock phase-locked loop and the speed of frequency switching, further, the public phase-locked loop (CLK_PLL) may also include two sub-phase-locked loops, a first sub-phase-locked loop (Sub_PLL2) and a second sub-phase-locked loop (Sub_PLL2). The Sub_PLL1 and Sub_PLL2 can be selected by a phase-locked loop selector (PLL_SEL), and the phase-locked loop controller can choose to output the clock signal of Sub_PLL1 or Sub_PLL2 as a common clock signal and input it to CLKGEN. The phase-locked loop selector can be a multiple-select-one switch, or a plurality of parallel one-to-one switches, or a multiple-select-multiple switch. The phase-locked loop selector can be located at the input end of the two sub-phase-locked loops or at the output end of the two sub-phase-locked loops. The phase-locked loop selector can also be a power module, which realizes the selection function by controlling the power supply control of the two sub-phase-locked loops. The frequency range covered by the two sub-phase-locked loops can be the same. Through the selection of the phase-locked loop selector, the speed of the fast frequency switching of the common phase-locked loop is improved. The frequency range covered by the architecture of the two sub-phase-locked loops can also be different. Through the selection of the phase-locked loop selector, the frequency coverage of the common phase-locked loop is improved.

[0109] Figure 7 A schematic diagram of another wireless transceiver provided in an embodiment of the present application. Based on the above embodiment, the RF transmission channel and the RF reception channel as well as the TL and RL of the SerDes may each include a corresponding local frequency divider.

[0110] Among them, CLK_ADC is the clock signal output from the common clock phase-locked loop to the ADC. CLK_ADC is divided by the local divider in the receiving channel to obtain the clock signal required by the ADC. Figure 7 Although only two RF receiving channels and two RF transmitting channels are shown, the wireless communication device in the embodiment of the present application is not limited thereto, and the wireless communication device may include other numbers of RF receiving channels and RF transmitting channels.

[0111] For example, taking two RF receiving channels as an example, assuming that the frequency of the clock signal required by the ADC is f ADC_CLKPLL The clock signals required by ADC1 and ADC2 in the first RF receiving channel (RX(101)) and the second RF receiving channel (RX(102)) are f ADC1_CLK 、f ADC2_CLK , then:

[0112]

[0113]

[0114] In the above formula, N DIVADC1 、N DIVADC2 They are the clock division ratios of the local analog-to-digital dividers divadc1 and divadc2 in the RF channel respectively.

[0115] After introducing local analog-to-digital dividers into multiple RF receiving channels, each RF receiving channel can be provided with its own required clock signal, so that each RF receiving channel can work in different bandwidth modes, increasing the flexibility of the RF receiver in receiving multiple signals. For example, the first local analog-to-digital divider (divadc1) is introduced into the first RF receiving channel (RX101) to divide the input clock signal (CLK_ADC) and then provide it to the first analog-to-digital converter (ADC1). The second local analog-to-digital divider (divadc2) is introduced into the second RF receiving channel (RX102) to divide the input clock signal (CLK_ADC) and then provide it to the first analog-to-digital converter (ADC2). Among them, CLK_DAC is the clock signal output from the common clock phase-locked loop to the DAC. The CLK_DAC signal is divided by the local digital-to-analog divider (DACDIV) of the RF transmitting channel and then input to the DAC of the corresponding transmitting channel. Taking two RF transmitting channels as an example, it is assumed that the frequency of the clock signal output from the common clock phase-locked loop to the DAC is f DAC_CLKPLL The clock signals required by DAC1 and DAC2 in the first RF transmission channel (TX(201)) and the second RF transmission channel (TX(202)) are f DAC1_CLK 、f DAC2_CLK , then:

[0116] In the above formula, N DIVDAC1 、N DIVDAC2They are respectively the clock division ratios of the local digital-to-analog dividers divdac1 and divdac2 in their respective RF transmit channels. Similar to the RF receive channel, after introducing local digital-to-analog dividers into multiple RF transmit channels, the DACs of the RF transmit channels can be provided with their respective required clock signals, so that the RF transmit channels can operate in different bandwidth modes, thereby increasing the flexibility of multi-channel transmit signals. Among them, CLK_SDS is the clock signal output from the common clock phase-locked loop to the SerDes. Since each transmit channel (TL) and receive channel (RL) of the SerDes may operate at different serial data rates, that is, each channel may require a clock signal of a different frequency. Therefore, each TL and RL each integrates a local divider, and the clock signal required by each channel is obtained by dividing the CLK_SDS through the local divider. Assume that the clock signal frequency of CLK_SDS is f SDS_CLKPLL , the clock signal frequencies required by channels TL1, TL2, ...TLp, RL1, RL2, ...RLq are f TL1_CLK 、f TL2_CLK ,...f Tlp_CLK 、f RL1_CLK 、f RL2_CLK ,...f RLq_CLK , then:

[0117]

[0118]

[0119] …

[0120]

[0121]

[0122]

[0123] …

[0124]

[0125] In the above formula, N DIVTL1 、N DIVTL2 ,...N DIVTLp 、N DIVRL1 、N DIVTR2 ,...N DIVRLpThey are the clock division ratios of the clock dividers DIVTL or DIVRL in the SerDes transmit channels TL1, TL2, ...TLp and receive channels RL1, RL2, ...RLq, respectively. The introduction of the local divider increases the flexibility of the clock signals required by the transmit and receive channels, so that each channel can work in different bandwidth modes.

[0126] Furthermore, the frequency division ratio of the local frequency divider of the RF receiving channel, the RF transmitting channel, and the transmitting and receiving channels of the SerDes often needs to be designed to be variable according to the needs of the ADC, DAC, SerDes, etc. for the clock frequency, so as to avoid affecting the stable operation of other channels due to the change of the frequency of the working clock of a certain channel. Each channel can change the frequency of its own working clock by adjusting the frequency division ratio of the corresponding local clock divider. Due to the introduction of the local frequency divider, the RF receiving channel, the RF transmitting channel, and the corresponding parallel-to-serial and serial-to-parallel converter (SerDes) with the local frequency divider can work in different bandwidth modes.

[0127] Figure 8 A schematic diagram of a receiver architecture provided for an embodiment of the present application. The receiver architecture can be called a zero intermediate frequency quadrature receiver. The receiver architecture can be applied to the RF receiving channel in each implementation of the present invention. The zero intermediate frequency quadrature receiver amplifies the received RF signal through a low noise amplifier (LNA), and then mixes it with two mutually orthogonal local oscillator signals through two mixers (MIX), and generates two signals, I (In-phase, in-phase) and Q (Quadrature, orthogonal) respectively. Since the frequency of the local oscillator signal is the same as the frequency of the RF signal, an analog baseband signal can be directly generated after mixing. The filter (Filter) then filters the analog baseband signal to suppress out-of-band interference or noise, improve the signal quality, reduce the deterioration of sampling aliasing of the analog-to-digital converter (ADC), and improve the signal-to-noise ratio. At the same time, the filter can usually provide a certain adjustable gain to adjust the amplitude of the analog baseband signal to obtain the desired signal strength at the ADC input end. The ADC then performs analog-to-digital conversion on the signal processed by the filter, generates a digital baseband signal and sends it to the baseband processor for processing. In the baseband processor, the digital baseband signal is demodulated, decoded and other operations to obtain data carrying useful information. Figure 8 Although the receiver is based on an orthogonal architecture and has two IQ paths, the receiver may further include a differential link, that is, each I path and Q path includes a corresponding differential path.

[0128] In addition to the above zero-IF receiver architecture, the superheterodyne receiver is also a very typical receiver architecture. The superheterodyne receiver is similar to the zero-IF receiver architecture, except that the local oscillator frequency is different from the RF frequency, and generally requires a second mixing before down-conversion to generate a baseband signal. In addition, the baseband signal generally needs to pass through an additional image rejection filter before being processed by the ADC.

[0129] The architecture of the RF transmission channel is similar to that of the RF receiving channel. In the transmission direction, the baseband processor first encodes and modulates the data carrying useful information, and then sends it to the DAC after preprocessing. The function of the DAC is to convert the transmitted digital baseband signal into an analog baseband signal and output it to the RFIC. The RFIC receives the analog baseband signal and first passes it through a filter to filter out the image signal substituted by the digital-to-analog conversion, and suppresses the digital baseband signal and the quantization noise substituted by the DAC. The filtered analog baseband signal is moved to the RF section through the RF modulator, and after power adjustment, it is output at a certain power.

[0130] Although this embodiment introduces a zero intermediate frequency or superheterodyne architecture, the RFIC of the wireless transceiver device used to implement the functions of the present invention may also be based on other forms of receiver or transmitter architecture.

[0131] Fig. 9 A schematic diagram of a local frequency divider based on an orthogonal architecture provided in an embodiment of the present application. On the basis of the above embodiments, when the RF receiving channel or the RF transmitting channel is an IQ two-way orthogonal architecture, since the signal bandwidths of the IQ two-way receiving channels are the same, the bandwidths of the ADC DACs of the IQ two-way channels are the same. An RF receiving channel or an RF transmitting channel only requires one local frequency divider to simultaneously provide clock signals for the ADCs or DACs of the IQ two-way channels in the same RF transceiver channel, thereby further saving the resources of the frequency divider, and also ensuring the consistency of the clock signals of the ADCs or DACs of the IQ two-way channels, and ensuring the consistency of the bandwidth processing of the IQ two-way signals. For example, the first RF receiving channel (RX101) is an orthogonal architecture, including two ADCs in the IQ two-way channels respectively, and the first receiving channel only requires one local frequency divider (DIVADC1) to provide the same clock reference signal for the two ADCs. Fig. 9 Although only two RF receiving channels and two RF transmitting channels are shown, the wireless communication device in the embodiment of the present application is not limited thereto, and the wireless communication device may include three or more RF receiving channels and RF transmitting channels.

[0132] On the basis of the above embodiments, taking into account the complexity of circuit implementation and implementation cost factors such as power consumption and area, the division ratio supported by each clock divider in the clock generator CLKGEN and each RF receiving channel or RF transmitting channel and the local divider in each transceiver channel in the SerDes can generally be designed to be a positive integer or a combination of a positive integer and a simple decimal.

[0133] For example, the division ratio of the frequency divider can be expressed as N DCLK :

[0134] N DCLK =N intg +N frac

[0135] In the above formula, N intg is a positive integer, that is:

[0136] N intg ={1, 2, 3, ...}

[0137] When N frac When defined as a negative integer power of 2, that is: N frac =2 F , where F = {-1, -2, -3, ...}, N frac is a simple decimal. N frac It can also be 0.

[0138] The frequency division ratios of the clock dividers DADC, DDAC, DDIG and DSDS in the clock generator CLKGEN described in the above embodiment, and the frequency division ratios of DIVADC in each RF receiving channel or DIVDAC in the RF transmitting channel and each transceiver channel DIVTL and DIVRL in the SerDes can be the relationship described by the above formula. The frequency division ratios of each frequency divider can be different, and the appropriate frequency division ratio should be selected according to the requirements of the ADC, DAC, SerDes, etc. for the clock frequency.

[0139] Fig.10 A schematic diagram of a radio frequency receiver and a radio frequency transmitter provided in an embodiment of the present application. Fig.10 Although only four RF receiving channels and two RF transmitting channels are shown in the figure, the RF chip in the embodiment of the present application is not limited thereto, and the RF chip may include more RF receiving channels and RF transmitting channels.

[0140] After the introduction of local analog-to-digital dividers and local digital-to-analog dividers, the bandwidth of each RF receiving channel and the bandwidth of the processed signal of the RF transmitting channel can be flexibly adjusted. Based on such a clock network architecture, the RF transmitting channel and RF receiving channel of the RF chip have the ability to simultaneously process carrier aggregation and MIMO on the basis of multiplexing clock dividers, and the bandwidth of the carrier unit of each channel can be different, which greatly improves the competitiveness of the RF chip and enables the same RF chip to support carrier aggregation and MIMO of different standards.

[0141] The RF receiver may include a first RF receiving channel (RX(101)), a second RF receiving channel (RX(102)), a third RF receiving channel (RX(103)), and a fourth RF receiving channel (RX(104)), wherein the first RF receiving channel is used to implement reception processing of a first RF signal, the second RF receiving channel is used to implement reception processing of a second RF signal, the third RF receiving channel is used to implement reception processing of a third RF signal, and the fourth RF receiving channel is used to implement reception processing of a fourth RF signal; the RF transmitter may also include a first RF transmitting channel (TX(201)) and a second RF transmitting channel (TX(202)); the first RF transmitting channel is used to implement transmission processing of a fifth RF signal, and the second RF transmitting channel is used to implement transmission processing of a sixth RF signal. The common clock phase-locked loop is used to provide corresponding clock signals for ADCs and DACs in each receiving channel and transmitting channel.

[0142] Further, the RF chip can realize the transmission and reception of DLCA (4CC) + ULCA (2CC) carrier aggregation. The first RF signal is CC1, the second RF signal is CC2, the third RF signal is CC3, the fourth RF signal is CC4, the fifth RF signal is CC5, and the sixth RF signal is CC6. Carrier aggregation can be continuous carrier aggregation or non-continuous carrier aggregation, but in a separate frequency band, it can be used as intra-band non-continuous carrier aggregation, and in different frequency bands, it can be used as inter-band non-continuous carrier aggregation. Since CC1 and CC4 are transmitted in different receiving channels, from the perspective of system optimization, CC1 to CC4 can be intra-band non-continuous downlink carrier aggregation or inter-band downlink carrier aggregation (DLCA). For example, CC1 and CC2 can be two non-continuous carriers in the same frequency band band A, while CC3 can be a carrier in frequency band B, and CC4 can be a carrier in frequency band C. For example, CC1 and CC2 can be two non-continuous carriers in the same frequency band band A, while CC3 and CC4 can be two non-continuous carriers in frequency band B.

[0143] Furthermore, since CC5 and CC6 are transmitted in different transmission channels, CC5 and CC6 can be non-continuous uplink carrier aggregation within the band or uplink carrier aggregation between bands (ULCA). For example, CC5 and CC6 can be two non-continuous carriers in the same frequency band, band A. CC5 and CC6 can also be two carriers located in frequency band A and frequency band B, respectively.

[0144] Furthermore, the RF chip can realize the transmission and reception of carrier aggregation of DLCA (5CC) + ULCA (2CC). The first RF signal is CC1, the second RF signal is CC2, the third RF signal is CC3, and the fourth RF signal is CC4+CC5, wherein CC1, CC2, and CC3 are downlink inter-band carrier aggregation (inter band DLCA), and CC4 and CC5 are downlink intra-band carrier aggregation (intra band DLCA). The RF chip can realize the reception of carrier aggregation of DLCA5CC; at the same time, the fifth RF signal is CC5, and the sixth RF signal is CC6, and the RF signal realizes the transmission of two carriers of ULCA.

[0145] Furthermore, the RFIC may also include a fifth RF receiving channel, a sixth RF receiving channel, and a seventh RF receiving channel. The fifth RF receiving channel is used to implement reception processing of the seventh carrier, the sixth RF receiving channel is used to receive processing of the eighth carrier signal, and the seventh RF receiving channel is used to receive processing of the ninth carrier signal; the seventh carrier signal, the eighth carrier signal and the ninth carrier signal have the same frequency band characteristics as the first carrier signal, and the seventh carrier signal, the eighth carrier signal, the ninth carrier signal and the first RF signal are received from different antennas; the common clock phase-locked loop is used to provide a clock signal for the analog-to-digital converters corresponding to the fifth RF receiving channel, the sixth RF receiving channel, and the seventh RF receiving channel, so that the seventh RF signal, the eighth RF signal and the ninth RF signal and the first RF signal constitute the reception of a 4X4 MIMO signal. The RFIC can support the characteristics of CA+MIMO.

[0146] Although this embodiment only lists the above two groups of carrier aggregation transceiver and one group of MIMO scenarios, the wireless communication device in the embodiment of the present application is not limited to this, and the wireless communication device may include other carrier aggregation transceiver and MIMO combinations.

[0147] Fig.11A schematic diagram of a radio frequency chip provided for an embodiment of the present application. Based on the above embodiment, the radio frequency chip further includes a first local oscillator phase-locked loop (LO_PLL1) for providing a local oscillator signal for the radio frequency receiver or transmitter. Preferably, the first local oscillator phase-locked loop (LO_PLL1) is used to provide a local oscillator signal for a mixer of a radio frequency transceiver channel supporting CA and MIMO characteristics.

[0148] The local oscillator signal of the RF transceiver, such as the local oscillator signal required by the RF transceiver channel to support LTE and NR characteristics, usually needs to meet the specific requirements of the RF transceiver channel. For example, when the transceiver channel needs to support the CA scenario specified in the protocol, especially the intra-band CA, a channel needs to cover tens of megabits or even hundreds of megabits of bandwidth, and the bandwidth requirements of the phase-locked loop required by the channel are very stringent. In addition, the required transceiver channel needs to ensure that the RF transceiver channel can be switched at any time according to the scenario, and the local oscillator signal needs to be able to switch quickly. Therefore, considering the huge differences in the requirements and performance of the common clock phase-locked loop that provides clock signals for ADC, DAC, and SerDes and the phase-locked loop that provides local oscillator signals for the RF transceiver channel, from the perspective of system design, using the first local oscillator phase-locked loop to provide local oscillator signals for the RF transceiver channel alone will make the system's clock signal design more efficient and performant.

[0149] The first local oscillator phase-locked loop can provide local oscillator signals for the down converter Down_MIX of the first RF receiving channel and the mixer up converter UP_MIX of the first transmitting channel at the same time.

[0150] Furthermore, the RF chip may also include a second local oscillator phase-locked loop (LO_PLL2), wherein the first local oscillator phase-locked loop provides a local oscillator signal for the mixer mix of the receiving channel, and the second local oscillator phase-locked loop provides a local oscillator signal for the mixer mix of the transmitting channel, thereby meeting the different requirements of the receiving and transmitting channels for the phase-locked loop and further optimizing the performance of the RF chip.

[0151] Furthermore, the reference signals of the common clock phase-locked loop, the first local oscillator phase-locked loop and the second local oscillator phase-locked loop can be provided by the same reference clock signal CLK_REF, and the reference signal CLK_REF can be input from the outside of the RF chip through the same RF chip pin, thereby reducing the control timing inside the chip and the synchronization error of the receiving and transmitting signals.

[0152] Although this embodiment only provides one RF receiving channel, one RF transmitting channel and three phase-locked loops, the RF chip in the embodiment of the present application is not limited to this. The RF chip may include other numbers of RF receiving channels and RF transmitting channels, and the phase-locked loop provides other types of local oscillator signals.

[0153] Fig.12 A schematic diagram of a phase-locked loop provided for an embodiment of the present application. The first sub-phase-locked loop, the second sub-phase-locked loop, the first local oscillator phase-locked loop and the second local oscillator phase-locked loop in the above-mentioned embodiment can be a digital phase-locked loop or an analog phase-locked loop. This embodiment is a typical phase-locked loop circuit structure that can be used for the first sub-phase-locked loop, the second sub-phase-locked loop, the first local oscillator phase-locked loop and the second local oscillator phase-locked loop in the present invention. The phase-locked loop includes an oscillator OSC, which is used to generate a clock signal of a certain frequency; a feedback divider DIV, which is used to divide the OSC output signal to generate a feedback signal CLK_DIV with a frequency close to that of the input reference clock CLK_REF; a phase detector PD, which is used to compare the phase difference between the feedback signal CLK_DIV and the reference clock CLK_REF, and output an output signal PD_OUT related to the phase difference of the two signals; a controller CTRL, which is used to process the phase detector output signal PD_OUT and generate an oscillator control signal VCTRL. Through the above description of each phase-locked loop key, it can be known that the phase-locked loop is a negative feedback system. Through the negative feedback mechanism, the frequency and phase synchronization of the output signal CLK_PLL and the input reference clock is achieved. Under the action of the negative feedback mechanism, the frequency f of the output signal CLK_PLL of the clock phase-locked loop is CLK_PLL Can be locked to:

[0154] f CLK_PLL =N FCW ·f CLK_REF

[0155] Where N FCW It is the division ratio control word, which is used to control the division ratio of the feedback divider.

[0156] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A wireless transceiver, characterized in that: include: A radio frequency receiver, a radio frequency transmitter, a first parallel-to-serial and serial-to-parallel converter, and a common clock phase-locked loop; The RF receiver, the RF transmitter, the first parallel-serial and serial-to-parallel converter, and the common clock phase-locked loop are integrated in a RF chip, the RF receiver includes a downconverter and an analog-to-digital converter, the RF transmitter includes an upconverter and a digital-to-analog converter, the pins of the first parallel-serial and serial-to-parallel converter are used to couple with the pins of the parallel-serial and serial-to-parallel converter in the baseband chip in a one-to-one correspondence, and the first parallel-serial and serial-to-parallel converter is used to provide a digital interface between the RF chip and the baseband chip; The common clock phase-locked loop is respectively coupled to the analog-to-digital converter, the digital-to-analog converter and the first parallel-to-serial and serial-to-parallel converter; The RF receiver includes a plurality of RF receiving channels, and the RF transmitter includes a plurality of RF transmitting channels; each of the RF receiving channels includes one of the analog-to-digital converters, and each of the RF transmitting channels includes one of the digital-to-analog converters; Each of the RF receiving channels further comprises a local analog-to-digital frequency divider, and the local analog-to-digital frequency divider in the RF receiving channel divides the signal output by the common clock phase-locked loop and provides the divided signal to the analog-to-digital converter in the RF receiving channel; Each of the radio frequency transmission channels also includes a local digital-to-analog frequency divider. The local digital-to-analog frequency divider in the radio frequency transmission channel divides the frequency of the signal output by the common clock phase-locked loop and provides the divided signal to the digital-to-analog converter in the radio frequency transmission channel.

2. The wireless transceiver according to claim 1, wherein: Also includes: The baseband chip comprises a second parallel-serial and serial-to-parallel converter, and the second parallel-serial and serial-to-parallel converter is used to provide a digital interface between the baseband chip and the radio frequency chip.

3. The wireless transceiver according to claim 1, wherein: The common clock phase-locked loop comprises a common phase-locked loop and a clock generator; The common phase-locked loop is used to generate a common clock signal; The clock generator is used to convert the common clock signal into multiple parallel clock signals, and output the multiple parallel clock signals to the analog-to-digital converter, the digital-to-analog converter and the first parallel-to-serial and serial-to-parallel converter respectively.

4. The wireless transceiver according to claim 3, wherein: The common phase-locked loop comprises a first sub-phase-locked loop, a second sub-phase-locked loop and a phase-locked loop selector; The phase-locked loop selector is used to select the first sub-phase-locked loop or the second sub-phase-locked loop to generate the common clock signal.

5. The wireless transceiver as claimed in claim 3, wherein: The clock generator includes a clock divider, which is used to divide the common clock signal to generate a divided clock signal, and output the divided clock signal to the analog-to-digital converter, the digital-to-analog converter or the first parallel-to-serial and serial-to-parallel converter.

6. The wireless transceiver according to claim 5, wherein: The clock frequency divider includes a first frequency divider, a second frequency divider and a frequency division selector; The first frequency divider and the second frequency divider have different frequency division ratios, and the frequency division selector is used to select the first frequency divider or the second frequency divider to divide the common clock signal.

7. The wireless transceiver according to any one of claims 1 to 6, characterized in that: The multiple RF receiving channels include a first RF receiving channel, a second RF receiving channel, a third RF receiving channel and a fourth RF receiving channel, the first RF receiving channel is used to receive a first carrier signal, the second RF receiving channel is used to receive a second carrier signal, the third RF receiving channel is used to receive a third carrier signal, and the fourth RF receiving channel is used to receive a fourth carrier signal; The multiple radio frequency transmission channels include a first radio frequency transmission channel and a second radio frequency transmission channel; The first radio frequency transmission channel is used to transmit a fifth carrier signal, and the second radio frequency transmission channel is used to transmit a sixth carrier signal; The first carrier signal, the second carrier signal, the third carrier signal, and the fourth carrier signal together constitute an inter-band downlink carrier aggregation; The fifth carrier signal and the sixth carrier signal together constitute non-continuous uplink carrier aggregation within a band or uplink carrier aggregation between bands.

8. The wireless transceiver according to claim 7, wherein: Each of the radio frequency receiving channels comprises an in-phase receiving branch and an orthogonal receiving branch, and each of the in-phase receiving branch and the orthogonal receiving branch comprises an analog-to-digital converter; The local analog-to-digital frequency divider in the radio frequency receiving channel is used to provide the same clock signal for the analog-to-digital converter in the in-phase receiving branch and the analog-to-digital converter in the orthogonal receiving branch in the radio frequency receiving channel.

9. The wireless transceiver according to claim 5 or 6, characterized in that: The division ratio of the clock divider is a positive integer, or the sum of a positive integer and a simple decimal, where the simple decimal is a negative integer power of 2.

10. The wireless transceiver according to claim 8, characterized in that: Also includes: A radio frequency front-end device, wherein the radio frequency front-end device comprises a low noise amplifier; The RF front-end device is located between the RF chip and the antenna; The radio frequency chip further includes a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor, wherein the source of the PMOS transistor is used to couple to a power supply terminal, and the source of the NMOS transistor is used to couple to a ground terminal; The drain of the PMOS transistor is coupled to the drain of the NMOS transistor as an output terminal for coupling to the down converter; The gate of the PMOS transistor and the gate of the NMOS transistor are coupled as input terminals for coupling to the low noise amplifier.

11. The wireless transceiver device according to claim 10, wherein: Also includes: The local oscillator phase-locked loop is used to provide the up-converter or the down-converter with a local oscillator signal required for frequency conversion.

12. The wireless transceiver according to claim 11, wherein: The wireless transceiver device also includes a power chip, which is coupled to the radio frequency chip. The power chip supplies power to the radio frequency chip and provides a reference clock signal for the common clock phase-locked loop.

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