A bias voltage generation circuit for a radio frequency front-end chip

Abstract

The present invention relates to the technical field of radio frequency front-end chips, and discloses a bias voltage generation circuit for a radio frequency front-end chip, which includes a voltage input terminal, a first voltage division unit, a second voltage division unit, a PMOS transistor MP1, a first current mirror unit, a second current mirror unit, an NMOS transistor MN1, a PMOS transistor MP2, a voltage step-down unit, and a voltage output terminal; in actual use, when the voltage input at the voltage input terminal is 3.3V, the PMOS transistor MP1 is turned on, and the current output by the PMOS transistor MP1 is mirrored by the first current mirror unit and the second current mirror unit, and a voltage drop is generated on the NMOS transistor MN1, causing the PMOS transistor MP2 to turn off, and the 3.3V voltage is output through the voltage step-down unit; when the voltage input at the voltage input terminal is 1.8V, the PMOS transistor MP1 is turned off, and no current is input to the first current mirror unit, and the first current mirror unit and the second current mirror unit do not work, and the 1.8V voltage is output through the PMOS transistor MP2. Therefore, the present invention can be compatible with the power supply voltage inputs of two voltage specifications, and reduce the working current and power consumption when the input voltage is 1.8V.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front - end chips, and particularly to a bias voltage generation circuit for a radio frequency front - end chip. Background Art

[0002] In the field of mobile communication technology, the power supply voltage specifications of radio frequency front - end chips are generally 3.3V or 1.8V, and are gradually developing towards 1.8V. Based on this, the design of radio frequency front - end chips needs to consider the compatibility of voltage levels, that is, to ensure normal operation when the voltage inputs of 3.3V and 1.8V are applied.

[0003] Currently, in radio frequency front - end chips, a dynamic bias circuit is often used to enable the radio frequency front - end chip to simultaneously accommodate power supply voltages of 3.3V and 1.8V. As Figure 1 shown, the existing dynamic bias circuit includes a bandgap reference circuit and an LDO circuit. The bandgap reference circuit inputs a reference voltage Vref to the LDO circuit, and the LDO voltage - regulating circuit provides a bias voltage to the remaining circuits of the radio frequency front - end chip. Among them, both the bandgap reference circuit and the LDO circuit consume a certain amount of operating current during operation, resulting in high power consumption. Moreover, the bandgap reference circuit and the LDO circuit are respectively closed - loop control circuits. In order to ensure their own stability, the operating current needs to be controlled simultaneously, and the establishment time is generally relatively slow, about 10 us, and the entire startup time is relatively long. The existing LDO circuit is as Figure 2 shown. The PMOS transistor MP1 is the output power transistor. By changing the ratio value of the resistors R1 and R2, the magnitude of the output voltage Vout of the LDO can be adjusted. When the input power supply voltage of the LDO circuit is 1.8V, the PMOS transistor MP1 operates in the linear region and is equivalent to a resistor, so the current consumption of the entire dynamic bias circuit is relatively large. Summary of the Invention

[0004] In view of the deficiencies of the background art, the present invention provides a bias voltage generation circuit for a radio frequency front - end chip, and the technical problem to be solved is that the operating current of the existing dynamic bias circuit of the radio frequency front - end chip is relatively large and the power consumption is relatively high.

[0005] To solve the above - mentioned technical problems, the present invention provides the following technical solution: A bias voltage generation circuit for a radio frequency front - end chip, comprising a voltage input terminal, a first voltage - dividing unit, a second voltage - dividing unit, a PMOS transistor MP1, a first current mirror unit, a second current mirror unit, an NMOS transistor MN1, a PMOS transistor MP2, a voltage - reducing unit, and a voltage output terminal;

[0006] The first voltage dividing unit, the second voltage dividing unit, the second current mirror unit, the source of PMOS transistor MP2, and the input end of the buck unit are respectively electrically connected to the voltage input end, and the drain of PMOS transistor MP2 and the output end of the buck unit are respectively connected to the voltage output end;

[0007] The voltage dividing node of the first voltage dividing unit is electrically connected to the source of PMOS transistor MP1, and the voltage dividing node of the second voltage dividing unit is electrically connected to the gate of PMOS transistor MP1. When the first voltage dividing unit and the second voltage dividing unit are turned on, the voltage of the voltage dividing node of the first voltage dividing unit is greater than the voltage of the voltage dividing node of the second voltage dividing unit, and the voltage difference between the voltage dividing node of the first voltage dividing unit and the ground terminal and the voltage difference between the voltage dividing node of the second voltage dividing unit and the ground terminal are both greater than 1.8V;

[0008] The first current mirror unit mirrors the output current of PMOS transistor MP1 to output a second current, the second current mirror unit mirrors the second current to output a third current, the third current is input to the drain of NMOS transistor MN1, the drain of NMOS transistor MN1 is electrically connected to the gate of PMOS transistor MP2, the gate of NMOS transistor MN1 is electrically connected to the second voltage dividing node of the second voltage dividing unit, and when the second voltage dividing unit is turned on, the voltage of the voltage dividing node of the second voltage dividing unit is greater than the voltage of the second voltage dividing node, and the source of NMOS transistor MN1 is grounded.

[0009] In actual use, when a power supply voltage of 3.3V is input to the voltage input end, the first voltage dividing unit and the second voltage dividing unit are turned on, PMOS transistor P1 is turned on. At this time, the first current mirror unit has current input, the first current mirror unit converts the input current into a second current, the second current mirror unit converts the second current into a third current, and the third current generates a voltage drop on NMOS transistor MN1. At this time, PMOS transistor MP2 is turned off, and the voltage input to the voltage input end is output through the buck unit;

[0010] When a voltage of 1.8V is input to the voltage input end, the first voltage dividing unit and the second voltage dividing unit are both not turned on. At this time, PMOS transistor MP1 is turned off, and PMOS transistor MP1 does not input current to the first current mirror unit. The 1.8V voltage is input to the gate of NMOS transistor MN1 through the second voltage dividing node of the second voltage dividing unit, making NMOS transistor MN1 turned on. At this time, the gate of PMOS transistor MP2 is grounded through NMOS transistor MN1, and PMOS transistor MP2 is turned on. The 1.8V voltage is input to the voltage output end through PMOS transistor MP2. Therefore, when a voltage of 1.8V is input to the voltage input end, the first voltage dividing unit, the second voltage dividing unit, the first current mirror unit, the second current mirror unit, and PMOS transistor MP1 of the circuit of the present invention do not work, and the overall power consumption of the circuit is small.

[0011] In some embodiments, the first voltage dividing unit includes a resistor R1, a diode D1, a diode D2, a diode D3, and a diode D4 connected in series in sequence. The negative electrode of the diode D4 is grounded. One end of the resistor R1 that is not electrically connected to the diode D1 is electrically connected to the voltage input terminal, and one end of the resistor R1 that is electrically connected to the diode D1 is electrically connected to the source electrode of the PMOS transistor MP1.

[0012] In some embodiments, the second voltage dividing unit includes a resistor R2, a diode D5, a diode D6, and a diode D7 connected in series in sequence. The negative electrode of the diode D7 is grounded. One end of the resistor R2 that is not electrically connected to the diode D5 is electrically connected to the voltage input terminal, and one end of the resistor 2 that is electrically connected to the diode D5 is electrically connected to the gate electrode of the PMOS transistor MP1.

[0013] In some embodiments, the first current mirror unit includes an NMOS transistor MN2, an NMOS transistor MN3, and an NMOS transistor MN4. The drain electrode of the PMOS transistor MP1 is electrically connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN2, and the gate electrode of the NMOS transistor MN3 respectively. The source electrodes of the NMOS transistor MN2 and the NMOS transistor MN3 are both grounded. The drain electrode of the NMOS transistor MN3 is electrically connected to the source electrode of the NMOS transistor MN4. The gate electrode of the NMOS transistor MN4 is electrically connected to the gate electrode of the PMOS transistor MP1. The drain electrode of the NMOS transistor MN4 is electrically connected to the second current mirror unit.

[0014] In some embodiments, the second current mirror unit includes a PMOS transistor MP3 and a PMOS transistor MP4. The source electrodes of the PMOS transistor MP3 and the PMOS transistor MP4 are electrically connected to the voltage input terminal. The gate electrode of the PMOS transistor MP3 is electrically connected to the gate electrode of the PMOS transistor MP4, the drain electrode of the PMOS transistor PM3, and the first current mirror unit respectively. The drain electrode of the PMOS transistor MP4 is electrically connected to the drain electrode of the NMOS transistor MN1.

[0015] In some embodiments, the buck unit includes a diode D8. The positive electrode and the negative electrode of the diode D8 are electrically connected to the voltage input terminal and the voltage output terminal respectively.

[0016] The beneficial effects of the present invention compared with the prior art are as follows: The circuit of the present invention detects the voltage input at the voltage input terminal through the first voltage dividing unit and the second voltage dividing unit, and then the PMOS transistor MP1 performs voltage-current conversion; when the voltage input at the voltage input terminal is 3.3V, the PMOS transistor MP1 is turned on, and the PMOS transistor MP1 inputs current to the first current mirror unit. This current is mirrored by the first current mirror unit and the second current mirror unit, generating a voltage drop across the NMOS transistor MN1, turning off the PMOS transistor MP2, and the 3.3V voltage is output through the voltage reduction unit; when a 1.8V voltage is input at the voltage input terminal, the PMOS transistor MP1 is turned off and does not input current to the first current mirror unit, and the first current mirror unit and the second current mirror unit do not work, and the 1.8V voltage is output through the PMOS transistor MP2. Therefore, when the circuit of the present invention is applied to a radio frequency front-end chip, the radio frequency front-end chip can be compatible with power supply voltage inputs of two voltage specifications, and can reduce the operating current when the input voltage is 1.8V. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural diagram of an existing dynamic bias circuit;

[0018] Figure 2 is Figure 1 a schematic diagram of the LDO circuit in

[0019] Figure 3 is a schematic structural diagram of the present invention in the embodiment;

[0020] Figure 4 is a circuit diagram of the present invention in the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.

[0022] As Figure 3 shown, a bias voltage generation circuit for a radio frequency front-end chip includes a voltage input terminal Vin, a first voltage dividing unit 1, a second voltage dividing unit 2, a PMOS transistor MP1, a first current mirror unit 3, a second current mirror unit 4, an NMOS transistor MN1, a PMOS transistor MP2, a voltage reduction unit 5, and a voltage output terminal Vout;

[0023] The source electrodes of the first voltage dividing unit 1, the second voltage dividing unit 2, the second current mirror unit 4, the PMOS transistor MP2, and the input terminal of the voltage reduction unit 5 are respectively electrically connected to the voltage input terminal Vin, and the drain electrode of the PMOS transistor MP2 and the output terminal of the voltage reduction unit 5 are respectively electrically connected to the voltage output terminal.

[0024] The voltage dividing node of the first voltage dividing unit 1 is electrically connected to the source of the PMOS transistor MP1, and the voltage dividing node of the second voltage dividing unit 2 is electrically connected to the gate of the PMOS transistor MP1. When the first voltage dividing unit 1 and the second voltage dividing unit 2 are turned on, the voltage of the voltage dividing node of the first voltage dividing unit 1 is greater than the voltage of the voltage dividing node of the second voltage dividing unit 2. The voltage difference between the voltage dividing node of the first voltage dividing unit 1 and the ground terminal Gnd and the voltage difference between the voltage dividing node of the second voltage dividing unit 2 and the ground terminal Gnd are both greater than 1.8V;

[0025] The first current mirror unit 3 mirrors the output current of the PMOS transistor MP1 to output a second current. The second current mirror unit 4 mirrors the second current to output a third current. The third current is input to the drain of the NMOS transistor MN1. The drain of the NMOS transistor MN1 is electrically connected to the gate of the PMOS transistor MP2. The gate of the NMOS transistor MN1 is electrically connected to the second voltage dividing node of the second voltage dividing unit 2. When the second voltage dividing unit 2 is turned on, the voltage of the voltage dividing node of the second voltage dividing unit 2 is greater than the voltage of the second voltage dividing node. The source of the NMOS transistor MN1 is grounded.

[0026] In actual use, when a power supply voltage of 3.3V is input to the voltage input terminal, the first voltage dividing unit and the second voltage dividing unit are turned on, and the PMOS transistor P1 is turned on. At this time, the first current mirror unit 3 has current input. The first current mirror unit 2 converts the input current into a second current, and the second current mirror unit 4 converts the second current into a third current. The third current generates a voltage drop across the NMOS transistor MN1. At this time, the PMOS transistor MP2 is turned off, and the voltage input to the voltage input terminal Vin is output through the voltage reducing unit 5;

[0027] When a voltage of 1.8V is input to the voltage input terminal Vin, neither the first voltage dividing unit 1 nor the second voltage dividing unit 2 is turned on. At this time, the PMOS transistor MP1 is turned off, and the PMOS transistor MP1 does not input current to the first current mirror unit 3. The 1.8V voltage is input to the gate of the NMOS transistor MN1 through the second voltage dividing node of the second voltage dividing unit 2, causing the NMOS transistor MN1 to be turned on. At this time, the gate of the PMOS transistor MP2 is grounded through the NMOS transistor MN1, and the PMOS transistor MP2 is turned on. The 1.8V voltage is input to the voltage output terminal Vout through the PMOS transistor MP2. Therefore, when a voltage of 1.8V is input to the voltage input terminal Vin, the first voltage dividing unit 1, the second voltage dividing unit 2, the first current mirror unit 3, the second current mirror unit 4, and the PMOS transistor MP1 of the circuit of the present invention do not work, and the overall power consumption of the circuit is small.

[0028] Such as Figure 4As shown, in this embodiment, the first voltage dividing unit 1 includes a resistor R1, a diode D1, a diode D2, a diode D3, and a diode D4 connected in series in sequence. The negative electrode of the diode D4 is grounded. One end of the resistor R1 that is not electrically connected to the diode D1 is electrically connected to the voltage input terminal Vin, and one end of the resistor R1 that is electrically connected to the diode D1 is electrically connected to the source electrode of the PMOS transistor MP1. The voltage drop of a common diode is 0.7V, and the total voltage drop of the diodes D1, D2, D3, and D4 is 2.8V. Therefore, the voltage difference between the voltage dividing node of the first voltage dividing unit 1 and the ground terminal Gnd is 2.8V.

[0029] As Figure 4 shown, the second voltage dividing unit 2 includes a resistor R2, a diode D5, a diode D6, and a diode D7 connected in series in sequence. The negative electrode of the diode D7 is grounded. One end of the resistor R2 that is not electrically connected to the diode D5 is electrically connected to the voltage input terminal Vin, and one end of the resistor 2 that is electrically connected to the diode D5 is electrically connected to the gate electrode of the PMOS transistor MP1. The voltage drop of a common diode is 0.7V, and the total voltage drop of the diodes D5, D6, and D8 is 2.1V. Therefore, the voltage difference between the voltage dividing node of the first voltage dividing unit 1 and the ground terminal Gnd is 2.1V.

[0030] During actual use, when the voltage input at the voltage input terminal Vin is 1.8V, neither the first voltage dividing unit 1 nor the second voltage dividing unit 2 conducts. When the voltage input at the voltage input terminal Vin is 3.3V, both the first voltage dividing unit 1 and the second voltage dividing unit 2 conduct. At this time, the voltage at the source electrode of the PMOS transistor MP1 is 2.8V, the voltage at the gate electrode of the PMOS transistor MP1 is 2.1V, and the PMOS transistor MP1 conducts.

[0031] As Figure 4 shown, the first current mirror unit 3 includes an NMOS transistor MN2, an NMOS transistor MN3, and an NMOS transistor MN4. The drain electrode of the PMOS transistor MP1 is electrically connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN2, and the gate electrode of the NMOS transistor MN3 respectively. The source electrodes of the NMOS transistor MN2 and the NMOS transistor MN3 are both grounded. The drain electrode of the NMOS transistor MN3 is electrically connected to the source electrode of the NMOS transistor MN4. The gate electrode of the NMOS transistor MN4 is electrically connected to the gate electrode of the PMOS transistor MP1. The drain electrode of the NMOS transistor MN4 is electrically connected to the second current mirror unit.

[0032] As Figure 4As shown, the second current mirror unit 4 includes PMOS transistor MP3 and PMOS transistor MP4. The sources of PMOS transistor MP3 and PMOS transistor MP4 are electrically connected to the voltage input terminal Vin. The gate of PMOS transistor MP3 is electrically connected to the gates of PMOS transistor MP4, the drain of PMOS transistor PM3, and the first current mirror unit. The drain of PMOS transistor MP4 is electrically connected to the drain of NMOS transistor MN1.

[0033] As Figure 4 shown, the buck unit 4 includes diode D8. The positive and negative electrodes of diode D8 are electrically connected to the voltage input terminal and the voltage output terminal respectively. In actual use, the nominal breakdown voltage of the devices in the circuit connected to the bias voltage generation circuit in the RF front-end chip is 2.5V. Under the condition that the performance is satisfied, in order to ensure the reliability of the RF front-end chip, the 3.3V voltage is supplied through diode D8 to achieve voltage reduction.

[0034] In addition, for the present invention, the establishment time for the output voltage of the present invention to reach a steady state is mainly limited by the slew rate at the gate terminal of PMOS transistor MP2. By setting the width and length of PMOS transistor MP2 to reduce the parasitic capacitance of PMOS transistor MP2, the startup time of the circuit, that is, the time required for the circuit to reach a steady state from the start of output, can be reduced. Preferably, the width of PMOS transistor MP2 is 200um, and the length of PMOS transistor MP2 is 0.24um.

[0035] In addition, by adjusting the width and length of NMOS transistor MN1, the on-resistance of NMOS transistor MN1 can be increased within the allowable power consumption to increase the gate voltage of PMOS transistor MP2, thereby reducing the on-time of PMOS transistor MP2 and reducing the startup time of the entire circuit. Preferably, the width of NMOS transistor MN1 is 0.5um, and the length of NMOS transistor MN1 is 20um.

[0036] In summary, the circuit of the present invention detects the voltage input at the voltage input terminal Vin through the first voltage dividing unit 1 and the second voltage dividing unit 2, and then the PMOS transistor MP1 performs voltage-current conversion; when the voltage input at the voltage input terminal Vin is 3.3V, the PMOS transistor MP1 is turned on, and the PMOS transistor MP1 inputs current to the first current mirror unit 3. After the current is mirrored by the first current mirror unit 3 and the second current mirror unit 4, a voltage drop is generated on the NMOS transistor MN1, turning off the PMOS transistor MP2, and the 3.3V voltage is output through the voltage reduction unit 5; when a 1.8V voltage is input at the voltage input terminal Vin, the PMOS transistor MP1 is turned off and does not input current to the first current mirror unit 3, and the first current mirror unit 3 and the second current mirror unit 4 do not work, and the 1.8V voltage is output through the PMOS transistor MP2. Therefore, when the circuit of the present invention is applied to a radio frequency front-end chip, the radio frequency front-end chip can be compatible with power supply voltage inputs of two voltage specifications, and can reduce the working current when the input voltage is 1.8V, thereby reducing power consumption.

[0037] Based on the inspiration of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A bias voltage generation circuit for a radio frequency front-end chip, characterized in that, it includes a voltage input terminal, a first voltage dividing unit, a second voltage dividing unit, a PMOS transistor MP1, a first current mirror unit, a second current mirror unit, an NMOS transistor MN1, a PMOS transistor MP2, a voltage step-down unit and a voltage output terminal; The first voltage dividing unit, the second voltage dividing unit, the second current mirror unit, the source electrode of the PMOS transistor MP2 and the input terminal of the voltage step-down unit are respectively electrically connected to the voltage input terminal, and the drain electrode of the PMOS transistor MP2 and the output terminal of the voltage step-down unit are respectively connected to the voltage output terminal; The voltage dividing node of the first voltage dividing unit is electrically connected to the source electrode of the PMOS transistor MP1, the voltage dividing node of the second voltage dividing unit is electrically connected to the gate electrode of the PMOS transistor MP1. When the first voltage dividing unit and the second voltage dividing unit are turned on, the voltage of the voltage dividing node of the first voltage dividing unit is greater than the voltage of the voltage dividing node of the second voltage dividing unit, and the voltage difference between the voltage dividing node of the first voltage dividing unit and the ground terminal and the voltage difference between the voltage dividing node of the second voltage dividing unit and the ground terminal are both greater than 1.8V; The first current mirror unit mirrors the output current of the PMOS transistor MP1 to output a second current, the second current mirror unit mirrors the second current to output a third current, the third current is input to the drain electrode of the NMOS transistor MN1, the drain electrode of the NMOS transistor MN1 is electrically connected to the gate electrode of the PMOS transistor MP2, the gate electrode of the NMOS transistor MN1 is electrically connected to the second voltage dividing node of the second voltage dividing unit. When the second voltage dividing unit is turned on, the voltage of the voltage dividing node of the second voltage dividing unit is greater than the voltage of the second voltage dividing node, and the source electrode of the NMOS transistor MN1 is grounded; The first voltage dividing unit includes a resistor R1, a diode D1, a diode D2, a diode D3 and a diode D4 connected in series in sequence. The negative electrode of the diode D4 is grounded, the end of the resistor R1 not electrically connected to the diode D1 is electrically connected to the voltage input terminal, and the end of the resistor R1 electrically connected to the diode D1 is electrically connected to the source electrode of the PMOS transistor MP1; The first current mirror unit includes an NMOS transistor MN2, an NMOS transistor MN3 and an NMOS transistor MN4. The drain electrode of the PMOS transistor MP1 is respectively electrically connected to the drain electrode of the NMOS transistor MN2, the gate electrode of the NMOS transistor MN2, and the gate electrode of the NMOS transistor MN3. The source electrodes of the NMOS transistor MN2 and the NMOS transistor MN3 are both grounded. The drain electrode of the NMOS transistor MN3 is electrically connected to the source electrode of the NMOS transistor MN4. The gate electrode of the NMOS transistor MN4 is electrically connected to the gate electrode of the PMOS transistor MP1, and the drain electrode of the NMOS transistor MN4 is electrically connected to the second current mirror unit.

2. The bias voltage generation circuit for a radio frequency front-end chip according to claim 1, characterized in that, The second voltage dividing unit includes a resistor R2, a diode D5, a diode D6, and a diode D7 connected in series in sequence. The negative electrode of the diode D7 is grounded. One end of the resistor R2 that is not electrically connected to the diode D5 is electrically connected to the voltage input terminal. One end of the resistor R2 that is electrically connected to the diode D5 is electrically connected to the gate of the PMOS transistor MP1.

3. The bias voltage generation circuit of a radio frequency front-end chip according to claim 1, wherein, the second current mirror unit includes a PMOS transistor MP3 and a PMOS transistor MP4. The source electrodes of the PMOS transistor MP3 and the PMOS transistor MP4 are electrically connected to the voltage input terminal. The gate of the PMOS transistor MP3 is electrically connected to the gate of the PMOS transistor MP4, the drain of the PMOS transistor PM3, and the first current mirror unit respectively. The drain of the PMOS transistor MP4 is electrically connected to the drain of the NMOS transistor MN1.

4. The bias voltage generation circuit of a radio frequency front-end chip according to claim 1, wherein, the buck unit includes a diode D8. The positive electrode and the negative electrode of the diode D8 are electrically connected to the voltage input terminal and the voltage output terminal respectively.

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