A multi-core embedded system, a communication method, a device and a storage medium

Abstract

The application provides a multi-core embedded system, a communication method, equipment and a storage medium. The communication method is applied to the multi-core embedded system. The system includes at least two kernel chips. The memory space of a target chip includes a shared space and at least two target spaces. The target chip is one of the at least two kernel chips. The at least two kernel chips correspond to the at least two target spaces respectively. The communication method includes the following steps: the at least two kernel chips respectively communicate with the corresponding master devices based on the corresponding target spaces; and the at least two kernel chips communicate based on the shared space. In the application, the multiple kernel chips of the multi-core embedded system can respectively communicate with the corresponding master devices, and the multiple kernel chips can also communicate with each other, so that multi-party communication between the at least two kernel chips and the master devices is realized. The speed and accuracy of data interaction in the communication process can be greatly improved, and the communication efficiency and the safety of automatic driving are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, in particular to a multi-core embedded system, a communication method, a device and a storage medium. BACKGROUND

[0002] In the prior art, when a multi-core embedded system as a slave device communicates with a master device based on a peripheral component interconnect express (PCIE) interface, only one core chip of the multi-core embedded system can be connected to the master device for communication, and in this case, other core chips of the multi-core embedded system cannot be connected to the master device for communication, that is, only two-party communication can be achieved in the prior art, resulting in low communication efficiency. SUMMARY

[0003] The present application provides a multi-core embedded system, a communication method, a device and a storage medium, which can at least solve the technical problem of being unable to perform multi-party communication in the prior art.

[0004] According to an aspect of the present application, a communication method based on a multi-core embedded system is provided, the multi-core embedded system including at least two core chips, a memory space of a target chip including a shared space and at least two target spaces, the target chip being one of the at least two core chips, the at least two core chips respectively corresponding to the at least two target spaces, and the communication method including:

[0005] The at least two core chips respectively communicate with respective master devices based on respective target spaces;

[0006] The at least two core chips communicate based on the shared space.

[0007] In a possible implementation, the at least two core chips include a first microprocessor, a second microprocessor and a programmable device, the target chip is the programmable device, and the at least two target spaces include a first target space, a second target space and a third target space.

[0008] The at least two core chips respectively communicating with respective master devices based on respective target spaces includes:

[0009] The first microprocessor communicates with a master device corresponding to the first microprocessor based on the first target space;

[0010] The second microprocessor communicates with a master device corresponding to the second microprocessor based on the second target space;

[0011] The programmable device communicates with the master device corresponding to the third microprocessor based on the third target space.

[0012] In a possible implementation, the communication method further includes:

[0013] The target chip monitors read-write states of the at least two target spaces.

[0014] In a possible implementation, the monitoring, by the target chip, of the read-write states of the at least two target spaces includes:

[0015] When the first target space is read or written by the second microprocessor or the programmable device, the programmable device sends first interrupt information to the first microprocessor, and the first microprocessor generates first error information according to the first interrupt information.

[0016] When the second target space is read or written by the first microprocessor or the programmable device, the programmable device sends second interrupt information to the second microprocessor, and the second microprocessor generates second error information according to the second interrupt information.

[0017] When the third target space is read or written by the first microprocessor or the second microprocessor, the programmable device generates third interrupt information, and the programmable device generates third error information according to the third interrupt information.

[0018] In a possible implementation, the at least two target spaces are respectively provided with first regions and second regions.

[0019] The at least two kernel chips respectively communicate with the master devices corresponding to the respective target spaces based on the respective target spaces includes:

[0020] The at least two kernel chips respectively perform write operations based on the respective first regions and perform read operations based on the respective second regions.

[0021] The master devices perform read operations based on the first regions corresponding to the master devices and perform write operations based on the second regions corresponding to the master devices.

[0022] In a possible implementation, the multi-core embedded system is provided with a target interface, the target interface is adapted to the target spaces corresponding to the at least two kernel chips respectively, and the target interface is connected to the master devices through a high-speed serial computer expansion bus.

[0023] In a possible implementation, before the at least two kernel chips respectively communicate with the master devices corresponding to the respective target spaces based on the respective target spaces, the communication method further includes:

[0024] The memory space of the programmable device is divided to obtain the first target space, the second target space, the third target space, and the shared space.

[0025] In addition, according to an aspect of the present application, a multi-core embedded system is provided, including at least two core chips, a memory space of a target chip including a shared space and at least two target spaces, the target chip being one of the at least two core chips, the at least two core chips respectively corresponding to the at least two target spaces;

[0026] The at least two core chips are respectively connected in communication with respective corresponding host devices based on respective corresponding target spaces;

[0027] The at least two core chips are connected in communication based on the shared space.

[0028] According to an aspect of the present application, a communication device based on a multi-core embedded system is provided, including:

[0029] a processor;

[0030] a memory for storing processor-executable instructions;

[0031] The processor is configured to execute the above method.

[0032] According to an aspect of the present application, a non-volatile computer-readable storage medium having computer program instructions stored thereon is provided, the computer program instructions being executed by a processor to implement the above method.

[0033] In the present application, the target chip is one of the at least two core chips whose memory is editable. The editable memory of the target chip can be divided to obtain a shared space and at least two target spaces, the at least two target spaces one-to-one corresponding to the at least two core chips, the target space can be a base address register (Bar), and the shared space can be an on-chip space. In the present application, the core chip can communicate with the corresponding host device based on the corresponding target space. The core chip can perform read and write operations based on the corresponding target space, and the host device corresponding to the core chip can also perform read and write operations based on the target space corresponding to the core chip, thereby realizing communication between the core chip and the host device.

[0034] The at least two core chips can respectively communicate with the respective corresponding host devices based on the respective corresponding target spaces, so as to realize communication between the plurality of core chips of the multi-core embedded system and the corresponding host devices. The plurality of core chips can be at least two core chips, and the number of host devices can be one or more. In one example, any host device can communicate with any core chip. In another example, the plurality of host devices and the plurality of core chips can have a corresponding relationship, one host device can communicate with a specific one or more core chips, and one core chip can communicate with a specific one or more host devices. In addition, the plurality of core chips of the multi-core embedded system can perform read and write operations based on the shared space, so as to realize communication between the plurality of core chips. Thus, in this application, the plurality of core chips of one multi-core embedded system can respectively communicate with the corresponding host devices, and the plurality of core chips can also communicate with each other, so as to realize multi-party communication between the at least two core chips and the corresponding host devices, wherein the number of parties is three or more.

[0035] In this application, the plurality of core chips and the at least one host device of the multi-core embedded system can be connected by one bus, and the multi-core embedded system and the host device in this application do not need to use a bus bridge. Based on the target space and the shared space of the target chip, multi-party communication between the at least two core chips and the at least one host device can be realized, and the bandwidth will not be reduced, the data transmission efficiency can be improved, and the communication quality can be improved.

[0036] The multi-core embedded system provided in this application can be applied to a vehicle with an automatic driving function, and can be used for analyzing, processing, calculating, etc. related data during vehicle driving. Through the multi-party communication between the plurality of core chips and the host device of the multi-core embedded system provided in this application, the speed and accuracy of data interaction in the communication process can be greatly improved, the communication efficiency can be improved, and the safety of automatic driving can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1 a block diagram of a multi-core embedded system and a host device according to an exemplary embodiment;

[0039] Figure 2 a block diagram of a multi-core embedded system and a host device according to another exemplary embodiment;

[0040] Figure 3 is a block diagram of a multi-core embedded system and a host device according to another exemplary embodiment;

[0041] Figure 4 1 is a flow chart showing a communication method based on a multi-core embedded system according to an exemplary embodiment;

[0042] Figure 5 The figure is a flow chart showing a communication method based on a multi-core embedded system according to another exemplary embodiment. DETAILED DESCRIPTION

[0043] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0044] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0045] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0046] The present application proposes a multi-core embedded system, communication method, device and storage medium, which can at least solve the technical problem of the inability to carry out multi-party communication in the prior art. The present application is specifically implemented by the following technical solution.

[0047] Combine Figures 1 to 3 As shown, an embodiment of this specification provides a multi-core embedded system, including at least two core chips, the memory space of a target chip includes a shared space and at least two target spaces, the target chip is one of the at least two core chips, and the at least two core chips correspond to the at least two target spaces respectively;

[0048] At least two core chips are respectively connected to communicate with respective corresponding main devices based on respective corresponding target spaces;

[0049] At least two core chips are connected for communication based on a shared space.

[0050] An embedded system is a special-purpose computer system that is completely embedded in a controlled device and designed for a specific application. The multi-core embedded system (MPSOC) in the embodiments of the present specification can include at least two core chips, which can be used to complete computing, receiving or storing commands, processing data, and the like. The target chip is one of the at least two core chips that has an editable memory. By dividing the editable memory of the target chip, a shared space and at least two target spaces can be obtained, and the at least two target spaces one-to-one correspond to the at least two core chips. The target space can be a base address register (Bar), and the shared space can be an on-chip space.

[0051] In the embodiments of the present specification, the core chip can communicate with the corresponding master device based on the corresponding target space. The core chip can perform read and write operations based on the corresponding target space, and the master device corresponding to the core chip can also perform read and write operations based on the target space corresponding to the core chip, thereby realizing communication between the core chip and the master device.

[0052] The at least two core chips can respectively communicate with the corresponding master devices based on the respective target spaces, thereby realizing communication between the multiple core chips of the multi-core embedded system and the corresponding master devices. The multiple core chips can be the at least two core chips, and the number of master devices can be one or more. In one example, any master device can communicate with any core chip. In another example, the multiple master devices and the multiple core chips can have a corresponding relationship, one master device can communicate with a specific one or more core chips, and one core chip can communicate with a specific one or more master devices. In addition, the multiple core chips of the multi-core embedded system can perform read and write operations based on the shared space, thereby realizing communication between the multiple core chips. Thus, in the embodiments of the present specification, the multiple core chips of one multi-core embedded system can respectively communicate with the corresponding master devices, and the multiple core chips can also communicate with each other, thereby realizing multi-party communication between the at least two core chips and the corresponding master devices, wherein the multi-party refers to the sum of the number of core chips and master devices being three or more.

[0053] In the related art, when one core chip of the multi-core embedded system is communicatively connected with a master device, other core chips of the multi-core embedded system cannot be communicatively connected with the master device, i.e., only two-party communication between one core chip and one master device can be realized.

[0054] In the embodiments of the present specification, a plurality of core chips and at least one host device of a multi-core embedded system can be connected through a bus, and the multi-core embedded system in the embodiments of the present specification does not need to use a bus bridge between the multi-core embedded system and the host device; based on the target space and the shared space of the target chip, multi-party communication between at least two core chips and at least one host device can be realized, and the bandwidth is not reduced, the data transmission efficiency can be improved, and the communication quality can be improved.

[0055] The multi-core embedded system provided by the embodiments of the present specification can be applied to a vehicle with an automatic driving function, and can be used for analyzing, processing, calculating and the like of related data in the driving process of the vehicle. Through the multi-party communication between the plurality of core chips and the host device of the multi-core embedded system provided by the embodiments of the present specification, the speed and accuracy of data interaction in the communication process can be greatly improved, the communication efficiency can be improved, and the safety of automatic driving can be improved.

[0056] In combination with Figure 2 As shown in the figure, in a possible implementation, the at least two core chips include a first microprocessor 11, a second microprocessor 12 and a programmable device 13, the target chip is the programmable device 13, and the at least two target spaces include a first target space, a second target space and a third target space;

[0057] The first microprocessor 11 is connected in communication with a host device corresponding to the first microprocessor 11 based on the first target space;

[0058] The second microprocessor 12 is connected in communication with a host device corresponding to the second microprocessor 12 based on the second target space;

[0059] The programmable device 13 is connected in communication with a host device corresponding to the programmable device 13 based on the third target space.

[0060] The embodiments of the present specification can improve the multi-core embedded system based on the multi-core embedded system, so that multi-party communication between a plurality of memory chips and a host device of the multi-core embedded system is realized. In an example, the model of the first microprocessor 11 of the multi-core embedded system (MPSOC) can be Coretex A53, the model of the second microprocessor 12 can be Coretex R5, and the programmable device 13 can be a field programmable gate array (FPGA, Field Programmable Gate Array).

[0061] Field programmable gate array (FPGA) has the advantages of programmability, flexibility and versatility. FPGA can include hardware resources such as logic cells and multipliers, and by reasonably organizing these hardware resources, hardware circuits such as multipliers, registers and address generators can be realized. FPGA can be designed by using block diagrams; FPGA can be reprogrammed infinitely, and it only takes a few hundred milliseconds to load a new design, and the use of reconfiguration can reduce hardware overhead. The working frequency of FPGA is determined by the FPGA chip and the design, and some stringent requirements can be met by modifying the design or replacing a faster chip.

[0062] In the embodiments of the present specification, the number of master devices and the correspondence between the master devices and the kernel chip can be set according to actual needs.

[0063] In combination with Figure 2 As shown in FIG. 1, in one example, one master device 20 is provided, and the first microprocessor 11, the second microprocessor 12 and the programmable device 13 (FPGA) all correspond to the master device 20; the first microprocessor 11 and the master device 20 can both perform read-write operations based on a first target space of the FPGA, the second microprocessor 12 and the master device 20 can both perform read-write operations based on a second target space of the FPGA, the FPGA and the master device 20 can both perform read-write operations based on a third target space of the FPGA, and the first microprocessor 11, the second microprocessor 12 and the FPGA can also perform read-write operations based on a shared space of the FPGA.

[0064] In combination with Figure 3 As shown in FIG. 2, in another example, the first master device 21 and the second master device 22 are provided, the first microprocessor 11 corresponds to the first master device 21 and the second master device 22, the second microprocessor 12 corresponds to the second master device 22, and the programmable device 13 (FPGA) corresponds to the second master device 22; the first microprocessor 11, the first master device 21 and the second master device 22 can all perform read-write operations based on a first target space of the FPGA, the second microprocessor 12 and the second master device 22 can both perform read-write operations based on a second target space of the FPGA, and the FPGA and the second master device 22 can both perform read-write operations based on a third target space of the FPGA. The first microprocessor 11, the second microprocessor 12 and the FPGA can also perform read-write operations based on a shared space of the FPGA.

[0065] The target chip in the embodiments of the present specification divides the space based on the FPGA, and the first target space, the second target space, the third target space and the shared space are obtained by dividing the memory space in the FPGA, which is easy to implement.

[0066] In a possible implementation, the target chip is configured to monitor the read-write states of the at least two target spaces.

[0067] In an embodiment of the present specification, the read-write state of the target space can reflect the kernel chip currently performing read-write operation on the target space, and the target chip can monitor the read-write process between each kernel chip and the target space based on the read-write state of the target space. In one example, the target chip can determine an abnormal access process according to the read-write state of the target space and preset mapping information; the preset mapping information can represent the correspondence between the plurality of target spaces and the plurality of kernel chips; the abnormal access process can be that the target space and the kernel chip accessing the space do not correspond. In an embodiment of the present specification, the FPGA can monitor the read-write state of the first target space, the second target space, the third target space and the shared space, ensure that the kernel chip performs read-write operation on the target space corresponding to it, avoid the chip other than the kernel chip corresponding to the target space performing read-write operation on the target space, and improve the accuracy and security of communication data transmission.

[0068] In a possible implementation, the programmable device 13 is configured to send first interrupt information to the first microprocessor 11 when the second microprocessor 12 or the programmable device 13 performs read-write operation on the first target space; and the first microprocessor 11 is configured to generate first error information according to the first interrupt information.

[0069] The programmable device 13 is configured to send second interrupt information to the second microprocessor 12 when the first microprocessor 11 or the programmable device 13 performs read-write operation on the second target space; and the second microprocessor 12 is configured to generate second error information according to the second interrupt information.

[0070] The programmable device 13 is configured to generate third interrupt information when the first microprocessor 11 or the second microprocessor 12 performs read-write operation on the third target space; and the programmable device 13 is configured to generate third error information according to the third interrupt information.

[0071] In an embodiment of the present specification, the first target space corresponds to the first microprocessor 11, and the first microprocessor 11 can perform read-write operation based on the first target space; if the second microprocessor 12 or the programmable device 13 performs read-write operation on the first target space, the programmable device 13 can monitor the read-write operation and send first interrupt information to the first microprocessor 11, indicating that the first microprocessor 11 currently has other kernel chips reading and writing the first target space, and the first microprocessor 11 can generate first error information according to the first interrupt information, and prohibit other kernel chips from reading and writing the first target space. The interrupt information in the present specification is information generated based on the interrupt mechanism.

[0072] In one example, the programmable device 13 can monitor the read-write state of the first target space, and the read-write state of the first target space can reflect the chip identification information of the core chip reading and writing the first target space. The programmable device 13 can perform matching processing on the read-write state of the first target space and the space identification information of the first target space according to the preset mapping information. The preset mapping information can represent the correspondence between the plurality of target spaces and the plurality of core chips. If the matching result is successful, it indicates that the core chip currently accessing the first target space can perform read-write operation based on the first target space. If the matching result is failed, it indicates that the core chip currently accessing the first target space cannot perform read-write operation based on the first target space, and the programmable device 13 sends the first interrupt information to the first microprocessor 11.

[0073] The second target space corresponds to the second microprocessor 12, and the second microprocessor 12 can perform read-write operation based on the second target space. If the first microprocessor 11 or the programmable device 13 performs read-write operation on the second target space, the programmable device 13 can monitor the read-write operation and send the second interrupt information to the second microprocessor 12, indicating that the second microprocessor 12 currently has other core chips reading and writing the second target space. The second microprocessor 12 can generate the second error information according to the second interrupt information, and prohibit other core chips from reading and writing the second target space.

[0074] The third target space corresponds to the programmable device 13, and the programmable device 13 can perform read-write operation based on the third target space. If the first microprocessor 11 or the second microprocessor 12 performs read-write operation on the third target space, the programmable device 13 can monitor the read-write operation and generate the third interrupt information, indicating that the programmable device 13 currently has other core chips reading and writing the third target space. The programmable device 13 can generate the third error information according to the third interrupt information, and prohibit other core chips from reading and writing the third target space.

[0075] The embodiments of the present specification can realize monitoring of the target space based on the FPGA, which is easy to implement, avoids the chips other than the core chip corresponding to the target space from performing read-write operation on the target space, and improves the accuracy and security of communication data transmission.

[0076] In one possible implementation, the at least two target spaces are respectively provided with first regions and second regions;

[0077] The at least two core chips perform write operation based on the respective corresponding first regions, and perform read operation based on the respective corresponding second regions;

[0078] The host device performs read operation based on the first region corresponding to the host device, and performs write operation based on the second region corresponding to the host device.

[0079] In combinationFigure 2 As shown, in one example, the host device 20 can read and write the first target space when communicating with the first microprocessor 11. The first target space can include a corresponding first region and a second region, wherein the first region of the first target space is used for the first microprocessor 11 to write and the host device 20 to read, and the second region of the first target space is used for the first microprocessor 11 to read and the host device 20 to write, so that the entire data interaction will not generate errors such as overwriting, and the first microprocessor 11 and the host device 20 can also notify each other based on the interrupt mechanism after the respective read and write ends.

[0080] The host device 20 can read and write the second target space when communicating with the second microprocessor 12. The second target space can include a corresponding first region and a second region, wherein the first region of the second target space is used for the second microprocessor 12 to write and the host device 20 to read, and the second region of the second target space is used for the second microprocessor 12 to read and the host device 20 to write, so that the second microprocessor 12 and the host device 20 can also notify each other based on the interrupt mechanism after the respective read and write ends.

[0081] The host device 20 can read and write the third target space when communicating with the programmable device 13. The third target space can include a corresponding first region and a second region. The first region of the third target space is used for the programmable device 13 to write and the host device 20 to read, and the second region of the third target space is used for the programmable device 13 to read and the host device 20 to write, so that the entire data interaction will not generate errors such as overwriting, and the programmable device 13 and the host device 20 can also notify each other based on the interrupt mechanism after the respective read and write ends.

[0082] In the embodiments of the present specification, each target space can include a first region and a second region, the first region is used for the corresponding kernel chip to perform a write operation and for the corresponding host device to perform a read operation, and the second region is used for the corresponding kernel chip to perform a read operation and for the corresponding host device to perform a write operation, so that the entire data interaction will not generate errors such as overwriting, and the accuracy of data interaction in the communication process can be improved.

[0083] In one possible implementation, the multi-core embedded system is provided with a target interface, the target interface is adapted to the respective target spaces of the at least two kernel chips, and the target interface is connected to the host device through a high-speed serial computer expansion bus.

[0084] In the embodiments of the present specification, the high-speed serial computer expansion bus can be a peripheral component interconnect express (PCIE) bus, and the target interface can be a PCIE interface. In the embodiments of the present specification, one PCIE bus can be connected to the PCIE interface of a multi-core embedded system and at least one host device at the same time. In the multi-core embedded system in the embodiments of the present specification, the multi-core embedded system and the host device do not need to use a bus bridge to realize multi-party communication between at least two kernel chips and the host device, and the bandwidth is not reduced, the data transmission efficiency is improved, and the communication quality is improved.

[0085] In the prior art, the peripheral component interconnect express (PCIE) interface of the high-speed serial computer expansion bus standard can only realize two-party communication between a host device (pcie host) and a slave device (pcie device). In the prior art, a multi-core embedded system (MPSOC) includes 4 CoretexA53, 2 coretexR5, and 1 fpga, and the fpga includes a large number of logic resources.

[0086] The multi-core embedded system provided in the embodiments of the present specification can construct a pcie slave device through fpga logic resources, so as to be connected with other peripherals; in some scenarios, CoretexA53 runs a linux operating system, CoretexR5 runs bare, and FPGA can all communicate with the pcie host through the pcie, to realize four-party communication, and all the four parties communicate through the PCIE interface. In the embodiments of the present specification, the 4 CoretexA53 can communicate with the corresponding host device based on the same target space, and the 2 coretexR5 can communicate with the corresponding host device based on the same target space.

[0087] The embodiments of the present specification improve the FPGA, construct a special pcie device logic based on the FPGA, and realize four-party communication based on the pcie interface. In the embodiments of the present specification, the memory space based on the FPGA is divided into 4 spaces for CoretexA53, CoretexR5, FPGA, and Host four-party communication interaction, wherein:

[0088] The first target space (bar1) is used for data read-write communication between the pcie host and CoretexA53, and if other read-write of the target space causes a corresponding read-write exception interrupt to CoretexA53.

[0089] Second target space (bar2): used for pcie host and Coretex R5 to communicate data read and write, if other read and write this target space will produce corresponding read and write exception interrupt to Coretex R5.

[0090] Third target space (bar3): used for pcie host and FPGA to communicate data read and write, if other read and write this target space will produce corresponding read and write exception interrupt to FPGA.

[0091] Shared space (On-Chip Space): used for Coretex A53, Coretex R5 and FPGA to communicate data read and write, this space is the read and write interaction space between the multi-core embedded system, this space cannot be accessed by pcie host because it is not reflected to pcie host through base address register (bar).

[0092] In the embodiment of the present specification, when pcie host communicates with Coretex A53, pcie host writes data to the first area of the first target space, then informs Coretex A53 based on the interrupt mechanism, then Coretex A53 reads the data in the first area of the first target space; conversely, when Coretex A53 communicates with pcie host, it can write data to the second area of the first target space, then informs pcie host based on the interrupt mechanism, then pcie host reads the data in the second area of the first target space. In this way, the communication between the two parties is realized, and the communication of the other several parties is carried out in the same way, thereby realizing the mutual communication of the four communication subjects.

[0093] In combination with Figures 4 to 5 The embodiment of the present specification provides a communication method based on a multi-core embedded system, applied to a multi-core embedded system, the multi-core embedded system includes at least two core chips, the memory space of a target chip includes a shared space and at least two target spaces, the target chip is one of the at least two core chips, and the at least two core chips correspond to the at least two target spaces respectively. The communication method comprises:

[0094] Step S101: at least two core chips respectively communicate with the respective corresponding master devices based on the respective corresponding target spaces;

[0095] Step S102: at least two core chips communicate based on the shared space.

[0096] An embedded system is a dedicated computer system that is completely embedded inside a controlled device and designed for a specific application. The multi-core embedded system (MPSOC) in the embodiments of this specification may include at least two core chips, which can be used to perform operations such as calculations, receiving or storing commands, and processing data. The target chip is a chip with editable memory among the at least two core chips. The editable memory of the target chip can be divided and processed to obtain a shared space and at least two target spaces, and the at least two target spaces correspond one to one to the at least two core chips. The target space can be a base address register (Bar), and the shared space can be an on-chip space.

[0097] In the embodiments of this specification, a core chip can communicate with a corresponding master device based on a corresponding target space. The core chip can perform read and write operations based on the corresponding target space, and the master device corresponding to the core chip can also perform read and write operations based on the target space corresponding to the core chip, thereby achieving communication between the core chip and the master device.

[0098] At least two core chips can communicate with their respective corresponding master devices based on their respective corresponding target spaces, thereby enabling communication between multiple core chips of a multi-core embedded system and their corresponding master devices, wherein the multiple core chips can be at least two core chips, and the number of master devices can be one or more. In one example, any master device can communicate with any core chip. In another example, there can be a corresponding relationship between multiple master devices and multiple core chips, where a master device can communicate with one or more specific core chips, and a core chip can communicate with one or more specific master devices. In addition, multiple core chips of a multi-core embedded system can perform read and write operations based on a shared space, thereby enabling communication between multiple core chips. Therefore, in the embodiments of this specification, multiple core chips of a multi-core embedded system can communicate with their corresponding master devices, and multiple core chips can also communicate with each other, thereby enabling multi-party communication between at least two core chips and their corresponding master devices, wherein multi-party means that the total number of core chips and master devices is three or more.

[0099] In related technologies, when one core chip of a multi-core embedded system is connected to a main device for communication, other core chips of the multi-core embedded system cannot be connected to the main device for communication, that is, only two-way communication can be achieved between one core chip and one main device.

[0100] In the embodiments of the present specification, a plurality of core chips and at least one host device of a multi-core embedded system can be connected through a bus, and the multi-core embedded system and the host device in the embodiments of the present specification do not need to use a bus bridge; based on a target space and a shared space of a target chip, multi-party communication between at least two core chips and at least one host device can be realized, and the bandwidth is not reduced, the data transmission efficiency can be improved, and the communication quality can be improved.

[0101] The multi-core embedded system provided by the embodiments of the present specification can be applied to a vehicle with an automatic driving function, and can be used for analyzing, processing, calculating and the like of related data in the driving process of the vehicle. Through the multi-party communication between the plurality of core chips and the host device of the multi-core embedded system provided by the embodiments of the present specification, the speed and accuracy of data interaction in the communication process can be greatly improved, the communication efficiency can be improved, and the safety of automatic driving can be improved.

[0102] In a possible implementation, the at least two core chips include a first microprocessor 11, a second microprocessor 12 and a programmable device 13, the target chip is the programmable device 13, and the at least two target spaces include a first target space, a second target space and a third target space.

[0103] Step S101 includes:

[0104] Step S1011: The first microprocessor 11 communicates with the host device corresponding to the first microprocessor based on the first target space.

[0105] Step S1012: The second microprocessor 12 communicates with the host device corresponding to the second microprocessor based on the second target space.

[0106] Step S1013: The programmable device 13 communicates with the host device corresponding to the third microprocessor based on the third target space.

[0107] In a possible implementation, the communication method further includes step S103:

[0108] The target chip monitors the read-write state of the at least two target spaces.

[0109] In a possible implementation, step S103 includes:

[0110] When the second microprocessor 12 or the programmable device 13 reads and writes the first target space, the programmable device 13 sends first interrupt information to the first microprocessor 11, and the first microprocessor 11 generates first error information according to the first interrupt information.

[0111] When the first microprocessor 11 or the programmable device 13 performs read and write on the second target space, the programmable device 13 sends second interrupt information to the second microprocessor 12, and the second microprocessor 12 generates second error report information according to the second interrupt information;

[0112] When the first microprocessor 11 or the second microprocessor 12 performs read and write on the third target space, the programmable device 13 generates third interrupt information, and the programmable device 13 generates third error report information according to the third interrupt information.

[0113] In a possible implementation, the at least two target spaces are respectively provided with a first region and a second region;

[0114] The at least two kernel chips respectively communicate with the respective corresponding master device based on the respective corresponding target space, and the communication comprises:

[0115] The at least two kernel chips respectively perform write operation based on the respective corresponding first region and perform read operation based on the respective corresponding second region;

[0116] The master device performs read operation based on the first region corresponding to the master device and performs write operation based on the second region corresponding to the master device.

[0117] In a possible implementation, the multi-core embedded system is provided with a target interface, the target interface is adapted to the respective corresponding target space of the at least two kernel chips, and the target interface is connected to the master device through a high-speed serial computer expansion bus.

[0118] In a possible implementation, before the step S101, the communication method further comprises:

[0119] The memory space of the programmable device 13 is divided to obtain the first target space, the second target space, the third target space and the shared space.

[0120] The embodiment of the present specification also provides a communication device based on a multi-core embedded system, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to execute the above method.

[0121] In addition, the embodiment of the present specification also provides a non-volatile computer readable storage medium, which stores computer program instructions, and the computer program instructions are executed by the processor to implement the above communication method based on the multi-core embedded system.

[0122] The computer program product can include a computer readable storage medium on which is loaded a computer readable program of instructions for causing a processor to implement various aspects of the present application.

[0123] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0124] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0125] Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0126] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0127] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0128] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0129] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0130] Embodiments of the present application have been described above, and the description is intended to be illustrative, and not restrictive, of the disclosed embodiments. Many modifications and variations of the described embodiments are possible, and all such modifications and variations are intended to be within the scope of the described embodiments. No aspect of this application is intended to be dedicated to the public unless the disclosure explicitly states otherwise. The use of the terms "embodiment" or "the embodiment" does not mean that a single embodiment is intended. Indeed, the specific embodiments of the present application are intended to be examples of embodiments of the present application and not a limitation thereof. The scope of the present application is intended to cover all possible modifications and variations.

Claims

1. A communication method based on a multi-core embedded system, characterized by, The multi-core embedded system comprises at least two core chips, a memory space of a target chip comprises a shared space and at least two target spaces, the target chip is one of the at least two core chips, the at least two core chips correspond to the at least two target spaces respectively, the at least two core chips comprise a first microprocessor, a second microprocessor and a programmable device, the target chip is the programmable device, and the at least two target spaces comprise a first target space, a second target space and a third target space. The communication method comprises: The first microprocessor communicates with a host device corresponding to the first microprocessor based on the first target space; the second microprocessor communicates with a host device corresponding to the second microprocessor based on the second target space; the programmable device communicates with a host device corresponding to the programmable device based on the third target space; the multi-core embedded system is provided with a target interface, the target interface is adapted to the target spaces corresponding to the at least two core chips respectively, and the target interface is connected with the host devices through a high-speed serial computer expansion bus. The at least two core chips communicate based on the shared space.

2. The communication method based on a multi-core embedded system according to claim 1, wherein, The communication method further comprises: The target chip monitors read and write states of the at least two target spaces.

3. The communication method based on a multi-core embedded system according to claim 2, wherein, The target chip monitors read and write states of the at least two target spaces, which comprises: When the second microprocessor or the programmable device reads and writes the first target space, the programmable device sends first interrupt information to the first microprocessor, and the first microprocessor generates first error information according to the first interrupt information; When the first microprocessor or the programmable device reads and writes the second target space, the programmable device sends second interrupt information to the second microprocessor, and the second microprocessor generates second error information according to the second interrupt information; When the first microprocessor or the second microprocessor reads and writes the third target space, the programmable device generates third interrupt information, and the programmable device generates third error information according to the third interrupt information.

4. The communication method based on a multi-core embedded system according to Claim 1, wherein, The at least two target spaces are respectively provided with a first region and a second region; The at least two core chips respectively communicate with the host devices corresponding to the at least two core chips based on the target spaces corresponding to the at least two core chips, which comprises: The at least two core chips respectively perform write operation based on the first regions corresponding to the at least two core chips and perform read operation based on the second regions corresponding to the at least two core chips; The host devices perform read operation based on the first regions corresponding to the host devices and perform write operation based on the second regions corresponding to the host devices.

5. The communication method based on a multi-core embedded system according to Claim 1, wherein, Before the at least two core chips respectively communicate with the host devices corresponding to the at least two core chips based on the target spaces corresponding to the at least two core chips, the communication method further comprises: The memory space of the programmable device is divided to obtain the first target space, the second target space, the third target space and the shared space.

6. A multi-core embedded system, characterized by The multi-core embedded system comprises at least two core chips, a memory space of a target chip comprises a shared space and at least two target spaces, the target chip is one of the at least two core chips, the at least two core chips correspond to the at least two target spaces respectively, the at least two core chips comprise a first microprocessor, a second microprocessor and a programmable device, the target chip is the programmable device, and the at least two target spaces comprise a first target space, a second target space and a third target space. The first microprocessor communicates with a host device corresponding to the first microprocessor based on the first target space. The second microprocessor communicates with a host device corresponding to the second microprocessor based on the second target space, and the programmable device communicates with a host device corresponding to the programmable device based on the third target space. The multi-core embedded system is provided with a target interface, the target interface is adapted to the target spaces corresponding to the at least two core chips respectively, and the target interface is connected with the host devices through a high-speed serial computer expansion bus.

7. A communication device based on a multi-core embedded system, characterized in that, The at least two core chips are connected in communication based on the shared space. It comprises: a processor; a memory for storing processor-executable instructions; 8. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein, wherein the processor is configured to perform the method of any one of claims 1 to 5. The computer program instructions, when executed by the processor, implement the method of any one of claims 1 to 5.

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