Data storage device and method of operating a data storage device

Abstract

The present technology relates to an electronic device. Based on the present technology, a storage device that provides improved security functions can include a memory device including a protected storage block configured to store information for authentication of data to be read from or written to the memory device, and protected by a security protocol; and a memory controller coupled to the memory device to control its operation, and configured to receive a command protocol unit associated with the security protocol in a command, the command including a host-side protection message requesting writing of data from a host to the protected storage block, and configured to perform a computation of a device message authentication code used in an authentication operation of the protected storage block, wherein the computation is performed concurrently with receiving a plurality of data units, the plurality of data units including data from the host to be written to the protected storage block.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2020-0154040, filed on November 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed technology relates to an electronic device, and more particularly, to a storage device and a method of operating the storage device. Background Technology

[0004] A data storage device is a means for storing or providing data in response to a request from a host device such as a computer or smartphone. Such a data storage device may include one or more memory devices for storing data and a memory controller for controlling the one or more memory devices. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices retain their data only while the device is powered on, and lose their data when power is turned off. Volatile memory devices can include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices retain stored data even when there is no power supply, so they do not lose their data when power is lost. Non-volatile memory devices include, for example, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0007] The embodiments of the disclosed technology relate to apparatus and methods that can improve the security of data storage devices, as well as methods for operating data storage devices.

[0008] A storage device based on embodiments of the disclosed technology includes a memory device including a protected storage block configured to store information for authentication of data to be read from or written to the memory device and protected by a security protocol, and a memory controller coupled to the memory device to control operation of the memory device and configured to receive a command protocol unit associated with the security protocol in a command including a host-side protection message requesting writing of data from a host to the protected storage block and to perform a computation of a device message authentication code used in an authentication operation of the protected storage block, the computation being performed concurrently with receiving a plurality of data units including data from the host to be written to the protected storage block.

[0009] In some embodiments of the disclosed technology, a data storage device providing improved security functionality and a method of operating the data storage device are provided. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a diagram illustrating an example of a data storage device based on embodiments of the disclosed technology.

[0011] Figure 2 is a diagram illustrating an example of a memory device of Figure 1 .

[0012] Figure 3 is a diagram illustrating an example configuration of a storage block of Figure 2 .

[0013] Figure 4 is a diagram illustrating an access operation to a replay protection block.

[0014] Figure 5 is a diagram illustrating a data structure of data transmitted between a replay protection block host controller and a replay protection block device controller.

[0015] Figure 6 is a diagram illustrating a structure of a basic header segment of a protocol unit or a protocol information unit (PIU).

[0016] Figure 7 is a diagram illustrating an example of a structure of a replay protection block message used when performing a replay protection block write operation or a replay protection block read operation.

[0017] Figure 8 is a diagram illustrating an example of a replay protection block write operation.

[0018] Figures 9A-9C is a diagram illustrating an example of a replay protection block read operation based on some embodiments of the disclosed technology. Figure 8FIG. 1 is a diagram illustrating an example of a replay protection block message provided during a replay protection block write operation.

[0019] Figure 10 FIG. 2 is a flowchart illustrating a replay protection block write operation based on embodiments of the disclosed technology.

[0020] Figure 11 FIG. 3 is a diagram illustrating an example of a command PIU based on some embodiments of the disclosed technology. Figure 10

[0021] Figure 12 FIG. 4 is a diagram illustrating an example of a response PIU based on some embodiments of the disclosed technology. Figure 10

[0022] Figure 13 FIG. 5 is a diagram illustrating an operation of a replay protection block host controller based on embodiments of the disclosed technology. Figure 4

[0023] Figure 14 FIG. 6 is a diagram illustrating an example of an operation by a data storage device to compute a message authentication code (MAC).

[0024] Figure 15 FIG. 7 is a diagram illustrating another embodiment of an operation by a data storage device to compute a MAC.

[0025] Figure 16 FIG. 8 is a block diagram illustrating an example of a structure of a data storage device based on embodiments of the disclosed technology.

[0026] Figure 17 FIG. 9 is a diagram illustrating another example of a memory controller based on some embodiments of the disclosed technology. Figure 1

[0027] FIG. 10 is a block diagram illustrating a memory card system including a data storage device based on embodiments of the disclosed technology. Figure 18

[0028] FIG. 11 is a block diagram illustrating a solid state drive (SSD) system including a data storage device based on embodiments of the disclosed technology. Figure 19

[0029] FIG. 12 is a block diagram illustrating a user system including a data storage device based on embodiments of the disclosed technology. Figure 20 DETAILED DESCRIPTION

[0030] The technology disclosed in this patent document can be implemented in some embodiments to provide data storage devices and data storage methods that, among other features and advantages, can provide improved security through the use of security protocols such as replay protection of storage blocks.​​​​

[0031] Figure 1 is a diagram showing an example of a data storage device based on an embodiment of the disclosed technology.

[0032] Referring to Figure 1 , the storage device 50 can include a memory device 100 and a memory controller 200. In this patent document, the term "storage device" is used to indicate a data storage device. The storage device 50 can be a device that stores data under the control of a host 400 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or a car infotainment system. Alternatively, the storage device 50 can be a device that stores data under the control of a host 400 that stores high-capacity data in one place such as a server or a data center.

[0033] Based on a host interface as a communication method with the host 400, the storage device 50 can be manufactured as one of various types of storage devices. For example, the storage device 50 can be configured as any one of various types of storage devices such as an SSD, a multimedia card in the form of an RS-MMC and a micro-SD, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a high-speed PCI (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0034] The storage device 50 can be manufactured as any one of various types of packages. For example, the storage device 50 can be manufactured as any one of various types of package types such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level package (WSP).

[0035] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 can include a memory cell array (not shown) including a plurality of memory cells that store data.

[0036] Each of the memory cells can be configured as a single layer cell (SLC) that stores one bit of data, a multi layer cell (MLC) that stores two bits of data, a triple layer cell (TLC) that stores three bits of data, or a quad layer cell (QLC) that is capable of storing four bits of data.

[0037] The memory cell array (not shown) can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. Each memory block can include a plurality of pages. In an embodiment, a page can be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block can be a unit for erasing data.

[0038] The memory blocks included in the memory device 100 can include a protected memory block, such as a replay protected block or a replay protected memory block (RPMB) 110a, and a normal block (Normal BLK) 110b.

[0039] The protected memory block is configured to store information for authenticating data to be read from or written to the memory device, and is protected by a security protocol. The replay protected block or RPMB 110a is one example of such a protected memory block that is accessible only through a security protocol, such as using a predetermined special command or authentication. The write count of the replay protected block 110a can be limited to a predetermined number by the host 400. When a write operation corresponding to the maximum write counter value of the replay protected block 110a is performed, only a read operation can be allowed for the replay protected block 110a.

[0040] In some embodiments, the replay protected block or RPMB can include a secure memory block for storing a small amount of sensitive information. In one example, the replay protected block or RPMB can be configured to enable a device to store data in a smaller specific area that is authenticated and protected from a replay attack, which occurs when a piece of malware running a replay attack intercepts an initial message between the correct entities and then resends or replays the same message at a later stage. To protect sensitive information from such a replay attack, RPMB authentication key information is first written to a secure memory block by the host, and then used by both the host and the memory device to authenticate read and write messages involving the RPMB area.

[0041] The size of the write data (e.g., data written to the protected memory block) of the protected memory block, such as the replay protected block 110a, can be predetermined. For example, the data stored in the replay protected block 110a can be in units of 128 KB (kilobytes). In an embodiment, the maximum data size of the data stored in the replay protected block 110a can be 16 MB (megabytes).

[0042] Access to the replay protection block 110a can be allowed only when authentication is successful. Authentication to the replay protection block 110a can be implemented by each of the host 400 and the storage 50 storing the same authentication key only once at first time, and determining whether a message authentication code (MAC) generated using the data to be stored by each of the host 400 and the storage 50 matches the authentication key. In some embodiments, the message authentication code includes a piece of information for confirming that a message is from a specified sender and has not been altered. In some embodiments, the MAC can be generated by each of the host 400 and the storage 50 using a hash-based MAC such as HMAC Secure Hash Algorithm (SHA)-256. In the replay protection block 110a, the data stored in the replay protection block 110a can be maintained while the authentication key and the value of the write counter are maintained.

[0043] In Figure 1 the memory device 100 includes one replay protection block 110a, but the memory device 100 can include two or more replay protection blocks 110a. In this case, each replay protection block 110a can have a unique authentication key and a write count value.

[0044] The normal block can be a storage block that can be accessed without requiring separate authentication. The normal block can be a storage block that stores data other than the data stored in the replay protection block 110a.

[0045] In an embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), or the like. In the present specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

[0046] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access a region selected by the addresses in the array of memory cells. The memory device 100 can perform an operation indicated by the commands on the region selected by the addresses. For example, the memory device 100 can perform a write operation (a program operation), a read operation, and an erase operation. During the program operation, the memory device 100 can program data in the region selected by the addresses. During the read operation, the memory device 100 can read data from the region selected by the addresses. During the erase operation, the memory device 100 can erase data stored in the region selected by the addresses.

[0047] The memory controller 200 can control overall operations of the storage 50.

[0048] When the storage 50 is powered on, the memory controller 200 can run a firmware (FW) operation. When the memory device 100 is a flash memory device, the memory controller 200 can run a firmware such as a flash translation layer (FTL) for controlling communication between the host 400 and the memory device 100.

[0049] In an embodiment, the memory controller 200 can receive data and a logical block address (LBA) from the host 400 and can convert the LBA to a physical block address (PBA) indicating an address of a memory cell in which data to be stored is included in the memory device 100.

[0050] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, or an erase operation based on a request of the host 400. During the program operation, the memory controller 200 can provide a program command, a PBA, and data to the memory device 100. During the read operation, the memory controller 200 can provide a read command and a PBA to the memory device 100. During the erase operation, the memory controller 200 can provide an erase command and a PBA to the memory device 100.

[0051] In an embodiment, the memory controller 200 can autonomously generate a command, an address, and data regardless of a request from the host 400 and transmit the command, the address, and the data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with a command, an address, and data for performing a program operation, a read operation, and an erase operation when wear leveling, read recycling, garbage collection, etc. are performed in conjunction.

[0052] In an embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 based on an interleaving method to improve operation performance. The interleaving method can be a method of controlling operations of at least two memory devices 100 to overlap each other.

[0053] The memory controller 200 can include a replay protection block device controller 210.

[0054] The replay protection block device controller 210 can process an access request to the replay protection block 110a.

[0055] The replay protection block device controller 210 can process a replay protection block write operation to store data in the replay protection block 110a and a replay protection block read operation to read data stored in the replay protection block 110a. Referring to a detailed description of the replay protection block device controller 210 to be described later, Figures 4-19 The specific method in which the replay protection block device controller 210 processes the replay protection block write operation and the replay protection block read operation will be described in more detail.

[0056] The host 400 can communicate with the memory device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multi-Media Card (MMC), Embedded MMC (eMMC), Dual In-Line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0057] The host 400 can further include a replay protection block host controller 410.

[0058] The replay protection block host controller 410 can generate various requests or commands for controlling the replay protection block 110a, and provide the various requests or commands to the replay protection block device controller 210. The replay protection block host controller 410 can receive a response or a processing result from the replay protection block device controller 210.

[0059] Figure 2 is a diagram illustrating an example of a memory device of Figure 1

[0060] Referring to Figure 2 , the memory device 100 can include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.​

[0061] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi. The plurality of memory blocks BLK1 to BLKi are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKi can be connected to the input / output circuit 140 through column lines CL. In an embodiment, the row lines RL can include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL can include bit lines.

[0062] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells can be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells can be defined as one physical page. That is, the memory cell array 110 can include a plurality of physical pages. Each of the memory cells of the memory device 100 can be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) capable of storing four bits of data.

[0063] The plurality of memory blocks BLK1 to BLKi can include a replay protection block 110a and a normal block 110b as shown in Figure 1

[0064] In an embodiment, the voltage generator 120, the address decoder 130, and the input / output circuit 140 can be collectively referred to as a peripheral circuit. The peripheral circuit can be used to operate the memory cell array 110 under the control of the control logic 150. The peripheral circuit can be used to perform a program operation, a read operation, and an erase operation on the memory cell array 110.

[0065] The voltage generator 120 is configured to generate a plurality of operating voltages using an external supply voltage supplied to the memory device 100. The voltage generator 120 operates in response to the control of the control logic 150.

[0066] In some embodiments, the voltage generator 120 can generate an internal supply voltage by regulating the external supply voltage. The internal supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100.

[0067] In some embodiments, the voltage generator 120 can generate a plurality of operating voltages using the external supply voltage or the internal supply voltage. The voltage generator 120 can be configured to generate various voltages required in the memory device 100. For example, the voltage generator 120 can generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selected read voltages, and a plurality of unselected read voltages.

[0068] ​The voltage generator 120 can include a plurality of pump capacitors that receive an internal power supply voltage to generate a plurality of operating voltages having various voltage levels, and can generate the plurality of operating voltages by selectively activating the plurality of pump capacitors in response to control of the control logic 150.

[0069] The generated plurality of operating voltages can be supplied to the memory cell array 110 by the address decoder 130.

[0070] The address decoder 130 is connected to the memory cell array 110 through a row line RL. The address decoder 130 is configured to operate in response to control of the control logic 150. The address decoder 130 can receive an address ADDR from the control logic 150. The address decoder 130 can decode a block address among the received address ADDR. The address decoder 130 can select at least one memory block among the memory blocks BLK1 to BLKi based on the decoded block address. The address decoder 130 can decode a row address among the received address ADDR. The address decoder 130 can select at least one word line among word lines of the selected memory block based on the decoded row address. In an embodiment, the address decoder 130 can decode a column address among the received address ADDR. The address decoder 130 can connect the input / output circuit 140 and the memory cell array 110 to each other based on the decoded column address.

[0071] For example, the address decoder 130 can include components such as a row decoder, a column decoder, and an address buffer.

[0072] The input / output circuit 140 can include a plurality of page buffers. The plurality of page buffers can be connected to the memory cell array 110 through bit lines. During a program operation, data can be stored in selected memory cells based on data stored in the plurality of page buffers.

[0073] During a read operation, data stored in selected memory cells can be sensed through bit lines, and the sensed data can be stored in the page buffers.

[0074] The control logic 150 can control the address decoder 130, the voltage generator 120, and the input / output circuit 140. The control logic 150 can operate in response to a command CMD transmitted from an external device. The control logic 150 can generate a control signal to control the peripheral circuit in response to the command CMD and the address ADDR.

[0075] Figure 3 is a diagram illustrating an example configuration of a memory block of Figure 2 .

[0076] The memory block BLKi is Figure 2any one of the storage blocks BLK1 to BLKi.

[0077] Referring to Figure 3 The plurality of word lines arranged in parallel with each other can be connected between a first selection line and a second selection line. Here, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically, the storage block BLKi can include a plurality of strings (strings of memory cells) ST connected between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn can be connected to the strings ST, respectively, and the source line SL can be commonly connected to the strings ST. Since the strings ST can be configured to be identical to each other, a string ST connected to the first bit line BL1 is specifically described as an example.

[0078] The string ST can include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. One string ST can include at least one or more of the source selection transistor SST and the drain selection transistor DST, and can include more memory cells MC1 to MC16 than the number shown in the drawing.

[0079] The source of the source selection transistor SST can be connected to the source line SL, and the drain of the drain selection transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different strings ST can be connected to the source selection line SSL, the gates of the drain selection transistors DST can be connected to the drain selection line DSL, and the gates of the memory cells MC1 to MC16 can be connected to the plurality of word lines WL1 to WL16. A group of memory cells among the memory cells included in different strings ST connected to the same word line can be referred to as a page PG. Accordingly, the storage block BLKi can include the number of pages PG of the word lines WL1 to WL16.

[0080] In some embodiments, each memory cell can function as a single-layer cell (SLC) to store one bit of data. In this case, one physical page PG can store data of one logical page (LPG). One logical page (LPG) data can include the same number of data bits as the number of cells included in one physical page PG.

[0081] In some embodiments, each memory cell can store two or more bits of data. In this case, one physical page PG can store data of two or more logical pages (LPGs).

[0082] Figure 4is a diagram showing an access operation to a replay protection block.

[0083] Referring to Figure 4 , the storage device 50 can include a replay protection block 110a and a replay protection block device controller 210 that controls the replay protection block 110a. The replay protection block 110a can be one of the storage blocks included in the memory device 100 as illustrated in FIG. 1, and the replay protection block device controller 210 can be included in the memory controller 200. Figure 1

[0084] The replay protection block 110a can include an authentication key 111, a write counter 112, a result register 113, and a replay protection block data area (RPMB Data Area) 114.

[0085] In some embodiments, the authentication key 111 can include a memory space of an authentication key. In some embodiments, the authentication key 111 can be stored only once, can not be read, and can be accessed only when a MAC for authentication is calculated. In an embodiment, the size of the authentication key 111 can be 32 bytes.

[0086] The write counter 112 can count the number of successful replay protection block write operations. The write counter 112 can store a write count value corresponding to 4 bytes. The initial value of the write counter 112 can be "0000 0000h". The write count value of the write counter 112 can not be reset or decreased. The value of the write counter 112 can not be increased after reaching "FFFF FFFFh" as a maximum value. Accordingly, when the value of the write counter 112 reaches the maximum value, data can not be stored in the replay protection block 110a any more, and the replay protection block 110a can operate as a read-only block.

[0087] The result register 113 can store a result of a replay protection block write operation or a replay protection block read operation.

[0088] In an embodiment, the authentication key 111, the write counter 112, and the result register 113 can be independently included for each replay protection block 110a, and can have unique values.

[0089] The replay protection block data area 114 can include an area configured to store data only when authentication is successful.

[0090] ​When the replay protection block write operation is performed, the replay protection block host controller 410 can provide a replay protection block message to the replay protection block device controller 210 according to a predetermined format. The replay protection block message provided by the replay protection block host controller 410 can include information required to perform an authentication operation on the replay protection block. For example, the replay protection block message can include authentication data and metadata. The authentication data can include a MAC generated by the replay protection block host controller 410.

[0091] The replay protection block device controller 210 can further include an authentication manager 211 and an access controller 212.

[0092] The authentication manager 211 can perform an authentication operation using the authentication data and metadata included in the replay protection block message and the authentication key 111 stored in the replay protection block 110a. The authentication manager 211 can provide a result of performing the authentication operation to the access controller 212. The access controller 212 can store data in the replay protection block 110a or prohibit storing data in the replay protection block 110a according to the result of performing the authentication operation.

[0093] When the authentication operation is successful, the access controller 212 can control the replay protection block 110a to store write data to be stored in the replay protection block in the replay protection block data area 114. The access controller 212 can increase the value of the write counter 112 and store information indicating that the replay protection block write operation is completed in the result register 113.

[0094] When the authentication operation fails, the access controller 212 can not store write data requested to be stored in the replay protection block in the replay protection block data area 114. The access controller 212 can maintain the value of the write counter 112 and store information indicating that the replay protection block write operation is completed in the result register 113.

[0095] When the replay protection block read operation is performed, the replay protection block host controller 410 can provide a replay protection block message to the replay protection block device controller 210 based on a predetermined format. The replay protection block message provided by the replay protection block host controller 410 can include information required to perform an authentication operation on the replay protection block. For example, the replay protection block message can include metadata.

[0096] The access controller 212 can read the data stored in the replay protection block and generate a replay protection block message to be provided to the replay protection block host controller 410. The access controller 212 can obtain some of the metadata included in the replay protection block message received from the replay protection block host controller 410 (e.g., the nonce) and generate metadata including some of the metadata included in the replay protection block message received from the replay protection block host controller 410 and the result of the replay protection block read operation. The access controller 212 can generate authentication data using the generated metadata and the authentication key 111 stored in the replay protection block 110a. The authentication data can include a MAC that is used for an authentication operation performed by the replay protection block host controller 410 to access the read data later.

[0097] The access controller 212 can generate a replay protection block message including the generated metadata and the authentication data and provide the read data and the replay protection block message to the replay protection block host controller 410. In an embodiment, the replay protection block message provided by the access controller 212 can include the result information stored in the result register 113.

[0098] Figure 5 is a diagram illustrating a data structure of data transmitted between a replay protection block host controller and a replay protection block device controller.

[0099] Referring to Figure 4 and Figure 5 , the replay protection block host controller 410 and the replay protection block device controller 210 can communicate using data packets. A data packet or message through which information such as security information is transferred between a host (e.g., a UFS host) and a data storage device can be referred to as a protocol unit or a protocol information unit (PIU). A protocol component (or PIU) can have a predefined data structure including a plurality of sequentially addressed bytes arranged as different fields, as will be discussed below.

[0100] Based on an operation to be performed by the replay protection block host controller 410 or the replay protection block device controller 210, a PIU can include a command PIU, a response PIU, a data-out PIU, a data-in PIU, and a “ready to transfer” PIU.

[0101] A command PIU can be a PIU transmitted when the host 400 transfers a command to the storage device 50.

[0102] A response PIU can be a PIU transferred when the storage device 50 provides a response to a command provided by the host 400.

[0103] The data output PIU can be a PIU transmitted when the host 400 provides data to the storage device 50.

[0104] The data input PIU can be a PIU transmitted when the storage device 50 provides data to the host 400.

[0105] The "ready to transfer" PIU can be transmitted to inform the storage device 50 that it is ready to receive the data output PIU from the host 400. The ready to transfer PIU can be transmitted when the storage device 50 has enough buffer space to store the data provided by the host 400.

[0106] In some embodiments, the size of the minimum PIU can be 32 bytes, and the maximum size of the PIU can be 65,600 bytes. The format of the PIU can have different sizes according to its type.

[0107] The PIU can include a basic header segment 61, a transaction specific field 62, an additional header segment 63, and a data segment 64.

[0108] The size of the basic header segment 61 can be 12 bytes. The basic header segment 61 can be included in all PIUs.

[0109] The transaction specific field 62 can be included in the byte address 12 to the byte address 31 of the PIU. The transaction specific field 62 can include a specific transaction code based on the type of the PIU.

[0110] The additional header segment 63 can be defined when the total additional header length (Total EHS Length) field of the basic header segment 61 has a non-0 value. The additional header segment 63 can start from the byte address 32 of the PIU. The additional header segment 63 can be an area in which data can be additionally stored when there can not be enough information included in the basic header segment 61.

[0111] The data segment 64 can be included in the data output PIU or the data input PIU, and can not be included in other PIUs.

[0112] In an embodiment, the additional header segment 63 and the data segment 64 can not be included in all protocol PIUs, but can be included only in specific PIUs.

[0113] Figure 6 FIG. 1 is a diagram illustrating the structure of a basic header segment of a PIU.

[0114] Referring to Figure 6The basic header segment 61 can include a transaction type, a flag, a logical unit number (LUN), a task tag, an initiator ID, a command set type, a query function / task management function, a response, a status, a total EHS length, device information, and a data segment length.

[0115] The transaction type can have a unique value based on the type of the PIU. An example of the transaction type based on the type of the PIU is shown in the following [Table 1].

[0116] [Table 1]

[0117]

[0118] The flag can be a field having different values based on the transaction type.

[0119] The logical unit number (LUN) can be a field indicating a serial number of a logical unit in which a corresponding operation is performed among a plurality of logical units included in an object on which an operation is to be performed.

[0120] The task tag can be a field having different values based on the transaction type.

[0121] The initiator ID can be a field identifying who is an initiator of a requested operation. Accordingly, the initiator ID can have different values in the case where a host generates a PIU and a storage device generates a PIU.

[0122] The command set type can be a field included in a command PIU and a response PIU. The command set type can be a field indicating which interface is supported by a command (for example, whether the command is a SCSI command, a UFS command, or a command defined by a manufacturer).

[0123] The query function / task management function can be a field input to a PIU, such as a query request, a query response, or a task management request.

[0124] The response can be a field indicating whether the execution of a requested operation is successful or failed.

[0125] The status can be a field indicating a SCSI status.

[0126] The total additional header segment length (ETotal EHS Length) can be a field indicating the size of the additional header segment in 32 bits. The total additional header segment length (ETotal EHS Length) can be used when the PIU includes the additional header segment. The length of the additional header segment can be in 4 bytes. The value of the total additional header segment length (ETotal EHS Length) can be a value obtained by dividing the total number of bytes of the additional header segment by 4. The maximum size of the additional header segment can be 1024 bytes. When the additional header segment is not used, the total additional header segment length (ETotal EHS Length) can be 0.

[0127] The device information can include information used only when a specific function is performed.

[0128] The data segment length can be a field indicating the length of the data segment of the PIU. When the PIU does not include the data segment, the data segment length can be 0.

[0129] Figure 7 is a diagram illustrating an example of a structure of a replay protection block message used when a replay protection block write operation or a replay protection block read operation is performed.

[0130] Referring to Figure 4 and Figure 7 , the replay protection block message (RPMB Message) can be a message provided when an operation is performed on the replay protection block.

[0131] The replay protection block message (RPMB Message) can include authentication data and metadata.

[0132] The authentication data can include padding bytes and a MAC. The MAC can be a result calculated by the replay protection block host controller 410 using a pre-stored authentication key and the metadata. That is, the MAC can be an authentication code calculated using a hash-based MAC (HMAC SHA-256). The length of the MAC can be 256 bits (32 bytes). The authentication key used to generate the MAC can be 256 bits.

[0133] The metadata can include a random number, a write counter, an address, a block count, a result, and a request message type / response message type.

[0134] The random number can be a random number value generated by the replay protection block host controller 410. The random number provided by the replay protection block host controller 410 can be copied to a response provided from the replay protection block device controller 210 to the replay protection block host controller 410.

[0135] The write counter can be the number of successful write operations performed on the replay protection block 110a.

[0136] The address can be a logical address at which data is to be stored in the replay protection block 110a, or a logical address at which data is to be read from the replay protection block 110a.

[0137] The block count can be the number of logical blocks for which a replay protection block write operation or a replay protection block read operation is requested. The block count can be the number of logical blocks in units of 256 bytes.

[0138] The result can be the result of performing the replay protection block write operation or the replay protection block read operation.

[0139] The request message type / response message type can indicate whether the replay protection block message is a message related to a replay protection block write operation or a replay protection block read operation.

[0140] Figure 8 is a diagram showing an example of a replay protection block write operation.

[0141] Referring to Figure 8 The replay protection block write operation to store data in the replay protection block involves a combination of three commands (protocol handshake) between the host 400 and the storage device 50.

[0142] Specifically, the replay protection block write operation includes an authentication write request, a result read request, and a result read response.

[0143] The authentication write request can be performed by performing a plurality of operation steps S801 to S807, the result read request can be performed by performing a plurality of operation steps S809 to S815, and the result read response can be performed by performing a plurality of operation steps S817 to S821.

[0144] The authentication write request can be a request to store data in the replay protection block and data to be stored.

[0145] The result read request can be a request for a command to transfer a value stored in a result register in which the result of performing the replay protection block write operation is stored.

[0146] The result read response can be a response to provide the value of the result register.

[0147] At S801, the host 400 can provide a command PIU to the storage device 50. The command PIU provided at S801 can include a replay protection block message. The storage device 50 can perform an authentication operation on the replay protection block using the MAC and metadata included in the replay protection block message.

[0148] At S803, the storage device 50 can provide a ready-to-transfer PIU to the host 400. The ready-to-transfer PIU can be a PIU provided when the storage device 50 is ready to receive data to be provided by the host 400. In an embodiment, the ready-to-transfer PIU can be a PIU providing a message indicating that the data-out PIU is ready to be received.

[0149] At S805, the host 400 can provide a data-out PIU to the storage device 50. The data-out PIU provided by the host 400 can include a plurality of data segments including data to be stored in the replay protection block.

[0150] In an embodiment, operations S803 and S805 can be repeated a number of times based on an amount of data to be stored in the replay protection block by the host 400.

[0151] At S807, the storage device 50 can provide a response PIU to the host 400. The response PIU provided by the storage device 50 can include a result of performing the replay protection block write operation.

[0152] At S809, the host 400 can provide a command PIU to the storage device 50. The command PIU provided at S809 can include a replay protection block message. In an embodiment, the replay protection block message included in the command PIU provided at S809 can include a message of a value stored in a command PIU request result register provided by the host 400.

[0153] At S811, the storage device 50 can provide a ready-to-transfer PIU to the host 400. The ready-to-transfer PIU can be a PIU provided when the storage device 50 is ready to receive data to be provided by the host 400. In an embodiment, the ready-to-transfer PIU can be a PIU providing a message indicating that the data-out PIU is ready to be received.

[0154] At S813, the host 400 can provide a data-out PIU to the storage device 50.

[0155] At S815, the storage device 50 can provide a response PIU to the host 400. At S815, the response PIU provided by the storage device 50 can include information indicating that a message received at S809 indicating a command of a value stored in a request result register was successfully received.

[0156] At S817, the host 400 can provide a PIU to the storage device 50. The command PIU provided at S817 can be a command to request data to be provided from the storage device 50.

[0157] At S819, the storage device 50 can provide the data-in PIU to the host 400.

[0158] At S821, the storage device 50 can provide the response PIU to the host 400. The response PIU received at S821 by the host 400 can include a replay protection block message including the value stored in the result register.

[0159] Figures 9A-9C is a diagram illustrating an example of a replay protection block message provided during a replay protection block write operation of Figure 8 is a diagram illustrating an example of a replay protection block message provided during a replay protection block write operation of

[0160] Figure 9A is a replay protection block message provided by the host 400 to the storage device 50 in an authenticate write request.

[0161] Referring to Figure 9A , the replay protection block message of the authenticate write request can be included in the command PIU provided by the host 400 to the storage device 50 at S801 as discussed above with reference to Figure 8

[0162] In particular, the replay protection block message of the authenticate write request can include a MAC computed by the host 400, a current write counter value, an address in the replay protection block where data is to be stored, a logical block count, a message indicating that the command PIU is an authenticate write request.

[0163] Figure 9B is a replay protection block message provided by the host 400 to the storage device 50 in a result read request.

[0164] Referring to Figure 9B , the replay protection block message of the result read request can be included in the command PIU provided by the host 400 to the storage device 50 at S809 as discussed above with reference to Figure 8

[0165] The replay protection block message of the result read request can include only a message indicating that the command PIU is a result read request, and the remaining fields can be 0.

[0166] Figure 9C is a replay protection block message provided by the storage device 50 to the host 400 in a result read response.

[0167] Referring to Figure 9C , the replay protection block message of the result read response can be included in the response PIU provided by the storage device 50 to the host 400 at S821 as discussed above with reference to Figure 8

[0168] Referring to​​​Figure 9C The replay protection block message of the result read response can include a MAC calculated by the storage device. The MAC calculated by the storage device can be an authentication code calculated by using an authentication key stored in the storage device and the metadata included in the replay protection block message of the result read response.

[0169] The replay protection block message of the result read response can include an updated write counter value having a value increased from the write counter value of the replay protection block message. Figure 9A

[0170] In an embodiment, the replay protection block message of the result read response can further include a message indicating that the command PIU is a message of the result read response.

[0171] Figure 10 is a flowchart illustrating a replay protection block write operation based on an embodiment of the disclosed technology.

[0172] Referring to Figure 10 At S1201, the host 400 can provide a command PIU to the storage device. The command PIU can include an additional header section. The additional header section can include a replay protection block message. The replay protection block message can include a message indicating that the command PIU is a PIU indicating a replay protection block write operation. For example, the replay protection block message included in the command PIU can be a replay protection block message of an authentication write request as discussed above with reference to Figure 9A

[0173] At S1203, the storage device 50 can provide a "ready to transfer" PIU to the host 400. The ready to transfer PIU can include a PIU provided when the storage device 50 is ready to receive data to be provided by the host 400. In an embodiment, the ready to transfer PIU can be a PIU providing a message indicating that the data output PIU is ready to be received. In an embodiment, the storage device 50 can provide the ready to transfer PIU to the host 400 when a buffer space for storing data to be received from the host 400 is secured.

[0174] At S1205, the host 400 can provide a data output PIU to the storage device 50. The data output PIU can include data to be stored in a replay protection block.

[0175] In an embodiment, operations S1203 and S1205 can be repeated several times according to an amount of data to be stored in a replay protection block by the host 400.

[0176] ​​At S1207, the storage device 50 can provide the response PIU to the host 400. The response PIU provided by the storage device 50 can include the replay protection block message. For example, the replay protection block message included in the response PIU can be the replay protection block message as discussed above with reference to Figure 9C At S1207, the storage device 50 can provide the response PIU to the host 400. The response PIU provided by the storage device 50 can include the replay protection block message. For example, the replay protection block message included in the response PIU can be the replay protection block message as discussed above with reference to

[0177] Figure 11 is an example of a diagram illustrating an embodiment of the command PIU based on some embodiments of the disclosed technology. Figure 10

[0178] With reference to Figure 11 , the command PIU can include the basic header segment, the transaction specific field, the additional header segment, and the data segment. Based on embodiments of the disclosed technology, because the command PIU of Figure 10 includes the additional header segment, the Total EHS Length field included in the basic header segment, which corresponds to the byte address 8, can have a non-0 (non-zero) value. Figure 10 The command PIU of Figure 10 may include data in the additional header segment corresponding to the size of the replay protection block message provided by the host 400. Thus,

[0179] Figure 12 is an example of a diagram illustrating an embodiment of the response PIU based on some embodiments of the disclosed technology. Figure 10

[0180] With reference to Figure 12 , the response PIU can include the basic header segment, the transaction specific field, the additional header segment, and the data segment. Based on embodiments of the disclosed technology, because the response PIU of Figure 10 includes the additional header segment, the Total EHS Length field included in the basic header segment, which corresponds to the byte address 8, can have a non-0 (non-zero) value. Figure 10 The response PIU of Figure 10 may include data in the additional header segment corresponding to the size of the replay protection block message provided by the storage device 50 to the host 400. Thus,

[0181] Figure 13 is an example of a diagram illustrating an embodiment of the response PIU based on some embodiments of the disclosed technology. Figure 4 ​​a diagram of the operation of a replay protection block host controller.

[0182] Referring to Figure 13 The replay protection block host controller 410 can include a host message authentication code calculator 411, a host authentication key storage 412, a host metadata generator 413, and a host protocol unit generator 414.

[0183] The host authentication key storage 412 can store an authentication key. The authentication key stored by the host authentication key storage 412 can be the same authentication key as the authentication key stored by the storage 50. The authentication key can be stored in advance before a write or read operation is performed on the replay protection block.

[0184] The host metadata generator 413 can generate metadata when a replay protection block write operation is performed. The metadata can include a current write counter value, an address of data to be stored, a block count of data to be stored, and information of a message requesting the replay protection block write operation.

[0185] The host metadata generator 413 can provide the generated metadata to the host message authentication code calculator 411 and the host protocol unit generator 414.

[0186] The host message authentication code calculator 411 can generate a MAC using the metadata and the authentication key. Specifically, the host message authentication code calculator 411 can generate the MAC using a hash-based MAC (HMAC SHA-256). The generated MAC can be used for the storage 50 to perform an authentication operation. The length of the MAC can be 256 bits (32 bytes). The authentication key used to generate the MAC can be 256 bits. The host message authentication code calculator 411 can provide the generated MAC to the host protocol unit generator 414.

[0187] The host protocol unit generator 414 can generate a PIU to be provided to the storage 50. Specifically, the host protocol unit generator 414 can generate a replay protection block message including authentication data and metadata. The authentication data can include the MAC generated by the host message authentication code calculator 411. The host protocol unit generator 414 can generate a command PIU including the replay protection block message in an additional header section, and provide the generated command PIU to the storage 50. The command PIU can include the additional header section, and a total additional header section length field in a basic header section can include a value other than 0.

[0188] The host protocol unit generator 414 can generate a data output PIU. The data output PIU can include a data segment. The host protocol unit generator 414 generates the data output PIU in which the write data to be stored in the replay protection block is included in the data segment, and provides the generated data output PIU to the storage device 50.

[0189] Figure 14 is a diagram illustrating an example of an operation of computing a MAC by a data storage device.

[0190] Referring to Figure 14 , the first period P1 can be a period in which the host 400 provides the authentication write request to the storage device 50. Specifically, at S1401, the host 400 can generate a command PIU. The generated command PIU can include an additional header segment. The additional header segment can include a replay protection block message. The replay protection block message can include a message indicating that the command PIU is a protocol unit indicating a replay protection block write operation. For example, the replay protection block message included in the command PIU can be a replay protection block message of the authentication write request as discussed above with reference to Figure 9A At S1403, the host 400 can provide the generated command PIU to the storage device 50. At S1405, the storage device 50 can receive the command PIU provided by the host.

[0191] The second period P2 can be a data transfer period in which the host 400 transfers data to be stored in the replay protection block to the storage device 50.

[0192] The data transfer represented by step S1407 can include a data transfer as discussed above with reference to Figure 10Each of steps S1203 and S1205 discussed herein. Specifically, storage device 50 may provide a Ready to Transmit PIU to host 400, and host 400 may respond to the Ready to Transmit PIU from storage device 50. The Ready to Transmit PIU may be a protocol unit provided when storage device 50 is ready to receive data to be provided by host 400. In an embodiment, the Ready to Transmit PIU may be a protocol unit providing a message indicating readiness to receive a Data Output PIU. In an embodiment, storage device 50 may provide a Ready to Transmit PIU to host 400 when buffer space for storing data to be received from host 400 is guaranteed. Host 400 may provide a Data Output PIU to storage device 50 in response to the Ready to Transmit PIU provided by storage device 50. The Data Output PIU may include data to be stored in a replay protection block. Data transmissions may be repeated, and the number of repetitions is determined based on the amount of data to be stored in the replay protection block by host 400. When multiple data transmissions are performed, the process of providing Ready to Transmit PIUs and Data Output PIUs between host 400 and storage device 50 may be repeated.

[0193] The third time period, P3, can be the time period during which data is stored in the replay protection block.

[0194] During this period, storage device 50 can use the metadata included in the replay protection block message included in the received data output PIU to calculate the MAC (S1409), and can store the data in the replay protection block based on whether the calculated MAC is the same as the MAC of the replay protection block message of the authentication write request included in the command PIU provided by host 400 at S1403 (S1411).

[0195] The fourth time period P4 may be the time period during which the storage device 50 provides the host 400 with the result of the replay protection block write operation.

[0196] Specifically, at S1413, the storage device 50 can generate through Figure 10 The response PIU described in step S1207. The response PIU may include a replay protection block message. For example, the replay protection block message included in the response PIU may be as described above. Figure 9C The discussed result reads the replay protection block message of the response. In an embodiment, the response PIU may include an additional header segment, and the replay protection block message may be included in the additional header segment. At S1415, the storage device 50 may provide the generated response PIU to the host 400, and at S1417, the host 400 may receive the response PIU provided by the storage device 50.

[0197] As mentioned above Figure 8In the replay protection block write operation in question, since the replay protection block write operation includes the authentication write request, the result read request, and the result read response, it is possible that an overhead of an increase in the run time of the entire replay protection block write operation occurs due to the time for the storage apparatus 50 to calculate the MAC.

[0198] However, in some embodiments of the disclosed technology (for example, Figure 10 ), when the replay protection block write operation is executed by providing one command PIU and one response PIU by steps S1201 to S1207, since the storage apparatus 50 calculates the MAC after receiving all the data, it is possible that an overhead of an increase in the run time of the entire replay protection block write operation occurs.

[0199] Figure 15 is a diagram showing another embodiment of the operation of calculating the MAC by the data storage apparatus.

[0200] Referring to Figure 15 , steps S1501 to S1505 included in the first period Pl are the same as steps S1401 to S1405 of Figure 14 . In addition, steps S1511 to S1515 included in the fourth period P4 are respectively the same as steps S1413 to S1417 of Figure 14 .

[0201] Figure 15 The difference between the embodiment of Figure 14 is that the storage apparatus 50 calculates the MAC in the second period P2, which is the data transfer period in which the host 400 transfers data to be stored in the replay protection block to the storage apparatus 50.

[0202] Specifically, the replay protection block message of the authentication write request included in the command PIU received at S1505 by the storage device 50 can include the MAC calculated by the host 400, the current write counter value, the address at which the data in the replay protection block is to be stored, the block count indicating the number of logical blocks to be stored in the replay protection block, and the message indicating that the command PIU is an authentication write request. Thus, the storage device 50 can identify the MAC that has been calculated by the host 400 and the size of the data to be stored in the replay protection block by the host 400 before receiving the data in the second period P2. The storage device 50 can receive a plurality of data output PIUs based on the size of the data that the host 400 intends to store in the replay protection block. The host 400 can provide the data output PIUs to the storage device 50 in response to the prepare transfer PIU provided by the storage device 50. In an embodiment, the prepare transfer PIU can include information about the size of the data that the storage device 50 can receive. The host 400 can provide the same size of data as the size of the data included in the prepare transfer PIU provided by the storage device 50 to the storage device 50 through the data output PIUs.

[0203] When the storage device 50 receives the data output PIUs, the storage device 50 can calculate the MAC using the metadata included in the replay protection block message included in the data output PIUs and the authentication key 111 stored in the replay protection block 110a as discussed above with reference to Figure 4

[0204] The MAC calculated using the metadata included in the replay protection block message included in the previous data output PIU can be used to calculate the MAC together with the metadata included in the replay protection block message included in the subsequent data output PIU.

[0205] When the storage device 50 receives the data output PIUs, the storage device 50 can calculate the MAC using the metadata included in the replay protection block message included in the data output PIUs and provide a prepare transfer PIU to the host 400 in order to request the next data output PIU.

[0206] After receiving all of the data, because the storage device 50 calculates the MAC in the second period P2, the data can be stored in the replay protection block based on whether the calculated MAC is the same as the MAC calculated by the host 400, which is included in the replay protection block message of the authentication write request included in the command PIU received at S1505 (S1509).

[0207] In some embodiments of the disclosed technology (e.g., Figure 15 ​) because the storage device 50 calculates the MAC at the same time (in parallel with the data reception) as the data is received, it is possible to prevent the occurrence of as much overhead as the time for calculating the MAC.

[0208] Figure 16 is a block diagram illustrating an example of a structure of a data storage device based on an embodiment of the disclosed technology.

[0209] Referring to Figure 16 , the replay protection block device controller 210 can further include an authentication manager 211 and an access controller 212.

[0210] The authentication manager 211 can perform an authentication operation using the authentication data and metadata included in the replay protection block message and the authentication key 111 stored in the replay protection block 110a. The authentication manager 211 can provide a result of performing the authentication operation to the access controller 212. The access controller 212 can store data in the replay protection block 110a or prohibit storing data in the replay protection block 110a based on the result of performing the authentication operation.

[0211] When the authentication operation is successful, the access controller 212 can control the replay protection block 110a to store write data to be stored in the replay protection block in the replay protection block data area 114. The access controller 212 can increase the value of the write counter 112 and store information indicating that the replay protection block write operation is completed in the result register 113.

[0212] When the authentication operation fails, the access controller 212 can not store write data requested to be stored in the replay protection block in the replay protection block data area 114. The access controller 212 can maintain the value of the write counter 112 and store information indicating that the replay protection block write operation is completed in the result register 113.

[0213] The authentication manager 211 can include a device message authentication code calculator 211a and a message authentication code comparator 211b.

[0214] During the replay protection block write operation, the device message authentication code calculator 211a can obtain metadata from the command PIU received from the replay protection block host controller 410. The device message authentication code calculator 211a can obtain the authentication key stored in the replay protection block. The device message authentication code calculator 211a can calculate a MAC using a hash-based MAC (HMAC SHA-256). The device message authentication code calculator 211a can provide the MAC calculated using the metadata of the replay protection block message received from the replay protection block host controller 410 and the authentication key stored in the replay protection block of the memory device to the authentication code comparator 211b.

[0215] In an embodiment, the access controller 212 can obtain metadata from the command PIU received from the replay protection block host controller 410. The metadata can include information indicating a size of write data to be stored based on the replay protection block write operation. Specifically, the metadata can include a block count indicating a number of logical blocks of the write data.

[0216] Thereby, the access controller 212 can identify the size of data to be stored through the replay protection block write operation. The access controller 212 can provide a prepare transfer PIU requesting data to be received through the replay protection block write operation to the host 400 based on a remaining capacity of the buffer memory 300. In an embodiment, the prepare transfer PIU can include a device replay protection block message. The device replay protection block message included in the prepare transfer PIU can include information about a size of write data that can be received through the access controller 212.

[0217] The host 400 can divide the write data into a plurality of write data chunks based on the prepare transfer PIU provided by the access controller 212, and provide the plurality of write data chunks to the memory controller 200.

[0218] The data output PIU can include the write data chunk and a data output replay protection block message indicating that the write data chunk is data to be stored in the replay protection block. The data output replay protection block message can include data output metadata for computing a device message authentication code. In an embodiment, the data output metadata can include a block count of the corresponding write data chunk.

[0219] Based on an embodiment of the disclosed technology, when the host 400 provides the write data chunk to the memory controller 200 using the data output PIU in response to the prepare transfer PIU, the device message authentication code calculator 211a can update (cumulatively compute) the data output metadata and the previously computed MAC included in the data output PIU using a hash-based MAC (HMAC SHA-256).

[0220] The device message authentication code calculator 211a can update the MAC using the data output metadata included in each of the data output PIUs while receiving all of the data output PIUs.

[0221] The message authentication code comparator 211b can obtain the MAC from the command PIU received from the replay protection block host controller 410. Specifically, the message authentication code comparator 211b can obtain the MAC generated by the replay protection block host controller 410 from the replay protection block message included in the command PIU received from the replay protection block host controller 410. The message authentication code comparator 211b can compare whether the MAC generated by the replay protection block host controller 410 and the MAC calculated by the device message authentication code calculator 211a are identical. The message authentication code comparator 211b can provide the comparison result to the access controller 212.

[0222] When the MAC generated by the replay protection block host controller 410 and the MAC calculated by the device message authentication code calculator 211a are identical, the access controller 212 can control the memory device to store data in the replay protection block. The access controller 212 can increase the write counter value, and store information indicating that the replay protection block write operation is successful in the result register.

[0223] When the MAC generated by the replay protection block host controller 410 and the MAC calculated by the device message authentication code calculator 211a are not identical, the access controller 212 can not store data in the replay protection block. In this case, the access controller 212 can not increase the write counter value, and store information indicating that the authentication fails in the result register.

[0224] The access controller 212 can generate a replay protection block message, and generate a PIU including the generated message. Specifically, the access controller 212 can generate a response PIU. The response PIU generated by the access controller 212 can include an additional header section. The access controller 212 can include the replay protection block message in the additional header section of the response PIU, and provide the replay protection block message to the host 400.

[0225] The response PIU provided by the access controller 212 to the host 400 can include the MAC calculated by the device message authentication code calculator 211a. The response PIU provided by the access controller 212 to the host 400 can further include a write count value, a result code, and a message indicating a response as a result of the replay protection block write operation. Here, when the replay protection block write operation is successful, the write count value can include the increased write count value. Also, the result code can be a result code indicating that the replay protection block write operation is successful. In contrast, when the replay protection block write operation fails, the write count value can include the existing write count value. Also, the result code can be a result code indicating a cause of the replay protection block write operation failure.

[0226] Figure 17 is shown Figure 1a diagram of another example of a memory controller.

[0227] Referring to Figure 17 , the memory controller 800 can include a processor 810, a RAM 820, an error correction code (ECC) circuit 830, a host interface 840, a ROM 850, and a flash interface 860.

[0228] The processor 810 can control overall operations of the memory controller 800. The RAM 820 can be used as a buffer memory, a cache memory, an operation memory, etc. of the memory controller 800.

[0229] The ROM 850 can store various information required for the memory controller 800 to operate in firmware form.

[0230] The memory controller 800 can communicate with an external device (e.g., the host 400, an application processor, etc.) through the host interface 840.

[0231] The memory controller 800 can communicate with the memory device 100 through the flash interface 860. The memory controller 800 can transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 and receive data DATA through the flash interface 860. For example, the flash interface 860 can include a NAND interface.

[0232] Figure 18 is a block diagram illustrating a memory card system including a data storage device based on an embodiment of the disclosed technology.

[0233] Referring to Figure 18 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0234] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 can be configured to control a read operation, a program operation, an erase operation, and a background operation of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host.

[0235] The memory controller 2100 is configured to perform firmware operations for controlling the memory device 2200. The configuration of the memory controller 2100 can be the same as or similar to that of the memory controller 200 shown in Figure 1 .

[0236] For example, the memory controller 2100 can include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0237] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Express PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the various communication standards described above.

[0238] For example, the memory device 2200 can include a non-volatile memory element such as an electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0239] The memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device such as a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro-SD, or eMMC), an SD card (SD, mini-SD, micro-SD, or SDHC), and a universal flash (UFS).

[0240] Figure 19 is a block diagram illustrating a solid state drive (SSD) system including a data storage device based on an embodiment of the disclosed technology.

[0241] Referring to Figure 19 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of non-volatile memories 3221 through 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0242] Based on embodiments of the disclosed technology, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to Figure 1 FIG. 1.

[0243] The SSD controller 3210 can control the plurality of nonvolatile memories 3221 through 322n in response to a signal received from the host 3100. For example, the signal can be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Express PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash (UFS), Wi-Fi, Bluetooth, and NVMe.

[0244] The auxiliary power supply 3230 is connected to the host 3100 through the power supply connector 3002. The auxiliary power supply 3230 can receive power from the host 3100 and can be charged. The auxiliary power supply 3230 can supply power to the SSD 3200 when the power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on a main board and can supply auxiliary power to the SSD 3200.

[0245] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of nonvolatile memories 3221 through 322n, or can temporarily store metadata (e.g., a mapping table) of the nonvolatile memories 3221 through 322n. The buffer memory 3240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0246] Figure 20 FIG. 4 is a block diagram illustrating a user system including a data storage apparatus based on embodiments of the disclosed technology.

[0247] Referring to Figure 20 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0248] The application processor 4100 can perform operations associated with hardware components, an operating system (OS), and / or a user program included in the user system 4000. For example, the application processor 4100 can include a controller, an interface, a graphic engine, etc. that control components included in the user system 4000. The application processor 4100 can be set as a system on chip (SoC).

[0249] The memory module 4200 can operate as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 can include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package on package (POP) and provided as one semiconductor package.

[0250] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communication such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0251] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transfer data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented with a non-volatile semiconductor memory element such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, and three-dimensional NAND flash. For example, the storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

[0252] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate identically to the memory device 100 described with reference to Figure 1 The storage module 4400 can operate identically to the storage 50 described with reference to Figure 1 the memory device 100 described with reference to

[0253] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 can include a user input interface such as a keypad, a key pad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezo element. The user interface 4500 can include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

Claims

1. A data storage device comprising: a memory device including a protected storage block storing information for an authentication operation on data to be read from or written to the memory device, and protected by a security protocol; and a memory controller coupled to the memory device to control operation of the memory device, and the memory controller: receiving from a host a command protocol unit associated with the security protocol in a command including a host-side protection message requesting writing of data from the host to the protected storage block; receiving from the host in sequence a plurality of data units including the data; and accumulatively computing a device message authentication code for one of the data units upon receiving a next data unit following the one data unit, from first metadata contained in the one data unit, and from a previously computed device message authentication code determined based on a previously received data unit received prior to the one data unit.

2. The data storage device of claim 1, further comprising: a buffer memory temporarily storing the data to be written to the protected storage block.

3. The data storage device of claim 2, wherein the memory controller includes: an authentication manager performing the authentication operation and outputting a result of the authentication operation; and an access controller controlling the protected storage block based on the result of the authentication operation, and wherein the host-side protection message includes: authentication data including a host message authentication code generated by the host; and metadata including data other than the authentication data.

4. The data storage device of claim 3, wherein the protected storage block includes a replay protection block including: an authentication key storage storing an authentication key for authenticating the replay protection block; a write counter storing a write count value corresponding to a number of successful write operations in the replay protection block; a result register storing a result of an operation performed on the replay protection block; and a replay protection block data area storing data.

5. The data storage device of claim 4, wherein the authentication manager includes: a device message authentication code calculator generating the device message authentication code using the metadata and the authentication key; and a message authentication code comparator generating the result of the authentication operation based on whether the host message authentication code and the device message authentication code are identical.

6. The data storage device of claim 5, wherein the data to be written to the protected storage block includes a plurality of data chunks to be written to the memory device, and each of the plurality of data units includes at least one of the plurality of data chunks to be written to the memory device.

7. The data storage device of claim 6, wherein the access controller notifies the host of a presence of a memory space in the buffer memory storing at least one of the plurality of data units. ​ ​ ​ ​ ​ 8. The data storage device of claim 6, wherein each of the plurality of data units comprises: one of the plurality of data chunks; and a data-out replay protection chunk message indicating that the one of the plurality of data chunks corresponds to data to be stored in the replay protection chunk, wherein the data-out replay protection chunk message comprises data-out metadata used to perform a computation of the device message authentication code.

9. The data storage device of claim 5, wherein the message authentication code comparator generates a result of the authentication operation based on whether the host message authentication code matches the device message authentication code after completion of receipt of the plurality of data units.

10. The data storage device of claim 9, wherein the access controller controls the memory device to store data in the replay protection chunk in response to a result of the authentication operation indicating that the host message authentication code matches the device message authentication code.

11. The data storage device of claim 10, wherein the access controller controls the memory device to increment a current write count value stored in the write counter, to store the incremented write count value in the write counter, and to store a result code indicating completion of a write operation to the replay protection chunk in the result register.

12. The data storage device of claim 11, wherein the access controller generates a device replay protection chunk message comprising the device message authentication code, the incremented write count value, an address at which write data is stored, the result code, and information indicating a response corresponding to the command protocol unit.

13. The data storage device of claim 12, wherein the access controller generates a response protocol unit comprising the device replay protection chunk message, and provides the response protocol unit to the host, and wherein the device replay protection chunk message is included in an additional header segment of the response protocol unit.

14. The data storage device of claim 9, wherein the access controller controls the memory device to store a result code in the result register in response to a result of the authentication operation indicating that the host message authentication code does not match the device message authentication code, the result code indicating a failure of a write operation to the replay protection chunk.

15. The data storage device of claim 14, wherein the access controller generates a device replay protection chunk message comprising the device message authentication code, a current write count value stored in the write counter, an address at which write data storage failed, the result code, and information indicating a response corresponding to the command protocol unit.

16. The data storage device of claim 15, wherein the access controller generates a response protocol unit including the device replay protection block message and provides the response protocol unit to the host, and wherein the device replay protection block message is included in an additional header section of the response protocol unit.

17. The data storage device of claim 1, wherein the command protocol unit includes: a base header section that is included in common in protocol units transmitted between the host and the memory controller; a transaction specific field that includes a unique value corresponding to a type of the protocol unit; and an additional header section that is a header section other than the base header section, and wherein the host side protection message is included in the additional header section.

18. The data storage device of claim 17, wherein the base header section includes a total additional header section length that indicates a length of the additional header section.

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