A chip wiring method, a chip wiring device, an electronic device, and a storage medium

Abstract

The present invention relates to a chip wiring method, a chip wiring device, an electronic device, and a storage medium. The chip wiring method includes adjusting the wiring spacing between adjacent traces based on the wiring parameters of the traces in the initial wiring status report to generate a predicted wiring status report; the wiring parameters include at least one of wiring density, trace type, and the corresponding empirical defect size distribution; and performing a wiring design on the chip based on the predicted wiring status report. The present invention solves the technical problem in the prior art that the high probability of chip failure caused by the inability to well control chip defects. The present invention reduces the probability of chip failure caused by defects falling on or between the traces of the chip through a method of backend physical implementation.

Description

Technical Field

[0001] The present invention belongs to the field of layout wiring, and particularly relates to a chip wiring method, a chip wiring device, an electronic device, and a storage medium. Background Art

[0002] With the development of semiconductor technology, in order to solve the problem of high cost, the requirement for the yield of chips is getting higher and higher. For a wafer manufacturing factory (Foundry), due to the complex process of chip manufacturing, defects in the manufacturing process cannot be completely avoided. Nowadays, the defect sizes that most wafer manufacturing factories (foundry) can control are between dozens of nanometers and more than ten micrometers. If a defect occurs on the wafer during the manufacturing process, it is very likely to cause short circuits and open circuits in the internal wiring of the chip, resulting in chip failure. Therefore, for the manufacturing of ultra-large-scale deep sub-micron integrated circuits, defects are an important factor affecting the yield.

[0003] A defect usually refers to the physical contamination or imperfection on a wafer, which is usually caused by the following factors:

[0004] 1. Physical abnormalities on the wafer (such as: dust, process residues, abnormal reaction products).

[0005] 2. Chemical contamination (such as: residual chemicals, organic solvents).

[0006] 3. Pattern defects (such as: abnormal imaging caused by development (Photo) or lithography (Etch), mechanical scratches and deformations, color abnormalities caused by uneven thickness).

[0007] 4. Lattice defects caused by the wafer itself or during the manufacturing process.

[0008] The existence of layout defects is currently an unavoidable problem in the industry. Especially for ultra-large-scale chips, the impact of fatal defects on the yield will be amplified. Therefore, in order to improve the yield of chips, it is necessary to consider from the design perspective at the same time, adopt special design methods, reduce the probability of failure caused by defects during the production process, and improve the production yield of chips.

[0009] In the prior art, reducing the failure probability caused by defects in large-area chips usually relies on the foundry to control the manufacturing process flow, capture through various sensors during the manufacturing process, and minimize the number of killer defects in the manufacturing process. In order to meet the requirements of chip performance, power consumption, area, etc., no prevention is done on defects from the design perspective, so the failure probability of defects remains uncontrollable. Summary of the Invention

[0010] To solve the technical problem that the prior art cannot well control the high chip failure probability caused by chip defects, the present invention provides a chip wiring method, a chip wiring device, an electronic device, and a storage medium. The present invention reduces the probability of chip failure caused by defects falling on the chip traces or between the traces through a back-end physical implementation method.

[0011] The technical solution of the present invention is as follows:

[0012] A chip wiring method includes the following steps:

[0013] Based on the wiring parameters of the traces in the initial wiring status report, adjust the wiring spacing between adjacent traces to generate a predicted wiring status report; the wiring parameters include at least one of wiring density, trace type, and the corresponding empirical defect size distribution;

[0014] Perform a wiring design on the chip based on the predicted wiring status report.

[0015] Further limited, the step of adjusting the wiring spacing between adjacent traces based on the wiring parameters of the traces in the initial wiring status report includes:

[0016] Based on the wiring parameters of the traces in the initial wiring status report, adjust the wiring spacing between adjacent traces within a predetermined area; the predetermined area is determined based on the wiring density and the empirical defect size.

[0017] Further limited,

[0018] The adjustment of the wiring spacing between adjacent traces includes: expanding the wiring spacing between associated traces and / or reducing the wiring spacing between non-associated traces,

[0019] The associated traces include traces that affect each other after conduction;

[0020] The non-associated traces include traces that do not affect each other after conduction.

[0021] Further limited, the step of adjusting the wiring spacing between adjacent traces within a predetermined area based on the wiring parameters of the traces in the initial wiring status report includes:

[0022] Divide the predetermined area into a first predetermined area and a second predetermined area based on the wiring density, where the wiring density of the first predetermined area is greater than that of the second area;

[0023] Adjust the wiring spacing between adjacent traces in the first predetermined area based on the wiring density, trace type, and corresponding empirical defect size distribution of the first predetermined area; and adjust the wiring spacing between adjacent traces in the second predetermined area based on the wiring density, trace type, and corresponding empirical defect size distribution of the second predetermined area.

[0024] Further define that if the adjacent traces are two adjacent signal lines, then expand the wiring spacing between the two adjacent signal lines by 1.5 to 2 times.

[0025] Further define that if the adjacent traces are adjacent power lines and ground lines, adjust the distance between the power line and the ground line to be greater than the maximum value of the interval with the largest proportion in the empirical defect size distribution interval.

[0026] Further define that adjusting the wiring spacing between adjacent traces in the predetermined area includes:

[0027] Determine the wiring spacing between adjacent traces in the predetermined area based on the total area of the predetermined area, the wiring density of the predetermined area, the trace degree of the predetermined area, and the number of wirings in the predetermined area.

[0028] A chip wiring device includes:

[0029] A predicted wiring status report generation module: Obtain the wiring parameters of the traces in the initial wiring report, adjust the wiring spacing between adjacent traces, and generate a predicted wiring status report; the wiring parameters include at least one of wiring density, trace type, and corresponding empirical defect size distribution;

[0030] And a wiring design module: Perform wiring design on the chip based on the predicted wiring status report.

[0031] An electronic device includes a processor and a memory coupled to each other, where

[0032] The memory: is used to store program instructions for implementing the above chip wiring method;

[0033] The processor: is used to execute the program instructions stored in the memory.

[0034] A computer-readable storage medium stores a program file, and the program file is executed to implement the above chip wiring method.

[0035] The beneficial effects of the present invention:

[0036] 1. The present invention adjusts the routing pitch between adjacent traces by obtaining a routing status report and based on the information of the routing congestion (i.e., routing density) during the chip layout and routing stage, reducing the probability of defects falling on signal lines and minimizing functional failures caused by chip signal short circuits or open circuits.

[0037] 2. Based on the routing density, a predetermined area is divided into a first predetermined area and a second predetermined area, where the routing density of the first predetermined area is greater than that of the second area; the adjustable area of the routing of the entire chip is divided into a first predetermined area and a second predetermined area, and the routing method is adjusted according to different congestion types (routing density), facilitating targeted routing adjustment based on different routing densities.

[0038] 3. A chip routing method provided by the present invention takes into account the influence of defects during layout design, appropriately adjusts the width, pitch, etc. of traces to increase the probability of defects falling between power / ground lines, effectively preventing chip failures caused by defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flowchart of an embodiment of a chip routing method of the present invention;

[0040] Figure 2 is a schematic diagram for distinguishing routing with different routing congestions;

[0041] Figure 3 is a schematic diagram of the regional division of the routing congestion types of the entire chip;

[0042] Figure 4 is a display of the defect optimization effect before and after increasing the routing pitch; Figure 1 ;

[0043] Figure 5 is a display of the defect optimization effect before and after increasing the routing pitch; Figure 2 ;

[0044] Figure 6 is a diagram showing the defect optimization effect before and after increasing the power network pitch;

[0045] Figure 7 is a schematic diagram of the structure of a chip routing device of the present invention;

[0046] Figure 8 is a schematic diagram of the structure of an electronic device of the present invention;

[0047] Figure 9 is a schematic diagram of the structure of a computer-readable storage medium of the present invention;

[0048] Among them, there are a 1 - predicted wiring status report generation module and a 2 - wiring design module. Detailed implementation manners

[0049] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. The present invention provides a chip wiring method, and a method implemented physically at the backend is used to reduce the probability that defects fall on the chip traces or between the traces, causing chip failure.

[0050] As Figure 1 shown, it is a flowchart of the implementation of a chip wiring method of the present invention. Specifically, the method includes:

[0051] Step S01: Based on the wiring parameters of the traces in the initial wiring status report, adjust the wiring spacing between adjacent traces to generate a predicted wiring status report; the wiring parameters include at least one of wiring density, trace type, and empirical defect size distribution.

[0052] Among them, the wiring density is the ratio of the total area of the traces to the unit area. As Figure 2 shown, the wiring density of non - crowded wiring is small, and the wiring density of crowded wiring is large; the trace types generally include signal lines, power lines, ground lines, etc. In the embodiments, the trace type also includes the trace width. Specifically, when generating the predicted wiring status report, the trace width should also be considered, and the spacing between the traces is determined based on the trace width. Among them, the empirical defect size distribution refers to detecting and analyzing the defect data existing in the previous formed chips, and after statistical analysis, obtaining the distribution interval and interval ratio of the empirical defect sizes.

[0053] Step S02: Perform wiring design on the chip based on the generated predicted wiring status report.

[0054] Specifically, the steps of adjusting the routing pitch between adjacent traces based on the routing parameters of the traces in the initial routing status report are as follows: Based on the routing parameters of the traces in the initial routing status report, adjust the routing pitch between adjacent traces within a predetermined area; wherein, the predetermined area is determined based on the routing density and the empirical defect size, and the predetermined area also refers to the adjustable area of the routing parameters on the chip. It can be understood that the predetermined area refers to the area where failure phenomena are likely to occur, that is, the routing congestion area. In this embodiment, adjusting the routing pitch between adjacent traces in the routing congestion area can reduce the probability of failure between adjacent traces in the congestion area. According to the routing parameters of the traces in the routing status report, determine the routing congestion degree information (i.e., the routing density), and adjust the routing pitch between adjacent traces, which can well reduce the probability of defects falling on the signal lines and reduce the functional failure problems caused by chip signal, power supply short circuit or open circuit; The present invention mainly reduces the probability of chip failure caused by defects falling on the chip traces or between the traces through the method of backend physical implementation, and improves the yield of the chip.

[0055] It should be noted that there is also an unadjustable area in the chip, where the routing density is very high and there is no adjustment space for routing. For this area, it is set as an unadjustable area. Specifically, the area with a routing density greater than or equal to the first density is a non-predetermined area, that is, an unadjustable area, because the routing is too dense and there is no adjustment space; the area with a routing density less than the first density is an adjustable area. Generally, the first density is taken as 90%, and of course, other density values can also be taken according to actual needs. The adjustment of the routing pitch and the trace width mentioned in this application are all based on the area with surplus and adjustment space.

[0056] In one embodiment, when adjusting the routing pitch between adjacent traces, the routing pitch between associated traces can be enlarged and / or the routing pitch between non-associated traces can be reduced. Associated traces include power lines and / or signal lines that affect each other after conduction; non-associated traces include power lines and / or signal lines that do not affect each other after conduction. Specifically, as Figure 6 shown, Figure 6 the schematic diagram on the left in shows the routing schematic diagram of the power line VDD and the ground line VSS. Among them, the distance between the associated power line VDD and the ground line VSS is small. When dust (black part) falls between the power line VDD and the ground line VSS, it will cause a short circuit. To solve this problem, the distance between the associated power line VDD and the ground line VSS is increased. In order not to affect the area of the chip, while increasing the distance between the associated power line VDD and the ground line VSS, the distance between the non-associated power line VDD and the ground line VSS is reduced. In Figure 6Among them, both a and c are power supply lines VDD, and both b and d are ground lines VSS. Among them, a and b, as well as c and d, are associated power supply line VDD and ground line VSS, and b and c are non-associated power supply line VDD and ground line VSS.

[0057] Generate an appropriate wiring pitch adjustment rule according to the wiring density, wiring type, and corresponding empirical defect size distribution in a predetermined area; the adjustment rule is: the wiring pitch becomes larger; increasing the probability that a defect falls into the gap between wirings, or increasing the probability that a defect does not completely cover a wiring.

[0058] Specific adjustment rule: Make the wiring pitch greater than the maximum value of the interval with the largest proportion in the empirical defect size distribution interval. For example, if the empirical defect size follows a normal distribution, then the interval with the largest proportion in the empirical defect size distribution interval is the size interval corresponding to the convex part in the normal distribution. Taking the maximum value of this interval is to ensure that most defects will not cause chip failure. Defects will fall between lines and also on single lines. If the distance between lines is greater than the maximum value of the interval, this can increase the probability that a defect falls into the gap between wirings, thereby improving the yield of the chip. Similarly, increasing the width of the wiring, even if a defect falls on the wiring, since the size of the defect is smaller than the width of the wiring, the basic performance of the wiring can still be guaranteed. When the wiring pitch is greater than the maximum value of the interval with the largest proportion in the empirical defect size distribution interval, even if dust falls between two lines, it will not short-circuit the two connected lines.

[0059] Adjust the wiring pitch within the area according to the generated adjustment rule:

[0060] Specifically, the placement and routing tool will expand the spacing of the wiring in the corresponding area according to the generated adjustment rule, reducing the overall unit wiring density. During the production process, the probability of signal lines being short-circuited or open-circuited due to defects on the wafer will be greatly reduced, thereby overall reducing the probability of chip functional failure caused by defects.

[0061] Specifically, adjusting the wiring pitch between adjacent wirings in the predetermined area includes: determining the wiring pitch between adjacent wirings in the predetermined area based on the total area of the predetermined area, the wiring density of the predetermined area, the wiring degree of the predetermined area, and the number of wirings in the predetermined area. In a specific embodiment, define the total area of the adjustable area as S, the wiring density of this area as k, the wire length as l, the original wiring pitch as d, and the adjustment rule as the adjusted wiring pitch d = S*(1 - k) / (n - 1)*l. Where n is the number of wirings in this area.

[0062] Specifically, in order to generate adjustment rules targeted, facilitate wiring adjustment, and increase the failure probability of the chip, it further includes: further dividing the adjustable area; dividing the area where the wiring density is greater than the second density and less than the first density into the first predetermined area; dividing the area where the wiring density is less than or equal to the second density into the second predetermined area, that is, the wiring density of the first predetermined area is greater than that of the second area; adjusting the wiring pitch between adjacent traces in the first predetermined area based on the wiring density, trace type, and corresponding empirical defect size distribution in the first predetermined area; and adjusting the wiring pitch between adjacent traces in the second predetermined area based on the wiring density, trace type, and corresponding empirical defect size distribution in the second predetermined area. Preferably, the first density is 90% and the second density is 50%. When in the second area, that is, when the wiring density is less than or equal to 50%, it indicates that in this area, there is a void area greater than or equal to half of the total area of the area. The adjustment rule for this area is: the wiring pitch is expanded by 1.5 to 2 times or the trace width is expanded by 1.5 to 2 times.

[0063] Embodiment 1: According to the information on the wiring congestion (i.e., wiring density) in the chip layout and wiring stage, the entire chip is divided into multiple regions. According to the wiring congestion status of each region, the wiring pitch in different wiring density regions is adjusted respectively, so that the wiring pitch in the region with a smaller wiring density on the chip increases, thereby making the average wiring pitch of all chip signal lines (including digital signals, analog signal lines, etc.) on the chip larger, thereby increasing the probability that a defect falls into the gap between traces and reducing the probability that it falls on the signal line.

[0064] As Figure 3 shown, for signal lines with a relatively narrow width, according to the information on the wiring congestion in the chip layout and wiring stage, the wiring information of the entire chip is divided into different regions. The two regions represented by the green and blue regions in the figure respectively: the green is the region with less wiring congestion, and the blue is the region with relatively more wiring congestion.

[0065] For the two regions, different wiring rules (Non-default Routing Rule) are generated, so as to perform local wiring adjustment, and different wiring pitches are set for the signal lines in different regions. For example, the green region is adjusted using the maximum wiring pitch, and the comparison diagram before and after adjustment is as Figure 4 shown; the blue region is adjusted using a slightly larger wiring pitch, and the comparison diagram before and after adjustment is as Figure 5 shown.

[0066] Constraints are imposed on the wiring rules for the blue and green areas. The placement and routing tool will expand the wiring spacing within this area according to the set rules, reducing the overall unit wiring density. If a defect occurs on the wafer during the production process, the probability of signal line short - circuit or open - circuit will be greatly reduced, thereby overall reducing the probability of chip functional failure caused by defects.

[0067] After adjustment, when a defect appears in the blue and green areas, due to the increased wiring pitch, the probability of the defect falling on the signal line will be reduced, thus reducing the probability of chip functional failure caused by the defect for the entire chip.

[0068] Embodiment 2: For a relatively wide chip power mesh, short - circuits and open - circuits caused by defects are more fatal. For the layout implementation, chip failure caused by defects needs to be considered from the layout planning stage. Since the power lines themselves appear in pairs, when making the power network plan, by increasing the relative spacing between the power lines, the probability of a defect falling between the power lines can be effectively reduced, reducing the failure risk.

[0069] In the traditional power / ground wiring method, to reduce the coupling capacitance between power and ground, the minimum spacing is used between the power line and the ground line to ensure the robustness of the power network. However, if a defect falls between the power line and the ground line, it is extremely easy to cause a short - circuit in the power supply network, an increase in the local supply current, burning out the transistors, and resulting in chip failure.

[0070] According to the empirical defect size distribution and wiring density provided by the factory, the spacing between the power / ground lines is formulated. While meeting the design requirements, appropriately increasing the spacing between the power / ground lines can effectively reduce the probability of a defect falling between the power and ground lines, preventing short - circuit problems. As Figure 6 shown in the schematic diagram of the effect before and after adjustment. By using this method and appropriately increasing the wiring spacing between the power / ground lines, even if a defect occurs during the production process, the probability of the defect falling between the power / ground lines is reduced, preventing chip failure caused by a short - circuit in the power network, and effectively improving the chip yield.

[0071] The present invention also provides a chip wiring device, specifically as Figure 7 shown. The chip wiring device includes: a predicted wiring status report generation module 1 and a wiring design module 2;

[0072] Predicted routing status report generation module 1: It is used to obtain the routing parameters of the traces in the initial routing report, adjust the routing spacing between adjacent traces, and generate a predicted routing status report; wherein, the routing parameters include at least one of routing density, trace type, and the corresponding empirical defect size distribution.

[0073] Routing design module 2: Perform routing design on the chip based on the predicted routing status report.

[0074] See Figure 8 , an electronic device according to the present invention, which includes a processor and a memory coupled to each other, wherein the memory: is used to store program instructions for implementing the above-mentioned chip routing method; the processor: is used to execute the program instructions stored in the memory.

[0075] See Figure 9 , a computer-readable storage medium according to the present invention, on which a program file is stored, and the program file is executed to implement the above-mentioned chip routing method.

Claims

1. A chip wiring method, characterized in that, Including the following steps: Based on the routing parameters of the traces in the initial routing status report, adjust the routing spacing between adjacent traces to generate a predicted routing status report; The routing parameters include at least one of routing density, trace type, and the corresponding empirical defect size distribution; Among them, the step of adjusting the routing spacing between adjacent traces based on the routing parameters of the traces in the initial routing status report includes: dividing a predetermined area into a first predetermined area and a second predetermined area based on the routing density, where the routing density of the first predetermined area is greater than that of the second predetermined area; adjusting the routing spacing between adjacent traces in the first predetermined area based on the routing density, trace type, and the corresponding empirical defect size distribution of the first predetermined area; and adjusting the routing spacing between adjacent traces in the second predetermined area based on the routing density, trace type, and the corresponding empirical defect size distribution of the second predetermined area; the predetermined area is determined based on the routing density and the empirical defect size; Perform routing design on the chip based on the predicted routing status report.

2. The chip routing method according to claim 1, wherein Adjusting the routing spacing between adjacent traces includes: expanding the routing spacing between associated traces and / or reducing the routing spacing between non-associated traces, The associated traces include traces that affect each other after conduction; The non-associated traces include traces that do not affect each other after conduction.

3. The chip wiring method according to claim 1, wherein If the adjacent traces are two adjacent signal lines, expand the routing spacing between the two adjacent signal lines by 1.5 to 2 times.

4. The chip wiring method according to claim 1 or 3, characterized in that If the adjacent traces are an adjacent power line and a ground line, adjust the distance between the power line and the ground line to be greater than the maximum value of the interval with the largest proportion in the empirical defect size distribution interval.

5. The chip wiring method according to claim 1, wherein Adjusting the routing spacing between adjacent traces in a predetermined area includes: Determine the routing spacing between adjacent traces in the predetermined area based on the total area of the predetermined area, the routing density of the predetermined area, the routing degree of the predetermined area, and the number of traces in the predetermined area.

6. A chip wiring device, characterized in that, Including: Predicted routing status report generation module (1): Obtain the routing parameters of the traces in the initial routing report, adjust the routing spacing between adjacent traces, and generate a predicted routing status report; The routing parameters include at least one of routing density, trace type, and the corresponding empirical defect size distribution; Among them, the step of adjusting the routing spacing between adjacent traces based on the routing parameters of the traces in the initial routing status report includes: dividing a predetermined area into a first predetermined area and a second predetermined area based on the routing density, where the routing density of the first predetermined area is greater than that of the second predetermined area; adjusting the routing spacing between adjacent traces in the first predetermined area based on the routing density, trace type, and the corresponding empirical defect size distribution of the first predetermined area; and adjusting the routing spacing between adjacent traces in the second predetermined area based on the routing density, trace type, and the corresponding empirical defect size distribution of the second predetermined area; the predetermined area is determined based on the routing density and the empirical defect size; And a routing design module (2): Perform routing design on the chip based on the predicted routing status report.

7. An electronic device, characterized in that, Comprising a processor and a memory coupled to each other, wherein, The memory: is used for storing program instructions for implementing the chip wiring method according to any one of claims 1-5; The processor: is used for executing the program instructions stored in the memory.

8. A computer-readable storage medium, characterized in that, A program file is stored, and the program file is executed to implement the chip wiring method according to any one of claims 1-5.

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