High-Voltage Terminal Structure for Power Semiconductor Element and Method for Manufacturing the Same

Abstract

The present invention relates to a high-voltage terminal structure for a power semiconductor device and a manufacturing method thereof. This high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction terminal extension region having a second conductivity type, a heavily doped channel stopper region having a first conductivity type, and a plurality of field plates. The junction terminal extension region is formed in the semiconductor body, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device. The heavily doped channel stopper region is formed in the semiconductor body, wherein the heavily doped channel stopper region is separated from the junction terminal extension region. The plurality of field plates are formed on the junction terminal extension region. The present invention also provides a method for manufacturing a high-voltage terminal structure for a power semiconductor device.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to a high-voltage terminal structure for power semiconductor devices and a method of manufacturing the same. Background Art

[0002] Reliable power semiconductor devices require high-voltage terminal structures. Nowadays, high-voltage terminal structures can be presented in a variety of different forms, including field plates, floating guard rings, junction termination extensions (JTEs), and combinations of floating guard ring and field plate structures. In addition, combinations of these basic terminal technologies are also applied to the latest wide-bandgap semiconductors. For example, the variable lateral doping region with a reduced concentration terminal region disclosed in U.S. Patent No. 8,564,088B2 and the double guard ring terminal for silicon carbide disclosed in U.S. Patent No. 9,640,609B2.

[0003] The selection of a high-voltage terminal structure is related to the required blocking voltage. Existing data indicates that power devices below 100 volts prefer to use field plate type terminal structures; power devices from 100 volts up to 1200 volts, as Figure 1A shown, mainly use a combination of field plate type terminal structures and floating guard rings; any power device above 1200 volts, such as power diodes, metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and thyristor type devices, prefer to use junction termination extension type structures and combinations of junction termination extensions, floating guard rings, and field plate type terminal structures. For even higher voltages, such as above 5000 volts, bevel type terminal structures are used. Figure 1A is a schematic diagram showing a conventional high-voltage terminal structure with a field plate and a floating guard ring.

[0004] The three main considerations for setting up a high-voltage terminal structure include: (1) the required process steps for setting up the high-voltage terminal structure; (2) the required area for setting up the high-voltage terminal structure; and (3) the reliability of withstanding surface charge (Qss) variations. Generally speaking, when the surface charge changes (mainly when the positive charge changes), the surface charge in the terminal region affects the depletion region under a given reverse bias. For example, if the surface charge is high, the width of the depletion region in the terminal region shrinks, resulting in an increase in the electric field to a critical value, thereby causing the device to break down at a lower applied voltage.

[0005] Among multiple traditional high-voltage terminal structures, the area required to set up a junction termination extension type high-voltage terminal structure is the smallest. However, the junction termination extension structure is particularly sensitive to surface charge changes. To improve the tolerance of the junction termination extension structure to surface charges, Temple and his colleagues proposed a multi-zone junction termination extension (MZ-JTE) structure, as Figure 1B shown. However, setting up this multi-zone junction termination extension structure requires a larger or additional area. Summary of the Invention

[0006] An object of the present invention is to provide a new high-voltage terminal structure that can improve the tolerance of surface charges while minimally increasing the area for setting up the high-voltage terminal structure.

[0007] Some embodiments of the present invention provide a high-voltage terminal structure for a power semiconductor device. This high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction termination extension region having a second conductivity type, a heavily doped channel stop region having the first conductivity type, and a plurality of field plates. The junction termination extension region is formed in the semiconductor body, wherein the junction termination extension region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is separated from the junction termination extension region. The plurality of field plates are formed on the junction termination extension region.

[0008] In some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0009] In some embodiments of the present invention, these field plates are made of a metal material.

[0010] In some embodiments of the present invention, these field plates are made of P-type polysilicon.

[0011] In some embodiments of the present invention, these field plates are made of N-type polysilicon.

[0012] Some embodiments of the present invention provide a high-voltage terminal structure for a power semiconductor device. The high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction terminal extension region having a second conductivity type, a heavily doped channel isolation region having the first conductivity type, and a plurality of depletable guard rings having the second conductivity type. The junction terminal extension region is formed in the semiconductor body, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device. The heavily doped channel isolation region is formed in the semiconductor body, wherein the heavily doped channel isolation region is separated from the junction terminal extension region. The plurality of depletable guard rings having the second conductivity type are formed in the semiconductor body, wherein the depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region.

[0013] In some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0014] Some embodiments of the present invention provide a high-voltage terminal structure for a power semiconductor device. The high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction terminal extension region having a second conductivity type, a plurality of lightly doped regions having the second conductivity type, and a heavily doped channel isolation region having the first conductivity type. The junction terminal extension region is formed in the semiconductor body, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device. The plurality of lightly doped regions are formed in the junction terminal extension region and are adjacent to an upper surface of the junction terminal extension region. The heavily doped channel isolation region is formed in the semiconductor body, wherein the heavily doped channel isolation region is separated from the junction terminal extension region.

[0015] In some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0016] In some embodiments of the present invention, a lateral width of these lightly doped regions increases in a direction toward the heavily doped channel isolation region.

[0017] In some embodiments of the present invention, a distance between a lightly doped region adjacent to the active region and the active region is greater than a distance between adjacent lightly doped regions.

[0018] In some embodiments of the present invention, the high-voltage terminal structure further includes a plurality of field plates formed on the junction terminal extension region. In another embodiment of the present invention, these field plates are made of a metallic material. In yet another embodiment of the present invention, these field plates are made of P-type polysilicon. In yet another embodiment of the present invention, these field plates are made of N-type polysilicon.

[0019] Some embodiments of the present invention provide a high-voltage terminal structure for a power semiconductor device. The high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction terminal extension region having a second conductivity type, a heavily doped channel isolation region having the first conductivity type, a plurality of depletable guard rings having the second conductivity type, and a plurality of lightly doped regions having the second conductivity type. The junction terminal extension region is formed in the semiconductor body, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device. The heavily doped channel isolation region is formed in the semiconductor body, wherein the heavily doped channel isolation region is separated from the junction terminal extension region. The plurality of depletable guard rings are formed in the semiconductor body, wherein the depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region. The plurality of lightly doped regions are formed in an upper portion of the junction terminal extension region and at least one of the depletable guard rings.

[0020] In some embodiments of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0021] In some embodiments of the present invention, the lateral width of the lightly doped regions increases in a direction toward the heavily doped channel isolation region.

[0022] In some embodiments of the present invention, a spacing between a lightly doped region adjacent to the active region and the active region is greater than a spacing between adjacent lightly doped regions.

[0023] In some embodiments of the present invention, a gap between the depletable guard rings increases in a direction toward the heavily doped channel isolation region.

[0024] In some embodiments of the present invention, the high-voltage terminal structure further includes a plurality of field plates formed on the junction terminal extension region. In another embodiment of the present invention, the field plates are made of a metal material. In yet another embodiment of the present invention, the field plates are made of P-type polysilicon. In yet another embodiment of the present invention, the field plates are made of N-type polysilicon.

[0025] Some embodiments of the present invention provide a method of manufacturing a high-voltage terminal structure for a power semiconductor device. The method includes: forming a heavily doped channel isolation region having the first conductivity type in a semiconductor body having the first conductivity type by ion implantation having a first conductivity type; forming a junction terminal extension region having the second conductivity type in the semiconductor body by ion implantation having a second conductivity type, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel isolation region; and forming a plurality of field plates on the junction terminal extension region.

[0026] Some embodiments of the present invention provide a method for manufacturing a high-voltage terminal structure for a power semiconductor device. This method includes: forming a heavily doped channel isolation region of a first conductivity type in a semiconductor body of a first conductivity type by ion implantation of a first conductivity type; forming a junction terminal extension region of a second conductivity type in the semiconductor body by ion implantation of a second conductivity type, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel isolation region; and forming a plurality of depletable guard rings of a second conductivity type on the semiconductor body by ion implantation of a second conductivity type, wherein these depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region.

[0027] In some embodiments of the present invention, the junction terminal extension region and these depletable guard rings are formed in the semiconductor body simultaneously.

[0028] Some embodiments of the present invention provide a method for manufacturing a high-voltage terminal structure for a power semiconductor device. This method includes: forming a heavily doped channel isolation region of a first conductivity type in a semiconductor body of a first conductivity type by ion implantation of a first conductivity type; forming a junction terminal extension region of a second conductivity type in the semiconductor body by ion implantation of a second conductivity type, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel isolation region; and forming a plurality of lightly doped regions of a second conductivity type in the junction terminal extension region by ion implantation of a first conductivity type, and these lightly doped regions are adjacent to an upper surface of the junction terminal extension region.

[0029] In some embodiments of the present invention, this method further includes forming a plurality of field plates on the junction terminal extension region.

[0030] Some embodiments of the present invention provide a method for manufacturing a high-voltage terminal structure for a power semiconductor device. This method includes: forming a heavily doped channel isolation region of a first conductivity type in a semiconductor body of a first conductivity type by ion implantation of a first conductivity type; forming a junction terminal extension region of a second conductivity type and a plurality of depletable guard rings of a second conductivity type in the semiconductor body by ion implantation of a second conductivity type, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel isolation region, and these depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region; and forming a plurality of lightly doped regions of a second conductivity type in the junction terminal extension region and these depletable guard rings by ion implantation of a second conductivity type, and these lightly doped regions are adjacent to an upper surface of the junction terminal extension region.

[0031] In some embodiments of the present invention, this method further includes forming a plurality of field plates on the junction terminal extension region.

[0032] Specific embodiments adopted in the present invention will be further described through the following embodiments and diagrams. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A is a schematic diagram showing a conventional high-voltage terminal structure with field plates and a floating guard ring;

[0034] Figure 1B is a schematic diagram showing a conventional high-voltage terminal structure with a multi-zone junction terminal extension (MZ-JTE) structure;

[0035] Figure 2A is a schematic diagram showing a high-voltage terminal structure with a lateral modulation junction terminal extension structure provided according to a first embodiment of the present disclosure;

[0036] Figure 2B shows the potential distribution of a silicon-based high-voltage terminal structure with a lateral modulation junction terminal extension structure under a 1300V bias and 5e 10 Cm -2 surface charge in an analog structure;

[0037] Figure 2C shows the potential distribution of a silicon-based high-voltage terminal structure with a lateral modulation junction terminal extension structure under a 1250V bias and 5e 11 Cm -2 surface charge in an analog structure;

[0038] Figure 2D shows the surface potential of a silicon-based high-voltage terminal structure with a lateral modulation junction terminal extension structure under a 1300V bias and 5e 10 Cm -2 surface charge in a drawing;

[0039] Figure 2E shows the surface potential of a silicon-based high-voltage terminal structure with a lateral modulation junction terminal extension structure under a 1250V bias and 5e 11 Cm -2 surface charge in a drawing;

[0040] Figure 3 is a schematic diagram showing a high-voltage terminal structure with a junction terminal extension structure having field plates provided according to a second embodiment of the present disclosure;

[0041] Figure 4A is a schematic diagram showing a high-voltage terminal structure with a junction terminal extension structure having a depletable guard ring provided according to a third embodiment of the present disclosure;

[0042] Figure 4B A simulation structure is used to display the potential distribution of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias voltage and a surface charge of 5e 10 Cm -2 , and this junction terminal extension structure has a depletable guard ring and a field plate;

[0043] Figure 4C A simulation structure is used to display the potential distribution of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias voltage and a surface charge of 5e 11 Cm -2 , and this junction terminal extension structure has a depletable guard ring and a field plate;

[0044] Figure 4D An attached figure is used to display the surface potential of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias voltage and a surface charge of 5e 10 Cm -2 , and this junction terminal extension structure has a depletable guard ring and a field plate;

[0045] Figure 4E An attached figure is used to display the surface potential of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias voltage and a surface charge of 5e 11 Cm -2 , and this junction terminal extension structure has a depletable guard ring and a field plate;

[0046] Figure 5 It is a schematic diagram showing a high-voltage terminal structure with a laterally modulated junction terminal extension structure provided according to the fourth embodiment of the present disclosure, and this laterally modulated junction terminal extension structure has a depletable guard ring and a field plate;

[0047] Figure 6 It is a schematic diagram showing a high-voltage terminal structure with a laterally modulated junction terminal extension structure provided according to the fifth embodiment of the present disclosure, and this laterally modulated junction terminal extension structure has a field plate;

[0048] Figures 7A to 7G It is a manufacturing process showing a high-voltage terminal structure with a junction terminal extension structure provided according to an embodiment of the present disclosure, and this junction terminal extension structure has a depletable guard ring and a field plate;

[0049] Figures 8A to 8G It is a manufacturing process showing a high-voltage terminal structure with a laterally modulated junction terminal extension structure provided according to an embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 100, 200, 300, 400, 500: High - voltage terminal structure

[0052] 110, 210, 310, 410, 510, 610, 710: N - type semiconductor body

[0053] 112, 212, 312, 412, 512: N - type semiconductor layer

[0054] 114, 214, 314, 414, 514: Cathode electrode

[0055] 120, 220, 320, 420, 520, 620, 720: P - type junction terminal extension region

[0056] 130a~130h, 430a~430e, 530a~530h, 730a~730f: P - type lightly doped region

[0057] 140, 240, 340, 440, 540, 640, 740: N - type heavily doped channel stopper region

[0058] 150, 250, 350, 450, 550: Active region

[0059] 151, 251, 351, 451, 551, 651, 751: P - type well

[0060] 152, 252, 352, 452, 552: P - type heavily doped region

[0061] 154, 254, 354, 454, 554, 654, 754: Anode electrode

[0062] 260, 360, 460, 560, 660, 760: Field plate

[0063] 370, 470, 670: P - type depletable guard ring

[0064] 652, 752: P - type anode region

[0065] 680, 780: Dielectric layer

[0066] 682, 782: Contact window

[0067] 690, 790: Passivation layer Detailed implementation manners

[0068] The following will describe the specific embodiments of the present disclosure in more detail with reference to the schematic diagrams. The advantages and features of the present disclosure will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present disclosure. For illustrative purposes, the following paragraphs describe N-type devices. However, P-type devices can also be manufactured by similar but opposite conductivity type processes.

[0069] As described above, the surface charge (Qss) in the terminal region affects the depletion region under a given reverse bias. To solve the above problems, the embodiments of the present disclosure provide a high-voltage terminal structure that can minimize the shrinkage of depletion diffusion in the terminal region and reduce the peak electric field change in the terminal region under low and high surface charge conditions, so as to improve the tolerance to surface charge changes.

[0070] Refer to Figure 2A , the following describes a high-voltage terminal structure with a laterally modulated junction terminal extension structure provided according to the first embodiment of the present disclosure.

[0071] As Figure 2A shown, the high-voltage terminal structure 100 includes an N-type semiconductor body 110, a P-type junction terminal extension region 120, a plurality of P-type lightly doped regions 130a - 130h, and an N-type heavily doped channel blocking region 140.

[0072] On a lower surface of the N-type semiconductor body 110, there is an N-type semiconductor layer 112 with a doping concentration higher than that of the N-type semiconductor body 110. The N-type semiconductor layer 112 is used to reduce the contact resistance between the N-type semiconductor body 110 and a cathode electrode 114 in the power semiconductor device.

[0073] The P-type junction terminal extension region 120 is formed on the upper part of the N-type semiconductor body 110. The P-type junction terminal extension region 120 is adjacent to an active region 150 of the power semiconductor device and extends from the active region 150 towards the edge. More precisely, the P-type junction terminal extension region 120 extends from the P-type well 151 of the active region 150 towards the edge of the power semiconductor device. The P-type well 151 is electrically connected to an anode electrode 154 through a P-type heavily doped region 152.

[0074] According to an embodiment of the present disclosure, the P-type junction terminal extension region 120 may have a fixed depth, and the depth of the P-type junction terminal extension region 120 may be equal to or less than the depth of the P-type well 151.

[0075] The P-type lightly doped regions 130a to 130h are formed in the upper portion of the P-type junction terminal extension region 120, that is, the portion close to the upper surface of the P-type junction terminal extension region 120. These P-type lightly doped regions 130a to 130h are separated from each other.

[0076] The N-type heavily doped channel stopper region 140 is formed in the upper portion of the N-type semiconductor body 110. The N-type heavily doped channel stopper region 140 is located outside the P-type junction terminal extension region 120 to limit the depletion region at the outer edge of the semiconductor device under reverse bias. In this embodiment, a metal layer is formed on the N-type heavily doped channel stopper region 140. However, it is not limited thereto. In other embodiments, the metal layer formed on the N-type heavily doped channel stopper region 140 may also be omitted.

[0077] The P-type junction terminal extension region 120 and the plurality of P-type lightly doped regions 130a to 130h located therein form a P-type laterally modulated junction terminal extension region. The N-type heavily doped channel stopper region 140 and the P-type junction terminal extension region 120 are separated by an N-type region. This N-type region is the surface portion of the N-type semiconductor body 110. That is, a lateral terminal structure having a P-type laterally modulated junction terminal extension region, an N-type region, and the N-type heavily doped channel stopper region 140 extends from the active region 150 to the edge. The structure of the P-type laterally modulated junction terminal extension region presents an alternating arrangement of P regions and P- regions, and the P regions and P- regions are close to the upper surface of the semiconductor body.

[0078] The P-type laterally modulated junction terminal extension region has a P-type junction terminal extension region with a uniform depth and a plurality of alternately arranged P and P- regions in the upper portion of the P-type junction terminal extension region to expand the depletion region. Thus, the P-type laterally modulated junction terminal extension region can control the peak value of the surface electric field without sacrificing too much breakdown voltage. That is, the P-type laterally modulated junction terminal extension region can reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0079] The number, lateral width, and spacing of the P-type lightly doped regions 130a to 130h in the P-type junction terminal extension region 120 can be adjusted to balance the blocking ability and the tolerance of the surface charge. As Figure 2AFurther shown, according to a preferred embodiment of the present disclosure, the lateral widths of the P-type lightly doped regions 130a to 130h increase along the direction toward the N-type heavily doped channel stopper region 140, and the distance between the P-type lightly doped region 130a adjacent to the active region 150 and the active region 150 is greater than the distance between adjacent P-type lightly doped regions 130a to 130h. By performing this doping modulation on the P-type junction terminal extension region 120, the contraction of the depletion expansion toward the N-type heavily doped channel stopper region 140 causes the depletion region at the P-type junction terminal extension region 120 to deepen its expansion depth along the direction toward the active region 150. The embodiments of the present invention are not limited thereto. Depending on the actual situation, the variation in the lateral widths of the P-type lightly doped regions 130a to 130h and the configuration of the P-type lightly doped regions 130a to 130h within the P-type junction terminal extension region 120 can be adjusted, and this does not depart from the scope of the present invention.

[0080] To more clearly understand the effects of the aforementioned laterally modulated junction terminal extension structure, please refer to Figures 2B to 2E . Figure 2B Thus, a simulated structure shows the potential distribution of a silicon-based high-voltage terminal structure with a laterally modulated junction terminal extension structure under a bias voltage of 1300V and a surface charge of 5e 10 Cm -2 . Figure 2C Thus, a simulated structure shows the potential distribution of a silicon-based high-voltage terminal structure with a laterally modulated junction terminal extension structure under a bias voltage of 1250V and a surface charge of 5e 11 Cm -2 . Figure 2D Thus, a drawing shows the surface potential of a silicon-based high-voltage terminal structure with a laterally modulated junction terminal extension structure under a bias voltage of 1300V and a surface charge of 5e 10 Cm -2 . Figure 2E Thus, a drawing shows the surface potential of a silicon-based high-voltage terminal structure with a laterally modulated junction terminal extension structure under a bias voltage of 1250V and a surface charge of 5e 11 Cm -2 .

[0081] The high-voltage terminal structure set in this simulation has a laterally modulated junction terminal extension structure, where the P-type junction terminal extension region has a fixed depth, and phosphorus ions are implanted in the P-type junction terminal extension region through mask windows of different sizes. The size of the phosphorus ion implantation window increases along the direction from the active region toward the N-type heavily doped channel stopper region (i.e., the die edge), and the distance between these implantation windows decreases along the direction from the active region toward the N-type heavily doped channel stopper region to increase the doping modulation. The method of phosphorus ion compensation implantation modulates the doping concentration of the P-type junction terminal extension region to form a laterally modulated junction terminal extension region.

[0082] As Figure 2B shown, in the case of low surface positive charge, i.e., 5e 10 Cm -2 of surface charge, the depletion region expands from the N-type heavily doped channel blocking region towards the surface region of the P-type junction terminal extension region. As Figure 2C shown, in the case of high surface positive charge, i.e., 5e 11 Cm -2 of surface charge, the degree of expansion of the depletion region from the P-type junction terminal extension region towards the N-type heavily doped channel blocking region is reduced. However, due to the doping modulation in the P-type junction terminal extension region, the reduction in the degree of expansion of the depletion region towards the N-type heavily doped channel blocking region causes the depletion region at the P-type junction terminal extension region to deepen its diffusion depth along the direction towards the active region.

[0083] As Figure 2D and Figure 2E shown, the simulation results of low surface charge and high surface charge show a uniform surface potential distribution at bias voltages of 1300V and 1250V. Therefore, the lateral modulation junction terminal extension structure provided according to the embodiments of the present invention can effectively prevent the power element from breaking down at a relatively low voltage. In practice, in both the case of low surface charge and high surface charge, the high-voltage terminal structure with the lateral modulation junction terminal extension structure can achieve a breakdown voltage of more than 1200V.

[0084] Refer to Figure 3 , the following describes a high-voltage terminal structure of a junction terminal extension structure with a field plate provided according to the second embodiment of the present disclosure.

[0085] As Figure 3 shown, the high-voltage terminal structure 200 includes an N-type semiconductor body 210, a P-type junction terminal extension region 220, an N-type heavily doped channel blocking region 240, and a plurality of field plates 260 (three field plates are shown in the figure).

[0086] On the lower surface of the N-type semiconductor body 210, there is an N-type semiconductor layer 212, whose doping concentration is higher than that of the N-type semiconductor body 210. The N-type semiconductor layer 212 is used to reduce the contact resistance between the N-type semiconductor body 210 and the cathode electrode 214 in the power semiconductor device.

[0087] The P-type junction terminal extension region 220 is formed in the upper portion of the N-type semiconductor body 210, that is, the portion close to its upper surface. The P-type junction terminal extension region 220 is adjacent to the active region 250 of the power semiconductor device and extends from the active region 250 toward the edge. More precisely, the P-type junction terminal extension region 220 extends from the P-type well 251 of the active region 250 toward the edge of the power semiconductor device. The P-type well 251 is electrically connected to the anode electrode 254 through a P-type heavily doped region 252.

[0088] The N-type heavily doped channel isolation region 240 is formed in the upper portion of the N-type semiconductor body 210 located outside the P-type junction terminal extension region 220 to limit the depletion region at the outer edge of the semiconductor device under reverse bias. The N-type heavily doped channel isolation region 240 is separated from the P-type junction terminal extension region 220 by an N-type region (a partial region of the upper portion of the N-type semiconductor body 210). That is, a lateral terminal structure having a P-type junction terminal extension region 220, an N-type region, and an N-type heavily doped channel isolation region 240 is formed. This embodiment further has a metal layer formed on the N-type heavily doped channel isolation region 240. However, in other embodiments, the metal layer formed on the N-type heavily doped channel isolation region 240 can be omitted.

[0089] A plurality of field plates 260 are formed on the P-type junction terminal extension region 220. The field plates 260 on the P-type junction terminal extension region 220 can disperse the electric field generated by the surface charge outward to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0090] In an embodiment of the present invention, the field plate 260 can be made of a metal material and form a Schottky contact with the P-type junction terminal extension region 220. In an embodiment of the present invention, the field plate 260 can be made of P-type polysilicon material and form an ohmic contact with the P-type junction terminal extension region 220. In an embodiment of the present invention, the field plate 260 can be made of N-type polysilicon material and form a PN junction with the P-type junction terminal extension region 220.

[0091] Refer to Figure 4A , the following describes a high-voltage terminal structure of a junction terminal extension structure with a depletable guard ring according to the third embodiment of the present disclosure.

[0092] As Figure 4A shown, the high-voltage terminal structure 300 includes an N-type semiconductor body 310, a P-type junction terminal extension region 320, an N-type heavily doped channel isolation region 340, a plurality of field plates 360 (three field plates are shown in the figure), and a plurality of P-type depletable guard rings 370 (four depletable guard rings are shown in the figure).

[0093] The lower surface of the N-type semiconductor body 310 has an N-type semiconductor layer 312 with a doping concentration higher than that of the N-type semiconductor body 310. The N-type semiconductor layer 312 is used to reduce the contact resistance between the N-type semiconductor body 310 and the cathode electrode 314 in the power semiconductor device.

[0094] The P-type junction terminal extension region 320 is formed in the upper part of the N-type semiconductor body 310. The P-type junction terminal extension region 320 is adjacent to the active region 350 of the power semiconductor device. More precisely, the P-type junction terminal extension region 320 is adjacent to the P-type well 351 of the active region 350 of the power semiconductor device. The P-type well 351 is electrically connected to the anode electrode 354 through a P-type heavily doped region 352.

[0095] The N-type heavily doped channel blocking region 340 is formed in the upper part of the N-type semiconductor body 310 located outside the P-type junction terminal extension region 320 to limit the depletion region at the outer edge of the semiconductor device under reverse bias. The N-type heavily doped channel blocking region 340 is separated from the P-type junction terminal extension region 320 by an N-type region (i.e., a partial region of the upper part of the N-type semiconductor body 310). This embodiment also has a metal layer formed on the N-type heavily doped channel blocking region 340. However, in other embodiments, the metal layer formed on the N-type heavily doped channel blocking region 340 can be omitted.

[0096] A plurality of P-type depletable guard rings 370 are formed in the upper part of the N-type semiconductor body 310 and are formed between the P-type junction terminal extension region 320 and the N-type heavily doped channel blocking region 340. These P-type depletable guard rings 370 are electrically floating. When a high bias voltage is applied to the power semiconductor device, the P-type depletable guard rings 370 are depleted to generate a charge balance region in the N-type region between the P-type junction terminal extension region 320 and the N-type heavily doped channel blocking region 340 to expand the depletion region. This helps to disperse the electric field generated by the surface charge to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0097] A plurality of field plates 360 are formed on the P-type junction terminal extension region 320 and the P-type depletable guard rings 370. The field plates 360 can disperse the electric field generated by the charge to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0098] To more clearly understand the effects produced by the aforementioned depletable guard rings and field plates together with the junction terminal extension structure, please refer to Figures 4B to 4E . Figure 4B Thus, an analog structure shows a silicon-based high-voltage terminal structure with a junction terminal extension structure at a 630V bias voltage and 5e 10 Cm-2 The potential distribution under the surface charge, and this junction terminal extension structure has a depletable guard ring and a field plate. Figure 4C An analog structure shows the potential distribution of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias and 5e 11 Cm -2 The potential distribution under the surface charge, and this junction terminal extension structure has a depletable guard ring and a field plate. Figure 4D An attached figure shows the surface potential of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias and 5e 10 Cm -2 The surface potential under the surface charge, and this junction terminal extension structure has a depletable guard ring and a field plate. Figure 4E An attached figure shows the surface potential of a silicon-based high-voltage terminal structure with a junction terminal extension structure under a 630V bias and 5e 11 Cm -2 The surface potential under the surface charge, and this junction terminal extension structure has a depletable guard ring and a field plate.

[0099] This simulated high-voltage terminal structure of the setting has a P-type junction terminal extension region with a fixed depth, five P-type depletable guard rings, and two field plates. The P-type depletable guard rings are located between the P-type junction terminal extension region and the N-type heavily doped channel isolation region.

[0100] Please refer to Figure 4B and Figure 4C Compared with the case of low surface positive charge, that is, 5e 10 Cm -2 of surface charge, in the case of high surface positive charge, that is, 5e 11 Cm -2 of surface charge, the depletion region between the last P-type depletable guard ring and the N-type heavily doped channel isolation region expands more towards the P-type junction terminal extension region than towards the N-type region. The field plates on the P-type depletable guard rings help to expand the depletion region in the N-type region between the last P-type depletable guard ring and the N-type heavily doped channel isolation region towards the grain edge to prevent the breakdown voltage from dropping.

[0101] As Figure 4D and Figure 4EAs shown, the simulation results of both low surface charge and high surface charge show that at a bias voltage of 630V, there is a uniform surface potential distribution. Therefore, the high-voltage terminal structure with a junction terminal extension structure combined with a depletable guard ring and a field plate provided according to an embodiment of the present invention can effectively prevent the power element from breaking down at a relatively low voltage. In practice, in both the case of low surface charge and high surface charge, the high-voltage terminal structure with a junction terminal extension structure combined with a depletable guard ring and a field plate can achieve a breakdown voltage of more than 600V.

[0102] Figure 3 The high-voltage terminal structure with a junction terminal extension structure combined with a depletable guard ring shown in Figure 4A The high-voltage terminal structure with a junction terminal extension structure combined with a depletable guard ring and a field plate shown in both have similar working principles. They both counter the problem of the depletion region shrinking caused by high surface charge, enabling the terminal structure of the power element to reach the required breakdown voltage. The field plate can be assumed to have the potential of the P-type region it contacts, such as the P-type junction terminal extension region or the P-type depletable guard ring, regardless of the type of electrical contact formed between the field plate and the P-type region. These field plates with the potential of the contacted P-type region can disperse the surface potential to a longer depletion region to reduce the phenomenon of the surface electric field increasing as the surface charge increases.

[0103] As Figure 3 and Figure 4A shown, the combination of a field plate and a depletable guard ring with a junction terminal extension structure can be used for power elements above 600V. As Figure 5 and Figure 6 shown, the combination of a field plate and a depletable guard ring with a laterally modulated junction terminal extension structure can provide additional capabilities to mitigate the reduction of the breakdown voltage caused by the increase in surface charge in power elements with a breakdown voltage reaching about 1200V or above.

[0104] Refer to Figure 5 for the following description of a high-voltage terminal structure with a laterally modulated junction terminal extension structure combined with a depletable guard ring and a field plate provided according to the fourth embodiment of the present disclosure.

[0105] As Figure 5 shown, the high-voltage terminal structure 400 includes an N-type semiconductor body 410, a P-type junction terminal extension region 420, a plurality of P-type lightly doped regions 430a - 430e, an N-type heavily doped channel isolation region 440, a plurality of field plates 460 (three field plates are shown in the figure), and a plurality of P-type depletable guard rings 470 (four depletable guard rings are shown in the figure).

[0106] The lower surface of the N-type semiconductor body 410 has an N-type semiconductor layer 412, whose doping concentration is higher than that of the N-type semiconductor body 410. The N-type semiconductor layer 412 is used to reduce the contact resistance between the N-type semiconductor body 410 and the cathode electrode 414 in the power semiconductor device.

[0107] The P-type junction terminal extension region 420 is formed in the upper part of the N-type semiconductor body 410. The P-type junction terminal extension region 420 is adjacent to the active region 450 of the power semiconductor device. More precisely, the P-type junction terminal extension region 420 is adjacent to the P-type well 451 of the active region 450 of the power semiconductor device. The P-type well 451 is electrically connected to the anode electrode 454 through a P-type heavily doped region 452.

[0108] The N-type heavily doped channel isolation region 440 is formed in the upper part of the N-type semiconductor body 410 located outside the P-type junction terminal extension region 420 to limit the depletion region at the outer edge of the semiconductor device under reverse bias. This embodiment also has a metal layer formed on the N-type heavily doped channel isolation region 440. However, in other embodiments, the metal layer formed on the N-type heavily doped channel isolation region 440 can also be omitted.

[0109] A partial P-type lightly doped region, that is, the P-type lightly doped region 430a, is formed in the upper part of the P-type junction terminal extension region 420. The P-type junction terminal extension region 420 and the P-type lightly doped region 430a inside it form a P-type lateral modulation junction terminal extension region.

[0110] These P-type depletable guard rings 470 are formed in the upper part of the N-type semiconductor body 410 and are located between the P-type junction terminal extension region 420 and the N-type heavily doped channel isolation region 440. These P-type depletable guard rings 370 are electrically floating. When a high bias voltage is applied to the power semiconductor device, the P-type depletable guard rings 370 will be depleted to generate a charge balance region in the N-type region between the P-type junction terminal extension region 420 and the N-type heavily doped channel isolation region 440 to expand the depletion region. This helps to disperse the electric field generated by the charge to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0111] These P-type lightly doped regions 430a - 430e are formed in the upper part of the P-type junction terminal extension region 420 and within the P-type depletable guard ring 470 to modulate the P-type junction terminal extension region 420 and the P-type depletable guard ring 470. As shown in the figure, the P-type lightly doped region 430a is located in the upper part of the P-type junction terminal extension region 420, and the P-type lightly doped regions 430b to 430e are respectively located within the respective P-type depletable guard rings 470. These P-type lightly doped regions 430a - 430e are separated from each other. As shown in the figure, this configuration forms a lateral terminal structure having a P-type laterally modulated junction terminal extension region, a P-type depletable guard ring 470, an N-type region (a partial region of the upper part of the N-type semiconductor body), and an N-type heavily doped channel stopper region 440, extending from the active region 450 to the edge.

[0112] Multiple field plates 460 are formed on the P-type junction terminal extension region 420 and the P-type depletable guard ring 470. These field plates 460 can disperse the electric field generated by the surface charge outward to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge. In an embodiment of the present invention, the field plate 460 can be made of a metal material and form a Schottky contact with the P-type region, that is, the P-type junction terminal extension region 420 or the P-type depletable guard ring 470. In an embodiment of the present invention, the field plate 460 can be made of P-type polysilicon material and form an ohmic contact with the P-type region. In an embodiment of the present invention, the field plate 460 can be made of N-type polysilicon material and form a PN junction with the P-type region.

[0113] As described above, the structure of the P-type laterally modulated junction terminal extension region presents multiple P regions and P- regions to reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge. The field plate and the depletable guard ring can counteract the problem of the depletion region shrinking caused by high surface charge, enabling the terminal structure of the power device to reach the required breakdown voltage.

[0114] Refer to Figure 6 , the following describes a high-voltage terminal structure of a laterally modulated junction terminal extension structure with a field plate according to the fifth embodiment of the present disclosure.

[0115] As Figure 6 shown, the high-voltage terminal structure 500 includes an N-type semiconductor body 510, a P-type junction terminal extension region 520, multiple P-type lightly doped regions 530a - 530h, an N-type heavily doped channel stopper region 540, and multiple field plates 560 (three field plates are shown in the figure).

[0116] The lower surface of the N-type semiconductor body 510 has an N-type semiconductor layer 512, whose doping concentration is higher than that of the N-type semiconductor body 510. The N-type semiconductor layer 512 is used to reduce the contact resistance between the N-type semiconductor body 510 and the cathode electrode 514 in the power semiconductor device.

[0117] The P-type junction terminal extension region 520 is formed in the upper portion of the N-type semiconductor body 510. The P-type junction terminal extension region 520 is adjacent to the active region 550 of the power semiconductor device and extends from the active region 550 toward the edge. More precisely, the P-type junction terminal extension region 520 is the P-type well 551 adjacent to the active region 550 of the power semiconductor device. The P-type well 551 is electrically connected to the anode electrode 554 through a P-type heavily doped region 552.

[0118] The P-type lightly doped regions 530a to 530h are formed in the upper portion of the P-type junction terminal extension region 520, that is, the portion close to the upper surface of the P-type junction terminal extension region 520. These P-type lightly doped regions 530a to 530h are separated from each other.

[0119] The N-type heavily doped channel isolation region 540 is formed in the upper portion of the N-type semiconductor body 510 located outside the P-type junction terminal extension region 520 to limit the depletion region at the outer edge of the semiconductor device under reverse bias. This embodiment also has a metal layer formed on the N-type heavily doped channel isolation region 540. However, in other embodiments, the metal layer formed on the N-type heavily doped channel isolation region 540 can also be omitted.

[0120] The P-type junction terminal extension region 520 and the plurality of P-type lightly doped regions 530a to 530h formed therein form a P-type laterally modulated junction terminal extension region. The N-type heavily doped channel isolation region 540 is separated from the P-type junction terminal extension region 520 by an N-type region, that is, the surface portion of the N-type semiconductor body 510. Thus, a lateral terminal structure having a P-type laterally modulated junction terminal extension region, an N-type region, and the N-type heavily doped channel isolation region 540 extends from the active region 550 to the edge. The structure of the P-type laterally modulated junction terminal extension region presents an alternating arrangement of P regions and P- regions, and the P regions and P- regions are close to the upper surface of the semiconductor body to spread the depletion region. Therefore, the P-type laterally modulated junction terminal extension region can reduce the reduction of the reverse breakdown voltage caused by the change of the surface charge.

[0121] Similar to Figure 2AIn the illustrated embodiment, according to a preferred embodiment of the present invention, the lateral widths of the P-type lightly doped regions 530a to 530h increase in the direction toward the N-type heavily doped channel stopper region 540, and the distance between the P-type lightly doped region 530a adjacent to the active region 550 and the active region 550 is greater than the distance between adjacent P-type lightly doped regions 530a to 530h. By doping modulation of the P-type junction terminal extension region 520, the shrinkage of the depletion expansion toward the N-type heavily doped channel stopper region 540 causes the depletion region at the P-type junction terminal extension region 520 to deepen its expansion depth in the direction toward the active region 550. The embodiments of the present invention are not limited thereto. Depending on the actual situation, the change in the lateral widths of the P-type lightly doped regions 530a to 530h and the configuration of the P-type lightly doped regions 530a to 530h within the P-type junction terminal extension region 520 can be adjusted without departing from the scope of the present invention.

[0122] A plurality of field plates 560 are formed on the P-type junction terminal extension region 520. These field plates 560 can counteract the problem of the depletion region shrinking caused by high surface charges, enabling the terminal structure of the power device to reach the required breakdown voltage. That is, the field plates 560 help reduce the reduction in the reverse breakdown voltage caused by surface charge variations. In an embodiment of the present invention, the field plates 560 can be made of a metal material and form a Schottky contact with the P-type junction terminal extension region 520. In an embodiment of the present invention, the field plates 560 can be made of P-type polysilicon material and form an ohmic contact with the P-type junction terminal extension region 520. In an embodiment of the present invention, the field plates 560 can be made of N-type polysilicon material and form a PN junction with the P-type junction terminal extension region 520.

[0123] Figures 7A to 7G shows a manufacturing process of a high-voltage terminal structure having a junction terminal extension structure according to an embodiment of the present disclosure, and this junction terminal extension structure has a depletable guard ring and field plates.

[0124] This manufacturing process uses a total of six masks. Mask 1 is used to define the channel stopper region. Mask 2 is used to perform the implantation process of the junction terminal extension region. Mask 3 is used to form the anode of the active region. Mask 4 is used to form the contacts. Mask 5 is used to form the metal layer. Mask 6 is used to form the passivation / polyimide layer.

[0125] Refer to Figure 7A , first, an N-type semiconductor body 610 is provided. Then, using Mask 1 to define a channel stopper window for forming the channel stopper region, and subsequently, an N-type heavily doped channel stopper region 640 is formed in the N-type semiconductor body 610 by ion implantation or diffusion. For example, but not limited thereto, dopants with a doping concentration between 1e15 Cm -2 to 1e 16 Cm -2 of phosphorus ions to form an N-type heavily doped channel stopper region 640, or form an N-type heavily doped channel stopper region 640 in the N-type semiconductor body 610 by using a POCl3 diffusion process.

[0126] Subsequently, referring to Figure 7B , use a mask 2 to define the positions of the P-type junction terminal extension region and the P-type depletable guard ring, and then perform an ion implantation step to simultaneously form a P-type junction terminal extension region 620 and a P-type depletable guard ring 670. The P-type junction terminal extension region 620 is adjacent to the active region of the power semiconductor device and is separated from the N-type heavily doped channel stopper region 640. The P-type depletable guard ring 670 is formed between the P-type junction terminal extension region 620 and the N-type heavily doped channel stopper region 640. For example, but not limited to this, boron ions with a doping concentration between 5e 12 Cm -2 to 2e 13 Cm -2 can be implanted into the N-type semiconductor body 610 to form the P-type junction terminal extension region 620 and the P-type depletable guard ring 670.

[0127] Subsequently, referring to Figure 7C , after the ion implantation step of Figure 7B , perform a high-temperature diffusion step to drive the P-type junction terminal extension region 620 and the P-type depletable guard ring 670 to diffuse to a deeper position. For example, but not limited to this, this high-temperature diffusion step can make the junction depth of the P-type junction terminal extension region 620 reach 5 um to 10 um.

[0128] Next, referring to Figure 7D , use a mask 3 to define the position of the anode region in the active region, and then perform an ion implantation step to form a P-type anode region 652 in the active region. For example, but not limited to this, boron ions with a doping concentration between 1e 14 Cm -2 to 5e 15 Cm -2 can be implanted into the P-type well 651 of the active region to form a P-type anode region 652.

[0129] Next, referring to Figure 7E, a dielectric layer 680 is deposited on the N-type semiconductor body 610. For example, but not limited thereto, the dielectric layer 680 can be an oxide layer, a phosphosilicate glass (PSG) layer, or a borophosphosilicate glass (BPSG) layer. Then, a contact window 682 is formed in the dielectric layer 680 by using a mask 4.

[0130] Next, referring to Figure 7F , a metal layer is deposited on the dielectric layer 680, and this metal layer fills the contact window 682. Subsequently, a mask 5 is used to define the anode electrode and the field plate, and then an etching step is performed to form the anode electrode 654 and the field plate 660. For example, but not limited thereto, depending on the junction depth, this metal layer can be an AlCu layer or an AlSiCu layer with or without a Ti / TiN buffer layer.

[0131] Referring to Figure 7G , after forming the anode electrode 654 and the field plate 660, a passivation layer 690 is deposited. For example, but not limited thereto, the passivation layer 690 can be a SiO2-type passivation layer or a Si3N4-type passivation layer. For example, but not limited thereto, a polyimide layer can be used to replace this passivation layer. After depositing the passivation layer 690, a mask 6 is used to define the pad area (not shown).

[0132] It should be noted that the foregoing manufacturing process uses a single mask (mask 2) to define the P-type junction terminal extension region 620 and the P-type depletable guard ring 670, and uses a single mask to define the anode electrode 654 and the field plate 660 to reduce the photolithography steps in the process.

[0133] Figures 8A to 8G shows the manufacturing process of a high-voltage terminal structure with a lateral modulation junction terminal extension structure according to an embodiment of the present disclosure.

[0134] This manufacturing process uses a total of seven masks. Mask 1 is used to define the channel isolation region. Mask 2 is used to perform the implantation process of the junction terminal extension region. Mask 3 is used to form a lightly doped region in the junction terminal extension region to form a lateral modulation junction terminal extension region. Mask 4 is used to form the anode of the active region. Mask 5 is used to form the contact. Mask 6 is used to form the metal layer. Mask 7 is used to form the passivation / polyimide layer.

[0135] Referring to Figure 8A, First, provide an N-type semiconductor body 710. Next, use a mask 1 to define a channel isolation window for forming a channel isolation region. Subsequently, through ion implantation or diffusion, form an N-type heavily doped channel isolation region 740 within the N-type semiconductor body 710. For example, but not limited to this, phosphorus ions with a doping concentration between 1e 15 Cm -2 and 1e 16 Cm -2 can be implanted into the N-type semiconductor body 710 to form the N-type heavily doped channel isolation region 740, or an N-type heavily doped channel isolation region 740 can be formed within the N-type semiconductor body 710 using a POCl3 diffusion process.

[0136] Subsequently, refer to Figure 8B , use a mask 2 to define the position of the P-type junction terminal extension region, and form the P-type junction terminal extension region through ion implantation. The P-type junction terminal extension region 720 is adjacent to the active region of the power semiconductor device and is separated from the N-type heavily doped channel isolation region 740. For example, but not limited to this, boron ions with a doping concentration between 5e 12 Cm -2 and 2e 13 Cm -2 can be implanted into the N-type semiconductor body 710 to form the P-type junction terminal extension region 720.

[0137] Next, refer to Figure 8C , use a mask 3 to define multiple lightly doped regions within the P-type junction terminal extension region 720, and then perform an ion implantation step to form P-type lightly doped regions 730a - 730f within the P-type junction terminal extension region 720. For example, but not limited to this, a dedicated mask 3 with different openings can be used to implant N-type doping into the P-type junction terminal extension region 720 to form these P-type lightly doped regions 730a - 730f in an anti-doping manner.

[0138] These P-type lightly doped regions 730a - 730f can be used to modulate the doping concentration of the P-type junction terminal extension region 720, causing it to vary from the active region towards the edge. For example, but not limited to this, the lateral width of these P-type lightly doped regions 730a - 730f increases along the direction from the active region towards the N-type heavily doped channel isolation region 740, and the distance between the P-type lightly doped region 730a adjacent to the active region and the active region is greater than the distance between adjacent lightly doped regions 730b - 730f.

[0139] After the ion implantation step, a high-temperature diffusion step may be performed to drive the P-type junction terminal extension region 720 and make it diffuse to a deeper position. For example, but not limited to, this high-temperature diffusion step can make the junction depth of the P-type junction terminal extension region 720 reach 5 μm to 10 μm.

[0140] Next, refer to Figure 8D , use mask 4 to define the position of the anode region in the active area. Subsequently, an ion implantation step is performed to form a P-type anode region 752. For example, but not limited to, boron ions with a doping concentration between 1e 14 Cm -2 to 5e 15 Cm -2 can be implanted to form a P-type anode region 752.

[0141] Subsequently, refer to Figure 8E , deposit a dielectric layer 780 on the N-type semiconductor body 710. For example, but not limited to, this dielectric layer 780 can be an oxide layer, a phosphosilicate glass layer, or a borophosphosilicate glass layer. Then, use mask 5 to form a contact window 782 in the dielectric layer 780.

[0142] Next, refer to Figure 8F , deposit a metal layer on the dielectric layer 780, and this metal layer fills the contact window 782. Subsequently, use mask 6 to define the anode electrode and the field plate, and then perform an etching step to form the anode electrode 754 and the field plate 760. For example, but not limited to, depending on the junction depth, this metal layer can be an AlCu layer or an AlSiCu layer with or without a Ti / TiN buffer layer.

[0143] Refer to Figure 8G , after forming the anode electrode 754 and the field plate 760, deposit a passivation layer 790. For example, but not limited to, this passivation layer 790 can be a SiO2-type passivation layer or a Si3N4-type passivation layer. For example, but not limited to, a polyimide layer can be used to replace the passivation layer 790. After depositing the passivation layer 790, use mask 7 to define the pad area (not shown).

[0144] It should be noted that the foregoing manufacturing process uses a single mask (mask 2) to define the P-type junction terminal extension region 720, making the lower part of the P-type junction terminal extension region 720 have consistency, and uses a modulated mask (mask 3) with different implantation window sizes to counter-dope the P-type junction terminal extension region 720. These implantation windows of different sizes can compensate for the doping concentration of the upper part of the P-type junction terminal extension region 720. The range of the opening area of the modulated mask (mask 3) can increase along the direction towards the edge of the device to form more P-type lightly doped regions 730a - 730f to disperse the depletion region.

[0145] Regarding Figure 1B For the conventional lateral modulation junction termination extension structure shown, in order to form a multi-region P-type junction termination extension region, more precise lithography capabilities are required, which are lacking in many power device manufacturers. Therefore, larger space or additional space is often needed to form the junction termination extension structure with the multi-region P-type junction termination extension region. In contrast, in this embodiment, a single P-type junction termination extension mask is used to maintain the uniformity of the deeper part of the P-type junction termination extension region, and a modulation mask with implantation windows of different sizes is used to counter-dope the P-type junction termination extension region to compensate for the doping concentration of the upper part of the P-type junction termination extension region, so as to disperse the depletion region near the surface region, thereby improving the tolerance of the junction termination extension structure to surface charges. The high-voltage terminal structure provided according to the embodiments of the present invention can improve its tolerance to surface charge variations with a minimal increase in the area required to set up the terminal structure.

[0146] Although the above embodiments of the present invention mainly relate to silicon semiconductor devices, the present disclosure is not limited thereto. For example, the high-voltage terminal structure provided according to other embodiments of the present invention can also form a semiconductor body composed of silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) without departing from the scope of the present invention.

[0147] Although the above embodiments of the present invention mainly relate to power diodes, the present disclosure is not limited thereto. For example, the high-voltage terminal structure provided according to other embodiments of the present invention can also be applied to semiconductor devices with metal-oxide semiconductor field effect transistors (MOSFETs), semiconductor devices with insulated gate bipolar transistors (IGBTs), and semiconductor devices with thyristor-type structures without departing from the scope of the present invention.

[0148] The above are only preferred embodiments of the present disclosure and do not impose any limitations on the present disclosure. Any person skilled in the art, within the scope of the technical means of the present disclosure, makes any form of equivalent replacement or modification and other changes to the technical means and technical content disclosed in the present disclosure, which are all within the content of the technical means of the present disclosure and still fall within the protection scope of the present disclosure.

Claims

1. A high-voltage terminal structure for a power semiconductor device, comprising: A semiconductor body of a first conductivity type; A junction terminal extension region of a second conductivity type is formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device; A heavily doped channel isolation region of the first conductivity type, formed in the semiconductor body, wherein the heavily doped channel isolation region and the junction terminal extension region are separated from each other; A plurality of depletable guard rings of the second conductivity type, formed in the semiconductor body, wherein the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region; A plurality of lightly doped regions of the second conductivity type, formed in an upper portion of the junction terminal extension region and at least one of the depletable guard rings, wherein there is a first distance between the plurality of lightly doped regions and the bottom surface of the junction terminal extension region, and there is a second distance between the lightly doped regions in the depletable guard ring and the bottom of the depletable guard ring; and A plurality of field plates, formed on the junction terminal extension region.

2. The high-voltage terminal structure for a power semiconductor device according to claim 1, wherein, The first conductivity type is N-type, and the second conductivity type is P-type.

3. The high-voltage terminal structure for a power semiconductor device according to claim 1, wherein, The plurality of field plates are made of a metal material.

4. The high-voltage terminal structure for a power semiconductor device according to claim 1, wherein, The plurality of field plates are made of P-type polysilicon.

5. The high-voltage terminal structure for a power semiconductor device according to claim 1, wherein, The plurality of field plates are made of N-type polysilicon.

6. A high-voltage terminal structure for a power semiconductor device, comprising: A semiconductor body of a first conductivity type; A junction terminal extension region of a second conductivity type is formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device; A heavily doped channel isolation region of the first conductivity type, formed in the semiconductor body, wherein the heavily doped channel isolation region and the junction terminal extension region are separated from each other; A plurality of depletable guard rings of the second conductivity type, formed in the semiconductor body, wherein the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region; and At least one lightly doped region of the second conductivity type, formed in at least one of the depletable guard rings, and there is a distance between the at least one lightly doped region and the bottom of the depletable guard ring.

7. The high-voltage terminal structure for a power semiconductor device according to claim 6, wherein, The first conductivity type is N-type, and the second conductivity type is P-type.

8. A high-voltage terminal structure for a power semiconductor device, comprising: A semiconductor body of a first conductivity type; A junction terminal extension region of a second conductivity type is formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device; A heavily doped channel isolation region of the first conductivity type, formed in the semiconductor body, wherein the heavily doped channel isolation region and the junction terminal extension region are separated from each other; A plurality of depletable guard rings of the second conductivity type, formed in the semiconductor body, wherein the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel isolation region; and A plurality of lightly doped regions of the second conductivity type, formed in an upper portion of the junction terminal extension region and at least one of the depletable guard rings, wherein there is a first distance between the plurality of lightly doped regions and the bottom surface of the junction terminal extension region, and there is a second distance between the lightly doped regions in the depletable guard ring and the bottom of the depletable guard ring.

9. The high-voltage terminal structure for a power semiconductor device according to claim 8, wherein, The first conductivity type is N-type, and the second conductivity type is P-type.

10. The high-voltage terminal structure for a power semiconductor device according to claim 8, wherein, The lateral widths of the plurality of lightly doped regions increase along the direction towards the heavily doped channel stopper region.

11. The high-voltage terminal structure for a power semiconductor device according to claim 8, wherein, A spacing between the lightly doped region adjacent to the active region and the active region is greater than a spacing between a plurality of adjacent lightly doped regions.

12. The high-voltage terminal structure for a power semiconductor device according to claim 8, wherein, A gap between the plurality of depletable guard rings increases along the direction towards the heavily doped channel stopper region.

13. A method for manufacturing a high-voltage terminal structure for a power semiconductor device, comprising: Forming a heavily doped channel stopper region of the first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; By means of ion implantation of a second conductivity type, a junction terminal extension region of the second conductivity type and a plurality of depletable guard rings of the second conductivity type are formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel stopper region, and the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel stopper region; Forming a plurality of lightly doped regions of the second conductivity type in an upper portion of the junction terminal extension region and the plurality of depletable guard rings by ion implantation of the second conductivity type, wherein there is a first distance between the plurality of lightly doped regions and the bottom surface of the junction terminal extension region, and there is a second distance between the lightly doped regions of the depletable guard rings and the bottom of the depletable guard rings; and Forming a plurality of field plates on the junction terminal extension region.

14. A method for manufacturing a high-voltage terminal structure for a power semiconductor device, comprising: Forming a heavily doped channel stopper region of the first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; By means of ion implantation of a second conductivity type, a junction terminal extension region of the second conductivity type is formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel stopper region; Forming a plurality of depletable guard rings of the second conductivity type in the semiconductor body by ion implantation of the second conductivity type, wherein the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel stopper region; and Forming a plurality of lightly doped regions of the second conductivity type in the plurality of depletable guard rings by ion implantation of the second conductivity type, wherein there is a distance between the lightly doped regions of the depletable guard rings and the bottom of the depletable guard rings.

15. The method of manufacturing a high-voltage terminal structure for a power semiconductor device according to claim 14, wherein, The junction terminal extension region and the plurality of depletable guard rings are formed in the semiconductor body simultaneously.

16. A method for manufacturing a high-voltage terminal structure for a power semiconductor device, comprising: Forming a heavily doped channel stopper region of the first conductivity type in a semiconductor body of the first conductivity type by ion implantation of the first conductivity type; By means of ion implantation of a second conductivity type, a junction terminal extension region of the second conductivity type and a plurality of depletable guard rings of the second conductivity type are formed in the semiconductor body, wherein, The junction terminal extension region is adjacent to an active region of the power semiconductor device and is separated from the heavily doped channel stopper region, and the plurality of depletable guard rings are formed between the junction terminal extension region and the heavily doped channel stopper region; and By means of ion implantation of the second conductivity type, a plurality of lightly doped regions of the second conductivity type are formed in an upper portion of the junction terminal extension region and the plurality of depletable guard rings, wherein there is a first distance between the plurality of lightly doped regions and the bottom surface of the junction terminal extension region, and there is a second distance between the lightly doped regions of the depletable guard rings and the bottom of the depletable guard rings.

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