Semiconductor element and method for manufacturing the same

Abstract

The present invention discloses a semiconductor element and a method for manufacturing the same, wherein the method for manufacturing the semiconductor element comprises: providing a substrate comprising a logic element region and a memory element region. Then, forming a memory stack structure on the memory element region, and forming a protective layer to cover the top surface and sidewalls of the memory stack structure. Then, forming a first interlayer dielectric layer on the protective layer, and performing a post-grinding etching process to remove a portion of the first interlayer dielectric layer and a portion of the protective layer on the top surface of the memory stack structure. Then, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the protective layer, and then forming an upper contact structure through the second interlayer dielectric layer and the protective layer on the top surface of the memory stack structure and contacting the memory stack structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a magnetoresistive random access memory (MRAM) element and a manufacturing method thereof. Background Art

[0002] Magnetoresistive random access memory (MRAM) is a new type of memory that has garnered significant attention in recent years. It combines the advantages of various existing memory types, such as access speed comparable to static random access memory (SRAM), the non-volatility and low power consumption of flash memory, and the high density and durability of dynamic random access memory (DRAM). Furthermore, it can be integrated with current semiconductor back-end-of-line (BEOL) manufacturing processes, making it potentially a key memory device used in semiconductor chips.

[0003] Magnetoresistive random access memory (MRAM) consists of a memory stack structure arranged between upper and lower interconnect structures. The memory stack primarily comprises a magnetic tunneling junction (MTJ). Unlike traditional memory, which stores data by storing charge, MRAM operates by applying an external magnetic field to the MTJ to control its magnetization, thereby generating different tunneling magnetoresistances (TMR) to store digital data.

[0004] Currently, the fabrication of magnetoresistive random access memories (MRAMs) still faces numerous challenges. For example, the interlayer dielectric layer covering the top surface of the memory stack, or the passivation layer used to passivate or protect the memory stack, can create an etch barrier during the etching process for the top contact structure used to electrically connect the memory stack. This can lead to shrinkage or incomplete etching of the bottom of the top contact structure, compromising the contact quality between the memory stack and the top contact plug, and causing abnormalities in writing or reading data in the MRAM. Summary of the Invention

[0005] To overcome the aforementioned problems, the present invention provides a semiconductor device and a method for manufacturing the same, which can be used to manufacture, for example, a magnetoresistive random access memory structure. By performing a post-grinding etch-back process after planarizing the interlayer dielectric layer to remove the interlayer dielectric layer and a portion of the protective layer on the top surface of the memory stack structure, the problem of bottom shrinkage or non-etching through of the upper contact structure can be reduced.

[0006] One embodiment of the present invention provides a method for manufacturing a semiconductor element, comprising the following steps. First, a substrate is provided, comprising a logic element region and a memory element region. A memory stack structure is then formed on the memory element region, and a protective layer is formed to cover a top surface and a side wall of the memory stack structure. Then, a first interlayer dielectric layer is formed on the protective layer, and a post-grinding etching process is performed to remove a portion of the first interlayer dielectric layer and a portion of the protective layer on the top surface of the memory stack structure. Next, a second interlayer dielectric layer is formed on the first interlayer dielectric layer and directly contacts the protective layer, and then an upper contact structure is formed, passing through the second interlayer dielectric layer and the protective layer on the top surface of the memory stack structure and contacting the memory stack structure.

[0007] Another embodiment of the present invention provides a semiconductor device comprising a substrate including a logic element region and a memory element region. A first interlayer dielectric layer is located on the substrate. A second interlayer dielectric layer is located on the first interlayer dielectric layer. A memory stack structure is located in the first interlayer dielectric layer of the memory element region. A protective layer covers a top surface and a sidewall of the memory stack structure, wherein the second interlayer dielectric layer directly contacts the protective layer. An upper contact structure passes through the second interlayer dielectric layer and the protective layer on the top surface of the memory stack structure and contacts the memory stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 10 Schematic diagram of the steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0009] Description of main component symbols

[0010] 10 base

[0011] 14 Logic element area

[0012] 16 Memory element area

[0013] 100 semiconductor components

[0014] 101 semiconductor substrate

[0015] 102 interlayer dielectric layer

[0016] 104 Lower layer internal connection structure

[0017] 106 Lower layer internal connection structure

[0018] 200 first interlayer dielectric layer

[0019] 202 Etch stop layer

[0020] 204 dielectric material layer

[0021] 206 dielectric material layer

[0022] 208 mask layer

[0023] 210 mask layer

[0024] 212 steps

[0025] 300 memory stack layers

[0026] 302 bottom electrode layer

[0027] 304 Magnetic Tunnel Junction Stack

[0028] 306 fixed layer

[0029] 308 fixed layer

[0030] 310 Tunneling Layer

[0031] 312 free layers

[0032] 314 cap layer

[0033] 316 top electrode layer

[0034] 402 Protection Layer

[0035] 500 conductive layer

[0036] 503 Grooves

[0037] 510 First internal connection structure

[0038] 600 Second interlayer dielectric layer

[0039] 602 Etch Stop Layer

[0040] 606 dielectric material layer

[0041] 608 conductive layer

[0042] 610 Second internal connection structure

[0043] 612 upper contact structure

[0044] 204a Concave surface

[0045] 330a top surface

[0046] 330b sidewall

[0047] CMP1 polishing process

[0048] CMP2 polishing process

[0049] EB1 back-etching process before grinding

[0050] EB2 post-grinding etch-back process

[0051] H1 Height

[0052] H2 Height

[0053] H3 step height

[0054] H4 step height

[0055] T1 thickness

[0056] T2 thickness

[0057] T3 thickness

[0058] T4 thickness

[0059] T5 thickness

[0060] T6 thickness

[0061] T7 Thickness DETAILED DESCRIPTION

[0062] To make the above-mentioned objectives, features, and advantages of the present invention more clearly understood, preferred embodiments are described below in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams and are not drawn to scale. Identical or similar features are generally depicted with the same reference numerals. The embodiments and drawings described herein are for reference and illustration only and are not intended to limit the present invention. The scope of the present invention is defined by the claims. Any equivalent to the claims of the present invention shall also be within the scope of the present invention.

[0063] The following description uses a magnetoresistive random access memory (MRAM) as an example semiconductor device. However, it should be understood that the present invention is also applicable to other semiconductor devices, including components integrated with back-end manufacturing processes, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), or resistive random access memory (RRAM), but is not limited thereto.

[0064] Please refer to Figures 1 to 10 , is a schematic diagram of the steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Figure 1As shown, a substrate 10 is first provided, and the substrate 10 includes a logic device region 14 and a memory device region 16. Then, an etch stop layer 202 and a dielectric material layer 204 are sequentially formed on the substrate 10, and then a memory stack layer 300 is formed on the dielectric material layer 204.

[0065] The substrate 10 may include a multi-layer structure, for example, a semiconductor substrate 101 and an interlayer dielectric layer 102 disposed on the semiconductor substrate 101. The semiconductor substrate 101 may be, for example, a silicon substrate, a silicon-on-insulator substrate, or a Group III-V semiconductor substrate, but is not limited thereto. The semiconductor substrate 101 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an isolation structure and an interlayer dielectric (ILD), which are not shown in the figure for simplicity.

[0066] The interlayer dielectric layer 102 may be made of silicon oxide (SiO2) or a low-k dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on silica glass (SGO), porous low-k dielectric material, or organic polymer dielectric material.

[0067] Interconnect structures may be formed in the interlayer dielectric layer 102, such as a lower interconnect structure 104 formed in the logic device region 14 and a lower interconnect structure 106 formed in the memory device region 16. The lower interconnect structures 104 and 106 may comprise a metal material, such as, but not limited to, tungsten (W), copper (Cu), or aluminum (Al). In some embodiments, the lower interconnect structures 104 and 106 may comprise copper.

[0068] Etch stop layer 202 is disposed between interlayer dielectric layer 102 and dielectric material layer 204. The material may include, but is not limited to, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or nitrogen-doped silicon carbide (NDC). Dielectric material layer 204 may be made of, for example, silicon oxide (SiO2) or a low-k dielectric material.

[0069] A plurality of contact plugs 208 may be formed in the memory device region 16 and extend through the dielectric material layer 204 and the etch stop layer 202 to contact and electrically connect to the underlying interconnect structure 106 of the memory device region 16. The contact plugs 208 may be made of a metal material such as, but not limited to, tungsten, copper, or aluminum. In some embodiments, the contact plugs 208 include tungsten.

[0070] The memory stack 300 may include, from bottom to top, a bottom electrode layer 302, a magnetic tunneling junction (MTJ) stack 304, a cap layer 314, and a top electrode layer 316. The bottom electrode layer 302 and the top electrode layer 316 each comprise a conductive material, such as, but not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. The bottom electrode layer 302 and the top electrode layer 316 may comprise the same or different conductive materials. The MTJ stack 304 is a multi-layer structure, and from bottom to top, may include a pinned layer 306, a pinned layer 308, a tunneling layer 310, and a free layer 312. Pinned layer 306 is used to pin or limit the magnetization direction of adjacent layers and primarily comprises an antiferromagnetic (AFM) material, such as, but not limited to, platinum manganese (PtMn), iridium manganese (IrMn), or platinum iridium (PtIr). Pinned layer 308 and free layer 312 primarily comprise ferromagnetic materials, such as, but not limited to, iron (Fe), cobalt (Co), nickel (Ni), iron-nickel (FeNi), iron-cobalt (FeCo), cobalt-nickel (CoNi), iron-boron (FeB), iron-platinum (FePt), iron-palladium (FePd), or cobalt-iron-boron (CoFeB). The magnetization direction of pinned layer 308 is fixed by pinned layer 306, while the magnetization direction of free layer 312 can be changed by an external magnetic field. The tunneling layer 310 is sandwiched between the pinned layer 308 and the free layer 312, and mainly comprises insulating materials such as magnesium oxide (MgO), aluminum oxide (Al2O3), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (Ta2O5), molybdenum oxide (MoO2), titanium oxide (TiO2), tungsten oxide (WO2), etc., but is not limited thereto. The pinned layer 306, pinned layer 308, tunneling layer 310 and free layer 312 can each be a single layer or a multi-layer structure, with the thickness of each layer being approximately several angstroms. The capping layer 314 may include a metal or metal oxide, such as aluminum (Al), magnesium (Mg), tantalum (Ta), ruthenium (Ru), tungsten oxide (WO2), nickel oxide (NiO), magnesium oxide (MgO), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), molybdenum oxide (MoO2), titanium oxide (TiO2), gadolinium oxide (GdO), manganese oxide (MnO), or a combination thereof, but is not limited thereto.

[0071] Please refer to Figure 2 A patterning process is then performed to pattern the memory stack layer 300 in the memory device region 16 into a plurality of memory stack structures 330 , and completely remove the memory stack layer 300 in the logic device region 14 .

[0072] According to one embodiment of the present invention, a method for patterning the memory stack layer 300, for example, first forms a patterned hard mask layer (not shown), such as a patterned silicon oxide layer or a patterned silicon nitride layer, on the top electrode layer 316, and then uses the patterned hard mask layer as an etching mask to perform a first stage etching process on the top electrode layer 316, such as a reactive ion etching (RIE) process, to transfer the pattern of the patterned hard mask layer to the top electrode layer 316, thereby forming a patterned top electrode layer 316. Next, the cap layer 314, the magnetic tunneling junction layer 304, and the bottom electrode layer 302 are subjected to a second stage of etching process, such as an ion beam etching (IBE) process, using the patterned top electrode layer 316 as an etching mask to transfer the pattern of the patterned top electrode layer 316 downward to the cap layer 314, the magnetic tunneling junction layer 304, and the bottom electrode layer 302, thereby forming a patterned cap layer 314, the magnetic tunneling junction layer 304, and the bottom electrode layer 302, and obtaining a structure as shown in FIG. Figure 2 The memory stack structure 330 is shown. According to one embodiment of the present invention, in order to ensure that the redundant portion of the memory stack layer 300 can be completely removed, the second stage ion beam etching process is preferably performed by over-etching to remove a portion of the dielectric material layer 204, thereby forming a recessed surface 204a in the dielectric material layer 204.

[0073] Please continue to refer to Figure 2 After forming the memory stack structure 330, a protective layer 402 is then formed to conformally cover the memory stack structure 330 and the recessed surface 204a of the dielectric material layer 204. According to one embodiment of the present invention, the protective layer 402 in the logic device region 14 can be selectively removed using a photolithography and etching process, for example, to expose the surface of the dielectric material layer 204 in the logic device region 14.

[0074] The protective layer 402 can be formed by a chemical vapor deposition (CVD) process. The material may include, but is not limited to, insulating materials such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN). According to one embodiment of the present invention, the protective layer 402 comprises silicon nitride. According to one embodiment of the present invention, the protective layer 402 is preferably formed in situ after the ion beam etching process in the aforementioned second stage of the etching process to prevent the magnetic tunneling junction layer 304 exposed from the sidewall 330b of the memory stack structure 330 after the ion beam etching process from reacting with ambient gases (e.g., oxidizing) or adsorbing contaminants.

[0075] like Figure 2 As shown, the portion of the protective layer 402 covering the recessed surface 204a of the dielectric material layer 204 has a thickness T1, the portion covering the top surface 330a of the memory stack structure 330 has a thickness T2, and the portion covering the sidewall 330b of the memory stack structure 330 has a thickness T3. According to one embodiment of the present invention, the thickness T1 and the thickness T2 are substantially equal, while the thickness T3 is less than the thickness T1 and the thickness T2, for example, approximately 60% to 80% of the thickness T1 or the thickness T2. For example, the thickness T1 and the thickness T2 may be approximately between 300 angstroms. to 360 angstroms The thickness T3 is about 180 angstroms. to 220 angstroms between.

[0076] Please refer to Figure 3 . Next, a dielectric material layer 206 is formed throughout the entire area to cover the logic element region 14 and the memory element region 16 and fill the gap between the memory stack structure 330. The memory stack structure 330 enables the surface of the dielectric material layer 206 in the memory element region 16 to be higher than the surface of the dielectric material layer 206 in the logic element region 14. The dielectric material layer 206 may include silicon oxide (SiO2) or a low-k dielectric material. The low-k dielectric material is, for example, fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric material, or organic polymer dielectric material, but is not limited thereto.

[0077] Please refer to Figure 4. Next, a mask layer 208 (e.g., a photoresist layer) is formed on the dielectric material layer 206 and an opening is formed in the mask layer 208 to expose a portion of the dielectric material layer 206 of the memory element region 16. Then, a pre-grinding etch-back process EB1 (e.g., a dry etching process) is performed using the mask layer 208 as a mask to remove a portion of the dielectric material layer 206 from the opening of the mask layer 208 until the surface of the dielectric material layer 206 of the memory element region 16 is higher than the surface of the dielectric material layer 206 of the logic element region 14 by a height H1. According to one embodiment of the present invention, the height H1 is approximately between 200 angstroms. to 300 angstroms In between, but not limited to.

[0078] Please refer to Figure 5 After removing the mask layer 208, the dielectric material layer 206 is subjected to a grinding process CMP1. According to one embodiment of the present invention, the loading effect of the grinding process CMP1 causes the surface of the dielectric material layer 206 after the grinding process CMP1 to still be higher than the surface of the dielectric material layer 206 of the logic element region 14 by a height H2. The height H2 may be substantially equal to or slightly less than the height H1. For example, the height H2 may be between 200 angstroms and 100 angstroms. to 300 angstroms Between, or between 160 angstroms to 200 angstroms After the polishing process CMP1, the etch stop layer 202, the dielectric material layer 204, and the dielectric material layer 206 together form the first interlayer dielectric layer 200. At this point in the manufacturing process, the protection layer 402 on the memory stack structure 330 is still covered by the dielectric material layer 206 of the first interlayer dielectric layer 200 and is not exposed.

[0079] Please refer to Figure 6 . Next, a mask layer 210 (e.g., a photoresist layer) is formed on the dielectric material layer 206, and an opening is formed in the mask layer 210 to expose a portion of the dielectric material layer 206 in the memory element region 16. A post-grinding etch-back process EB2 (e.g., a dry etching process) is then performed using the mask layer 210 as an etching mask to etch away a portion of the dielectric material layer 206 above the memory stack structure 300 until the protective layer 402 covering the top surface 303 is exposed, and the etching is continued to remove a portion of the protective layer 402 without exposing any portion of the memory stack structure 300. After the post-grinding etch-back process EB2, the protective layer 402 remaining on the top surface 303 has a thickness T4. According to one embodiment of the present invention, the thickness T4 is preferably approximately the thickness of the etching stop layer 602 (refer to the etching stop layer 602 of the second interlayer dielectric layer 600 formed subsequently) Figure 10 ) is between 30% and 50% of the thickness. For example, the thickness T4 may be approximately between to In between, but not limited to.

[0080] Please continue to refer to Figure 6 After the post-grinding etch-back process EB2, the surface of the dielectric material layer 206 of the memory element region 16 is lower than the surface of the dielectric material layer 206 of the logic element region 14, and a step portion 212 is formed near the junction of the logic element region 14 and the memory element region 16, with a step height H3. According to some embodiments of the present invention, the step height H3 can be between to In between, but not limited to.

[0081] Please refer to Figures 7 and 8 . After removing the mask layer 210, a dual damascene process may be performed to form a first interconnect structure 510 in the first interlayer dielectric layer 200. In detail, a trench 503 may be formed before the logic element region 14, penetrating the dielectric material layer 206, the dielectric material layer 204, and the etch stop layer 202 of the first interlayer dielectric layer 200 and exposing the surface of the underlying interconnect structure 104. Then, a conductive layer 500 may be formed on the first interlayer dielectric layer 200 and fill the trench 503. The conductive layer 500 may include a conductive material, such as a conductive metal such as tungsten, copper, or aluminum, but is not limited thereto. According to one embodiment of the present invention, the conductive layer 500 includes copper. The conductive layer 500 directly contacts the protective layer 402 on the top surface 330a of the memory stack structure 330. According to one embodiment of the present invention, the conductive layer 500 may include a barrier layer (not shown) located at the interface between the dielectric material layer 206 and the protective layer 402.

[0082] Please refer to Figure 9 Next, a polishing process (CMP2) is performed to remove the conductive layer 500 outside the trench 503 until the surface of the dielectric material layer 206 is exposed. The conductive layer 500 remaining in the trench 503 forms a first interconnect structure 510. The bottom of the first interconnect structure 510 contacts and is electrically connected to the underlying interconnect structure 104.

[0083] It is worth noting that since the polishing slurry used in the polishing process CMP2 is mainly used to remove the conductive layer 500, it has a high selectivity for the dielectric material layer 206 and the protective layer 402, and can be well controlled to stop on the dielectric material layer 206 and the protective layer 402. Therefore, the polishing process CMP2 does not significantly cause a loss in the thickness of the dielectric material layer 206 and the insulating layer 402 or affect the uniformity. In other words, after the polishing process CMP2, the step portion 212 is still present near the junction of the logic element region 14 and the memory element region 16, and has a step height H4. The step height H4 can be substantially equal to or slightly less than the step height H3, for example, approximately between to The protective layer 402 covering the top surface 330a of the memory stack structure 330 has a thickness T5, which may be substantially equal to or slightly less than the thickness T4, for example, approximately between to between.

[0084] Please refer to Figure 10 Next, a second interlayer dielectric layer 600 is formed on the first interlayer dielectric layer 200. The second interlayer dielectric layer 600 may include an etch stop layer 602 and a dielectric material layer 606 located on the etch stop layer 602. A second interconnect structure 610 and an upper contact structure 612 are then formed in the second interlayer dielectric layer 600 in the logic device region 14 and the memory device region 16, respectively.

[0085] like Figure 10 As shown, the etch stop layer 602 directly contacts the protective layer 402, the dielectric material layer 206 and the dielectric material layer 206, and conformally covers the step portion 212 near the junction of the logic element region 14 and the memory element region 16. The etch stop layer 602 material may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON) or nitrogen-doped silicon carbide (NDC), but is not limited thereto. According to one embodiment of the present invention, the etch stop layer 602 and the etch stop layer 202 may include the same material, such as nitrogen-doped silicon carbide (NDC). According to one embodiment of the present invention, the etch stop layer 602 is approximately between to between.

[0086] The dielectric material layer 606 may include silicon oxide (SiO2) or a low-k dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on silica glass (SGO), porous low-k dielectric material, or organic polymer dielectric material. According to one embodiment of the present invention, the dielectric material layer 606 and the dielectric material layer 206 may include the same material, for example, both including at least one of the low-k dielectric materials exemplified above.

[0087] The upper contact structure 612 passes through the second interlayer dielectric layer 600 of the memory device region 16 and the protective layer 402 on the top surface 330a of the memory stack structure 330 and directly contacts the top electrode layer 316 of the memory stack structure 330. The second interconnect structure 610 passes through the second interlayer dielectric layer 600 of the logic device region 14 and directly contacts the first interconnect structure 510. In some embodiments, the upper contact structure 612 and the second interconnect structure 610 can be formed simultaneously using the same fabrication process, for example, by forming them in the second interlayer dielectric layer 600 using a dual damascene process. The upper contact structure 612 and the second interconnect structure 610 can include a conductive layer 608. The conductive layer 608 primarily includes a conductive material, such as, but not limited to, a conductive metal such as tungsten, copper, or aluminum. According to one embodiment of the present invention, the conductive layer 608 includes copper. According to one embodiment of the present invention, the conductive layer 608 may include a barrier layer (not shown) located at the interface between the dielectric material layer 606 , the etch stop layer 602 , the protection layer 402 and the top electrode layer 316 .

[0088] Please continue to refer to Figure 10 According to one embodiment of the present invention, a semiconductor device 100 includes a substrate 10, which includes a logic device region 14 and a memory device region 16, and a first interlayer dielectric layer 200 located on the substrate 10. The portion of the first interlayer dielectric layer 200 located in the memory device region 16 has a thickness T6, which is smaller than the thickness T7 of the portion located in the logic device region 14, and a step portion 212 is formed near the junction of the logic device region 14 and the memory device region 16. In some embodiments, the difference between the thickness T6 and the thickness T7 is approximately between to The step height H4 of the step portion 212 is approximately between to A second interlayer dielectric layer 600 is located on the first interlayer dielectric layer 200 and covers the stepped portion 212. At least one memory stack structure 330 is located in the first interlayer dielectric layer 200 of the memory element region 16. A protective layer 402 covers the top surface 330a and sidewalls 330b of the memory stack structure 330, wherein the second interlayer dielectric layer 600 directly contacts the protective layer 402, so that a portion of the protective layer 402 is sandwiched between the top surface 330a of the memory stack structure 330 and the second interlayer dielectric layer 600. The portion of the protective layer 402 located on the top surface 330a of the memory stack structure 330 has a thickness T5, which is less than the thickness T3 of the portion located on the sidewall 330b. In some embodiments, the thickness T5 is, for example, between to The thickness T3 is, for example, between 180 angstroms. to 220 angstroms An upper contact structure 612 passes through the second interlayer dielectric layer 600 and the protection layer 402 on the top surface 330 a of the memory stack structure 330 and contacts the memory stack structure 330 .

[0089] In summary, the present invention performs a post-grinding etch-back process after planarizing the interlayer dielectric layer to remove the interlayer dielectric layer and part of the protective layer on the top surface of the memory stack structure, so that the thickness of the material layer to be etched through at the bottom of the upper contact structure is closer to the thickness of the material layer to be etched through at the bottom of the second internal connection structure. By controlling the post-grinding etch-back process, a protective layer with a more uniform thickness can be obtained on the top surface of the memory stack structure, thereby reducing the difficulty in etching control caused by the thickness variation of the interlayer dielectric layer after the grinding process. Therefore, when the upper contact structure and the second internal connection structure are manufactured at the same time, the problem of shrinkage or non-etching at the bottom of the upper contact structure can be reduced, thereby improving the product yield.

[0090] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a substrate including a logic element region and a memory element region; forming a memory stack structure on the memory element region; forming a protective layer to cover the top surface and sidewalls of the memory stack structure; forming a first interlayer dielectric layer on the protective layer; Performing a post-grinding etch-back process to remove a portion of the first interlayer dielectric layer and a portion of the protective layer on the top surface of the memory stack structure; forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the protective layer; as well as forming an upper contact structure, passing through the second interlayer dielectric layer and the protective layer on the top surface of the memory stack structure and contacting the memory stack structure; The steps of the post-grinding etching process include: forming a mask layer on the substrate, wherein the mask exposes the first interlayer dielectric layer in the memory element region; Etching the exposed first interlayer dielectric layer using the mask layer as an etching mask; as well as The mask layer is removed.

2. The manufacturing method according to claim 1 , wherein the step of forming the first interlayer dielectric layer comprises: forming a dielectric material layer on the substrate; Performing a pre-grinding etch-back process to remove a portion of the first interlayer dielectric layer in the memory device area; as well as After the pre-grinding etch-back process, a grinding process is performed to planarize the dielectric material layer.

3. The manufacturing method according to claim 2, wherein after the pre-grinding etch-back manufacturing process, the surface of the dielectric material layer in the memory device area is higher than the surface of the dielectric material layer in the logic device area. to 4. The manufacturing method according to claim 2, wherein after the grinding process, the surface of the dielectric material layer in the memory element region is higher than the surface of the dielectric material layer in the logic element region. to The manufacturing method according to claim 1 , wherein the second interlayer dielectric layer directly contacts the protection layer.

6. The manufacturing method according to claim 1 , wherein after the post-grinding etch-back process, the thickness of the protective layer on the top surface of the memory stack structure is between to The thickness of the protective layer on the sidewall of the memory stack structure is between to between. The manufacturing method according to claim 1 , further comprising removing the protection layer from the logic element region.

8. The method of claim 1, further comprising: forming a trench in the first interlayer dielectric layer in the logic element region; forming a conductive layer on the first interlayer dielectric layer and filling the trench, wherein the conductive layer directly contacts the protective layer on the top surface of the memory stack structure; as well as A grinding process is performed to remove the conductive layer outside the trench, and a first interconnect structure is formed in the trench.

9. The method of claim 8, further comprising: A second interconnect structure is formed, passing through the second interlayer dielectric layer and contacting the first interconnect structure.

10. A semiconductor device manufactured by the manufacturing method according to claim 1, characterized in that: include A substrate including a logic element region and a memory element region; a first interlayer dielectric layer located on the substrate; a second interlayer dielectric layer located on the first interlayer dielectric layer; A memory stack structure is located in the first interlayer dielectric layer of the memory element region; a protective layer covering a top surface and sidewalls of the memory stack structure, wherein the second interlayer dielectric layer directly contacts the protective layer; as well as An upper contact structure passes through the second interlayer dielectric layer and the protection layer on the top surface of the memory stack structure and contacts the memory stack structure. 11 . The semiconductor device as claimed in claim 10 , wherein a thickness of the first interlayer dielectric layer in the memory device region is smaller than a thickness of the first interlayer dielectric layer in the logic device region.

12. The semiconductor device according to claim 11, wherein the thickness of the first interlayer dielectric layer in the logic device region differs from the thickness of the first interlayer dielectric layer in the memory device region by to 13 . The semiconductor device as claimed in claim 10 , wherein the first interlayer dielectric layer adjacent to a boundary between the logic device region and the memory device region comprises a stepped portion.

14. The semiconductor device according to claim 13 , wherein the step portion has a step height between to between.

15. The semiconductor device according to claim 10 , wherein the thickness of the protection layer between the top surface of the memory stack structure and the second interlayer dielectric layer is between to between.

16. The semiconductor device according to claim 10, further comprising: A first interconnect structure is located in the first interlayer dielectric layer of the memory device region; and The second interconnect structure is located in the second interlayer dielectric layer and contacts the first interconnect structure, wherein the height of the memory stack structure is smaller than the height of the first interconnect structure.

17. The semiconductor device according to claim 10 , wherein the second interlayer dielectric layer comprises: an etch stop layer contacting the first interlayer dielectric layer and the protection layer; and The second dielectric material layer is located on the etch stop layer. 18 . The semiconductor device of claim 17 , wherein the etch stop layer comprises carbon-doped silicon nitride (NDC), the second dielectric material layer comprises a low-k dielectric layer, and the protection layer comprises silicon nitride.

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