A power reconfigurable matching circuit and power amplifier

Abstract

The application discloses a power reconfigurable matching circuit, which comprises a first microstrip line TL1, a first bias branch, a third microstrip line TL3, a second capacitor C2, a third capacitor C3, a fourth microstrip line TL4, a reconfiguration branch, a sixth capacitor C6, a seventh microstrip line TL7, a ninth microstrip line TL9, a second bias branch, a first input terminal P1, a second input terminal P8 and an output terminal P4; the first microstrip line TL1, the third microstrip line TL3, the third capacitor C3, the fourth microstrip line TL4, the reconfiguration branch, the sixth capacitor C6, the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected in series; one end of the second capacitor C2 is connected to a terminal where the third microstrip line TL3 and the third capacitor C3 are connected, and the other end is connected to a grounding point G1; and the output terminal P4 is connected to the reconfiguration branch. The working state of the reconfigurable element is changed through an external control signal, and the switching of different power modes of a power amplifier is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to power matching circuit and power amplifier, and particularly relates to a power reconfigurable matching circuit and power amplifier. BACKGROUND

[0002] Multifunctional integrated electronic system gradually becomes the mainstream of development. Multifunctional integrated electronic system can realize target search and signal transmission functions at the same time by sharing a set of hardware equipment, and has advantages such as saving platform resources compared with traditional single function system. However, when the same set of equipment needs to realize different functions, different transmission power is often required, which requires the power amplifier itself to have the characteristics of power reconfigurable operation. In the power switching mode realized by switches, the switch and the power amplifier are designed separately and then cascaded, which cannot simplify the system size, and the transmission efficiency is low. SUMMARY

[0003] The purpose of the present application is to provide a power reconfigurable matching circuit and power amplifier which can realize different output powers of the power amplifier when different modulation signals enter.

[0004] The power reconfigurable matching circuit of the present application comprises a first microstrip line TL1, a first bias branch, a third microstrip line TL3, a second capacitor C2, a third capacitor C3, a fourth microstrip line TL4, a reconfiguration branch, a sixth capacitor C6, a seventh microstrip line TL7, a ninth microstrip line TL9, a second bias branch, a first input terminal P1, a second input terminal P8 and an output terminal P4. The first microstrip line TL1, the third microstrip line TL3, the third capacitor C3, the fourth microstrip line TL4, the reconfiguration branch, the sixth capacitor C6, the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected in series. One end of the second capacitor C2 is connected to a terminal where the third microstrip line TL3 and the third capacitor C3 are connected, and the other end is connected to a grounding point G1. The output terminal P4 is connected to the reconfiguration branch.

[0005] The first bias branch is connected between the output terminal of the first microstrip line TL1 and a first bias voltage source P2, and the second bias branch is connected between the output terminal of the seventh microstrip line TL7 and a second bias voltage source P7.

[0006] The input terminal of the first microstrip line TL1 and the output terminal of the ninth microstrip line TL9 are the first input terminal P1 and the second input terminal P8 respectively.

[0007] Further, the reconstruction branch comprises a first transistor K1, a fifth microstrip line TL5, a fourth capacitor C4, a sixth microstrip line TL6, a fifth capacitor C5, a second transistor K2, and a third transistor K3; one end of the fifth microstrip line TL5 is connected to the output terminal of the fourth microstrip line TL4, and the other end is connected to the drain of the second transistor K2 in series with the sixth microstrip line TL6; the drain of the first transistor K1 is connected to the terminal where the fourth microstrip line TL4 and the fifth microstrip line TL5 are connected, the source is connected to the grounding point G1, and the gate is connected to the first control voltage source P3; one end of the fourth capacitor C4 is connected to the terminal where the fifth microstrip line TL5 and the sixth microstrip line TL6 are connected, and the other end is connected to the grounding point G1; the fifth capacitor C5 is connected between the terminal where the sixth microstrip line TL6 and the drain of the second transistor K2 are connected and the output terminal P4; the source of the second transistor K2 is connected to the input terminal of the sixth capacitor C6, and the gate is connected to the second control voltage source P5; the drain of the third transistor K3 is connected to the terminal where the drain of the second transistor K2 and the sixth capacitor C6 are connected, the source is connected to the grounding point G1, and the gate is connected to the third control voltage source P6.

[0008] Further, the first bias branch comprises a first capacitor C1 and a second microstrip line TL2; the second microstrip line TL2 is connected between the terminal where the first microstrip line TL1 and the third microstrip line TL3 are connected and the first bias voltage source P2, and the first capacitor C1 is connected between the terminal where the second microstrip line TL2 and the first bias voltage source P2 are connected and the grounding point G1.

[0009] Further, the second bias branch comprises a seventh capacitor C7 and an eighth microstrip line TL8; the eighth microstrip line TL8 is connected between the terminal where the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected and the second bias voltage source P7, and the seventh capacitor C7 is connected between the terminal where the eighth microstrip line TL8 and the second bias voltage source P7 are connected and the grounding point G1.

[0010] The power amplifier of the application comprises an output matching network, an input matching network, a mode one intercircuit, and a mode two intercircuit; the output matching network adopts the power reconfigurable matching circuit of the application; the common end of the input matching network serves as an input end, and the other two ports are connected to the input terminals of the mode one intercircuit and the mode two intercircuit, respectively; the output terminals of the mode one intercircuit and the mode two intercircuit are connected to the first input terminal P1 and the second input terminal P8 of the power reconfigurable matching circuit, respectively.

[0011] Further, the mode one inter-stage circuit comprises n transistors and n-1 inter-stage matching networks, n is an integer greater than or equal to 1, the n transistors are connected in series, when n is greater than or equal to 2, an inter-stage matching network is connected in series between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is used as the output terminal, and the sources of all the transistors are connected to the ground.

[0012] Further, the mode two inter-stage circuit comprises m transistors and m-1 inter-stage matching networks, m is an integer greater than or equal to 1, the m transistors are connected in series, when m is greater than or equal to 2, an inter-stage matching network is connected in series between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is used as the output terminal, and the sources of all the transistors are connected to the ground.

[0013] Further, the physical structure type of the transistor is a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor or a heterojunction bipolar transistor.

[0014] Further, the power amplifier circuit is implemented in the form of a monolithic integrated circuit or a hybrid integrated circuit.

[0015] Compared with the prior art, the present application has the following remarkable effects: 1. The present application changes the working state of the reconfigurable element through an external control signal, and realizes the switching of different power modes of the power amplifier and meets the working requirements of different power modes in a multifunctional electronic system through different modulation modes of the reconfigurable element; 2. The present application reduces the loss of the output matching circuit and improves the efficiency of the power amplifier by integrating the reconfigurable element into the output matching circuit to serve as a circuit matching branch, compared with a traditional power amplifier cascade switch; meanwhile, the design of the reconfigurable element using parallel and series-parallel switching tubes improves the isolation of different power modes; 3. The structure of the present application is simple and easy to implement, and has expandability. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 Fig. 1 is a structural schematic diagram of the power reconfigurable matching circuit of the present application;

[0017] Figure 2 Fig. 2 is a schematic diagram of the power amplifier of the present application;

[0018] Figure 3 Fig. 3 is a schematic diagram of the power amplifier of the present application, wherein (a) is an output power and efficiency test result schematic diagram of the power amplifier mode one circuit of the present application, and (b) is an output power result schematic diagram of the power amplifier mode two circuit of the present application. DETAILED DESCRIPTION

[0019] The application will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] As Figure 1 TL4, the reconfiguration branch, the sixth capacitor C6, the seventh microstrip line TL7, the ninth microstrip line TL9 are connected in series; the reconfiguration branch is composed of the first transistor K1, the fifth microstrip line TL5, the fourth capacitor C4, the sixth microstrip line TL6, the fifth capacitor C5, the second transistor K2, the third transistor K3; the first bias branch is composed of the first capacitor C1 and the second microstrip line TL2, and is connected between the output terminal of the first microstrip line TL1 and the first bias voltage source P2; the second bias branch is composed of the seventh capacitor C7 and the eighth microstrip line TL8, and is connected between the output terminal of the seventh microstrip line TL7 and the second bias voltage source P7.

[0021] In the reconfiguration branch, one end of the fifth microstrip line TL5 is connected to the output terminal of the fourth microstrip line TL4, and the other end is connected to the drain of the second transistor K2 after being connected in series with the sixth microstrip line TL6; the drain of the first transistor K1 is connected to the terminal where the fourth microstrip line TL4 and the fifth microstrip line TL5 are connected, the source is connected to the grounding point G1 (which is the reference potential of the power reconfigurable matching circuit), and the gate is connected to the first control voltage source P3; one end of the fourth capacitor C4 is connected to the terminal where the fifth microstrip line TL5 and the sixth microstrip line TL6 are connected, and the other end is connected to the grounding point G1; the fifth capacitor C5 is connected between the terminal where the sixth microstrip line TL6 and the drain of the second transistor K2 are connected and the output terminal P4; the source of the second transistor K2 is connected to the input terminal of the sixth capacitor C6, and the gate is connected to the second control voltage source P5; the drain of the third transistor K3 is connected to the terminal where the drain of the second transistor K2 and the sixth capacitor C6 are connected, the source is connected to the grounding point G1, and the gate is connected to the third control voltage source P6. The process of realizing reconfigurable matching by the reconfiguration branch is as follows:

[0022] Mode one circuit: when the first control voltage source P3, the second control voltage source P5 are-28V, the third control voltage source P6 is 0V, the transistor K1 and K2 are closed, K3 is turned on, at this time, the parallel switch transistor K1 is equivalent to the parallel capacitor to ground, the series switch transistor K2 and the parallel switch transistor K3 to ground form a series-parallel structure, and the switch transistor K2 is equivalent to a capacitor, and the switch transistor K3 is equivalent to a small resistance, which improves the isolation of the mode one and mode two circuits, at this time, a path is formed from the first input terminal P1 to the output terminal P4, and the second input terminal P8 to the output terminal P4 is disconnected.

[0023] Mode two circuit: when the first control voltage source P3, the second control voltage source P5 are 0V, the third control voltage source P6 is-28V, the transistor K1 and K2 are turned on, K3 is closed, at this time, the switch transistor K1 and K2 are equivalent to a small resistance, and the switch transistor K3 is equivalent to a capacitor, a path is formed from the second input terminal P8 to the output terminal P4, and the first input terminal P1 to the output terminal P4 is disconnected.

[0024] In the first bias branch, the second microstrip line TL2 is connected between the terminal where the first microstrip line TL1 and the third microstrip line TL3 are connected and the first bias voltage source P2, and the first capacitor C1 is connected between the terminal where the second microstrip line TL2 and the first bias voltage source P2 are connected and the ground point G1. The first bias branch is a leakage source path of the mode one circuit.

[0025] In the second bias branch, the eighth microstrip line TL8 is connected between the terminal where the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected and the second bias voltage source P7, and the seventh capacitor C7 is connected between the terminal where the eighth microstrip line TL8 and the second bias voltage source P7 are connected and the ground point G1. The second bias branch is a leakage source path of the mode two circuit.

[0026] As shown in Figure 2 The power amplifier of the application comprises an input matching network, a mode one intercircuit, a mode two intercircuit and an output matching network, and the output matching network adopts the power reconfigurable matching circuit of the application. The common terminal of the input matching network serves as the input terminal of the power amplifier, and the other two terminals are connected with the input terminals of the mode one intercircuit and the mode two intercircuit respectively, and the output terminals of the mode one intercircuit and the mode two intercircuit are connected with the two input terminals (i.e. the first input terminal P1 and the second input terminal P8) of the power reconfigurable matching structure.

[0027] The mode one interstage circuit comprises a front-stage transistor, an intermediate-stage transistor, an interstage matching network and a final-stage transistor, and the mode two interstage circuit also comprises a front-stage transistor, an intermediate-stage transistor, an interstage matching network and a final-stage transistor.

[0028] The mode one interstage circuit comprises n transistors and n-1 interstage matching networks, n is an integer greater than or equal to 1, the n transistors are connected in series, when n is greater than or equal to 2, an interstage matching network is connected in series between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is the output terminal of the mode one interstage circuit, and the source of each transistor is connected to the ground.

[0029] The mode two interstage circuit comprises m transistors and m-1 interstage matching networks, m is an integer greater than or equal to 1, the m transistors are connected in series, when m is greater than or equal to 2, an interstage matching network is connected in series between two adjacent transistors, the gate of the first transistor is connected to the output terminal of the input matching network, the drain of the last transistor is the output terminal of the mode two interstage circuit, and the source of each transistor is connected to the ground.

[0030] The physical structure type of the above-mentioned front-stage transistor, intermediate-stage transistors and final-stage transistor can be a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor or a heterojunction bipolar transistor.

[0031] The power amplifier of the present application is implemented as a monolithic integrated circuit or a hybrid integrated circuit.

[0032] Embodiment

[0033] As Figure 2As shown, it is a power amplifier using the power reconfigurable matching circuit. Its frequency range is 7-13GHz, including input matching network, mode one interstage circuit, mode two interstage circuit and output matching network. The output matching network uses the power reconfigurable matching circuit of the application. The common terminal of the input matching network is the input terminal of the power amplifier, and the other two terminals are connected with the input terminals of the mode one interstage circuit and the mode two interstage circuit respectively, and the output terminals of the mode one interstage circuit and the mode two interstage circuit are connected with the two input terminals of the power reconfigurable matching circuit respectively. The mode one interstage circuit includes the eleventh transistor Q1, a first interstage matching network, the twelfth transistor Q2, a second interstage matching network and the thirteenth transistor Q3, the gate of the eleventh transistor Q1 is connected with the output terminal of the input matching network, the first interstage matching network is connected between the drain of the eleventh transistor Q1 and the gate of the twelfth transistor Q2, the second interstage matching network is connected between the drain of the twelfth transistor Q2 and the gate of the thirteenth transistor Q3, and the drain of the thirteenth transistor Q3 is connected with the first input terminal P1 of the power reconfigurable matching circuit. The mode two interstage circuit includes the fourteenth transistor Q4, a first interstage matching network and the fifteenth transistor Q5, the gate of the fourteenth transistor Q4 is connected with the output terminal of the input matching network, the first interstage matching network is connected between the drain of the fourteenth transistor Q4 and the gate of the fifteenth transistor Q5, the drain of the fifteenth transistor Q5 is connected with the second input terminal P8 of the power reconfigurable matching circuit, and the first bias branch and the second bias branch in the power reconfigurable matching circuit provide direct current power supply for the drain of the thirteenth transistor Q3 of the mode one interstage circuit and the drain of the fifteenth transistor Q5 of the mode two interstage circuit respectively. In addition, the interstage matching network circuit structures in the mode one interstage circuit and the mode two interstage circuit can be different, and the sources of the transistors in the branches are all connected with the ground.

[0034] Figure 2 When the Q1, Q2 and Q3 transistors are turned on, the Q4 and Q5 transistors are turned off, the gates of the first and second transistors K1 and K2 in the output matching network are applied with negative voltage, and the gate of the third transistor K3 is applied with 0V, the output matching network participates in the mode one circuit matching to realize 25W high-power output.

[0035] Figure 3Fig. 1 is a schematic diagram of the output power and additional efficiency test results of the power amplifier mode one circuit in the application, and Fig. 2 is a schematic diagram of the output power results of the power amplifier mode two circuit in the application. It can be seen that the power reconfigurable power amplifier circuit in the application has a power output of 25W and an additional efficiency of 40% in the frequency range of 7-13GHz under the mode one circuit operation, and has a power output of 2W and a flatness better than ±1dB under the mode two circuit operation. In addition, the power amplifier of the power reconfigurable circuit in the application is suitable for radio frequency, microwave and millimeter wave application occasions.

[0036] The above examples are only for illustrating the technical route of the application, and cannot limit the protection scope of the application. Any modification made according to the technical route of the application, on the basis of the technical route, falls within the protection scope of the application.

Claims

1. A power reconfigurable matching circuit, characterized by, The first microstrip line TL1, the first bias branch, the third microstrip line TL3, the second capacitor C2, the third capacitor C3, the fourth microstrip line TL4, the reconstruction branch, the sixth capacitor C6, the seventh microstrip line TL7, the ninth microstrip line TL9, the second bias branch, the first input terminal P1, the second input terminal P8 and the output terminal P4 are connected in series. The first microstrip line TL1, the third microstrip line TL3, the third capacitor C3, the fourth microstrip line TL4, the reconstruction branch, the sixth capacitor C6, the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected in series; one end of the second capacitor C2 is connected to a terminal where the third microstrip line TL3 and the third capacitor C3 are connected, and the other end is connected to the grounding point G1; the output terminal P4 is connected to the reconstruction branch. One end of the first bias branch is connected to a terminal where the first microstrip line TL1 and the third microstrip line TL3 are connected, and the other end is connected to the first bias voltage source P2; one end of the second bias branch is connected to a terminal where the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected, and the other end is connected to the second bias voltage source P7. One end of the first microstrip line TL1 is connected to the first bias branch, and the other end is connected to the first input terminal P1. One end of the ninth microstrip line TL9 is connected to the second bias branch, and the other end is connected to the second input terminal P8. The reconstruction branch includes the first transistor K1, the fifth microstrip line TL5, the fourth capacitor C4, the sixth microstrip line TL6, the fifth capacitor C5, the second transistor K2 and the third transistor K3; one end of the fifth microstrip line TL5 is connected to an output terminal of the fourth microstrip line TL4, and the other end is connected to a drain electrode of the second transistor K2 after being connected in series with the sixth microstrip line TL6. A drain electrode of the first transistor K1 is connected to a terminal where the fourth microstrip line TL4 and the fifth microstrip line TL5 are connected, a source electrode is connected to the grounding point G1, and a gate electrode is connected to the first control voltage source P3; one end of the fourth capacitor C4 is connected to a terminal where the fifth microstrip line TL5 and the sixth microstrip line TL6 are connected, and the other end is connected to the grounding point G1. The fifth capacitor C5 is connected between a terminal where the sixth microstrip line TL6 and the drain electrode of the second transistor K2 are connected and the output terminal P4; a source electrode of the second transistor K2 is connected to an input terminal of the sixth capacitor C6, and a gate electrode is connected to the second control voltage source P5; a drain electrode of the third transistor K3 is connected to a terminal where the drain electrode of the second transistor K2 and the sixth capacitor C6 are connected, a source electrode is connected to the grounding point G1, and a gate electrode is connected to the third control voltage source P6.

2. The power reconfigurable matching circuit of claim 1, wherein, The first bias branch includes the first capacitor C1 and the second microstrip line TL2; the second microstrip line TL2 is connected between a terminal where the first microstrip line TL1 and the third microstrip line TL3 are connected and the first bias voltage source P2, and the first capacitor C1 is connected between a terminal where the second microstrip line TL2 and the first bias voltage source P2 are connected and the grounding point G1.

3. The power reconfigurable matching circuit of claim 1, wherein, The second bias branch comprises a seventh capacitor C7 and an eighth microstrip line TL8; the eighth microstrip line TL8 is connected between a terminal where the seventh microstrip line TL7 and the ninth microstrip line TL9 are connected and a terminal where the second bias voltage source P7 is connected, and the seventh capacitor C7 is connected between a terminal where the eighth microstrip line TL8 and the second bias voltage source P7 are connected and the ground point G1.

4. A power amplifier, characterized by The power amplifier comprises an output matching network, an input matching network, a mode one inter-stage circuit and a mode two inter-stage circuit; the output matching network adopts the power reconfigurable matching circuit according to any one of claims 1-3; the common terminal of the input matching network is used as an input terminal, and the other two terminals are connected with input terminals of the mode one inter-stage circuit and the mode two inter-stage circuit respectively, and output terminals of the mode one inter-stage circuit and the mode two inter-stage circuit are connected with the first input terminal P1 and the second input terminal P8 of the power reconfigurable matching circuit respectively; The mode one inter-stage circuit comprises n transistors and n-1 inter-stage matching networks, n is an integer greater than or equal to 1, the n transistors are connected in series, when n is greater than or equal to 2, an inter-stage matching network is connected in series between adjacent two transistors, the gate of the first transistor is connected with the output terminal of the input matching network, the drain of the last transistor is used as an output terminal, and the source of all the transistors is connected with the ground. The mode two inter-stage circuit comprises m transistors and m-1 inter-stage matching networks, m is an integer greater than or equal to 1, the m transistors are connected in series, when m is greater than or equal to 2, an inter-stage matching network is connected in series between adjacent two transistors, the gate of the first transistor is connected with the output terminal of the input matching network, the drain of the last transistor is used as an output terminal, and the source of all the transistors is connected with the ground.

5. The power amplifier of claim 4, wherein, The physical structure type of the transistor is a junction field effect transistor, a metal-oxide-semiconductor field effect transistor, a heterojunction field effect transistor, a bipolar junction transistor or a heterojunction bipolar transistor.

6. The power amplifier of claim 4, wherein, The power amplifier is implemented in a monolithic integrated circuit or a hybrid integrated circuit.

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