Lithography Improvement Based on Defect Probability Distribution and Critical Dimension Variation

Abstract

Certain aspects relate to a method for improving a lithography configuration. In a lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focused exposure window (FEW). The defect-based FEW is a region of depth of focus and exposure latitude for the lithography configuration with an acceptable defect level on the wafer. The defect-based FEW is determined based on a predicted probability distribution of defects occurring on the wafer. The processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is a region of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. The CD-based FEW is determined based on a predicted CD on the wafer. The lithography configuration is modified based on increasing an overlap region between the defect-based FEW and the CD-based FEW.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 905,771, “Stochastic Window Centering for Semiconductor Process Defect Mode,” filed on September 25, 2019, and U.S. Provisional Patent Application Serial No. 62 / 907,901, “Stochastic Window Centering for Semiconductor Process Defect Mode,” filed on September 30, 2019. The subject matter of all of the foregoing is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to lithography, and more particularly, to improving lithography processes using predictions of defects and critical dimensions. Background Art

[0004] One step in the manufacture of semiconductor wafers involves photolithography. In a typical photolithography process, a source generates light that is collected and directed by collection / illumination optics to illuminate a mask. Projection optics relay the pattern generated by the illuminated mask onto the wafer, exposing the resist on the wafer according to the illumination pattern. The patterned resist is then used in the process of fabricating structures on the wafer. For a given mask, the photolithography equipment can operate over a range of focus settings and a range of exposure settings while still producing acceptable results. This range is referred to as the depth of focus (e.g., focus expressed in nanometers) and the exposure latitude (e.g., exposure expressed in millijoules per square centimeter). The area defined by the acceptable depth of focus and exposure latitude is referred to as the focus exposure window (FEW) of the photolithography configuration for the mask and photolithography equipment.

[0005] As lithography moves toward shorter wavelength ranges (e.g., EUV at approximately 13.3nm-13.7nm) and smaller geometries (e.g., 10nm, 7nm, and smaller technology nodes, with 20nm, 14nm, and smaller feature sizes), sensitivity to manufacturing variations increases. For example, higher photon energies result in lower photon counts for the same energy exposure. This can lead to random defect mechanisms that are negligible or non-existent at longer wavelengths and larger geometries. Current lithography optimization methods may ignore these effects and, therefore, may result in suboptimal lithography configurations. Summary of the Invention

[0006] Certain aspects relate to a method for improving a lithography configuration. In a lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focused exposure window (FEW). The defect-based FEW is a region of depth of focus and exposure latitude for the lithography configuration with an acceptable defect level on the wafer. The defect-based FEW is determined based on a predicted probability distribution of defects occurring on the wafer. The processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is a region of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. The CD-based FEW is determined based on a predicted CD on the wafer. The lithography configuration is modified based on increasing an overlap region between the defect-based FEW and the CD-based FEW.

[0007] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other techniques related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0009] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The accompanying drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0010] Figure 1 An EUV lithography system suitable for use with embodiments of the present disclosure is depicted.

[0011] Figure 2 Depicted is a flow chart for improving a lithography system based on critical dimension and defect probability models, according to some embodiments of the present disclosure.

[0012] Figure 3 A flow chart for improving a lithography system based on optimizing a source is depicted.

[0013] Figure 4 A flow chart for improving a lithography system based on optimizing a mask is depicted.

[0014] Figure 5 Depicted is a flow chart for creating a random model.

[0015] Figures 6A to 6C Depicted are examples of source mask optimization using a CD-based process window and a defect-based process window.

[0016] Figure 7Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0017] Figure 8 An abstract diagram depicts an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure relate to improvements in lithography based on defect probability distribution and critical dimension variation. In order to manufacture semiconductor devices, a lithography tool must be able to image within a range of focus settings and exposure settings for a given mask. This range is called the depth of focus (e.g., focus measured in nanometers) and exposure latitude (e.g., exposure measured in millijoules per square centimeter). The depth of focus and exposure latitude define a two-dimensional space. Over certain regions of this space, the lithography tool will meet the critical dimension (CD) requirements on the wafer. This region can be called the process window or focus exposure window (FEW). In addition, random pattern failures caused by random variations in the lithography process are also affected by the depth of focus and exposure latitude. Therefore, there are two types of FEW: one based on CD variation (CD-based process window) and one based on the probability of defect occurrence (defect-based process window).

[0019] In typical design approaches, these two process windows may not have a significant overlap. For example, if random variation is assumed to be negligible or otherwise ignored, the defect-based process window will not be considered during the design process. The resulting design may have a defect-based process window that does not significantly overlap with the CD-based process window. This would reduce overall yield. Conversely, considering both CD variation and defect probability distribution during the design phase can produce a lithography configuration with a larger overlap between the two process windows, thereby providing greater tolerance in operating the lithography equipment and increasing yield.

[0020] Figure 1 An extreme ultraviolet (EUV) lithography system suitable for use with embodiments of the present disclosure is depicted. In this system, a source 110 generates EUV light, which is collected and directed by collection / illumination optics 120 to illuminate a mask 130. Projection optics 140 relay the pattern produced by the illuminated mask onto a wafer 150, exposing resist on the wafer according to the illumination pattern. The exposed resist is then developed, producing a patterned resist on the wafer. This is used to fabricate structures on the wafer, for example, by deposition, doping, etching, or other processes.

[0021] exist Figure 1In the EUV wavelength range, light is in the EUV wavelength range, approximately 13.5 nm or in the range of 13.3 nm to 13.7 nm. At these wavelengths, components are generally reflective rather than transmissive. Mask 130 is a reflective mask, and optics 120 and 140 are also reflective and off-axis. This is just one example. Other types of lithography systems can also be used, including at other wavelengths, using transmissive masks and / or optics, and using positive or negative resists.

[0022] Figure 2 A flow chart for improving a lithography system based on a critical dimension and defect probability model is depicted. The dashed box includes a simulation or model of the overall lithography configuration 200. For convenience, separate boxes are shown to correspond to physical components or processes, but simulation need not be implemented in this manner. For example, source 210 represents a model of source 110, and illumination optics 212 represents the effect of illumination optics 120. These are used to predict the source illumination 215 of the mask. However, actual simulations may or may not use separate models for source 210 and optics 212. In some cases, the two can be combined into a single model or simulation that predicts the source illumination 215. Mask 220 models the effect of mask 130 on incident illumination 215. Projection optics 222 represents the effect of optics 140. Source illumination 215 is filtered by mask 220 and relayed by projection optics 220 to produce an aerial image 225, which exposes the resist on the wafer. The resist is modeled through exposure 230 and development 232, resulting in patterned resist 235. Additional modeling can be used to predict etching, doping, deposition, or other semiconductor manufacturing processes.

[0023] One measure of the quality of patterned resist 235 is the critical dimension (CD). The CD is the size of a significant feature in the patterned resist. Typically, the CD is the smallest line or space width printed in the resist. Therefore, it is a measure of the resolution of the resist and the lithography process. Model 200 can be used to predict 260 the CD for a given lithography configuration. Changes to lithography configuration 200 will result in changes to patterned resist 235 and changes 262 in the CD.

[0024] Two important operating parameters of a lithography system are exposure and focus. Exposure (or dose) is the amount of energy that illuminates the resist. Variations in exposure can be referred to as exposure latitude. Focus refers to the optical alignment of different components, for example, how well the projection optics are aligned to perfectly image the mask onto the resist. Variations in focus can be referred to as defocus. Given a model 200, it is possible to predict CD variations 262 that depend on exposure latitude and defocus. Conversely, it is also possible to predict values ​​of exposure latitude and defocus that produce an acceptable level of CD variation. This is referred to as a CD-based process window 265.

[0025] Another measure of the quality of the patterned resist 235 is defects. Examples of defects include when two printed lines that should be separate are merged, when a printed line that should be continuous has a break, and when a printed feature that should have a hole in the center is actually filled.

[0026] The lithography process has random variations. For example, the quality of the resist pattern 235 depends on the uniformity of photon absorption events during exposure and the uniformity of subsequent photochemical reactions in the resist. As the source photon counting output decreases, photon statistics (e.g., shot noise) become increasingly important because the number of photon absorption events is one random process in a chain of random processes in the lithography process. EUV lithography systems are characterized by both low photon output and low source throughput through the tool. For these reasons, photon shot noise may play a larger role in EUV systems, especially at technology nodes with feature sizes of 14nm or less. Consider that a random process generates defect predictions 270, which are probabilistic 272 rather than deterministic. For example, a simulation can generate a probability distribution of defects occurring on a wafer - the probability or defect rate of realizing any particular defect for a wafer (or portion of a wafer).

[0027] Given the ability to predict defect probability 272 based on exposure latitude and defocus, it is also possible to determine a defect-based process window 275. This is the exposure latitude and defocus values ​​that produce an acceptable level of defect probability.

[0028] Given a CD-based process window 265 and a defect-based process window 275, an overlap 280 between the two windows can be determined. This represents the available process window, at least in terms of CD variation and defect probability. Even if the two separate process windows 265, 275 are large, if they are shifted relative to each other, the available process window 280 will be relatively small. Therefore, the lithography configuration 200 can be modified 290 to improve the overlap area. In some cases, the overlap area 280 can be increased by improving the alignment or centering of the two process windows 265, 275 relative to each other. In other cases, the overlap area 280 can be increased by increasing the area of ​​one or both process windows 265, 275.

[0029] Figure 3 and Figure 4 Different types of improvements to the lithographic configuration are depicted. Figure 3In one approach, a defect probability model is used in source mask optimization (SMO) to optimize the source shape to prevent defects. A cost function is used with SMO to drive the source shape to reduce defects on the wafer. This can be achieved by constructing a final source shape that allows more photons (higher exposure energy) to achieve the desired CD. The probability of a defect is inversely proportional to the number of photons. However, the CD will also change with the number of photons, so the source must account for both effects.

[0030] After the source is selected, other parts of the lithography configuration can be further optimized, such as the mask. This can be achieved through optical proximity correction (OPC), sub-resolution assist features (SRAF) and / or phase shifting (in the case of phase-shift masks). Figure 4 As shown in , these mask optimization techniques can also be used to modify 490 the mask independently of source optimization.

[0031] In these optimization cases, a cost function can be used to reduce the probability of a defect. For example, the probability of a defect can be improved from 3 sigma to 5 sigma.

[0032] exist Figures 2 to 4 In

[272] , defect probabilities can be calculated in different ways. In one approach, a probability distribution for random variations in the lithography configuration is used to calculate the probability distribution of defects occurring on the wafer. For example, the photon counts can have a known distribution that depends on the total number of photons per region. Simulation can predict the average number of photons that expose the resist, and then the average number of photons can be overlaid with the probability distribution based on the average number of photon counts. Similar methods can be used for other random variations. The probability distribution can be based on first principles, heuristic approximations, or empirical observations.

[0033] Alternatively, different components in the modeling of the lithography arrangement 200 can have random components, and these random components can be propagated through the simulation. For example, assume that all random components have a Gaussian distribution. Then, the probability distribution at different points in the simulation can be tracked by calculating the mean and variance at that point in the simulation. If the source 210 has a certain mean and variance, and the effect of the illumination optics 212 is known, the mean and variance of the source illumination 215 can be calculated. Different components can also be random individually. For example, the scattering from the mask 220 can have some random variation, which is added to the source illumination 215.

[0034] Figure 5A flowchart for creating an example of a stochastic model is depicted. As shown, during a first calibration 510, parameters 514 of a resist process are used together with an optical model 512 to generate a resist model 516. During a stochastic calibration 520, stochastic parameters 522 are used together with the resist model 516 to generate a stochastic model 524. In some embodiments, the optical model 512 and the resist model 516 determine an optical signal intensity and an optical signal threshold associated with the optical signal. In some embodiments, the stochastic model 524 obtains a determined optical signal intensity and a determined optical signal threshold associated with the optical signal. Alternatively, in some embodiments, the stochastic model 524 determines the optical signal intensity and the optical signal threshold.

[0035] In some embodiments, extracting the optical signal profile using an optical signal threshold is performed. Extracting the optical signal profile can be performed randomly. Typically, the profile of a function of two variables (such as the optical signal intensity I(x) and the point x on the surface where the optical signal arrives) is a curve along which the function has a constant value so that the curve connects points of equal value. In some embodiments, the optical signal profile is a planar cross-section of a two-dimensional graph of the function I(x) parallel to the x-plane. In some embodiments, a signal field associated with the optical signal is created. Thereafter, an optical signal threshold associated with the optical signal for pattern transfer is determined. In some embodiments, the optical signal threshold is a constant. In some embodiments, the optical signal threshold is defined by the number of photons expected to arrive at a point, i.e., a cutoff dose divided by a dose associated with the region. For example, if the optical signal threshold is 0.2 and the dose associated with the region is 20 photons per square nanometer, the probability that a particular region with a cross-section of 1 square nanometer receives a cutoff dose of less than or more than 4 photons (i.e., 20*0.2) indicates the uncertainty of forming an edge on the particular region. In some embodiments, the edge does not have infinite slope and curvature at the optical signal threshold position, which would result in possible finite blurring once the correlation effects of adjacent voxels (i.e., three-dimensional pixels) are taken into account. As an example, for positive imaging, it is assumed that the optical signal above the optical signal threshold is cleared, and the optical signal below the optical signal threshold is assumed to remain intact.

[0036] More details can be found in U.S. Provisional Application No. 62 / 980,913, “Stochastic Signal Prediction in Compact Modeling,” and U.S. Provisional Application No. 63 / 035,468, “Calibrating Stochastic Signals in Compact Modeling,” which are incorporated herein by reference.

[0037] In yet another approach, a Monte Carlo method may be used to develop a probability distribution of defects.

[0038] Figures 6A to 6C Depicted are examples of source mask optimization using the above techniques. Each figure shows a different situation, starting with Figure 6A proceed to Figure 6C In each figure, the smaller black and white image is the source mask 610. The main color image plots different amounts depending on defocus (x-axis) and exposure latitude (y-axis).

[0039] Figure 6A The situation is shown after source mask optimization has been performed, but only taking into account CD effects and not random defects. The resulting source mask 610A is shown. Figure 6A Pairs of identically colored curves are plotted, with the band between the two curves representing the region of acceptable CD variation. Cyan region 620A represents the overall acceptable process window for all curves, as it falls within the inner band of all curve pairs. Ellipse 665A is a best-fit ellipse inscribed within cyan region 620A. It has an exposure latitude of 6% and a depth of focus of 118nm, but it represents the process window based solely on CD.

[0040] Figure 6B Shows the Figure 6A Defect-based process window for the same situation. Mask 610A with Figure 6B For clarity, Figure 6A The curve pairs are not shown. Figure 6B The new color curve in the cyan region 620B represents the region of acceptable defect probability. The cyan region 620B represents the overall acceptable process window for all curves because it falls within the acceptable range for all color curves. Ellipse 675B is the best fit ellipse inscribed within the cyan region 620B. It has an exposure latitude of 6% and a depth of focus of 43nm. This is better than Figure 6A The process window 680A is much smaller, but it is the actual process window for source mask 610A because it also takes defects into account.

[0041] Figure 6C The following diagram shows the situation when the source mask is optimized taking into account both CD effects and random defects. For convenience, only the color curves for the defect probability are shown. The CD color curves are not shown because they are not restrictive. The resulting source mask 610C is different from the previous one. However, the overall process window 680C has an exposure latitude of 6% and a depth of focus of 70nm, which is significantly greater than Figure 6A and Figure 6B Available Processes window.

[0042] Figure 7An example set of processes 700 used during the design, verification, and manufacture of an article of manufacture, such as an integrated circuit, is illustrated to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' stands for the term 'electronic design automation'. These processes begin with the creation of a product concept 710 using information provided by a designer, which is transformed to produce an article of manufacture using a set of EDA processes 712. When the design is completed, the design is taped out 734, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to create a mask set, which is then used to manufacture the integrated circuit. After tapeout, semiconductor die are manufactured 736, and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0043] The specification of a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. Using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera, circuits and systems can be designed using a high level of abstraction. The HDL description can be converted into a register transfer level ('RTL') description at the logic level, a gate level description, a layout level description or a mask level description. Each lower level of abstraction (i.e. less abstract description) adds more useful detail to the design description, for example more detail for the modules that comprise the description. The lower levels of abstraction (i.e. less abstract descriptions) may be computer generated, derived from a design library or created by another design automation process. An example of a specification language for lower levels of abstraction that is used to specify more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is enabled for use by the corresponding tools at that layer (e.g. formal verification tools). The design process may use Figure 7 The sequence described in . The described process is enabled by an EDA product (or tool).

[0044] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0045] During logic design and functional verification 717, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the specifications of the designed circuit or system. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems called 'simulators' or 'prototyping systems' are used to accelerate functional verification.

[0046] During synthesis and design for testing 718, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are manufactured layered products that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0047] During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0048] During layout or physical implementation 724, physical placement (placement of circuit components (such as transistors or capacitors)) and routing (connection of circuit components through multiple conductors) are performed, and selection of cells from a library to enable specific logic functions may be performed. As used herein, the term 'cell' may specify a collection of transistors, other components, and interconnects that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit 'block' may refer to more than two cells. Both cells and circuit blocks may be referred to as modules or components and may be enabled for both physical structures and simulations. Parameters such as size are specified for the selected cells (based on 'standard cells') and made accessible in a database for use by EDA products.

[0049] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows for refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit functionality matches the HDL design specifications. During parsing enhancement 730, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0050] During tape-out, data is created for use in producing lithographic masks (after applying lithographic enhancements if appropriate).During mask data preparation 732, 'tape-out' data is used to generate lithographic masks, which are used to produce finished integrated circuits.

[0051] Computer systems (such as Figure 8 The storage subsystem of the computer system 800) can be used to store programs or data structures that are used by some or all of the EDA products described herein and by products used to develop units of the library and products used to design physical and logical designs using the library.

[0052] Figure 8 The diagram illustrates an example computer system 800 within which a set of instructions, operable to cause the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., connected to a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client computer in a cloud computing infrastructure or environment.

[0053] The machine may be a personal computer (PC), a tablet computer, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. Furthermore, while a single machine is illustrated, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0054] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.

[0055] The processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 may be configured to execute instructions 826 to perform the operations and steps described herein.

[0056] The computer system 800 may also include a network interface device 808 for communicating over a network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generating device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0057] The data storage device 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. During execution of the instructions 826 by the computer system 800, the instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802, with the main memory 804 and the processing device 802 also constituting machine-readable storage media.

[0058] In some embodiments, the instructions 826 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) to store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding an instruction set for execution by a machine and causing the machine and processing device 802 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0059] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0060] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clearly indicated from this disclosure, it should be understood that throughout this description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0061] The present disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0062] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used in conjunction with the program according to the teachings herein, or it may prove easy to construct a more specialized device to perform the method. Additionally, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0063] The present disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. Machine-readable media includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0064] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It is apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same reference numerals. Therefore, the present disclosure and the accompanying drawings should be considered illustrative rather than restrictive.

Claims

1. A method for improving a lithography arrangement comprising a source for illuminating a mask to expose resist on a wafer, the method comprising: determining, by a processor, a defect-based focused exposure window based on a predicted probability distribution of defects occurring on the wafer, wherein the defect-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable defect level on the wafer; determining, by a processor, a critical dimension-based focused exposure window based on a predicted critical dimension on the wafer; wherein the critical dimension-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable level of critical dimension variation on the wafer; as well as The lithography configuration is modified based on increasing an overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

2. The method of claim 1 , wherein determining the defect-based focused exposure window is based on a defect rate of the wafer, and the defect rate of the wafer is determined based on the predicted probability distribution of defects occurring on the wafer.

3. The method of claim 1, wherein the lithography configuration operates in the extreme ultraviolet (EUV) wavelength range, and the probability distribution of defects occurring on the wafer is a result of random variations in photons exposing the resist.

4. The method of claim 1, wherein the probability distribution of defects occurring on the wafer is calculated using a probability distribution for random variations in the lithographic configuration.

5. The method of claim 1, wherein the probability distribution of defects occurring on the wafer is calculated using a Monte Carlo simulation of the lithography configuration.

6. The method according to claim 1, further comprising: Predicting the probability distribution of defects occurring on the wafer, wherein predicting the probability distribution of defects occurring comprises: determining a profile of an optical signal exposing the resist, wherein the optical signal is characterized by a probability distribution; defining a first parameter based at least in part on an intensity of the optical signal; defining a second parameter indicative of a portion of the optical signal absorbed by the resist; and The probability distribution of the occurrence of a defect is predicted based at least in part on the optical signal profile and the first parameter and the second parameter.

7. The method of claim 1 , wherein modifying the lithographic configuration comprises: Alignment between the defect-based focused exposure window and the critical dimension-based focused exposure window is improved.

8. The method of claim 1 , wherein modifying the lithographic configuration comprises: At least one of the mask and the source is modified based on increasing the overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

9. The method of claim 8, wherein modifying the mask further comprises: The mask is modified using at least one of sub-resolution assist features and optical proximity correction.

10. The method of claim 8, wherein the mask includes phase shifting elements, and modifying the mask further comprises: The phase shift element is modified based on increasing the overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

11. The method of claim 1 , wherein the lithography configuration operates in the extreme ultraviolet (EUV) wavelength range and at a technology node having a feature size of 14 nm or less.

12. The method of claim 1 , wherein modifying the lithographic configuration comprises: defining a cost function that depends on the overlap area between the defect-based focused exposure window and the critical dimension-based focused exposure window; as well as The lithographic configuration is modified based on improving the cost function.

13. A system for improving a lithography arrangement including a source for illuminating a mask to expose resist on a wafer, the system comprising: Memory, which stores instructions; as well as a processor coupled to the memory and executing the instructions, which, when executed, cause the processor to: determining a defect-based focused exposure window based on a predicted probability distribution of defects occurring on the wafer, wherein the defect-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable defect level on the wafer, determining a critical dimension-based focused exposure window based on a predicted critical dimension on the wafer; wherein the critical dimension-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable level of critical dimension variation on the wafer; as well as The lithography configuration is modified based on increasing an overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

14. The system of claim 13, wherein the lithography configuration operates in an extreme ultraviolet (EUV) wavelength range, and the probability distribution of defects occurring on the wafer is a result of random variations in photons exposing the resist.

15. The system of claim 13, wherein the lithography configuration operates in the extreme ultraviolet (EUV) wavelength range and at a technology node having a feature size of 14 nm or less.

16. A non-transitory computer readable medium comprising stored instructions for improving a lithography configuration, the lithography configuration comprising a source that illuminates a mask to expose resist on a wafer, the instructions, when executed by a processor, causing the processor to: determining a defect-based focused exposure window based on a predicted probability distribution of defects occurring on the wafer, wherein the defect-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable defect level on the wafer, determining a critical dimension-based focused exposure window based on a predicted critical dimension on the wafer; wherein the critical dimension-based focused exposure window is a region of focus depth and exposure latitude for the lithography configuration with an acceptable level of critical dimension variation on the wafer; and The lithography configuration is modified based on increasing an overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

17. The non-transitory computer-readable medium of claim 16, wherein modifying the lithographic configuration comprises: The source is modified to improve alignment between the defect-based focused exposure window and the critical dimension-based focused exposure window.

18. The non-transitory computer-readable medium of claim 16, wherein modifying the lithographic configuration comprises: At least one of the mask and the source is modified based on increasing the overlap area between the defect-based focus exposure window and the critical dimension-based focus exposure window.

19. The non-transitory computer readable medium of claim 16, wherein modifying the lithographic configuration is based on improving alignment of the defect-based focused exposure window with the critical dimension-based focused exposure window.

20. The non-transitory computer readable medium of claim 16, wherein modifying the lithographic configuration is based on increasing the area of ​​the defect-based focus exposure window and / or increasing the area of ​​the critical dimension-based focus exposure window.

Images