Convert load instructions

Abstract

The processor core processes a translation load instruction including a protection field that specifies a desired access protection specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that the translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

Description

Technical Field

[0001] The present invention relates generally to data processing and, in particular, to translation load instructions which, when executed by a processor, cause desired translation entries to be selectively loaded into an address translation structure. Background Art

[0002] A conventional multiprocessor (MP) computer system includes multiple processing units (each of which may include one or more processor cores and their different cache memories), input / output (I / O) devices, and data storage devices, which may include both system memory (which may be volatile or non-volatile) and non-volatile mass storage devices. In order to provide sufficient addresses for memory-mapped I / O operations and data and instructions used by the operating system and application software, MP computer systems typically reference an effective address space that includes a much larger number of effective addresses than the number of memory-mapped I / O devices and physical storage locations in the system memory. Therefore, in order to perform memory-mapped I / O or access system memory, a processor core within a computer system that utilizes effective addressing is required to convert an effective address to a real address assigned to a particular I / O device or a physical storage location within the system memory.

[0003] In many architectures, the effective address space is divided into multiple memory pages, each of which has a corresponding associated address descriptor called a page table entry (PTE). The PTE corresponding to a particular memory page contains, among other things, a base effective address of the memory page and an associated base real address of a page frame, thereby enabling the processor core to translate any effective address within the memory page into a real address in the system memory. PTEs created in the system memory, for example, under the direction of an operating system and / or hypervisor software, are collected in a page frame table.

[0004] In order to speed up the translation of effective addresses to real addresses during the processing of memory-mapped I / O and memory access instructions (hereinafter, together referred to as "memory reference instructions"), conventional processor cores often employ, among other translation structures, a cache known as a translation lookaside buffer (TLB) to buffer recently accessed PTEs within the processor core. Of course, as data is moved into and out of physical storage locations in system memory (e.g., in response to the invocation of a new process or a context switch), entries in the TLB must be updated to reflect the presence of the new data, and TLB entries associated with data removed from system memory (e.g., paged out to non-volatile mass storage) must be invalidated.

[0005] The present applicant recognizes that it would be useful and desirable to provide improved techniques for loading translation entries into address translation structures (such as page frame tables and TLBs) of a data processing system.

[0006] Therefore, there is a need in the art to solve the above problems. Summary of the invention

[0007] Viewed from a first aspect, the present invention provides a method for processing in a data processing system including a system memory, the method comprising: a processor core processing a translation load instruction, wherein the translation load instruction includes a protection field, the protection field specifies an expected access protection specified in a translation entry for a memory page, and wherein processing the translation load instruction comprises: calculating an effective address within the memory page; and ensuring that the translation entry containing the expected access protection is stored within at least one translation structure of the data processing system.

[0008] From another aspect, the present invention provides a processing unit for a data processing system, the processing unit comprising: a processor core, including: a memory management unit, which converts an effective address into a real address; and an execution unit that executes instructions; wherein the processor core is configured to perform: processing a conversion load instruction, wherein the conversion load instruction includes a protection field, the protection field specifies the desired access protection specified in a conversion entry for a memory page, and wherein processing the conversion load instruction includes: calculating an effective address within the memory page; and ensuring that the conversion entry containing the desired access protection is stored in at least one conversion structure of the data processing system.

[0009] From another aspect, the present invention provides a design structure that is tangibly embodied in a machine-readable storage device for designing, manufacturing or testing integrated circuits, the design structure comprising: a processing unit for a data processing system, the processing unit comprising: a processor core, the processor core comprising: a memory management unit that converts an effective address into a real address; and an execution unit that executes instructions; wherein the processing unit is configured to perform: processing a conversion load instruction, wherein the conversion load instruction includes a protection field, the protection field specifies the desired access protection specified in a conversion entry for a memory page, and wherein processing the conversion load instruction includes: calculating an effective address within the memory page; and ensuring that a conversion entry containing the desired access protection is stored in at least one conversion structure of the data processing system.

[0010] In at least one embodiment, a processor core processes a translation load instruction that includes a protection field that specifies a desired access protection specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that the translation entry containing the desired access protection is stored within at least one translation structure of the data processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will now be described, by way of example only, with reference to preferred embodiments as illustrated in the following drawings:

[0012] Figure 1 is a high-level block diagram of an exemplary data processing system according to one embodiment;

[0013] Figure 2 is a more detailed block diagram of an exemplary processing unit according to one embodiment;

[0014] Figure 3 An exemplary conversion load instruction is shown according to one embodiment;

[0015] Figure 4 shows an exemplary page table entry according to one embodiment;

[0016] Figure 5 is a high-level logic flow diagram of an exemplary method for a processor core to process a translation load instruction according to one embodiment;

[0017] Figure 6 is a high-level logic flow chart of an exemplary method for a page fault handler to resolve a page fault according to one embodiment;

[0018] Figure 7 is a high-level logic flow chart of an exemplary method for a protection fault handler to resolve a protection fault according to one embodiment; and

[0019] Figure 8 is a data flow diagram showing the design process. DETAILED DESCRIPTION

[0020] Referring now to the drawings, wherein like reference numerals refer to like and corresponding parts throughout, and in particular to Figure 1 , a high-level block diagram depicting an exemplary data processing system 100 according to one embodiment is shown. In the illustrated embodiment, data processing system 100 is a cache-coherent symmetric multiprocessor (SMP) data processing system that includes a plurality of processing nodes 102 for processing data and instructions. Processing nodes 102 are coupled to a system interconnect 110 to communicate address, data, and control information. System interconnect 110 may be implemented, for example, as a bus interconnect, a switch interconnect, or a hybrid interconnect.

[0021] In the depicted embodiment, each processing node 102 is implemented as a multi-chip module (MCM) containing four processing units 104a to 104d, each of which is preferably implemented as a respective integrated circuit. The processing units 104 within each processing node 102 are coupled for communication with each other and with the system interconnect 110 via a local interconnect 114, which is similar to the system interconnect 110 and can be implemented, for example, using one or more buses and / or switches. The system interconnect 110 and the local interconnect 114 together form a system structure.

[0022] See below Figure 2 Describing in more detail, processing units 104 each include a memory controller 106 that is coupled to local interconnect 114 to provide an interface to a respective system memory 108. Data and instructions residing in system memory 108 are generally accessible, cached, and modified by a processor core in any processing unit 104 of any processing node 102 within data processing system 100. System memory 108 thus forms the lowest level of memory storage in the distributed shared memory system of data processing system 100. In alternative embodiments, one or more memory controllers 106 (and system memory 108) may be coupled to system interconnect 110 instead of local interconnect 114.

[0023] Those skilled in the art will recognize that Figure 1 The SMP data processing system 100 may include many additional components not shown, such as interconnect bridges, non-volatile memory, ports for connecting to a network or attached devices, etc. Because such additional components are not necessary for understanding the described embodiments, they are not described in detail. Figure 1 However, it should also be understood that the enhancements described herein are applicable to data processing systems of different architectures and are by no means limited to Figure 1 The general data processing system architecture is shown.

[0024] See now Figure 2 , depicts a more detailed block diagram of an exemplary processing unit 104 and system memory 108 according to one embodiment. In the depicted embodiment, each processing unit 104 is an integrated circuit that includes one or more processor cores 200 for processing instructions and data. In the depicted example, the processor core 200 includes one or more execution units 202 that execute instructions from multiple concurrently executing hardware threads.

[0025] The processor core 200 additionally includes a memory management unit (MMU) 204, which is responsible for translating effective addresses determined by the execution of memory reference instructions in the execution unit 202 into real addresses. The MMU 204 performs effective to real address translations by referencing one or more translation structures 206, such as a translation lookaside buffer (TLB), an effective to real address translation (ERAT) cache, a segment lookaside buffer (SLB), etc. The number and / or type of these translation structures vary between implementations and architectures. As discussed further below, the translation structures 206 reduce latency associated with address translations by buffering local copies of selected address translations that can be retrieved from the system memory 108.

[0026] The operation of each processor core 200 is supported by a multi-level memory hierarchy having at its lowest level a system memory 108 shared by all processing units 104 and accessible via an integrated memory controller 106. As shown, the system memory 108 stores one or more system data structures (SDS) 224 that define addresses for which effective to real address translation is legal (possibly through one or more intervening memory spaces) and current access protections for different regions of the address space. In addition, the system memory 108 stores a page frame table 220 containing a plurality of page table entries (PTEs) 222, each of which specifies an effective-real address translation for a respective corresponding memory page present in the system memory 108. The PTEs 222 accessed from the page frame table 220 by the MMU 204 may be cached by the MMU 204 for subsequent accesses, such as in a TLB implemented between the translation structures 206. SDS 224 and page frame table 220 may be established, maintained, and updated, for example, by operating system and / or hypervisor software executing within data processing system 100 .

[0027] The multi-level memory hierarchy of each processor core 200 additionally includes one or more levels of cache memory, which in the illustrative embodiment include a direct-store level 1 (L1) cache 208 within and dedicated to each processor core 200 and a corresponding store level 2 (L2) cache 230 for each processor core 200. Although the cache hierarchy shown includes only two levels of cache, those skilled in the art will appreciate that alternative embodiments may include additional levels (L3, L4, etc.) of on-chip or off-chip, private or shared, in-line or lookaside cache that may fully contain, partially contain, or not contain the contents of the upper levels of cache.

[0028] Each processing unit 104 also includes an integrated and distributed fabric controller 214 that is responsible for controlling the flow of operations on the system fabric including the local interconnect 114 and the system interconnect 110, and for implementing the coherent communications required to implement the desired cache coherence protocol. The processing unit 104 also includes an integrated I / O (input / output) controller 216 that supports the attachment of one or more I / O devices such as an accelerator 217. The processing unit 104 also includes a nested memory management unit (NMMU) 218 ​​that provides address translation services to other agents (such as the accelerator 217) upon request, which lack their own address translation facilities. It should be understood that in other embodiments, the NMMU 218 can be communicatively coupled to provide address translation services to agents including the accelerator 217 in an alternative or additional manner, such as by coupling to the system interconnect 110 instead of coupling to the local interconnect 114.

[0029] See now Figure 3 , shows an exemplary conversion load instruction 300 according to one embodiment. The conversion load instruction 300 may be executed, for example, by the execution unit 202 of the processor core 200, as described below. Figure 5 Further described.

[0030] In the depicted embodiment, the translation load instruction 300 includes an operation code (opcode) field 302 that specifies an architecture-dependent opcode that identifies the instruction 300 as a translation load instruction. In addition, the translation load instruction 300 includes an address field 314 that identifies one or more registers from whose contents the effective address of a virtual memory page can be calculated.

[0031] The conversion load instruction 300 also includes a protection field 304, which includes, for example, a read-only (R) bit 306, a read-write (RW) bit 308, and an executable (E) bit 310. The R bit 306 is set (e.g., to 1) and the RW bit 308 is reset (e.g., to 0) to indicate that the memory page identified by the address calculated using the address field 314 is read-only. The R bit 306 is reset (e.g., to 0) and the RW bit 308 is set (e.g., to 1) to indicate that the memory page will be subject to both read and write accesses. The E bit 310 is independently set (e.g., to 1) to indicate that the memory page will be considered to contain executable instructions, otherwise it is reset (e.g., to 0).

[0032] The translation load instruction 300 additionally includes a load (LD) field 312. In at least some embodiments, the LD field 312 may be implemented with one or more bits, each bit corresponding to a respective one of the translation structures 206 in the processor core 200. In this example, the bits set in the LD field 312 indicate that in response to execution of the translation load instruction 300, a translation for the address of the referenced memory page is to be loaded into the associated translation structure 206 in the processor core 200, if necessary.

[0033] See now Figure 4 , depicts an exemplary format for a page table entry 222 according to one embodiment. In this example, the page table entry 222 includes an effective address field 400 indicating a base effective address of a memory page in the effective address space, a real address field 402 indicating a base real address of a corresponding memory page in the system memory 108, a size field 403 indicating the size of the memory page, and a valid field 412 indicating whether the page table entry 222 is valid and therefore can be used for address translation. The page table entry 222 also includes a protection field 404, which includes a read-only (R) bit 406, a read-write (RW) bit 408, and an executable (E) bit 410. As in the protection field 304 of the translation load instruction 302, the R bit 406 is set (e.g., to 1) and the RW bit 408 is reset (e.g., to 0) to indicate that the memory page is read-only, and the R bit 406 is reset (e.g., to 0) and the RW bit 408 is set (e.g., to 1) to indicate that the memory page can be read and written. The E bit 410 is independently set (eg, set to 1) to indicate that the memory page contains executable instructions, and is reset (eg, set to 0) otherwise.

[0034] See now Figure 5 , shows a high-level logic flow diagram of an exemplary method for execution unit 202 of processor core 200 to execute conversion load instruction 300 according to one embodiment.

[0035] Figure 5 The process of 206 begins at block 500, for example, in response to execution unit 202 receiving a translation load instruction 300 to be executed. In some use cases, one or more translation load instructions 300 may be executed within a hardware thread of execution of processor core 200 to load one or more address translations into translation structure 206 prior to executing a memory reference instruction (in the same or another hardware thread of processor core 200) that depends on those address translations. As a result, execution of subsequent memory reference instructions will be accelerated by the ability of MMU 204 to have low latency access to address translations within translation structure 206 (rather than having to access each required address translation from page frame table 220).

[0036] In other use cases, the processor core 200 may execute the translation load instruction 300 in response to an interrupt caused by the NMMU 218. For example, if the NMMU 218 has been requested by the accelerator 217 to translate a specific effective address, and the corresponding PTE 222 does not exist in the page frame table 220 or the PTE 222 does not provide the requested access protection, the NMMU 218 may interrupt the processor core 200 to cause execution of the translation load instruction 300 for the specific effective address.

[0037] In response to execution of the translation load instruction 300, the execution unit 202 calculates an effective address within the memory page based on the contents of the address field 314 of the translation load instruction 300 (block 502). Based on the effective address calculated by the execution unit 202 at block 502, the executing processor core 200 optionally determines at blocks 504 and 506, respectively, whether a translation entry for the effective address exists in each of the core translation structures indicated by the LD field 312 and has at least the access protection indicated by the protection field 304. In response to affirmative determinations at both optional blocks 504 and 506, no further processing of the translation load instruction 300 is required, and Figure 5 The process ends at block 530. However, if a positive determination is made at block 504 and a negative determination is made at block 506, a protection fault is detected, and Figure 5 The process accordingly passes through page connector A to block 520, which will be described below. If a negative determination at block 504 or if optional blocks 504 and 506 are omitted, then Figure 5 The processing proceeds to box 510.

[0038] At block 510, the processor core 200 initiates a walk of the page frame table 220 by the MMU 204 to locate (if possible) the PTE 222 corresponding to the effective address determined at block 502. At block 512, the MMU 204 determines whether the walk of the page frame table 220 finds the relevant PTE 222 in the page frame table 220. If so, the process proceeds to block 516 described below. If not, a page fault is detected, and the executing processor core 200 invokes a page fault handler (block 514). See below. Figure 6 The processing performed by the exemplary page fault handler to resolve the page fault is described. After the execution of the page fault handler at block 514, Figure 5 The process ends at box 530.

[0039] Referring now to Figure 516, the execution processor core 200 determines whether the PTE 222 found by traversing the page frame table 220 includes access permissions in the protection field 404 of the PTE 222 that are at least as large as those specified in the protection field 304 of the translation load instruction 300. For example, if the protection field 304 of the translation load instruction 300 specifies a read-only page (R=0) and the protection field 404 specifies a read-only page or a read-write page (R=0..1), then a positive determination will be made at block 516. Similarly, if the protection field 304 of the translation load instruction 300 specifies a non-executable memory page (E=0) and the protection field 404 indicates a non-executable or executable memory page (E=0..1), then a positive determination will be made at block 516. Conversely, if the protection field 304 of the converted load instruction 300 specifies a read-write page (RW=1) and the protection field 404 specifies a read-only page (RW=0), or if the protection field 304 of the converted load instruction 300 specifies an executable memory page (E=1) and the protection field 404 indicates a non-executable memory page (E=0), a negative determination will be made at block 516.

[0040] In response to a positive determination at block 516, the process proceeds to block 522 described below. However, if a negative determination is made at block 516, a protection fault is detected and the executing processor core 200 invokes a protection fault handler (block 520). See below. Figure 7 The processing performed by the exemplary protection fault handler to resolve the protection fault is described. After executing the protection fault handler, Figure 5 The process ends at box 530.

[0041] Block 522 shows the execution processor core 200 determining whether any bit in the LD field 312 of the translation load instruction 300 is set to indicate that the requested address translation is loaded into the one or more translation structures 206. If not, then the processing of the translation load instruction 300 is complete, and Figure 5The process thus ends at block 530. However, if the executing processor core 200 determines at block 522 that at least one bit is set in the LD field 312 to indicate that the requested address translation is to be loaded into one or more translation structures 206, then the executing processor core 200 further determines at block 524 whether the requested address translation is present in each translation structure 206 indicated by the LD field 312 of the translation load instruction 300. If not, the executing processor core 200 loads a translation entry providing the address translation into each translation structure 206 indicated by the LD field 312 of the translation load instruction 300 (block 526). As will be appreciated, loading the address translation entry into the translation structure 206 does not cause pollution of the cache hierarchy (i.e., L1, L2, etc.) of the executing processor core 200 because the updates to the translation structures 206 performed in response to the processing of the translation load instruction 300 are not connected to any conventional data load access, data storage access, or instruction fetch. After block 526 or in response to a positive determination at block 524, processing of the conversion load instruction 300 by the processor core 200 is complete, and Figure 5 The process ends at box 530.

[0042] See now Figure 6 , depicts a high-level logic flow diagram of an exemplary method for a page fault handler to resolve a page fault according to one embodiment. As described above, for example, Figure 5 In response to detecting a page fault, block 514 of Figure 6 process.

[0043] Figure 6 The process begins at block 600, where execution of a page fault handler is invoked by processor core 200 of data processing system 100. The process proceeds from block 600 to blocks 602-604, which illustrate the page fault handler accessing system data structure 224 to determine whether the effective address for which a translation is requested is a valid address for translation. If not, the page fault handler indicates that the translation failed and terminates execution of the program requesting the invalid address translation (block 606). Thereafter, Figure 6 The process ends at box 614.

[0044] In response to the page fault handler determining at block 604 that the effective address is a valid address for translation, the page fault handler creates a new physical page in the system memory 108 corresponding to the effective address (block 608). In addition, at block 610, the page fault handler creates a PTE 222 corresponding to the new physical page in the system memory 108 within the page frame table 220 and sets its valid bit 412 (block 610). The protection field 404 remains unset, ensuring that at least one execution of the protection fault handler sets the requested access protection for the memory page. When the new PTE 222 is created in the page frame table 220 and the corresponding physical page in the system memory 108, the page fault handler may remove one or more other PTEs 222 from the page frame table 220 and remove (page out) the corresponding physical page from the system memory 108.

[0045] After establishing the PTE 222 providing the requested translation in the page frame table 220, the page fault handler ends its execution and initiates re-execution of the instruction that caused the page fault (block 612). In the event that the instruction that caused the page fault was the translation load instruction 300, the translation load instruction 300 will then be re-executed, as described above with reference to FIG. Figure 5 However, because the PTE 222 that provides the required translation will exist in the page frame table 220 when the translation load instruction 300 is re-executed, a positive determination will be made at block 512 (or block 504, if implemented), and a page fault will not occur again. However, when the protection bit is not set in the protection field 404, a protection fault will occur on the newly created PTE 222 (the protection fault handler is called at block 520). After block 612, Figure 6 The process ends at box 614.

[0046] See now Figure 7 , shows a high-level logic flow chart of an exemplary method for a protection fault handler to resolve a protection fault according to one embodiment. As described above, for example, Figure 5 In response to detecting a protection fault, block 520 of Figure 7 process.

[0047] Figure 7 The process begins at block 700, where processor 200 of data processing system 100 invokes execution of a protection fault handler. The process proceeds from block 700 to blocks 702-704, which illustrate that the protection fault handler accesses system data structure 224 to determine whether the requested upgrade of access permissions (e.g., from read-only to read-write or setting the E bit 410 to indicate that a memory page contains executable instructions) is legal. If not, the protection fault handler indicates a protection failure and terminates execution of the program requesting the illegal modification of page protection (block 706). Thereafter, Figure 7The process ends at box 714.

[0048] In response to the protection fault handler determining at block 704 that the requested modification of the page protection is legal, the protection fault handler invalidates any entries of the associated effective address in all translation structures 206 throughout the data processing system 100 (block 708). This invalidation may be accomplished, for example, by executing a translation invalidation software sequence specific to the selected architecture. Additionally, at block 710, the protection fault handler updates the protection field 404 of the associated PTE 222 within the page frame table 220 to reflect, for example, the new value requested in the protection field 304 of the translation load instruction 300 (block 710). The protection fault handler thereafter terminates its execution and initiates re-execution of the instruction that caused the protection fault (block 712). In the event that the instruction that caused the protection fault was a translation load instruction 300, the translation load instruction 300 will then be re-executed, as described above with reference to FIG. Figure 5 However, because the PTE 222 providing the requested protection will be present in the page frame table 220 when the translation load instruction 300 is re-executed, a positive determination will be made at block 516 (or block 506, if implemented), and the protection fault will not occur again. After block 712, Figure 7 The process ends at box 714.

[0049] Although the above Figure 6-7 The described embodiment utilizes separate handler routines to resolve page faults and protection faults, but in other embodiments, the page fault handler can also detect and resolve protection faults. In some cases, such an embodiment can reduce the number of times the conversion load instruction 300 is re-executed at the expense of executing a longer and more complex page fault handler.

[0050] See now Figure 8 , depicts a block diagram of an exemplary design flow 800 used, for example, in semiconductor IC logic design, simulation, testing, layout, and manufacturing. The design flow 800 includes a method for processing a design structure or device to generate the above-mentioned and Figure 1-2The process, machine and / or mechanism for producing a logically or other functionally equivalent representation of the design structure and / or device shown in . The design structure processed and / or generated by the design flow 800 can be encoded on a machine-readable transmission or storage medium to include data and / or instructions that, when executed or otherwise processed on a data processing system, generate a logically, structurally, mechanically or other functionally equivalent representation of a hardware component, circuit, device or system. Machines include, but are not limited to, any machine used in an IC design process (such as designing, manufacturing or simulating a circuit, component, device or system). For example, a machine may include: a photolithography machine, a machine and / or device for generating masks (e.g., an electron beam writer), a computer or device for simulating a design structure, any device used in a manufacturing or testing process, or any machine for programming a functionally equivalent representation of a design structure into any medium (e.g., a machine for programming a programmable gate array).

[0051] The design flow 800 may vary depending on the type of representation being designed. For example, the design flow 800 for building an application specific IC (ASIC) may be different from the design flow 800 for designing a standard component, or different from the design flow 800 for instantiating a design into a programmable array (e.g., a Inc. or The design flow 800 in a programmable gate array (PGA) or a field programmable gate array (FPGA) provided by the company.

[0052] Figure 8 A plurality of such design structures are shown, including an input design structure 820 that is preferably processed by the design process 800. The design structure 820 may be a logical analog design structure that is generated and processed by the design process 800 to produce a logically equivalent functional representation of a hardware device. The design structure 820 may also or alternatively include data and / or program instructions that, when processed by the design process 800, generate a functional representation of the physical structure of the hardware device. Whether or not representing functional and / or structural design features, the design structure 820 may be generated using electronic computer-aided design (ECAD), such as that implemented by a core developer / designer. When encoded on a machine-readable data transmission, gate array, or storage medium, the design structure 820 may be accessed and processed by one or more hardware and / or software modules within the design process 800 to simulate or otherwise functionally represent, for example, a device or system. Figure 1-28. As such, design structure 820 may include files or other data structures, including human and / or machine readable source code, compiled structures, and computer executable code structures, which, when processed by a design or simulation data processing system, functionally simulate or otherwise represent a circuit or other level of hardware logic design. Such data structures may include hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​(such as Verilog and VHDL) and / or high-level design languages ​​(such as C or C++).

[0053] The design process 800 preferably employs and combines hardware and / or software modules for synthesizing, transforming, or otherwise processing Figure 1-2 820 to generate a netlist 880 that may contain a design structure (e.g., design structure 820). Netlist 880 may include, for example, a compiled or otherwise processed data structure representing a list of wiring, discrete components, logic gates, control circuits, I / O devices, models, etc. that describe connections to other elements and circuits in the integrated circuit design. Netlist 880 may be synthesized using an iterative process in which netlist 880 is resynthesized one or more times based on design specifications and device parameters. As with other design structure types described herein, netlist 880 may be recorded on a machine-readable storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium, such as a magnetic or optical drive, a programmable gate array, a compact flash, or other flash memory. Additionally or in an alternative, the medium may be a system or cache memory or buffer space.

[0054] The design process 800 may include hardware and software modules for processing various input data structure types including a netlist 880. Such data structure types may reside in, for example, a library element 830 and include a collection of commonly used elements, circuits, and devices for a given manufacturing technology (e.g., different technology nodes, 32nm, 45nm, 90nm, etc.), including models, layouts, and symbolic representations. The data structure types may also include design specifications 840, characterization data 850, verification data 860, design rules 870, and test data files 885, which may include input test patterns, output test results, and other test information. The design process 800 may further include, for example, standard mechanical design processes, such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and compression molding. A person of ordinary skill in the field of mechanical design may understand the extent of possible mechanical design tools and applications used in the design process 800 without departing from the scope of the present invention. The design process 800 may also include modules for performing standard circuit design processes, such as timing analysis, verification, design rule checking, location and routing operations, etc.

[0055] The design process 800 employs and combines logical and physical design tools (e.g., HDL compilers) and simulation model building tools to process the design structure 820 along with some or all of the supporting data structures depicted, along with any additional mechanical design or data (if applicable), to generate a second design structure 890. The design structure 890 resides on a storage medium or programmable gate array in a data format for data exchange of mechanical devices and structures (e.g., information stored in IGES, DXF, Parafolix XT, JT, DRG, or any other suitable format for storing or presenting such mechanical design structures). Similar to the design structure 820, the design structure 890 preferably includes one or more files, data structures, or other computer-coded data or instructions that reside on a transmission or data storage medium and that when processed by the ECAD system generates Figure 1-2 In one embodiment, the design structure 890 may include a logically or otherwise functionally equivalent form of one or more embodiments of the present invention shown in FIG. Figure 1-2 A compiled executable HDL simulation model of the device shown in .

[0056] Design structure 890 may also be in a data format for layout data exchange of integrated circuits and / or a symbolic data format (e.g., information stored in GDS11 (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 890 may include information such as symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, shapes, data for routing through manufacturing lines, and information generated by a manufacturer or other designer / developer as described above and described in detail in the text. Figure 1-2 Design structure 890 may then proceed to stage 895 where, for example, design structure 890: proceeds to tape-out, is released to manufacturing, is released to a mask room, is sent to another design house, is sent back to a customer, etc.

[0057] As described above, in at least one embodiment, a processor core processes a translation load instruction that includes a protection field that specifies a desired access protection specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

[0058] Although various embodiments have been specifically shown and described, those skilled in the art will understand that various changes in form and details may be made therein without departing from the scope of the appended claims, and such alternative implementations are within the scope of the appended claims.

[0059] The flow charts and block diagrams in the accompanying drawings show the architecture, functions and operations of the possible implementations of the system, method and computer program product according to different embodiments of the present invention. To this end, each box in the flow chart or block diagram may represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the box may not occur in the order marked in the figure. For example, depending on the functions involved, the two blocks shown in succession can actually be executed substantially simultaneously, or these blocks can sometimes be executed in reverse order. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0060] Although aspects have been described with respect to a computer system executing program code that directs the functions of the present invention, it should be understood that the present invention may alternatively be implemented as a program product including a computer-readable storage device storing program code that can be processed by a processor of a data processing system to cause the data processing system to perform the described functions. The computer-readable storage device may include volatile or non-volatile memory, optical or magnetic disks, etc., but does not include non-statutory subject matter, such as propagating signals themselves, transmission media themselves, and forms of energy themselves.

[0061] As an example, a program product may include data and / or instructions that, when executed or otherwise processed on a data processing system, generate a logically, structurally, or otherwise functionally equivalent representation (including a simulation model) of a hardware component, circuit, device, or system disclosed herein. Such data and / or instructions may include hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​(such as Verilog and VHDL) and / or higher-level design languages ​​(such as C or C++). In addition, the data and / or instructions may also be in a data format and / or symbolic data format for layout data exchange of integrated circuits (e.g., information stored in GDS11 (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).

Claims

1. A method for processing in a data processing system including a system memory, the method comprising: A processor core that processes a translation load instruction, wherein the translation load instruction includes a protection field that specifies a desired access protection specified in a translation entry for a memory page, and wherein processing the translation load instruction includes: Calculating an effective address within the memory page; determining that a translation entry containing the desired access protection is stored in at least one translation structure of the data processing system; and ending processing of the translation load instruction without further processing the translation load instruction based on determining that a translation entry containing the desired access protection is stored in at least one translation structure of the data processing system; The processor core that processes the translation load instruction executes the translation load instruction to load one or more address translations into a translation structure prior to executing a memory reference instruction that depends on the address translation.

2. The method according to claim 1, wherein: The at least one switch structure comprises a switch structure in the processor core; The conversion load instruction includes a load field; The method further includes installing, by the processor core, the translation entry for the effective address in the translation structure in the processor core based on the load field being set.

3. The method according to claim 2, wherein: The translation structure includes a translation lookaside buffer.

4. The method according to any one of claims 1 to 3, wherein: The at least one translation structure includes a page frame table in the system memory.

5. The method according to any one of claims 1 to 3, wherein: The protection field in the conversion load instruction is a first protection field; The translation entry includes a second protection field; and The method further includes invoking, by the processor core, a protection fault handler based on a mismatch of access protections specified in the first protection field and the second protection field.

6. The method according to claim 5, further comprising: determining whether a modification of the access protection requested by the translation load instruction is legal; as well as In response to determining that the modification of the access protection requested by the translation load instruction is legal, updating the second protection field in the translation entry.

7. The method according to any one of claims 1 to 3, wherein: The data processing system includes a nested memory management unit coupled to a system architecture of the data processing system; and The processing includes the processor core processing the converted load instruction based on receiving an interrupt initiated by the nested memory management unit.

8. A processing unit for use in a data processing system including a system memory, the processing unit comprising: Processor core, including: a memory management unit that converts effective addresses to real addresses; and an execution unit, which executes instructions; The processor core is configured to execute: processing a translation load instruction, wherein the translation load instruction includes a protection field that specifies a desired access protection specified in a translation entry for a memory page, and wherein processing the translation load instruction comprises: Calculating an effective address within the memory page; determining that a translation entry containing the desired access protection is stored in at least one translation structure of the data processing system; and ending processing of the translation load instruction without further processing the translation load instruction based on determining that a translation entry containing the desired access protection is stored in at least one translation structure of the data processing system; The processor core that processes the translation load instruction executes the translation load instruction to load one or more address translations into a translation structure prior to executing a memory reference instruction that depends on the address translation.

9. The processing unit according to claim 8, wherein: The at least one switch structure comprises a switch structure in the processor core; The conversion load instruction includes a load field; The processor core is configured to install the translation entry for the effective address in the translation structure in the processor core based on the load field being set.

10. The processing unit according to claim 9, wherein: The translation structure includes a translation lookaside buffer.

11. The processing unit according to any one of claims 8 to 10, wherein: The at least one translation structure includes a page frame table in the system memory.

12. The processing unit according to any one of claims 8 to 10, wherein: The protection field in the conversion load instruction is a first protection field; The translation entry includes a second protection field; and The processor core invokes a protection fault handler based on a mismatch of access protections specified in the first protection field and the second protection field.

13. The processing unit according to claim 12, wherein: The processor core is further configured to perform: determining whether a modification of the access protection requested by the translation load instruction is legal; and In response to determining that the modification of the access protection requested by the translation load instruction is legal, updating the second protection field in the translation entry.

14. A processing unit according to any one of claims 8 to 10, wherein: The data processing system includes a nested memory management unit coupled to a system structure of the data processing system; as well as The processor core processes the translation load instruction based on receiving an interrupt initiated by the nested memory management unit via the system structure. 15 . A data processing system, comprising a plurality of processing units according to claim 8 and a system configuration coupling the plurality of processing units.

16. A computer program product for processing in a data processing system including a system memory, the computer program product comprising: A computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform the method according to any one of claims 1 to 7.

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