semiconductor modules

Abstract

The semiconductor module (1) of the present invention comprises: two semiconductor elements (10, 20) having a substantially quadrilateral shape when viewed from above, stacked in the vertical direction with at least a portion overlapping; conductive components (121, 123, 125) stacked on the upper surface side or the lower surface side of the two semiconductor elements and electrically connected to at least one of the two semiconductor elements; and a resin mold (130) that integrally seals the two semiconductor elements and the conductive components. The lower semiconductor element (20) of the two semiconductor elements is arranged so that when the semiconductor module is viewed from above without the resin mold, the positions of the two end portions (21 to 24) of at least two substantially orthogonal sides of the substantially quadrilateral can be observed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on Japanese Patent Application No. 2019-182499 filed on October 2, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor module comprising a plurality of semiconductor elements. Background Art

[0004] Patent Document 1 describes a semiconductor module in which two semiconductor elements, each roughly rectangular in shape when viewed from above, are stacked vertically and integrally housed within a resin mold. The two semiconductor elements have their long sides of the roughly rectangular shape oriented in the same direction, and are positioned offset from each other along the long sides.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-130894

[0006] In Patent Document 1, when viewed from above, more than half of the upper surface of the lower semiconductor element is covered and obscured by the upper semiconductor element. Therefore, after stacking the two semiconductor elements, it is difficult to observe the position of the lower semiconductor element, making it impossible to detect positional misalignment. Summary of the Invention

[0007] In view of the foregoing, an object of the present disclosure is to provide a technology capable of easily detecting positional displacement of a semiconductor element in a semiconductor module including two stacked semiconductor elements.

[0008] The present disclosure provides a semiconductor module comprising: two semiconductor elements having a substantially quadrilateral shape when viewed from above, stacked in a vertical direction with at least a portion of the elements overlapping; a conductive member stacked on the upper or lower surface of the two semiconductor elements and electrically connected to the semiconductor elements; and a resin mold that integrally seals the two semiconductor elements and the conductive member. In this semiconductor module, the lower semiconductor element of the two semiconductor elements is positioned so that, when viewing the semiconductor module from above without the resin mold present, the positions of the ends of at least two substantially orthogonal sides of the substantially quadrilateral are observable.

[0009] According to the present disclosure, two semiconductor elements having a substantially quadrilateral shape when viewed from above are arranged and stacked so that, when the semiconductor module is viewed from above without the presence of a resin mold, the positions of the two end portions of the substantially orthogonal sides of the substantially quadrilateral of the lower semiconductor element arranged below can be observed. By observing the positions of these two end portions, the position of the lower semiconductor element can be detected, thereby easily detecting positional deviation between the two stacked semiconductor elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above-mentioned object and other objects, features and advantages of the present disclosure will become more apparent through the following detailed description with reference to the accompanying drawings.

[0011] Figure 1 is a plan view showing a semiconductor module according to the first embodiment.

[0012] Figure 2 It is shown in Figure 1 The semiconductor module shown is a perspective view of a state where the resin mold is removed.

[0013] Figure 3 It is shown in Figure 1 The semiconductor module shown is a top view showing a state where the resin mold is removed.

[0014] Figure 4 yes Figure 3 IV-IV line cross-sectional view,

[0015] Figure 5 It shows Figure 1 A cross-sectional view of the element structure of a semiconductor element in the semiconductor module shown,

[0016] Figure 6 is a schematic diagram of an electric power steering system to which the semiconductor module according to the first embodiment is applied.

[0017] Figure 7 It shows Figure 6 The diagram of the driving circuit of the electric power steering system is shown in FIG.

[0018] Figure 8 This is a diagram explaining position deviation detection.

[0019] Figure 9 This is a diagram explaining position deviation detection.

[0020] Figure 10 This is a diagram explaining position deviation detection.

[0021] Figure 11 is a plan view showing a semiconductor module according to a second embodiment.

[0022] Figure 12 It is shown in Figure 11 The semiconductor module shown is a perspective view of a state where the resin mold is removed.

[0023] Figure 13 It is shown in Figure 11 The semiconductor module shown is a top view showing a state where the resin mold is removed.

[0024] Figure 14 yes Figure 13 The XIV-XIV line cross-sectional view,

[0025] Figure 15 It is a plan view showing a semiconductor module according to a fourth embodiment. DETAILED DESCRIPTION

[0026] (First embodiment)

[0027] like Figures 1 to 4 As shown, the semiconductor module 1 according to the first embodiment includes an upper semiconductor element 10 and a lower semiconductor element 20, a resin mold 130 that integrally seals the upper semiconductor element 10 and the lower semiconductor element 20, and external terminals 101 to 104 and 111 to 114. Figures 1 to 4 The x-axis and y-axis directions shown are lateral directions of the semiconductor module 1, and the xy plane direction is the plane direction of the semiconductor module 1. The z-axis direction is the up-down direction orthogonal to the plane direction.

[0028] like Figure 1 As shown, the semiconductor module 1 has eight external terminals 101 to 104 and 111 to 114 protruding in the y-axis direction from a resin mold 130, which has a generally rectangular shape when viewed from above. The external terminals 101 to 104 are arranged in this order from the positive direction of the x-axis toward the negative direction in the positive direction of the y-axis (first direction), which is the lateral side of the resin mold 130, with the y-axis direction serving as the longitudinal direction. The external terminals 111 to 114 are arranged in this order from the positive direction of the x-axis toward the negative direction in the negative direction of the y-axis, which is a second direction sandwiching the resin mold 130 and opposite to the first direction, with the y-axis direction serving as the longitudinal direction.

[0029] like Figures 2-4As shown, an upper semiconductor element 10 and a lower semiconductor element 20 are integrally sealed within a resin mold 130, stacked in the z-axis direction. The upper and lower semiconductor elements 10 and 20 have identical structures, shapes, and sizes, and are generally rectangular when viewed from above. When the upper and lower semiconductor elements 10 and 20 are stacked vertically in the same orientation without any offset in the planar direction, corners 11 and 21, corners 12 and 22, corners 13 and 23, and corners 14 and 24 are approximately aligned in the planar direction.

[0030] The upper semiconductor element 10 and the lower semiconductor element 20 have Figure 5 The vertical insulated gate semiconductor device having the device structure shown is, more specifically, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor: MOSFET).

[0031] The upper semiconductor element 10 and the lower semiconductor element 20 include a semiconductor substrate 60, a source electrode 71, and a drain electrode 72. The source electrode 71 is formed in contact with the upper surface 60u of the semiconductor substrate 60. The drain electrode 72 is formed in contact with the lower surface 60b of the semiconductor substrate 60. The upper surface 60u corresponds to the first surface, and the lower surface 60b corresponds to the second surface. In the semiconductor substrate 60, an n+ region 61, an n- region 62, and a p+ region 63 are stacked in this order from the lower surface 60b. An n+ region 64 is formed on a portion of the upper surface of the p+ region 63. A trench 73 is formed from the upper surface 60u of the semiconductor substrate 60, penetrating the n+ region 64 and the p+ region 63 and reaching the upper surface of the n- region 62. A gate insulating film 74 is formed on the inner wall of the trench 73. A gate electrode 75 is filled in the trench 73, insulated from the semiconductor substrate 60 by the gate insulating film 74. The upper surface of the gate electrode 75 is covered with an insulating film 76, and the gate electrode 75 and the source electrode 71 are insulated by the insulating film 76. The material of the semiconductor substrate 60 is not particularly limited, but examples thereof include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0032] When a positive voltage is applied to the gate electrodes 75 of the upper semiconductor element 10 and the lower semiconductor element 20, an n-type channel is formed in the p+ region 63 along the gate insulating film 74, and n-type carriers move from the source electrode 71 side to the drain electrode 72 side in the semiconductor substrate 60. As a result, current flows from the drain electrode 72 side to the source electrode 71 side. In other words, by controlling the gate voltage applied to the gate electrodes 75 in the upper semiconductor element 10 and the lower semiconductor element 20, the on / off control of the switching elements involved in the upper semiconductor element 10 and the lower semiconductor element 20 can be performed. The source electrode 71 corresponds to the first electrode, and the source terminal electrically connected to the source electrode 71 among the external terminals corresponds to the first terminal. In addition, the drain electrode 72 corresponds to the second electrode, and the drain terminal electrically connected to the drain electrode 72 among the external terminals corresponds to the second terminal.

[0033] The upper semiconductor element 10 and the lower semiconductor element 20 are stacked in such a manner that the source electrode 71 is at the top (positive direction of the z-axis) and the drain electrode is at the bottom (negative direction of the z-axis). Figures 2-4 As shown, the upper semiconductor element 10 is arranged with its longitudinal direction in the y-axis direction when viewed from above, and the lower semiconductor element 20 is arranged with its longitudinal direction in the x-axis direction when viewed from above. That is, when viewed from above, the upper semiconductor element 10 is arranged in an orientation rotated approximately 90° counterclockwise about the vertical direction relative to the lower semiconductor element 20.

[0034] like Figures 2-4 As shown, the semiconductor module 1 includes a first conductive member 121, a second conductive member 123, an upper semiconductor element 10, a third conductive member 124, a fourth conductive member 125, a lower semiconductor element 20, and an electrode pad 122, stacked in this order from top to bottom. The semiconductor module 1 also includes conductive bonding pads 105, 106, 115, and 116 located at the same positions in the vertical direction as the electrode pad 122. The bonding pad 105 is integrally formed with the external terminal 101. The bonding pad 106 is integrally formed with the external terminals 102 to 104. The bonding pad 115 is integrally formed with the external terminal 111. The bonding pad 116 is integrally formed with the external terminals 112 to 114. Furthermore, the external terminals 101 to 104, 111 to 114, the bonding pads 105, 106, 115, and 116, and the electrode pad 122 are formed on a lead frame. The semiconductor module 1 also includes conductive gate connection members 107 and 117.

[0035] The second conductive component 123 corresponds to a source electrode formed on the upper surface side of the upper semiconductor element 10. When viewed from above, the second conductive component 123 has a rectangular shape with one of the four corners cut away, and the gate pad of the upper semiconductor element 10 is provided in this cut-away portion. The upper surface of the second conductive component 123 is bonded to the lower surface of the first conductive component 121 via solder. The gate pad of the upper semiconductor element 10 and the gate pad of the lower semiconductor element 20 are provided at positions that are substantially the same when viewed from above. More specifically, the gate pad of the upper semiconductor element 10 is provided near corner 14, and the gate pad of the lower semiconductor element 20 is provided near corner 24.

[0036] The first conductive member 121 has a generally L-shaped top view and extends in the positive direction of the y-axis to a position above the bonding plate 106. The first conductive member 121 has a connecting portion 121a extending downward from the bonding plate 106 to a position above the bonding plate 106. The lower surface of the connecting portion 121a is bonded to the upper surface of the bonding plate 106 via solder. This electrically connects the source electrode of the upper semiconductor element 10 to the external terminals 102 to 104.

[0037] The lower upper surface of the upper semiconductor element 10 serves as a drain electrode and is soldered to the upper surface of the third conductive member 124. The fourth conductive member 125 corresponds to a source electrode formed on the upper surface of the lower semiconductor element 20. The fourth conductive member 125 is soldered to the third conductive member 124.

[0038] The third conductive component 124 has a roughly L-shaped shape when viewed from above, and extends in the negative direction of the y-axis to a position above the bonding plate 116. The third conductive component 124 has a connection portion 124a extending downward to a position reaching the bonding plate 116 at a position above the bonding plate 116. The lower surface of the connection portion 124a is bonded to the upper surface of the bonding plate 116 via solder. As a result, the drain electrode of the upper semiconductor element 10 and the source electrode of the lower semiconductor element 20 are electrically connected to the external terminals 112 to 114. The first conductive component 121 and the third conductive component 124 are so-called clips, but in addition to clips, wire bonding, wire ribbons, etc. can also be used.

[0039] The second conductive member 123 and the fourth conductive member 125 serve as the source electrodes for the upper semiconductor element 10 and the lower semiconductor element 20, respectively, and have identical shapes and sizes. Similar to the positional relationship between the upper and lower semiconductor elements 10 and 20, the second conductive member 123 is positioned approximately 90° counterclockwise relative to the fourth conductive member 125, with the vertical axis as the axis. This arrangement ensures that the gate pad of the upper semiconductor element 10 is positioned at an angle between the positive x-axis and the positive y-axis, while the gate pad of the lower semiconductor element 20 is positioned at an angle between the positive x-axis and the negative y-axis.

[0040] The lower surface side of the lower semiconductor element 20 is a drain electrode, which is bonded to the electrode pad 122 via solder. Figure 1 As shown in (b), the electrode pad 122 is exposed on the lower surface of the resin mold 130 and is electrically connected to the drain electrode of the lower semiconductor element 20. The drain electrode of the lower semiconductor element 20 is not electrically connected to any of the external terminals 101 to 104 and 111 to 114.

[0041] The first conductive member 121, the second conductive member 123, the third conductive member 124, and the fourth conductive member 125 are thicker than the electrode pads 122. Each conductive member is thicker and heavier, thereby suppressing positional deviation of the upper semiconductor element 10 and the lower semiconductor element 20, which are stacked and in contact with any of the conductive members. Specifically, by making each conductive member thicker than the electrode pads 122, positional deviation of various structures within the resin mold 130 of the semiconductor module 1 can be suppressed.

[0042] The gate connection member 107 includes a columnar portion extending vertically from the upper surface of the bonding plate 105, and a beam-shaped portion extending from the columnar portion in an oblique direction corresponding to the negative x- and y-axis directions to the gate pad on the upper surface of the upper semiconductor element 10. The lower surface of the columnar portion is bonded to the upper surface of the bonding plate 105 via solder. The beam-shaped portion is electrically connected to the gate electrode of the upper semiconductor element 10 via the gate pad. This electrically connects the gate electrode of the upper semiconductor element 10 to the external terminal 101.

[0043] The gate connection component 117 includes a columnar portion extending in the vertical direction on the upper surface of the bonding plate 115, and a beam-shaped portion extending from the columnar portion in the positive direction of the y-axis to the gate pad on the upper surface of the lower semiconductor element 20. The lower surface of the columnar portion is bonded to the upper surface of the bonding plate 115 via solder. The beam-shaped portion is electrically connected to the gate electrode of the lower semiconductor element 20 via the gate pad. As a result, the gate electrode of the lower semiconductor element 20 is electrically connected to the external terminal 111. The gate connection components 107 and 117 are so-called gate clips, but in addition to clips, wire bonding, wire straps, etc. can also be used.

[0044] External terminal 101 is a first gate terminal G1 electrically connected to the gate electrode of the upper semiconductor element 10. External terminal 111 is a second gate terminal G2 electrically connected to the gate electrode 75 of the lower semiconductor element 20. External terminals 102 to 104 are a first source terminal S1 electrically connected to the source electrode of the upper semiconductor element 10. External terminals 112 to 114 are a second source terminal S2 electrically connected to the source electrode of the lower semiconductor element 20 and a first drain terminal D1 electrically connected to the drain electrode of the upper semiconductor element 10.

[0045] The semiconductor module according to this embodiment can be applied to Figure 6 The driving circuit of the electric power steering system (EPS) 80 of the vehicle shown in the figure. EPS80 includes a steering wheel 90, a steering shaft 91, a pinion 92, a rack shaft 93, and an EPS device 81 constituting a handle. The steering shaft 91 is connected to the steering wheel 90. A pinion 92 is provided at the front end of the steering shaft 91. The pinion 92 is engaged with the rack shaft 93. The wheels 95 are rotatably connected to both ends of the rack shaft 93 via a tie rod or the like. If the driver rotates the steering wheel 90, the steering shaft 91 rotates. The rotational motion of the steering shaft 91 is converted into the linear motion of the rack shaft 93 by the pinion 92, and the wheels 95 are turned to a steering angle corresponding to the displacement of the rack shaft 93.

[0046] The EPS system 81 includes a torque sensor 94, a speed reducer 96, a rotary motor 82, and an excitation circuit unit 83. The torque sensor 94 is mounted on the steering shaft 91 and detects the steering torque Trq, or the output torque of the steering shaft 91. The rotary motor 82 generates an assist torque corresponding to the detected steering torque Trq and the steering direction of the steering wheel 90. The excitation circuit unit 83 controls the drive of the rotary motor 82. The speed reducer 96 decelerates the rotation of the rotary shaft of the rotor of the rotary motor 82 and transmits the assist torque to the steering shaft 91.

[0047] like Figure 2 As shown, a permanent magnet excitation type or a winding excitation type rotating electric machine can be used as the rotating electric machine 82. The stator of the rotating electric machine 82 includes a first winding group M1 and a second winding group M2. The first winding group M1 includes a first U-phase winding U1, a first V-phase winding V1, and a first W-phase winding W1 connected in a star configuration. The second winding group M2 includes a second U-phase winding U2, a second V-phase winding V2, and a second W-phase winding W2 connected in a star configuration. The first ends of the first U-, V-, and W-phase windings U1, V1, and W1 are connected at a neutral point. The first U-, V-, and W-phase windings U1, V1, and W1 are offset by 120 degrees in electrical angle θe. The first ends of the second U-, V-, and W-phase windings U2, V2, and W2 are connected at a neutral point. The second U-, V-, and W-phase windings U2, V2, and W2 are offset by 120 degrees in electrical angle θe.

[0048] The exciting circuit unit 83 includes a first inverter INV1 and a second inverter INV2 as power converters, and a first relay RL1 and a second relay RL2 as power supply relays.

[0049] In the first inverter INV1, the second end of the first U-phase winding U1 is connected to the connection point between the upper arm switch SU1p and the lower arm switch SU1n of the first U-phase. The second end of the first V-phase winding V1 is connected to the connection point between the upper arm switch SV1p and the lower arm switch SV1n of the first V-phase. The second end of the first W-phase winding W1 is connected to the connection point between the upper arm switch SW1p and the lower arm switch SW1n of the first W-phase. In the second inverter INV2, the second end of the second U-phase winding U2 is connected to the connection point between the upper arm switch SU2p and the lower arm switch SU2n of the second U-phase. The second end of the second V-phase winding V2 is connected to the connection point between the upper arm switch SV2p and the lower arm switch SV2n of the second V-phase. The second end of the second W-phase winding W2 is connected to the connection point between the upper arm switch SW2p and the lower arm switch SW2n of the second W-phase.

[0050] The high-potential-side terminals of the upper arm switches SU1p, SV1p, and SW1p of the first U, V, and W phases are connected to the positive terminal of the battery 97, serving as a DC power supply, via the first relay RL1. The low-potential-side terminals of the lower arm switches SU1n, SV1n, and SW1n of the first U, V, and W phases are grounded via resistors RU1, RV1, and RW1. The high-potential-side terminals of the upper arm switches SU2p, SV2p, and SW2p of the second U, V, and W phases are connected to the positive terminal of the battery 97 via the second relay RL2. The low-potential-side terminals of the lower arm switches SU2n, SV2n, and SW2n of the second U, V, and W phases are grounded via resistors RU2, RV2, and RW2. The negative terminal of the battery 97 is grounded.

[0051] As each switch SU1p to SW2n, a MOSFET such as that exemplified in the upper semiconductor element 10 and the lower semiconductor element 20 can be used. In each arm, two switches SU1p and SU1n, SV1p and SV1n, SW1p and SW1n, SU2p and SU2n, SV2p and SV2n, and SW2p and SW2n connected in series are connected in series by connecting the source electrode of the former MOSFET to the drain electrode of the latter MOSFET.

[0052] The semiconductor module 1 can be used as a semiconductor module SU1, SV1, SW1, SU2, SV2, SW2 integrating two switches SU1p and SU1n, SV1p and SV1n, SW1p and SW1n, SU2p and SU2n, SV2p and SV2n, and SW2p and SW2n connected in series in each arm.

[0053] When semiconductor module 1 is used as semiconductor modules SU1-SW2, upper arm switches SU1p, SV1p, SW1p, SU2p, SV2p, and SW2p correspond to lower semiconductor element 20, and lower arm switches SU1n, SV1n, SW1n, SU2n, SV2n, and SW2n correspond to upper semiconductor element 10. By connecting electrode pads 122 of semiconductor module 1 to power relays RL1 and RL2 and external terminals 102-104 to resistors RU1-RW2, semiconductor module 1 can be applied to first inverter INV1 and second inverter INV2 to form an inverter circuit.

[0054] MOSFETs, such as those exemplified in the upper semiconductor element 10 and the lower semiconductor element 20, can be used as the switches SP1 and SC1 that constitute power relay RL1, and the switches SP2 and SC2 that constitute power relay RL2. Switches SP1 and SP2 serve as power relay switches, while switches SC1 and SC2 serve as reverse connection protection relays. The two switches SP1 and SC1, and SP2 and SC2 connected in series in each arm connect their MOSFET source electrodes to each other.

[0055] Furthermore, when MOSFETs such as the upper semiconductor element 10 and the lower semiconductor element 20 are used as the switches SU1p to SW2n, SP1, SC1, SP2, and SC2, the body diodes can be used as freewheeling diodes. Figure 7 Although the freewheeling diodes connected in antiparallel to the switches SU1p to SW2n, SP1, SC1, SP2, and SC2 are not described, freewheeling diodes may be connected to the switches SU1p to SW2n, SP1, SC1, SP2, and SC2.

[0056] The excitation circuit unit 83 detects the current flowing through the resistors RU1, RV1, and RW1 and outputs it as first U-, V-, and W-phase currents Iur1, Ivr1, and Iwr1. It also detects the current flowing through RU2, RV2, and RW2 and outputs it as second U-, V-, and W-phase currents Iur2, Ivr2, and Iwr2.

[0057] The excitation circuit unit 83 includes an ECU mainly composed of a microcomputer. The ECU operates the switches of the first inverter INV1 and the second inverter INV2 to control the torque of the rotating motor 82 to the torque command value Tr*. For example, the torque command value Tr* is set based on the steering torque Trq detected by the torque sensor 94. The excitation circuit unit 83 calculates the electrical angle θe of the rotating motor 82 based on the output signal of the angle sensor through the ECU. In addition, as an example of an angle sensor, there can be exemplified an angle sensor including a magnet as a magnetic generating unit provided on the rotor side of the rotating motor 82 and a magnetic detection element provided near the magnet. The functions provided by the above-mentioned ECU can be provided, for example, by software recorded in a physical memory device and a computer or hardware that executes the software, or a combination thereof.

[0058] As described above, the semiconductor module 1 can be applied to the EPS 80 , and can be applied as the semiconductor modules SU1 to SW2 including two switches connected in series to the excitation circuit unit 83 corresponding to the drive circuit of the EPS 80 .

[0059] Specifically, the semiconductor module 1 can be applied to inverter circuits shown as a first inverter INV1 and a second inverter INV2 , and the upper semiconductor element 10 and the lower semiconductor element 20 are applied to the inverter circuits as switching elements connected in series.

[0060] Furthermore, a semiconductor module in which the upper semiconductor element 10 is turned upside down relative to the semiconductor module 1 can be applied to Figure 7 The power supply relays RL1 and RL2 shown in the figure. In this case, for example, the first conductive member 121 extends to the bonding plate 116 side instead of the bonding plate 106 and is bonded to the bonding plate 106, and the third conductive member 124 extends to the bonding plate 106 side instead of the bonding plate 116 and is bonded to the bonding plate 116. With this replacement, the external terminals 102-104 serve as the first source terminal S1 and the second source terminal S2. Furthermore, the external terminals 112-114 serve as the first drain terminal D1.

[0061] In the semiconductor module 1 , the lower semiconductor element 20 is arranged so that the positions of both ends of two substantially orthogonal sides of the substantially quadrilateral on the upper surface of the lower semiconductor element 20 can be observed when the semiconductor module 1 is viewed from above without the resin mold 130 .

[0062] like Figure 3As shown, the various structures included in the resin mold 130 of the semiconductor module 1 are arranged so that the four corners 21 to 24 of the substantially rectangular upper surface of the lower semiconductor element 20 are visible when viewed from above. Therefore, for example, the long side connecting corners 21 and 23, and the short side connecting corners 21 and 22, can be selected as two substantially perpendicular sides of the substantially quadrilateral. Alternatively, for example, the long side connecting corners 22 and 24, and the short side connecting corners 23 and 24, can be selected as two substantially perpendicular sides of the substantially quadrilateral. The substantially perpendicular sides of the substantially quadrilateral can be selected from the long side and the short side of the substantially rectangular upper surface of the lower semiconductor element 20.

[0063] The two ends of the two substantially orthogonal sides of the substantially rectangular shape are corners 21 to 24 and their surrounding areas on each side of the substantially rectangular shape. For example, on the long side connecting corners 21 and 23, the two ends are defined by a length L1 defined along the positive x-axis from corner 21 and a length L2 defined along the negative x-axis from corner 23. If the length of the long side connecting corners 21 and 23 is L0, the defined lengths L1 and L2 are preferably less than L0 / 2, more preferably less than or equal to approximately L0 / 3, and even more preferably less than or equal to approximately L0 / 4.

[0064] By observing the positions of the two ends of the two substantially orthogonal sides of the substantially quadrilateral on the upper surface of the lower semiconductor element 20, the positional deviation of the lower semiconductor element 20 can be detected. Figures 2-4 After the resin mold 130 is formed as shown, the resin mold 130 is formed. Figure 3 As shown, by observing the various structures of the semiconductor module 1 , positional deviation of the lower semiconductor element 20 and the like can be detected.

[0065] Regarding the method of detecting the positional deviation of the lower semiconductor element 20, an example is given and described in detail. Figures 8-10 As shown, by calculating the positions of both ends of the lower semiconductor element 20 relative to the reference lines B1 and B2 in the xyz coordinate system, it is possible to detect positional deviation of the lower semiconductor element 20. The reference lines B1 and B2 are straight lines parallel to the long side and short side, respectively, of a reference position B representing the position of the lower semiconductor element 20 when there is no positional deviation.

[0066] First, if Figure 8As shown, the positional deviation in the plane direction of the lower semiconductor element 20 can be detected by calculating the positions of the three end portions of the lower semiconductor element 20 relative to the reference lines B1 and B2 ( Figure 8 Position offset in the xy plane shown).

[0067] The positions of the two end portions on the reference lines B1 and B2 can be expressed using the coordinates of any point on the reference lines included in the two end portions. Figure 8 In the example, the coordinates (x0, y0, z0) and (x1, y1, z1) are the positions of the two ends of baseline B1. Furthermore, the coordinates (x2, y2, z2) and (x3, y3, z3) are the positions of the two ends of baseline B2. The coordinates (x0, y0, z0) and (x1, y1, z1) are the coordinates of the two ends of baseline B1, while the coordinates (x2, y2, z2) and (x3, y3, z3) are the coordinates of baseline B2.

[0068] The positions of both ends of each side of the lower semiconductor element 20 can be expressed using the coordinates of any point on the side of the rectangle included in each of the two ends. Figure 8 In the example, the coordinates (x5, y5, z5) and (x7, y7, z7) are used as the positions of the two ends of the long side 20L. The coordinates (x4, y4, z4), (x5, y5, z5), and (x1, y1, z1) are used as the positions of the two ends of the short side 20S. The coordinates (x4, y4, z4), (x5, y5, z5), and (x7, y7, z7) are the coordinates of the two ends of the long side 20L or the two ends of the short side 20S, and correspond to the coordinates of the corners 22, 21, and 23 of the lower semiconductor element 20.

[0069] Furthermore, by using an optical position detection device, the position of the upper surface of the lower semiconductor element 20 can be detected three-dimensionally. While not limited to optical position detection sensors, for example, a transmissive laser displacement sensor, which is a non-contact laser displacement sensor, can be suitably used. Transmissive laser sensors can detect the edge position of an object with greater accuracy, and thus can accurately detect the position coordinates of the long side 20L and short side 20S, which constitute the edge portion of the upper surface of the lower semiconductor element 20.

[0070] The x-direction positional offset dx1 of the lower semiconductor element 20 relative to the reference line B1 is expressed as the following equation (1), and can be represented by the difference in x-coordinates between the midpoint of the reference line B1 and the midpoint of the short side 20S. The y-direction positional offset dy1 of the lower semiconductor element 20 relative to the reference line B2 is expressed as the following equation (2), and can be represented by the difference in y-coordinates between the midpoint of the reference line B2 and the midpoint of the long side 20L.

[0071] dx1=(x4+x5) / 2-(x1+x0) / 2…(1)

[0072] dy1=(y7+y5) / 2-(y3+y2) / 2...(2)

[0073] The reference lines B1 and B2 are parallel to the y-axis and the x-axis, respectively. When the position of the lower semiconductor element 20 is offset counterclockwise by an offset angle α with respect to the reference position B around the coordinates (x5, y5, z5), the offset angle α is expressed by the following formula (3).

[0074] α=Atan{(y7-y5) / (x7-x5)}…(3)

[0075] Next, if Figure 9 As shown, as the positional offset of the lower semiconductor element 20 in the vertical direction, the positional offset in the yz plane is detected. The positional offset dy2 of the lower semiconductor element 20 in the y direction relative to the reference line B1 is expressed as the following formula (4), and can be expressed by the difference in y coordinates between the midpoint of the reference line B1 and the midpoint of the short side 20S. The positional offset dz1 of the lower semiconductor element 20 in the z direction relative to the reference line B1 is expressed as the following formula (5), and can be expressed by the difference in z coordinates between the midpoint of the reference line B1 and the midpoint of the short side 20S. When the position of the lower semiconductor element 20 is offset by an offset angle β counterclockwise with respect to the coordinates (x4, y4, z4) as the center relative to the reference position B, the offset angle β is expressed as the following formula (6).

[0076] dy2=(y5+y4) / 2-(y1+y0) / 2...(4)

[0077] dz1=(z5+z4) / 2-(z1+z0) / 2...(5)

[0078] β=Atan{(z5-z4) / (y5-y4)}…(6)

[0079] Next, if Figure 10 As shown, as the positional offset of the lower semiconductor element 20 in the vertical direction, the positional offset in the zx plane is detected. The positional offset dx2 of the lower semiconductor element 20 in the x direction relative to the reference line B2 is expressed as the following formula (7), and can be expressed by the difference in x coordinates between the midpoint of the reference line B2 and the midpoint of the long side 20L. The positional offset dz2 of the lower semiconductor element 20 in the z direction relative to the reference line B2 is expressed as the following formula (8), and can be expressed by the difference in z coordinates between the midpoint of the reference line B2 and the midpoint of the long side 20L. When the position of the lower semiconductor element 20 is offset by an offset angle γ counterclockwise with respect to the coordinates (x5, y5, z5) as the center relative to the reference position B, the offset angle γ is expressed by the following formula (6).

[0080] dx2=(x7+x5) / 2-(x3+x2) / 2…(7)

[0081] dz2=(z7+z5) / 2-(z3+z2) / 2…(8)

[0082] γ=Atan{(z7-z5) / (x7-x5)}…(9)

[0083] As described above, the various components of semiconductor module 1 are configured so that the positions of the ends of long side 20L and short side 20S can be observed from above when viewing semiconductor module 1 without resin mold 130. Therefore, before forming resin mold 130, the positions of the ends of long side 20L and short side 20S can be three-dimensionally detected using optical mechanisms or other means. Furthermore, by calculating the extent to which the lower semiconductor element 20 has shifted in the planar direction or in the vertical direction relative to a reference position, it is possible to detect positional deviation of the lower semiconductor element 20.

[0084] Furthermore, in the semiconductor module 1, as Figure 3 As shown, the various components of semiconductor module 1 contained within resin mold 130 are arranged so that, when viewed from above, the four corners 11 to 14 of the substantially rectangular top surface of upper semiconductor element 10 and the four sides of the substantially rectangular top surface near these corners 11 to 14 are observable. Specifically, upper semiconductor element 10 is arranged so that, when viewing semiconductor module 1 from above without resin mold 130 present, the positions of the two ends of two substantially orthogonal sides of the substantially rectangular top surface of upper semiconductor element 10 are observable. Therefore, positional deviation of upper semiconductor element 10, in addition to lower semiconductor element 20, can also be detected.

[0085] (Second embodiment)

[0086] like Figures 11-14 As shown, in the semiconductor module 2 according to the second embodiment, similarly to the semiconductor module 1 , the upper semiconductor element 10 is arranged in a direction rotated approximately 90° counterclockwise about the vertical direction relative to the lower semiconductor element 20 in a plan view.

[0087] The semiconductor module 2 includes a first conductive member 221, a second conductive member 223, an upper semiconductor element 10, a third conductive member 224, a fourth conductive member 225, a lower semiconductor element 20, and an electrode pad 222, stacked in this order from top to bottom. The semiconductor module 2 also includes external terminals 201 to 204, 211 to 214, and conductive bonding pads 205, 206, 215, and 216, located at the same positions in the vertical direction as the electrode pad 222. The semiconductor module 2 also includes gate connecting members 207 and 217. The gate pad of the upper semiconductor element 10 is located near corner 13, and the gate pad of the lower semiconductor element 20 is located near corner 24.

[0088] In the semiconductor module 2, the external terminals 201 to 204 are arranged in this order from the negative direction to the positive direction of the x-axis, opposite to the external terminals 101 to 104. Accordingly, the bonding plate 205 is arranged on the negative side of the x-axis, and the bonding plate 206 is arranged on the positive side of the x-axis.

[0089] Corresponding to the configuration of the bonding plate 205, the second conductive component 223, when viewed from above, has a shape obtained by cutting out the corners of the rectangle closest to the bonding plate 205, which are in the negative x-axis direction and the positive y-axis direction. The gate pad of the upper semiconductor element 10 is provided in this cutout portion. The fourth conductive component 225, when viewed from above, has a shape obtained by cutting out the corners of the rectangle closest to the bonding plate 215, which are in the positive x-axis direction and the negative y-axis direction. The gate pad of the lower semiconductor element 20 is provided in this cutout portion. That is, in the second embodiment, while the upper semiconductor element 10 and the lower semiconductor element 20 have the same shape and size, they differ from the first embodiment in that the gate pads are provided at different locations.

[0090] The gate connection member 207 is arranged on the negative x-axis side opposite to the gate connection member 107. The gate connection member 207 includes a columnar portion extending vertically on the upper surface of the bonding plate 205, and a beam portion extending from the columnar portion in the negative y-axis direction to the upper surface of the semiconductor element 10 above.

[0091] External terminal 201 is a first gate terminal G1 electrically connected to the gate electrode of the upper semiconductor element 10. External terminal 211 is a second gate terminal G2 electrically connected to the gate electrode of the lower semiconductor element 20. External terminals 202 to 204 are a first source terminal S1 electrically connected to the source electrode of the upper semiconductor element 10. External terminals 212 to 214 are a second source terminal S2 electrically connected to the source electrode of the lower semiconductor element 20 and a first drain terminal D1 electrically connected to the drain electrode of the upper semiconductor element 10.

[0092] like Figure 13As shown, even in semiconductor module 2, lower semiconductor element 20 is positioned so that, when viewing semiconductor module 2 from above without resin mold 230, the positions of the two ends of two substantially orthogonal sides of the substantially quadrilateral upper surface of lower semiconductor element 20 are observable. More specifically, the various structures of semiconductor module 2 contained within resin mold 230 are positioned so that, when viewing from above, the three corners 21, 23, and 24 of the substantially rectangular upper surface of lower semiconductor element 20 are observable. Therefore, the long side connecting corners 21 and 23, and the short side connecting corners 23 and 24, can be selected as the two substantially orthogonal sides of the substantially quadrilateral.

[0093] In addition, in the semiconductor module 2, as Figure 13 As shown, the various structures contained within the resin mold 230 of the semiconductor module 2 are arranged so that, when viewed from above, the four corners 11 to 14 of the roughly rectangular upper surface of the upper semiconductor element 10 and the four sides of the roughly rectangular shape near these corners 11 to 14 are observable. Specifically, the upper semiconductor element 10 is arranged so that, when viewing the semiconductor module 1 from above without the resin mold 230 present, the positions of the two ends of the roughly perpendicular sides of the roughly rectangular upper surface of the upper semiconductor element 10 are observable. Therefore, positional misalignment of the upper semiconductor element 10, in addition to the lower semiconductor element 20, can also be detected. Even in cases where the gate pads of the upper semiconductor element 10 and the gate pads of the lower semiconductor element 20 are not positioned substantially identically when viewed from above, as in the case of the semiconductor module 2, this arrangement allows for easy detection of positional misalignment of the lower semiconductor element 20 and the like.

[0094] The other structures of the semiconductor module 2 are the same as those of the semiconductor module 1, and thus description thereof is omitted. The semiconductor module 2 can be applied to the EPS 80, and more specifically, can be applied to the inverter circuits shown as the first inverter INV1 and the second inverter INV2.

[0095] (Third embodiment)

[0096] Figure 15 1 is a diagram showing the internal structure of the resin mold in the semiconductor module 3 from above. Figure 15As shown, the semiconductor module 3 according to the third embodiment differs from the semiconductor module 1 in that an upper semiconductor element 30 and a lower semiconductor element 40 are provided instead of the upper semiconductor element 10 and the lower semiconductor element 20. The upper semiconductor element 30 and the lower semiconductor element 40 are semiconductor elements having the same structure, shape, size, etc. Compared with the upper semiconductor element 10 and the lower semiconductor element 20, the upper semiconductor element 30 and the lower semiconductor element 40 are substantially rectangular in a plan view in a direction of the short side ( Figure 15 The length (in the x-axis direction) is longer and has a shape close to a square.

[0097] The upper semiconductor element 30 is arranged with its longitudinal direction in the y-axis direction when viewed from above, and the lower semiconductor element 40 is arranged with its longitudinal direction in the x-axis direction when viewed from above. That is, when viewed from above, the upper semiconductor element 30 is arranged in an orientation that is rotated approximately 90° counterclockwise with respect to the vertical direction of the lower semiconductor element 40. Furthermore, if the upper semiconductor element 30 and the lower semiconductor element 40 are stacked vertically with the same orientation and no offset in the planar direction, then corners 31 and 41, corners 32 and 42, corners 33 and 43, and corners 34 and 444 will be approximately aligned in the planar direction.

[0098] The semiconductor module 3 includes a first conductive member 321, a second conductive member 323, an upper semiconductor element 30, a third conductive member 324, a fourth conductive member 325, a lower semiconductor element 40, and an electrode pad 322, stacked in this order from top to bottom. The semiconductor module 3 also includes external terminals 301 to 304, 311 to 314, and conductive bonding pads 305, 306, 315, and 316 at the same positions in the vertical direction as the electrode pad 322. The semiconductor module 3 also includes gate connecting members 307 and 317.

[0099] In the semiconductor module 3, the sizes of the first conductive component 321, the third conductive component 324, and the electrode pad 322 are enlarged in the positive direction of the x-axis according to the sizes of the upper semiconductor element 30 and the lower semiconductor element 40. For example, in the first conductive component 321, the connection portion 321a connected to the bonding plate 306 extends in the positive direction of the x-axis to the same position as the external terminal 302. The beam-shaped portion of the gate connection component 307 extends from the columnar portion in the negative direction of the y-axis to the upper surface of the upper semiconductor element 10. The gate pad of the upper semiconductor element 30 and the gate pad of the lower semiconductor element 40 are arranged at positions that are approximately the same when viewed from above. More specifically, the gate pad of the upper semiconductor element 30 is arranged near corner 34, and the gate pad of the lower semiconductor element 40 is arranged near corner 44.

[0100] External terminal 301 is a first gate terminal G1 electrically connected to the gate electrode of the upper semiconductor element 30. External terminal 311 is a second gate terminal G2 electrically connected to the gate electrode of the lower semiconductor element 40. External terminals 302 to 304 are a first source terminal S1 electrically connected to the source electrode of the upper semiconductor element 30. External terminals 312 to 314 are a second source terminal S2 electrically connected to the source electrode of the lower semiconductor element 40 and a first drain terminal D1 electrically connected to the drain electrode of the upper semiconductor element 10.

[0101] like Figure 15 As shown, in semiconductor module 3, lower semiconductor element 40 is also positioned so that when viewing semiconductor module 3 from above without the resin mold, the two ends of two substantially orthogonal sides of the substantially rectangular upper surface of lower semiconductor element 40 are observable. More specifically, the various structures of semiconductor module 3 contained within the resin mold are positioned so that the four corners 41 to 44 of the substantially rectangular upper surface of lower semiconductor element 40 are observable from above. Therefore, for example, the long side connecting corners 41 and 43, and the short side connecting corners 41 and 42, can be selected as the two substantially orthogonal sides of the substantially rectangular upper surface.

[0102] In addition, in the semiconductor module 3, as Figure 15 As shown, the various components of semiconductor module 3 contained within the resin mold are arranged so that, when viewed from above, the four corners 31 to 34 of the substantially rectangular upper surface of upper semiconductor element 30 and the four sides of the substantially rectangular shape near these corners 31 to 34 are observable. Specifically, upper semiconductor element 30 is arranged so that, when viewed from above without the resin mold present, the positions of the two ends of two substantially orthogonal sides of the substantially rectangular upper surface of upper semiconductor element 30 are observable. Therefore, positional deviation of upper semiconductor element 30, in addition to lower semiconductor element 40, can also be detected.

[0103] The other structures of the semiconductor module 3 are the same as those of the semiconductor module 1, and thus description thereof is omitted. The semiconductor module 3 can be applied to the EPS 80, and more specifically, can be applied to the inverter circuits shown as the first inverter INV1 and the second inverter INV2.

[0104] As described above, even in the case of semiconductor module 3 having relatively large upper and lower semiconductor elements 30 and 40, the upper and lower semiconductor elements 30 and 40 can be arranged so that the positions of the two ends of the substantially orthogonal sides of the upper and lower semiconductor elements 30 and 40 can be observed. For example, such an arrangement can be achieved by adjusting the size and shape of the first conductive member 321, third conductive member 324, gate connector members 307 and 317, and electrode pad 322, which serve as the clip. In other words, in semiconductor modules 1-3, even if the shapes and sizes of the upper and lower semiconductor elements 10 and 30 and 20 and 40 are changed, by adjusting the size and shape of the various structures within the resin mold of the semiconductor modules, the respective structures can be arranged so that the positions of the two ends of the substantially orthogonal sides of the upper and lower semiconductor elements can be observed, similar to semiconductor modules 1-3.

[0105] While semiconductor modules 1 to 3 illustrate and describe a case where the upper and lower semiconductor elements are of the same size, different sizes of upper and lower semiconductor elements may also be used. For example, the third conductive member 124, fourth conductive member 125, lower semiconductor element 20, and electrode pad 122 in semiconductor module 1 may be replaced with the third conductive member 324, fourth conductive member 325, lower semiconductor element 40, and electrode pad 322 in semiconductor module 3, respectively. When stacking two semiconductor elements of different sizes, the upper surface area of ​​the lower semiconductor element is preferably larger than that of the upper semiconductor element.

[0106] When the area of ​​the upper surface of the lower semiconductor element is larger than that of the upper semiconductor element, it is easy to ensure that, when looking down at the semiconductor module without the resin mold, the positions of the two ends of the roughly quadrilateral on the upper surface of the lower semiconductor element can be observed. Furthermore, it is possible to achieve both the ability to observe the positions of the two ends of the roughly quadrilateral on the upper surface of the lower semiconductor element and the ability to ensure an overlapping area between the upper and lower semiconductor elements. Therefore, it is possible to achieve both easy detection of positional deviation of the lower semiconductor element and suppression of positional deviation of various structures within the resin mold of the semiconductor module.

[0107] According to each of the above-described embodiments, the following effects can be obtained.

[0108] Semiconductor modules 1-3 include: two semiconductor elements 10, 20, 30, and 40, each having a substantially rectangular shape when viewed from above, stacked vertically with at least a portion of the elements overlapping; a conductive member stacked on either the upper or lower surface of the two semiconductor elements and electrically connected to at least one of the two semiconductor elements; and resin molds 130 and 230, which integrally seal the two semiconductor elements and the conductive member. By observing the positions of the two ends, the position of the underlying semiconductor element can be detected, making it easy to detect any misalignment between the stacked semiconductor elements.

[0109] Semiconductor elements 10, 20, 30, and 40 are vertical insulated gate semiconductor elements comprising a gate electrode 75, a first electrode (e.g., source electrode 71), and a second electrode (e.g., drain electrode 72). In semiconductor elements 10, 20, 30, and 40, application of a voltage to the gate electrode causes current to flow from the first electrode side to the second electrode side of semiconductor element 10, 20, 30, and 40. In this case, the gate pad electrically connected to gate electrode 75 can be positioned substantially at the same position when viewed from above. This allows for greater design flexibility, as either semiconductor element can be positioned at the top.

[0110] In semiconductor modules 1-3, the second electrode (e.g., drain electrode 72) of the lower semiconductor element is preferably electrically connected to an electrode pad (e.g., electrode pad 122) exposed on the lower surface of the resin mold. Furthermore, it is more preferable that the conductive components (e.g., first conductive component 121, second conductive component 123, third conductive component 124, and fourth conductive component 125) included in semiconductor modules 1-3 are thicker than the electrode pads. The thickness and weight of each conductive component can help prevent positional shifting of various components within the resin mold 130 of semiconductor module 1.

[0111] The two semiconductor elements may be of the same size. Alternatively, the plurality of semiconductor elements may include semiconductor elements of different sizes. More preferably, the area of ​​the upper surface of the lower semiconductor element is larger than the area of ​​the upper surface of the upper semiconductor element. In the lower semiconductor element, when the semiconductor module is viewed from above without the resin mold, the positions of the two ends of the substantially quadrilateral on the upper surface of the lower semiconductor element can be easily observed.

[0112] The upper semiconductor elements 10 and 30 are preferably arranged in an orientation rotated approximately 90 degrees about the vertical direction relative to the lower semiconductor element 20. When the upper semiconductor element 10 and the lower semiconductor elements 20 and 40 are arranged in this positional relationship, it is easy to ensure that the positions of the two ends of the two substantially orthogonal sides of the substantially quadrilateral on the upper surface of the lower semiconductor element can be observed.

[0113] Furthermore, in each of the above embodiments, a trench gate type MOSFET is exemplified and described as an element structure of two stacked semiconductor elements, but the present invention is not limited thereto, and any two semiconductor elements stacked in a semiconductor module may be used. For example, a planar gate type may be used, or a structure in which two semiconductor elements are stacked may be used. Figure 5 The p-channel type, resulting from the substitution of p-type and n-type, may also be an insulated gate bipolar transistor (IGBT) or a reverse conducting IGBT (RC-IGBT). Furthermore, when the semiconductor element is an IGBT, the emitter electrode corresponds to the first electrode, and the collector corresponds to the second electrode. The external terminal electrically connected to the emitter electrode corresponds to the first terminal, and the external terminal electrically connected to the collector corresponds to the second terminal.

[0114] In addition, Figure 7 In the embodiment, the switches SU1p-SW2n and SP1, SC1, SP2, and SC2 are not limited to MOSFETs such as the upper semiconductor element 10 and the lower semiconductor element 20. Voltage-controlled semiconductor switching elements such as IGBTs may also be used. When IGBTs without freewheeling diodes are used as the switches SU1p-SW2n, it is preferable to provide a freewheeling diode for each switch SU1p-SW2n. Specifically, for example, a freewheeling diode may be connected in antiparallel to each switch SU1p-SW2n, or a reverse-conducting IGBT (RC-IGBT) in which a freewheeling diode is formed on the same semiconductor substrate as the IGBT may be used as each switch SU1p-SW2n.

[0115] As the semiconductor modules 1 to 3, a semiconductor module in which two stacked semiconductor elements are modularized as one is exemplified and described, but the present invention is not limited thereto and a semiconductor module including three or more semiconductor elements may be used. Figures 2-4 The structures inside the resin mold 130 shown are arranged three times along the x-axis direction and housed in one resin mold, thereby modularizing six semiconductor elements including three sets of two semiconductor elements stacked together. When six semiconductor elements are modularized together like this, for example, Figure 7 The semiconductor module shown is an integrated semiconductor module of SU1, SV1, and SW1. In addition, the semiconductor module may include not only two stacked semiconductor elements but also unstacked semiconductor elements.

[0116] While the present disclosure has been described based on embodiments, it should be understood that the present disclosure is not limited to the aforementioned embodiments and configurations. The present disclosure also encompasses various modifications and variations within the scope of equivalents. Furthermore, various combinations and configurations, including combinations and configurations involving only one element, more than one element, or less than one element, also fall within the scope and spirit of the present disclosure.

Claims

1. A semiconductor module comprising two semiconductor elements, a conductive member, and a resin mold, wherein: The two semiconductor elements are quadrilateral in shape when viewed from above, and are stacked in the vertical direction with at least a portion overlapping. The conductive component is stacked on the upper surface side or the lower surface side of the two semiconductor elements and is electrically connected to at least one of the two semiconductor elements. The resin mold seals the two semiconductor elements and the conductive component as a whole. In the semiconductor module, The lower semiconductor element of the two semiconductor elements is arranged so that when the semiconductor module is viewed from above without the resin mold, the positions of both ends of at least two orthogonal sides of the quadrilateral can be observed. The above-mentioned two semiconductor elements are vertical insulated gate type semiconductor elements having a gate electrode and a first electrode formed on the first surface side of the semiconductor substrate, and a second electrode formed on the second surface side of the above-mentioned semiconductor substrate opposite to the above-mentioned first surface, and utilizing a channel formed by applying a voltage to the above-mentioned gate electrode to move carriers from the above-mentioned first electrode side to the above-mentioned second electrode side of the above-mentioned semiconductor element, and the gate pad electrically connected to the above-mentioned gate electrode is arranged at the same position when the above-mentioned two semiconductor elements are viewed from above.

2. The semiconductor module according to claim 1, wherein The two semiconductor elements are stacked in an orientation rotated 90° with the vertical direction as an axis.

3. The semiconductor module according to claim 1 or 2, wherein: The two semiconductor elements are of the same size.

4. The semiconductor module according to claim 1 or 2, wherein: An area of ​​an upper surface of the lower semiconductor element is larger than an area of ​​an upper surface of an upper semiconductor element stacked above the lower semiconductor element.

5. A semiconductor module comprising two semiconductor elements, a conductive member, and a resin mold, wherein: The two semiconductor elements are quadrilateral in shape when viewed from above, and are stacked in the vertical direction with at least a portion overlapping. The conductive component is stacked on the upper surface side or the lower surface side of the two semiconductor elements and is electrically connected to at least one of the two semiconductor elements. The resin mold seals the two semiconductor elements and the conductive component as a whole. In the semiconductor module, The lower semiconductor element of the two semiconductor elements is arranged so that when the semiconductor module is viewed from above without the resin mold, the positions of both ends of at least two orthogonal sides of the quadrilateral can be observed. The two semiconductor elements include a gate electrode and a first electrode formed on a first surface side of a semiconductor substrate, and a second electrode formed on a second surface side of the semiconductor substrate opposite to the first surface. The two semiconductor elements are vertical insulated gate type semiconductor elements in which carriers move from the first electrode side to the second electrode side of the semiconductor elements by utilizing a channel formed by applying a voltage to the gate electrodes. The second electrode of the lower semiconductor element is electrically connected to an electrode pad exposed on the lower surface of the resin mold. The conductive member is thicker than the electrode pad. The semiconductor module according to claim 5 , wherein: The two semiconductor elements are stacked in an orientation rotated 90° with the vertical direction as an axis.

7. The semiconductor module according to claim 5 or 6, wherein: The two semiconductor elements are of the same size.

8. The semiconductor module according to claim 5 or 6, wherein: An area of ​​an upper surface of the lower semiconductor element is larger than an area of ​​an upper surface of an upper semiconductor element stacked above the lower semiconductor element.

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