Deposition and silicon oxide liner for forming isolation regions

Abstract

The present disclosure relates to depositing and oxidizing a silicon liner for forming isolation regions. A method includes: etching a semiconductor substrate to form trenches and semiconductor strips. Sidewalls of the semiconductor strips are exposed to the trenches. The method further includes depositing a silicon-containing layer extending into the trenches, wherein the silicon-containing layer extends on the sidewalls of the semiconductor strips; filling the trenches with a dielectric material, wherein the dielectric material is located on the sidewalls of the silicon-containing layer; and oxidizing the silicon-containing layer to form a liner. The liner includes oxidized silicon. The liner and the dielectric material form some portions of the isolation regions. The isolation regions are recessed such that portions of the semiconductor strips protruding above the top surface of the isolation regions form semiconductor fins.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to depositing and oxidizing a silicon liner for forming isolation regions. Background Art

[0002] Transistors are basic components in integrated circuits. In the development of integrated circuits, fin field-effect transistors (FinFETs) have been formed to replace planar transistors. When forming a FinFET, an isolation region is formed that extends into a semiconductor substrate, and the isolation region is recessed to form semiconductor fins. A dummy gate is formed on the semiconductor fins, and then source / drain regions are formed. Then, the dummy gate stack is removed to form a trench between the gate spacers. Then, a replacement gate is formed in the trench. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method is provided that includes: etching a semiconductor substrate to form a trench and a semiconductor strip, wherein sidewalls of the semiconductor strip are exposed to the trench;

[0004] depositing a silicon-containing layer that extends into the trench, wherein the silicon-containing layer extends on sidewalls of the semiconductor strip; filling the trench with a dielectric material, wherein the dielectric material is located on sidewalls of the silicon-containing layer; oxidizing the silicon-containing layer to form a first liner, wherein the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form some portions of an isolation region; and recessing the isolation region, wherein portions of the semiconductor strip that protrude above a top surface of the isolation region form semiconductor fins.

[0005] According to another embodiment of the present disclosure, a method is provided that includes: etching a semiconductor substrate to form a semiconductor strip and a trench, wherein the semiconductor strip is located on one side of the trench and has a first longitudinal direction parallel to a second longitudinal direction of the trench, wherein the semiconductor strip includes silicon and germanium, and sidewalls of the semiconductor strip are exposed; depositing a first liner that extends into the trench and contacts the sidewalls of the semiconductor strip, wherein the first liner includes silicon oxide; depositing a second liner on the first liner, wherein the second liner includes silicon and extends from a top surface of the semiconductor substrate to a bottom of the trench; depositing a dielectric material to fill the trench, wherein a portion of the second liner is located under the dielectric material; curing the dielectric material to form an oxide layer; and converting the second liner into a third liner.

[0006] According to another embodiment of the present disclosure, a method is provided, including: depositing a silicon-containing liner into a trench in a semiconductor substrate; oxidizing the silicon-containing liner into a first oxidized silicon liner such that a ratio of a volume of the first oxidized silicon liner to a volume of the silicon-containing liner is greater than 0 and not greater than 2.25; depositing a dielectric material into the trench, wherein the first oxidized silicon liner includes a first portion located under the dielectric material, and the dielectric material and the first oxidized silicon liner form an isolation region; recessing the isolation region, wherein a portion of the semiconductor substrate located between the recessed isolation regions forms a protruding semiconductor fin; forming a gate dielectric extending over the isolation region; and forming a gate electrode over the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1-3A 、 Figure 3B 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figures 6-15 、 Figure 16A and Figure 16B show cross-sectional views and perspective views of intermediate stages of forming an isolation region and a FinFET in accordance with some embodiments.

[0009] Figure 17 show a process flow for forming a FinFET in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0012] According to some embodiments, an isolation region, a fin field effect transistor (FinFET) based on the isolation region, and a method for forming the same are provided. According to some embodiments, an intermediate stage of forming an isolation region and a FinFET is shown. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, similar reference numerals are used to designate similar elements. According to some embodiments of the present disclosure, a silicon liner is formed and then oxidized into a silicon oxide liner in an annealing process. When the silicon liner is oxidized into a silicon oxide liner, the volume increases. Due to the oxidation, beneficial strain is generated in the channel of the resulting FinFET. Therefore, SiGe channel protection, additional tensile strain, and charge trapping reduction can be achieved by introducing a shallow trench isolation (STI) oxide liner.

[0013] Figures 1-4 , Figure 5A , Figure 5B , Figures 6-15 , Figure 16A and Figure 16B 1 shows a perspective view and a cross-sectional view of an intermediate stage of forming an isolation region (alternatively referred to as an STI region) and a FinFET according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Figure 17 In the process flow 200 shown.

[0014] Figure 1 A perspective view of an initial structure is shown. The initial structure includes a wafer 10, which also includes a substrate 20. The substrate 20 can be formed of silicon, silicon germanium, carbon-doped silicon, or multiple layers thereof. According to some embodiments of the present disclosure, the region shown is a p-type device region, where a p-type transistor such as a p-type FinFET will be formed. The substrate 20 may include a substrate (portion) 20-1 and an epitaxial semiconductor layer 20-2 located above the substrate 20-1. The substrate 20-1 may be a bulk substrate or a semiconductor-on-insulator substrate. According to some embodiments, the silicon substrate 20-1 may not contain germanium, or may include silicon germanium having a germanium percentage (e.g., less than about 10%) that is lower than the germanium percentage in the epitaxial semiconductor layer 20-2. The epitaxial semiconductor layer 20-2 may be epitaxially grown on top of the substrate 20-1 (which may be a silicon substrate) to form the substrate 20. In the example Figure 17In the process flow 200 shown, the corresponding process is shown as process 202. According to some embodiments of the present disclosure, the epitaxial semiconductor layer 20-2 is formed of silicon germanium (SiGe) or germanium (without silicon therein), or includes silicon germanium or germanium. The percentage of germanium atoms in the epitaxial semiconductor layer 20-2 is higher than the percentage of germanium atoms in the substrate portion 20-1. According to some embodiments of the present disclosure, the atomic percentage in the epitaxial semiconductor layer 20-2 is in the range of about 30% to 100%. The epitaxial semiconductor layer 20-2 can also be formed of SiP, SiC, SiPC, SiGeB, or III-V compound semiconductors (such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

[0015] According to an alternative embodiment of the present disclosure, an n-type device is provided on the same wafer, in which an n-type transistor, such as an n-type FinFET, is to be formed. The substrate in the n-type device region can include a silicon substrate (e.g., the same as 20-1), and the epitaxial layer 20-2 formed on the silicon substrate may not be present.

[0016] A hard mask layer 22 is formed on the semiconductor substrate 20. In the Figure 17 process flow 200 shown, the corresponding process is shown as process 204. According to some embodiments, the hard mask layer 22 includes a hard mask (sub) layer 22A and a hard mask (sub) layer 22B located above the hard mask layer 22A. The hard mask layer 22A can be a thin film formed of silicon oxide and is sometimes referred to as a pad oxide layer. According to some embodiments of the present disclosure, the pad oxide layer 22A is formed by a deposition process, which can include chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. According to an alternative embodiment, the pad oxide layer 22A is formed by a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 22A serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 22B. The hard mask layer 22A can also serve as an etch stop layer for etching the hard mask layer 22B. According to some embodiments of the present disclosure, the hard mask layer 22B is formed of, for example, silicon nitride. The formation method can include low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The hard mask layer 22B serves as a hard mask during subsequent lithography processes.

[0017] According to an alternative embodiment, the hard mask layer 22 is formed of a homogeneous material in contact with the substrate 20. For example, the homogeneous material may include materials such as silicon nitride, such as SiCN, SiOC, etc. According to yet another alternative embodiment, the hard mask layer 22 includes a silicon layer 22C, a pad oxide layer 22A located above the silicon layer 22C, and a hard mask layer 22B located above the pad oxide layer 22A. The silicon layer 22C can be formed by deposition (e.g., using CVD, ALD, etc.). The silicon layer 22C can be a crystalline silicon layer.

[0018] Reference Figure 2 , the hard mask layer 22 is patterned. For example, the hard mask layer 22 is etched by using a patterned photoresist (not shown) as an etch mask, such that the underlying semiconductor substrate 20 is exposed. Then, the exposed semiconductor substrate 20 is etched by using the patterned hard mask layer 22 as an etch mask, thereby forming the trench 26. In the process flow 200 as Figure 17 shown, the corresponding process is shown as process 206. Hereinafter, the portion of the semiconductor substrate 20 between adjacent trenches 26 is referred to as a semiconductor strip 30. Some portions of the trenches 26 may have a strip shape parallel to each other (when observed in a top view of the wafer 10), and the trenches 26 are close to each other in position. According to some embodiments of the present disclosure, the aspect ratio (depth-to-width ratio) of the trenches 26 is greater than about 7, and may be greater than about 10. Although one semiconductor strip 30 is shown, a plurality of semiconductor strips 30 may be formed parallel to each other, where the trenches 26 separate the plurality of semiconductor strips 30 from each other. According to some embodiments of forming the epitaxial semiconductor layer 20-2, the bottom of the trench 26 is lower than the interface 23 between the substrate portion 20-1 and the epitaxial semiconductor layer 20-2.

[0019] Reference Figure 3A , an oxide layer 32 is formed according to some embodiments of the present disclosure. In the Figure 17In the process flow 200 shown, the corresponding process is shown as process 208. Throughout the specification, the oxide layer 32 is alternatively referred to as a silicon oxide liner. According to some embodiments, the oxide layer 32 is formed by a conformal deposition process (such as an ALD process, a CVD process, etc.). Thus, the oxide layer 32 has a horizontal portion and a vertical portion, where the thickness T1 of the horizontal portion and the thickness T1' of the vertical portion are equal to each other or substantially equal to each other. For example, the absolute value of the ratio (T1' - T1) / T1 can be less than about 0.2 or less than about 0.1. When using ALD, precursors such as dichlorosilane (DCS, SiH2Cl2), silane (SiH4), disilane (Si2H6), hexamethyldisilane (HMDS), etc. can be pulsed and then purged, followed by pulsing and purging another process gas such as O2, O3, etc., in order to deposit an atomic layer of the silicon oxide layer. These two types of gases are pulsed and purged alternately to increase the thickness of the oxide layer to a desired value. The thickness of the oxide layer 32 is thick enough to allow the oxide layer 32 to be an effective barrier for protecting the semiconductor strip 30 from oxidation, such that the oxidation of the subsequently deposited silicon layer 34 can be more easily controlled. On the other hand, the oxide layer 32 cannot be too thick. Otherwise, the strain generated by the oxidation of the subsequently deposited silicon layer 34 cannot be effectively applied to the semiconductor strip 30. According to some embodiments, the thicknesses T1 and T1' of the oxide layer 32 are in the range of about and about In the range between. The ALD process can be, for example, a thermal ALD process performed at a temperature in the range of about 250 °C to 450 °C. When using CVD, precursors such as silane, disilane, HMDS, DCS, O2, O3, etc. can be used. According to some embodiments of the present disclosure, by using a silicon oxide layer instead of a silicon nitride layer as the barrier, silicon nitride with a high density of traps (DIT) and prone to charge trapping (which results in a higher leakage current) is not used, but a silicon oxide layer with a lower DIT and a higher bandgap is used.

[0020] Further referring to Figure 3A According to some embodiments of the present disclosure, the silicon layer 34 is deposited on the oxide layer 32. Throughout the specification, the silicon layer 34 is alternatively referred to as a silicon liner. In as Figure 17In the process flow 200 shown, the corresponding process is shown as process 210. Deposition can be performed by a conformal deposition process (such as a CVD process or an ALD process). When using ALD, precursors such as DCS, silane, disilane, HMDS, etc. can be pulsed and purged, and then another process gas, such as H2, can be pulsed and purged. These two types of gases are alternately pulsed and purged to increase the thickness of the silicon layer to the desired value. The ALD process can be a thermal ALD process, which is performed, for example, at a temperature in the range of about 350°C to about 500°C. When using CVD, precursors such as silane, disilane, HMDS, DCS, H2, etc. can be used.

[0021] The silicon layer 34 can be free or substantially free of other elements, such as germanium, carbon, etc. For example, the atomic percentage of silicon in the silicon layer 34 can be higher than about 95% or higher than about 99%. The silicon layer 34 can be formed as an amorphous silicon layer or a polycrystalline silicon layer, which can be achieved, for example, by adjusting the temperature and growth rate in the deposition process.

[0022] The silicon layer 34 has a horizontal portion and a vertical portion, where the thickness T2 of the horizontal portion and the thickness T2' of the vertical portion are equal to or substantially equal to each other. For example, the absolute value of the ratio (T2' - T2) / T2 can be less than about 0.2 or less than about 0.1. The thicknesses T2 and T2' of the silicon layer 34 can be greater than about 0.5 nm so that sufficient strain can be generated during the subsequent oxidation of the silicon layer 34. On the other hand, the thicknesses T2 and T2' should not be too high to avoid introducing too much strain. According to some embodiments, the thickness of the silicon layer 34 can be in the range between about 0.5 nm and about 2 nm. It should be recognized that the optimal thicknesses T2 and T2' are related to the pitch of the adjacent semiconductor strips 30, as will be discussed in the following paragraphs. Throughout the specification, the oxide layer 32 and the silicon layer 34 are collectively referred to as the liner 33.

[0023] When adopting Figure 3A the embodiment in which the oxide layer 32 is deposited before the deposition of the silicon layer 34, the silicon oxide hard mask layer 22A can be omitted or separated from the epitaxial semiconductor material 20-2. For example, the hard mask layer 22 can be formed of a homogeneous material such as silicon nitride, or can have the following structure, which includes a silicon layer 22C ( Figure 1 ) that contacts the epitaxial semiconductor material 20-2, a liner oxide layer 22A located above the silicon layer 22C, and a hard mask layer 22B located above the liner oxide layer 22A. If the liner oxide layer is in direct contact with the material (such as SiGe) of the epitaxial semiconductor material 20-2, severe oxidation may occur at the interface between the liner oxide layer and the epitaxial semiconductor material 20-2, especially at the position where the interface connects the silicon oxide layer 32.

[0024] Figure 3BDeposition of the liner according to some alternative embodiments is shown. In these embodiments, instead of depositing the oxide layer 32 before depositing the silicon layer 34, the silicon layer 34 is directly deposited on the hard mask layer 22, the semiconductor substrate 20, and the semiconductor strip 30. Thus, the silicon layer 34 is in physical contact with the sidewalls of the semiconductor strip 30 and the exposed top surface of the semiconductor substrate 20.

[0025] The silicon layer 34 can be deposited using ALD, CVD, etc., and thus is formed as a conformal layer. Thus, the horizontal thickness T2 ( Figure 3A ) of the horizontal portion and the thickness T2' of the vertical portion are equal to or substantially equal to each other. For example, the absolute value of the ratio (T2' - T2) / T2 is less than about 0.2 or less than about 0.1. The thicknesses T2 and T2' of the silicon layer 34 can be greater than about 0.5 nm and can be in the range between about 0.5 nm and about 2 nm, such that a desired strain can be applied through subsequent oxidation of the silicon layer 34.

[0026] Then a dielectric material 40 is deposited to fill the remaining portion of the trench 26, thereby forming Figure 4 the structure shown. In the process flow 200 as shown in Figure 17 the corresponding process is shown as process 212. The method of forming the dielectric material 40 can be selected from flowable chemical vapor deposition (FCVD), spin coating, CVD, ALD, high density plasma chemical vapor deposition (HDPCVD), low pressure CVD (LPCVD), etc.

[0027] According to some embodiments using FCVD, silicon- and nitrogen-containing precursors (e.g., trisilazane (TSA), disilazane (DSA), etc.) are used, and thus the resulting dielectric material 40 is deposited as flowable. According to alternative embodiments of the present disclosure, a flowable dielectric material 40 is formed using an alkylamino silane-based precursor. During deposition, a plasma is turned on to activate the gas precursor for forming a flowable oxide. The dielectric material 40 is deposited until its top surface is higher than the top surface of the hard mask layer 22.

[0028] Referring to Figure 5A , after depositing the dielectric material 40, an annealing (curing) process 43 is performed, which converts the flowable dielectric material 40 into a solid dielectric material and oxidizes the silicon layer 34. In as Figure 17In the process flow 200 shown, the corresponding process is shown as process 214. The solidified dielectric material is also referred to as dielectric material 40. According to some embodiments of the present disclosure, the annealing process is performed in an oxygen-containing environment. The annealing temperature can be higher than about 200 °C, for example, in the temperature range between about 550 °C and about 700 °C. The duration of the annealing process can be in the range between about 1 hour and about 3 hours. During the annealing process, an oxygen-containing process gas is introduced into the process chamber where the wafer 10 is placed. The oxygen-containing process gas can include oxygen (O2), ozone (O3), or a combination thereof. Water vapor (H2O) can also be used, which also provides oxygen. The annealing process can be performed in an oven where the pressure is one atmosphere. According to other embodiments, the annealing process is performed in a vacuum chamber where the oxygen-containing process gas is conducted. For example, the flow rate of the oxygen-containing process gas can be in the range between about 100 sccm and about 1000 sccm. As a result of the oxygen-containing process gas, the dielectric material 40 is cured and solidified. The resulting dielectric material 40 can be an oxide such as silicon oxide.

[0029] The annealing process is performed with a selected temperature and duration (e.g., as described above) such that the silicon layer 34 is oxidized and converted into a silicon oxide layer (liner) 38, as Figure 5A shown. As a result, the silicon oxide layer 38 includes a horizontal portion that is directly below and in physical contact with the dielectric material 40, and sidewall portions on the sidewalls of the dielectric material 40. According to some embodiments of forming the silicon oxide layer 32 (as Figure 5A shown), the silicon oxide layer 38 is between and in contact with the silicon oxide layer 32 and the dielectric material 40. The silicon oxide layers 32 and 38 are hereinafter collectively referred to as the silicon oxide liner (layer) 41. According to alternative embodiments where the silicon oxide layer 32 is not formed (as Figure 5C shown), the silicon oxide layer 38 is in contact with the semiconductor substrate 20 and the semiconductor strip 30.

[0030] It should be recognized that depending on the material and composition (elements, and percentages of elements), the silicon oxide layer 38 may or may not be distinguishable from the silicon oxide layer 32 and the dielectric material 40. For example, in addition to silicon and oxygen, the dielectric material 40 may or may not include other elements such as carbon, hydrogen, nitrogen, etc. Furthermore, the density of the silicon oxide layer 32 and the silicon oxide layer 38 can be lower than, equal to, or higher than the density of the dielectric material 40. The distinction between the silicon oxide layers 32 and 38 and the dielectric material 40 can be achieved by, for example, determining the elements and the corresponding atomic percentages of the elements in these layers / materials using X-ray photoelectron spectroscopy (XPS).

[0031] According to some embodiments, when the silicon layer 34 is thick, but the annealing temperature is not high enough and / or the annealing duration is not sufficient to oxidize the entire silicon layer 34, the bottom portion of the silicon layer 34 may remain unoxidized. The remaining portion is referred to as portion 34A, as Figure 5B shown. According to some embodiments as Figure 5B shown, since the top portion of the silicon layer 34 receives oxygen earlier than the lower portion, the top portion near the top surface of the wafer 10 may be oxidized while the lower portion is not oxidized, such that the unoxidized portion 34A has a profile as Figure 5B shown. The unoxidized silicon portion 34A can be oxidized by a subsequent thermal budget when forming the corresponding semiconductor wafer (thereafter the entire unoxidized silicon portion 34A is oxidized into the silicon oxide layer 38), or can be left in the final structure, for example, in the FinFET 96 as Figure 15 , 16A and 16B shown.

[0032] A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process can be performed to make the top surface of the dielectric material 40 flush. In the planarization process, the hard mask 22 can be used as a stop layer. The remaining dielectric material 40 and the dielectric layers 32 and 38 after the planarization process are collectively referred to as the isolation region 42, which is also referred to as the shallow trench isolation (STI) region 42. The line 43 shows the corresponding top surface of the isolation region 42 after planarization.

[0033] According to some embodiments, the oxidation of the silicon layer 34 is achieved before the planarization process, so the oxidation of the silicon layer 34 and the complete solidification of the dielectric material 40 are performed in the same annealing process. According to alternative embodiments, the solidification of the dielectric material 40 is performed before the planarization process. In this case, the dielectric material 40 can be partially solidified to the extent that a CMP process can be performed. The CMP process can remove the top portion of the dielectric material 40, such that for example, it is easier to completely convert the remaining dielectric material 40 into silicon oxide, and it is easier to oxidize the silicon layer 34 into the silicon oxide layer 38 with a lower thermal budget. According to these embodiments, in the partial solidification, the silicon layer 34 can remain unoxidized, or can be partially oxidized while some portions of the silicon layer 34 (e.g., the bottom portion 34A as Figure 5B shown) are left. The annealing process performed after the CMP process can completely solidify the dielectric material 40 and completely oxidize the silicon layer 34 into the silicon oxide layer 38.

[0034] According to some embodiments where the dielectric material 40 is formed of a non-flowing material using, for example, CVD, PECVD, etc., the annealing process can be performed before or after the planarization process.

[0035] According to some embodiments, by depositing and oxidizing the silicon layer 34, the strain of the channel of the corresponding FinFET 96 is improved. When silicon is oxidized to form silicon oxide, the volume of the silicon oxide is 2.25 times the volume of the silicon. Thus, the expanded volume causes squeezing in the Y direction towards the semiconductor strip 30 ( Figure 5A ). Since the volume of the semiconductor strip 30 is fixed, when squeezed, tensile stress is generated in the semiconductor strip 30 in the Y direction. Thereby, the performance of the resulting FinFET 96 ( Figure 15 ) is improved. Experimental results performed on a silicon wafer show that by adopting the embodiments of the present disclosure, the tensile stress can be increased by 0.3%. It should be recognized that in order to generate strain, an oxidation process needs to be performed after depositing the dielectric material 40. Otherwise, the expansion is towards free space and no strain or very little strain is generated. Additionally, the generated strain is related to both the thickness of the silicon layer 34 and the pitch P1 ( Figure 16B ) of the adjacent semiconductor strips 30, and the thicker the silicon layer 34 and / or the smaller the pitch P1, the greater the generated strain. For example, when the thickness of the silicon layer 34 is between about 0.5 nm and about 1.5 nm, the pitch P1 is less than about 25 nm or less than about 20 nm to be able to cause a significant strain improvement.

[0036] Next, as Figure 6 shown, the isolation region 42 is recessed in an etching process. In the process flow 200 as Figure 17 shown, the corresponding process is shown as process 216. The portion of the semiconductor strip 30 that is above the top surface of the remaining isolation region 42 is referred to as the protruding (semiconductor) fin 44. According to some embodiments of the present disclosure, the top surface of the isolation region 42 is higher than the interface 23 between the epitaxial layer 20-2 (if formed) and the underlying substrate portion 20-1. The recessing of the dielectric region can be performed using a dry etching process. For example, HF3 and NH3 can be used as etching gases. According to alternative embodiments of the present disclosure, a wet etching process is used to perform the recessing of the dielectric region. For example, the etching compound can include a diluted HF solution.

[0037] In the embodiments shown above, the semiconductor fins can be formed by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the semiconductor fins. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that obtained using a single direct lithography process in other ways. For example, in one embodiment, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers or mandrels can be used to pattern the fins.

[0038] Reference Figure 7 , the dummy gate stack 46 is formed to cross the protruding fin 44. In the process flow 200 as shown in Figure 17 , the corresponding process is shown as process 218. The dummy gate stack 46 may include a dummy gate dielectric 48 and a dummy gate electrode 50 located above the dummy gate dielectric 48. The dummy gate dielectric 48 may be formed of silicon oxide or other dielectric materials. For example, polysilicon or amorphous silicon may be used to form the dummy gate electrode 50, and other materials may also be used. Each dummy gate stack 46 may further include one (or more) hard mask layers 52 located above the dummy gate electrode 50. The hard mask layer 52 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multi-layer thereof. The dummy gate stack 46 may cross a single or multiple protruding fins 44 and / or STI regions 42. The dummy gate stack 46 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 44. The formation of the dummy gate stack 46 includes depositing a dummy gate dielectric layer, depositing a gate electrode layer above the dummy gate dielectric layer, depositing a hard mask layer, and patterning the stacked layers to form the dummy gate stack 46.

[0039] Next, referring to Figure 8 , gate spacers 54 are formed on the sidewalls of the dummy gate stack 46. In the process flow 200 as shown in Figure 17 , the corresponding process is shown as process 220. The formation of the gate spacers 54 may include depositing a blanket dielectric layer, and performing an anisotropic etching process to remove the horizontal portions of the dielectric layer, so that the gate spacers 54 remain on the sidewalls of the dummy gate stack 46. According to some embodiments of the present disclosure, the gate spacers 54 are formed of an oxygen-containing dielectric material (oxide) such as SiO2, SiOC, SiOCN, etc. According to some embodiments of the present disclosure, the gate spacers 54 may further include a non-oxide dielectric material, such as silicon nitride.

[0040] Subsequently, an etching process (hereinafter referred to as fin recess) is performed to etch the portions of the protruding fin 44 that are not covered by the dummy gate stack 46 and the gate spacers 54, so as to form the structure shown in Figure 9 , as shown in Figure 17In the process flow 200 shown, the corresponding process is shown as process 222. The recessing of the protruding fin 44 can be performed by an anisotropic etching process, so that the portion of the protruding fin 44 located directly below the dummy gate stack 46 and the gate spacer 54 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 30 can be lower than the top surface 42A of the STI region 42. Thus, a groove 60 is formed between the STI regions 42. The groove 60 is located on opposite sides of the dummy gate stack 46.

[0041] Next, an epitaxial region (source / drain region) 62 is formed by selectively growing semiconductor material from the groove 60, thereby forming the Figure 10 structure in. As in Figure 17 In the process flow 200 shown, the corresponding process is shown as process 224. According to some embodiments of the present disclosure, the epitaxial region 62 includes silicon germanium, silicon, or silicon carbide. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped during epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to alternative embodiments of the present disclosure, the epitaxial region 62 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the epitaxial region 62 completely fills the groove 60, the epitaxial region 62 begins to expand horizontally and can form facets.

[0042] After the epitaxial step, the epitaxial region 62 can be further implanted with p-type or n-type impurities to form the source region and the drain region, which are also denoted by the reference numeral 62. According to alternative embodiments of the present disclosure, when the epitaxial region 62 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation process is skipped.

[0043] According to some alternative embodiments of the present disclosure, instead of recessing the protruding fin 44 and regrowing the source / drain region 62, a source / drain region is formed that wraps around. According to these embodiments, the protruding fin 44 shown in Figure 9 is not recessed, and an epitaxial region (not shown) is grown on the protruding fin 44. The material of the grown epitaxial region can be similar to that in Figure 11The material of the epitaxial semiconductor material 62 shown depends on whether the resulting FinFET is a p-type or n-type FinFET. Thus, the source / drain region 62 includes the protruding fin 44 and the epitaxial region. An implantation process may (or may not) be performed to implant n-type impurities or p-type impurities.

[0044] Figure 11 A perspective view of the structure after forming the contact etch stop layer (CESL) 66 and the interlayer dielectric (ILD) 68 is shown. In the process flow 200 as Figure 17 shown, the corresponding processes are shown as process 226. The CESL 66 may be formed of silicon nitride, silicon carbonitride, etc. For example, the CESL 66 may be formed by a conformal deposition process such as ALD or CVD. The ILD 68 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD 68 may also be formed of an oxygen-containing dielectric material, which may be a silica-based material such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical polishing process is performed to make the top surfaces of the ILD 68, the dummy gate stack 46, and the gate spacers 54 flush with each other. An annealing process may be employed when forming the ILD 68.

[0045] Next, the dummy gate stack 46 (which includes the hard mask layer 52, the dummy gate electrode 50, and the dummy gate dielectric 48) is etched in one or more etching processes, thereby forming a trench 70 between opposite portions of the gate spacers 54, as Figure 12 shown. The etching process may be performed using, for example, a dry etching process. The etching gas is selected based on the material to be etched. For example, when the hard mask 36 includes silicon nitride, the etching gas may include a fluorine-containing process gas such as CF4 / O2 / N2, NF3 / O2, SF6, or SF6 / O2, etc. A mixture of C2F6, CF4, SO2, HBr, Cl2, and O2, or a mixture of HBr, Cl2, O2, and CF2, etc. may be used to etch the dummy gate electrode 50. A mixture of NF3 and NH3 or a mixture of HF and NH3 may be used to etch the dummy gate dielectric 48. If a silicon layer 22C ( Figure 1 ) is formed on the sidewalls of the dummy gate stack 46, the silicon layer is also removed.

[0046] Next, referring to Figure 13 , a (replacement) gate stack 72 is formed, which includes a gate dielectric 74 and a gate electrode 76. In the as Figure 17In the process flow 200 shown, the corresponding process is shown as process 228. The formation of the gate stack 72 includes forming / depositing multiple layers and then performing a planarization process such as a CMP process or a mechanical polishing process. The gate dielectric 74 extends into the trench 70( Figure 13 ). According to some embodiments of the present disclosure, the gate dielectric 74 includes an interface layer (IL) 78( Figure 16A and 16B ) as its lower part. The IL 78 is formed on the exposed surface of the protruding fin 44. The IL 78 may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process or deposition process of the protruding fin 44. The gate dielectric 74 may further include a high-k dielectric layer 80( Figure 16A and 16B ) located above the IL 78. The high-k dielectric layer 80 may include a high-k dielectric material, such as HfO2, ZrO2, HfZrO x , HfSiO x , HfSiON, ZrSiO x , HfZrSiO x , Al2O3, HfAlO x , HfAlN, ZrAlO x , La2O3, TiO2, Yb2O3, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer 80 is formed as a conformal layer and extends on the sidewalls of the protruding fin 44 and the sidewalls of the gate spacer 54. According to some embodiments of the present disclosure, the high-k dielectric layer 80 is formed using ALD or CVD.

[0047] As Figure 13 shown, the gate electrode 76 is formed on the top of the gate dielectric 74 and fills the remaining part of the trench left by the removed dummy gate stack. The sub-layers in the gate electrode 76 are not shown separately, and in fact, these sub-layers are distinguishable from each other due to their different compositions. The deposition of at least the lower sub-layer can be performed using a conformal deposition method such as ALD or CVD, so that the thickness of the vertical part and the horizontal part of the sub-layer in the gate electrode 76 are substantially equal to each other.

[0048] The sub - layers in the gate electrode 76 may include, but are not limited to, a titanium silicon nitride (TSN) layer, a tantalum nitride (TaN) layer, a titanium nitride (TiN) layer, a titanium - and aluminum - containing layer (such as TiAl or TiAlC), additional TiN and / or TaN layers, and a fill metal. Some of these layers define the work function of the corresponding FinFET. Additionally, the metal layer of a p - type FinFET and the metal layer of an n - type FinFET may be different from each other such that the work function of the metal layer is suitable for the corresponding p - type or n - type FinFET. The fill metal may include aluminum, copper, cobalt, etc.

[0049] Next, as Figure 14 shown, a hard mask 82 is formed. In the process flow 200 as Figure 17 shown, the corresponding process is shown as process 230. According to some embodiments of the present disclosure, the formation of the hard mask 82 includes: recessing the replacement gate stack 72 by etching to form a groove, filling a dielectric material into the groove, and performing a planarization process to remove the excess portion of the dielectric material. The remaining portion of the dielectric material is the hard mask 82. According to some embodiments of the present disclosure, the hard mask 82 is formed of silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon oxynitride, etc.

[0050] Figure 15 The subsequent steps for forming the contact plug 86 are shown, which include forming a contact opening by etching into the ILD 68 and the CESL 66 to expose the source / drain regions 62. The silicide region 84 and the source / drain contact plug 86 are then formed in the contact opening. In the process flow 200 as Figure 17 shown, the corresponding process is shown as process 232. The top edges of the silicon oxide layers 32 and 38 may contact the silicide region 84 or the source / drain contact plug 86, depending on the position where the silicide region 84 extends. Alternatively, the top edges of the silicon oxide layers 32 and 38 may contact the source / drain regions 62.

[0051] In a subsequent process, as Figure 16A and 16B shown, an etch stop layer 88 is formed, and then an ILD 90 is formed. Figure 16A Shows from Figure 15A cross-sectional view obtained in the same plane containing line A-A. According to some embodiments of the present disclosure, the etch stop layer 88 is formed of SiN, SiCN, SiC, SiOCN, or another dielectric material. The forming method may include PECVD, ALD, CVD, etc. The material of the ILD 90 may be selected from the same candidate materials (and methods) used to form the ILD 68, and the ILD 68 and 90 may be formed of the same or different dielectric materials. According to some embodiments of the present disclosure, the ILD 90 is formed using PECVD, FCVD, ALD, spin coating, etc., and may include silicon oxide (SiO2).

[0052] The ILD 90 and the etch stop layer 88 are etched to form openings. The etching may be performed using, for example, reactive ion etching (RIE). The gate contact plug 92 and the source / drain contact plug 94 are formed in the openings to be electrically connected to the gate electrode 76 and the source / drain contact plug 86, respectively. Thus, the FinFET 96 is formed.

[0053] Figure 16B A cross-sectional view of the FinFET 96 obtained from another plane, which is the same as the plane containing line B-B. Figure 16A in. Figure 16B The silicon oxide layers 32 and 38 are shown relative to other features. According to an alternative embodiment, a bottom portion of the silicon layer 34 may be present between the silicon oxide layers 32 and 38, as Figure 5B shown.

[0054] Embodiments of the present disclosure have some advantageous features. In the formation of the isolation region, by depositing a silicon liner and then oxidizing the silicon liner into a silicon oxide liner, beneficial strain can be improved, and the performance of the resulting transistor is improved.

[0055] According to some embodiments of the present disclosure, a method includes: etching a semiconductor substrate to form trenches and semiconductor strips. Sidewalls of the semiconductor strips are exposed to the trenches. The method further includes: depositing a silicon-containing layer extending into the trenches, wherein the silicon-containing layer extends on sidewalls of the semiconductor strips; filling the trenches with a dielectric material, wherein the dielectric material is located on sidewalls of the silicon-containing layer; and oxidizing the silicon-containing layer to form a first liner. The first liner includes oxidized silicon. The first liner and the dielectric material form part of an isolation region. The isolation region is recessed such that a portion of the semiconductor strips protruding above a top surface of the isolation region forms semiconductor fins. In an embodiment, the method further includes: depositing a silicon oxide layer contacting the sidewalls of the semiconductor strips before the silicon-containing layer is deposited. In an embodiment, the silicon oxide layer contacts the silicon-containing layer. In an embodiment, the dielectric material is deposited as a flowable material, and the method further includes solidifying the flowable material, and wherein the flowable material is solidified by the step of oxidizing the silicon-containing layer. In an embodiment, the silicon-containing layer is completely oxidized to silicon oxide. In an embodiment, the silicon-containing layer has a thickness greater than about 0.5 nm. In an embodiment, the silicon-containing layer is deposited using atomic layer deposition.

[0056] According to some embodiments of the present disclosure, a method includes: etching a semiconductor substrate to form semiconductor strips and trenches, wherein the semiconductor strips are located on one side of the trenches and have a first longitudinal direction parallel to a second longitudinal direction of the trenches, wherein the semiconductor strips include silicon and germanium, and sidewalls of the semiconductor strips are exposed; depositing a first liner extending into the trenches and contacting the sidewalls of the semiconductor strips, wherein the first liner includes silicon oxide; depositing a second liner on the first liner, wherein the second liner includes silicon, and the second liner extends from a top surface of the semiconductor substrate to a bottom of the trenches; depositing a dielectric material to fill the trenches, wherein a portion of the second liner is located below the dielectric material; solidifying the dielectric material to form an oxide layer; and converting the second liner into a third liner. In an embodiment, the first liner has a thickness in a range between about and about In an embodiment, the second liner has a thickness greater than about 0.5 nm. In an embodiment, the second liner includes amorphous silicon. In an embodiment, solidifying the dielectric material and converting the second liner are performed by the same annealing process. In an embodiment, the method further includes: recessing the first liner, the second liner, and the oxide layer; and forming a gate stack extending over the recessed first liner, second liner, and oxide layer. In an embodiment, the second liner is completely converted to silicon oxide.

[0057] According to some embodiments of the present disclosure, a method includes: depositing a silicon-containing liner into a trench in a semiconductor substrate; oxidizing the silicon-containing liner into a first oxidized silicon liner such that a ratio of a volume of the first oxidized silicon liner to a volume of the silicon-containing liner is greater than 0 and not greater than 2.25; depositing a dielectric material into the trench, wherein the first oxidized silicon liner includes a first portion located under the dielectric material, and the dielectric material and the first oxidized silicon liner form an isolation region; recessing the isolation region, wherein a portion of the semiconductor substrate located between the recessed isolation regions forms a protruding semiconductor fin; forming a gate dielectric extending over the isolation region; and forming a gate electrode over the gate dielectric. In an embodiment, the silicon-containing liner includes crystalline silicon. In an embodiment, the method further includes: depositing a silicon oxide layer extending into the trench before the silicon-containing liner is deposited, wherein the silicon-containing liner includes amorphous silicon. In an embodiment, oxidizing the silicon-containing liner is performed using a process gas selected from the group consisting of oxygen (O2), water vapor, and combinations thereof. In an embodiment, the silicon-containing liner is oxidized after the dielectric material is deposited.

[0058] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0059] Example 1. A method includes:

[0060] etching a semiconductor substrate to form a trench and a semiconductor strip, wherein sidewalls of the semiconductor strip are exposed to the trench;

[0061] depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on sidewalls of the semiconductor strip;

[0062] filling the trench with a dielectric material, wherein the dielectric material is on sidewalls of the silicon-containing layer;

[0063] oxidizing the silicon-containing layer to form a first liner, wherein the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form some portions of an isolation region; and

[0064] Indent the isolation region, wherein a portion of the semiconductor strip that protrudes above the top surface of the isolation region forms a semiconductor fin.

[0065] Example 2. The method according to Example 1, further comprising: depositing a silicon oxide layer in contact with the sidewalls of the semiconductor strip before the silicon-containing layer is deposited.

[0066] Example 3. The method according to Example 2, wherein the silicon oxide layer is in contact with the silicon-containing layer.

[0067] Example 4. The method according to Example 1, wherein the silicon-containing layer is oxidized after the dielectric material is deposited.

[0068] Example 5. The method according to Example 1, wherein the dielectric material is deposited as a flowable material, and the flowable material is solidified by the step of oxidizing the silicon-containing layer.

[0069] Example 6. The method according to Example 1, wherein the silicon-containing layer is completely oxidized to silicon oxide.

[0070] Example 7. The method according to Example 1, wherein the silicon-containing layer has a thickness greater than about 0.5 nm.

[0071] Example 8. The method according to Example 1, wherein the silicon-containing layer is deposited using atomic layer deposition.

[0072] Example 9. A method, comprising:

[0073] Etching a semiconductor substrate to form a semiconductor strip and a trench, wherein the semiconductor strip is located on one side of the trench and has a first longitudinal direction parallel to a second longitudinal direction of the trench, wherein the semiconductor strip comprises silicon and germanium, and sidewalls of the semiconductor strip are exposed;

[0074] Depositing a first liner that extends into the trench and contacts the sidewalls of the semiconductor strip, wherein the first liner comprises silicon oxide;

[0075] Depositing a second liner on the first liner, wherein the second liner comprises silicon, and the second liner extends from a top surface of the semiconductor substrate to a bottom of the trench;

[0076] Depositing a dielectric material to fill the trench, wherein a portion of the second liner is located under the dielectric material;

[0077] Solidifying the dielectric material to form an oxide layer; and

[0078] Converting the second liner to a third liner.

[0079] Example 10. The method according to Example 9, wherein the first liner has a thickness in the range of from about to about .

[0080] Example 11. The method according to Example 9, wherein the second liner has a thickness greater than about 0.5 nm.

[0081] Example 12. The method according to Example 9, wherein the second liner comprises amorphous silicon or polycrystalline silicon.

[0082] Example 13. The method according to Example 9, wherein curing the dielectric material and converting the second liner are performed by the same annealing process.

[0083] Example 14. The method according to Example 9, further comprising:

[0084] depressing the first liner, the second liner, and the oxide layer; and

[0085] forming a gate stack extending over the depressed first liner, second liner, and oxide layer.

[0086] Example 15. The method according to Example 9, wherein the second liner is completely converted to silicon oxide.

[0087] Example 16. A method comprising:

[0088] depositing a silicon-containing liner into a trench in a semiconductor substrate;

[0089] oxidizing the silicon-containing liner to a first oxidized silicon liner such that a volume ratio of the first oxidized silicon liner to the silicon-containing liner is greater than 0 and not greater than 2.25;

[0090] depositing a dielectric material into the trench, wherein the first oxidized silicon liner includes a first portion located under the dielectric material, and the dielectric material and the first oxidized silicon liner form an isolation region;

[0091] depressing the isolation region, wherein a portion of the semiconductor substrate located between the depressed insulating regions forms a protruding semiconductor fin;

[0092] forming a gate dielectric extending over the isolation region; and

[0093] forming a gate electrode over the gate dielectric.

[0094] Example 17. The method according to Example 16, wherein the silicon-containing liner comprises crystalline silicon.

[0095] Example 18. The method according to Example 16 further includes: depositing a silicon oxide layer extending into the trench before the silicon-containing liner is deposited, wherein the silicon-containing liner includes amorphous silicon.

[0096] Example 19. The method according to Example 16, wherein oxidizing the silicon-containing liner is performed using a process gas selected from the group consisting of oxygen (O2), water vapor, and combinations thereof.

[0097] Example 20. The method according to Example 16, wherein the silicon-containing liner is oxidized after the dielectric material is deposited.

Claims

1. A method for forming a semiconductor device, comprising: etching a semiconductor substrate to form trenches and semiconductor strips, wherein sidewalls of the semiconductor strips are exposed to the trenches; depositing a silicon-containing layer extending into the trenches, wherein sidewall portions of the silicon-containing layer are on the sidewalls of the semiconductor strips; filling the trenches with a dielectric material, wherein the dielectric material is on the sidewalls of the silicon-containing layer; oxidizing the silicon-containing layer to form a first liner, wherein an entire upper portion of the sidewall portions is oxidized, a lower portion of the sidewall portions remains as a semiconductor layer including silicon, the first liner includes oxidized silicon, and wherein the first liner and the dielectric material form some portions of an isolation region; and recessing the isolation region, wherein portions of the semiconductor strips protruding above a top surface of the isolation region form semiconductor fins.

2. The method according to claim 1 further comprises: Before the silicon-containing layer is deposited, an oxide layer in contact with the sidewalls of the semiconductor strips is deposited.

3. The method according to claim 2, wherein, The oxide layer is in contact with the silicon-containing layer.

4. The method according to claim 1, wherein, The silicon-containing layer is oxidized after the dielectric material is deposited.

5. The method according to claim 1, wherein The dielectric material is deposited as a flowable material, and the flowable material is solidified by the step of oxidizing the silicon-containing layer.

6. The method according to claim 1, wherein An entire upper portion of the sidewall portions of the silicon-containing layer is completely oxidized to silicon oxide.

7. The method according to claim 1, wherein The silicon-containing layer has a thickness greater than 0.5 nm.

8. The method according to claim 1, wherein, The silicon-containing layer is deposited using atomic layer deposition.

9. A method for forming a semiconductor device, comprising: etching a semiconductor substrate to form semiconductor strips and trenches, wherein the semiconductor strips are on one side of the trenches and have a first longitudinal direction parallel to a second longitudinal direction of the trenches, wherein the semiconductor strips include silicon and germanium, and sidewalls of the semiconductor strips are exposed; depositing a first liner, the first liner extending into the trenches and in contact with the sidewalls of the semiconductor strips, wherein the first liner includes silicon oxide; depositing a second liner on the first liner, wherein the second liner includes silicon, and the second liner includes: sidewall portions extending from a top surface of the semiconductor substrate to a bottom of the trenches, wherein the sidewall portions include an upper portion and a lower portion below the upper portion; and a bottom portion located at the bottom of the trenches and connected to the lower portion of the sidewall portions; depositing a dielectric material to fill the trenches, wherein a portion of the second liner is under the dielectric material; solidifying the dielectric material to form an oxide layer; and converting the second liner to a third liner, wherein an entire upper portion of the sidewall portions of the second liner is oxidized, and the lower portion remains as a silicon layer.

10. The method according to claim 9, wherein The first inner lining has a thickness within the range between and .

11. The method according to claim 9, wherein, The second liner has a thickness greater than 0.5 nm.

12. The method according to claim 9, wherein, The second liner includes amorphous silicon or polycrystalline silicon.

13. The method according to claim 9, wherein Solidifying the dielectric material and converting the second liner are performed by the same annealing process.

14. The method according to claim 9, further comprising: recessing the first liner, the second liner, and the oxide layer; and Form a gate stack that extends over the recessed first liner, second liner, and oxide layer.

15. The method according to claim 9, wherein, The second liner is completely converted to silicon oxide.

16. A method for forming a semiconductor device, comprising: Depositing a silicon-containing liner into a trench in a semiconductor substrate, wherein the silicon-containing liner includes a horizontal portion and a vertical portion, the horizontal portion is below the vertical portion and connected to the vertical portion, and the horizontal portion includes a top surface; Oxidizing the entire top of the silicon-containing liner into a first oxidized silicon liner such that the volume ratio of the first oxidized silicon liner to the volume of the silicon-containing liner is greater than 0 and not greater than 2.25, wherein the lowermost end of the top is higher than the top surface of the horizontal portion, and the bottom of the silicon-containing liner remains after the oxidation; Depositing a dielectric material into the trench, wherein the first oxidized silicon liner includes a first portion located below the dielectric material, and the dielectric material and the first oxidized silicon liner form an isolation region; Recessing the isolation region, wherein a protruding semiconductor fin is formed in a portion of the semiconductor substrate located between the recessed insulating regions; Forming a gate dielectric that extends over the isolation region; and Forming a gate electrode over the gate dielectric, wherein the silicon-containing liner is oxidized after the dielectric material is deposited.

17. The method according to claim 16, wherein, The silicon-containing liner includes crystalline silicon.

18. The method according to claim 16, further comprising: Before the silicon-containing liner is deposited, a silicon oxide layer that extends into the trench is deposited, wherein the silicon-containing liner includes amorphous silicon.

19. The method according to claim 16, wherein, Oxidizing the silicon-containing liner is performed using a process gas selected from the group consisting of oxygen (O2), water vapor, and combinations thereof.

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