Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method for manufacturing the semiconductor structure comprising: providing a substrate, the substrate having a first region and a second region arranged adjacently; forming a plurality of grooves in the first region and the second region of the substrate, the plurality of grooves being arranged at intervals along a first direction. Forming a word line in the groove, the characteristic size of the word line in the first region is different from the characteristic size of the word line in the second region. Forming a contact structure on the word line with a larger characteristic size. The present invention can reduce the difficulty of setting the contact structure, reduce the contact resistance at the connection between the contact structure and the word line, ensure the stability of the connection between the two, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] A dynamic random access memory includes a plurality of repeated memory cells, each of which generally includes a capacitor and a transistor, wherein the gate of the transistor is connected to a word line (WL), the drain is connected to a bit line, and the source is connected to a capacitor. The voltage signal on the word line can control the opening or closing of the transistor, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor through the bit line for storage. The word line is connected to a word line driver through a contact structure (LICON) located in the peripheral area of ​​the memory cell, so that the word line driver can input a voltage signal into the word line.

[0004] However, as the feature size of DRAM devices continues to shrink, the spacing between adjacent word lines decreases, resulting in increased difficulty in setting up the contact structure and increased contact resistance. In addition, open circuits and short circuits are prone to occur at the contact structure, affecting the storage performance of semiconductor memory. Summary of the invention

[0005] In order to solve at least one of the problems mentioned in the background technology, the present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure, which can reduce the difficulty of setting up a contact structure, reduce the contact resistance at the connection between the contact structure and the word line, ensure the stability of the connection between the two, and improve the performance of the semiconductor structure.

[0006] In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate having a first region and a second region disposed adjacent to each other.

[0008] A plurality of grooves are formed in the first region and the second region of the substrate, and the plurality of grooves are arranged at intervals along a first direction.

[0009] Word lines are formed in the trenches, wherein a characteristic size of the word lines in the first region is different from a characteristic size of the word lines in the second region.

[0010] A contact structure is formed on the word line with a larger feature size.

[0011] The manufacturing method of the semiconductor structure provided by the present invention forms a plurality of mutually independent grooves in a substrate. In the process of groove formation, the characteristic size of the grooves in the first region is different from the characteristic size of the grooves in the second region because the structural density of the first region is different from the structural density of the second region. Therefore, when a word line is formed in the groove, the characteristic size of the word line in the first region can be ensured to be different from the characteristic size of the word line in the second region. The contact structure is arranged on the word line with a larger characteristic size, thereby reducing the difficulty of arranging the contact structure on the word line, and at the same time increasing the contact area between the word line and the contact structure, improving the connection stability between the two, reducing the contact resistance at the connection between the two, so as to ensure that the contact structure can stably connect the word line and the word line driver. The spacing between adjacent word lines in the region where the contact structure is located is large, so that the width of the contact structure can be appropriately increased, and at the same time, the short circuit between the contact structure and the adjacent word line can be avoided, so as to improve the stability of signal transmission between the two, thereby ensuring the performance of the semiconductor structure.

[0012] In the above-mentioned method for manufacturing a semiconductor structure, optionally, a step of forming a plurality of trenches in both the first region and the second region of the substrate, wherein the plurality of trenches are arranged at intervals along the first direction, comprises:

[0013] A trench mask layer is formed on both the first region and the second region of the substrate, wherein the trench mask layer has a first trench mask pattern and a second trench mask pattern, and the first trench mask pattern and the second trench mask pattern are alternately arranged along a first direction.

[0014] The first and second regions of the substrate are etched using the first and second trench mask patterns to form first and second trenches in the first and second regions.

[0015] The etching rate of the first region of the substrate is greater than the etching rate of the second region of the substrate.

[0016] Such an arrangement can ensure the formation of trenches with different characteristic sizes, so as to facilitate the formation of word lines in the trenches.

[0017] In the above method for manufacturing a semiconductor structure, optionally, the first trench mask pattern has a first mask protrusion relative to the second trench mask pattern.

[0018] The second trench mask pattern has a second mask protrusion relative to the first trench mask pattern.

[0019] The first mask protrusion and the second mask protrusion are both located in the first area and at two opposite sides of the second area.

[0020] Such an arrangement can form a first trench and a second trench in the first region, respectively.

[0021] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the first trench mask pattern has the same characteristic size in the first region and the second region of the substrate.

[0022] The second trench mask pattern has the same feature size in the first region and the second region of the substrate.

[0023] Such a configuration can reduce the difficulty of preparing the trench mask layer.

[0024] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the etching rate is an etching rate of the substrate in the first direction.

[0025] The characteristic size of the first trench in the first region is greater than the characteristic size of the first trench in the second region.

[0026] The characteristic size of the second trench in the first region is greater than the characteristic size of the second trench in the second region.

[0027] Such an arrangement can form a word line with a larger characteristic size in the first region, and form a word line with a smaller characteristic size in the second region.

[0028] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the step of forming a word line in the trench includes:

[0029] A first word line is formed in the first trench.

[0030] A second word line is formed in the second trench.

[0031] The first word lines and the second word lines are alternately arranged along a first direction.

[0032] Such an arrangement can form a first word line and a second word line, which are alternately arranged to form a word line structure in the first region and the second region.

[0033] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the step of forming a contact structure on a word line having a larger characteristic size includes:

[0034] A first contact structure is formed on a first word line in the first region.

[0035] A second contact structure is formed on the second word line of the first region.

[0036] The first contact structure and the second contact structure are respectively located at two opposite sides of the second region.

[0037] Such a configuration reduces the difficulty of configuring the first contact structure and the second contact structure in the first region due to the larger characteristic size of the word line in the first region, and simultaneously reduces the contact resistance between the contact structure and the word line.

[0038] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the first contact structures are arranged in a staggered manner along the first direction, and / or the second contact structures are arranged in a staggered manner along the first direction.

[0039] Such a configuration can increase the spacing between adjacent contact structures, thereby reducing the problem of signal interference.

[0040] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the etching gas in the etching process is sulfur fluoride gas, chlorine gas, difluoromethane, nitrogen gas and helium gas. Such a setting can achieve the purpose of controlling the etching rate of the etching process by adjusting the etching process parameters, thereby improving the controllability of the etching process.

[0041] In a second aspect, the present invention provides a semiconductor structure, comprising:

[0042] A substrate having a first region and a second region disposed adjacent to each other;

[0043] A word line, the word line is located in the first region and the second region; wherein a characteristic size of the word line in the first region is different from a characteristic size of the word line in the second region;

[0044] Contact structure: The contact structure is located on the word line with larger feature size.

[0045] The semiconductor structure provided by the present invention forms a plurality of word lines arranged at intervals along a first direction in a substrate, the characteristic size of the word lines in the first region is different from the characteristic size of the word lines in the second region, and a contact structure is provided on the word line with a larger characteristic size, so that the difficulty of providing the contact structure on the word line can be reduced, and at the same time, the contact area between the word line and the contact structure is increased, the connection stability between the two is improved, and the contact resistance at the connection between the two is reduced, so as to ensure that the contact structure can stably connect the word line and the word line driver, reduce the problem of signal interference between adjacent contact structures, and improve the stability of signal transmission between the two. The spacing between adjacent word lines in the region where the contact structure is located is large, so that the short circuit between the word line and the word line driver can be reduced, thereby ensuring the performance of the semiconductor structure.

[0046] In the above semiconductor structure, optionally, a characteristic size of the word line in the first region is greater than a characteristic size of the word line in the second region.

[0047] Such a configuration can reduce the difficulty of configuring a contact structure on the word line in the first region.

[0048] In the above semiconductor structure, optionally, a characteristic size of the word line in the first region is less than 1.5 times a characteristic size of the word line in the second region.

[0049] Such a configuration can avoid the problem of short circuit between adjacent word lines.

[0050] In the above semiconductor structure, optionally, the word line includes a first word line and a second word line.

[0051] The first word lines and the second word lines are alternately arranged along a first direction.

[0052] The first word line has a first word line protrusion relative to the second word line, the second word line has a second word line protrusion relative to the first word line, and the first word line protrusion and the second word line protrusion are respectively located at two opposite sides of the second region.

[0053] Such a configuration can facilitate the formation of word lines with larger characteristic dimensions in the first region, and facilitate the subsequent configuration of contact structures.

[0054] In the above semiconductor structure, optionally, the contact structure includes a first contact structure located on the first word line protrusion in the first region and a second contact structure located on the second word line protrusion in the first region.

[0055] The first contact structures are arranged in a staggered manner along a first direction.

[0056] The second contact structures are arranged in a staggered manner along the first direction.

[0057] Such a configuration can increase the spacing between adjacent contact structures and reduce the problem of signal interference.

[0058] In the above semiconductor structure, optionally, a width of the first contact structure is not less than a width of a first word line in the first region, and a length of the first contact structure is not greater than a length of the first word line in the first region.

[0059] And / or, the width of the second contact structure is not less than the width of the second word line of the first region, and the length of the second contact structure is not greater than the length of the second word line of the first region.

[0060] Such a setting can ensure that the contact metal layer of the contact structure is in electrical contact with the metal layer of the word line, realize signal transmission between the two, and can reduce the difficulty of setting the contact structure, reduce the contact resistance at the connection between the contact structure and the word line, and ensure the stability of the connection between the two.

[0061] In the above semiconductor structure, optionally, the characteristic size range of the first word line and / or the second word line in the second region is 6-30nm, the characteristic size range of the first word line and / or the second word line in the first region is 10-60nm, and the characteristic size range of the first contact structure and / or the second contact structure is 10-80nm.

[0062] The construction of the present invention and other objects and advantageous effects thereof will become more apparent through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 A schematic diagram of the structure of word lines and bit lines in a semiconductor structure of the related art;

[0065] Figure 2 A schematic diagram of a word line and a contact structure in a semiconductor structure of the related art;

[0066] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0067] Figure 4 A schematic diagram of a process for forming a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0068] Figure 5 A schematic diagram of a process for forming a trench mask layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0069] Figure 6 A schematic diagram of a process of etching a substrate along a trench mask layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0070] Figure 7 A schematic diagram of a process of forming a word line in a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0071] Figure 8 A schematic diagram of a process of forming a contact structure in a word line in a peripheral region of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0072] Fig. 9 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0073] Fig.10 A schematic structural diagram of a word line of a semiconductor structure provided by an embodiment of the present invention;

[0074] Fig.11 A schematic structural diagram of a trench mask layer of a semiconductor structure provided by an embodiment of the present invention;

[0075] Fig.12 A schematic diagram of a structure in which a groove is formed on a substrate of a semiconductor structure provided by an embodiment of the present invention;

[0076] Fig.13 A schematic diagram of a structure for forming a word line in a trench of a semiconductor structure provided by an embodiment of the present invention;

[0077] Fig.14 A schematic diagram of the structure of a word line in a trench of a semiconductor structure provided by an embodiment of the present invention;

[0078] Fig.15 A cross-sectional view of a semiconductor structure provided by an embodiment of the present invention in a first cutting direction;

[0079] Fig.16 A cross-sectional view of a semiconductor structure provided by an embodiment of the present invention in a second cutting direction;

[0080] Fig.17 A schematic diagram of the structure of a single word line in the peripheral region of a semiconductor structure provided by an embodiment of the present invention;

[0081] Fig.18 A schematic diagram of a structure for forming a contact opening on a word line in a peripheral region of a semiconductor structure provided by an embodiment of the present invention;

[0082] Fig.19 A schematic diagram of a structure in which a contact structure is formed on a word line in a peripheral region of a semiconductor structure provided by an embodiment of the present invention.

[0083] Description of reference numerals:

[0084] 10-substrate; 11-array region; 12-peripheral region; 20-trench mask layer; 21-trench mask pattern;

[0085] 211 - first array trench mask pattern; 212 - second array trench mask pattern;

[0086] 213 - first peripheral trench mask pattern; 214 - second peripheral trench mask pattern;

[0087] 30-groove; 31-first array groove; 32-second array groove; 33-first peripheral groove;

[0088] 34 - second peripheral groove; 40 - word line; 41 - first word line; 411 - first word line protrusion;

[0089] 42 - second word line; 421 - second word line protrusion; 43 - first dielectric layer; 44 - word line metal layer;

[0090] 45 - second dielectric layer; 46 - interlayer dielectric layer; 40a - blank word line; 50 - contact structure;

[0091] 51 - contact opening; 52 - contact metal layer; 60 - active area; 70 - bit line; 80 - connection metal layer. DETAILED DESCRIPTION

[0092] The inventors of the present application have found in the actual research process that the current dynamic random access memory includes a plurality of repeated storage cells, each of which generally includes a capacitor and a transistor, the gate of the transistor is connected to a word line (Word line, referred to as WL), the drain is connected to a bit line, and the source is connected to a capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor for storage through the bit line. The word line is connected to the word line driver through a contact structure (Local interconnect contact, referred to as LICON) located in the peripheral area of ​​the storage cell, so that the word line driver can input a voltage signal into the word line. Figure 1 The diagram is a schematic diagram of the structure of word lines and bit lines in a semiconductor structure of the related art. Figure 2 FIG. 1 is a schematic diagram of a word line and a contact structure in a semiconductor structure of the related art. Figure 1 and Figure 2 As shown, the current semiconductor memory is generally provided with a substrate, on which word lines 40 and bit lines 70 are sequentially arranged, and the word lines 40 and bit lines 70 are arranged alternately. Figure 1 The first direction L1 is arranged at intervals.

[0093] Among them, active areas 60 arranged in an array are provided on the substrate, and the active areas 60 form an array area 11, such as the area within the dotted line in the figure, and a peripheral area 12 is formed around the array area 11. The active areas 60 are connected to the word lines 40 and the bit lines 70 respectively. A contact structure 50 is generally provided on the word lines 40 in the peripheral area 12, so as to electrically connect the word lines 40 to the word line driver. The first word lines 41 and the second word lines 42 in the current word lines 40 are alternately spaced along the first direction, and the widths of the first word lines 41 and the second word lines 42 in the active area 60 and in the peripheral area 12 are the same, and the spacing between adjacent word lines 40 (that is, the spacing between the first word lines 41 and the second word lines 42) is Figure 2 a0 shown in . As the feature size of DRAM devices continues to shrink, the spacing between adjacent word lines 40 decreases, that is, a0 decreases, which will reduce the space around the word line 40. During the setting process of the contact structure 50, the alignment accuracy requirement of the contact opening 51 and the word line 40 increases accordingly, which leads to an increase in the difficulty of setting the contact structure 50. In addition, since the width of the word line in the peripheral area 12 is small, the contact area between the contact structure 50 and the word line is small, so the contact resistance at the connection between the contact structure 50 and the word line increases accordingly, making it easy for the connection between the contact structure 50 and the word line to be broken or short-circuited. Furthermore, even after the contact structure 50 is set on the word line, the problem of signal interference is easy to occur due to the small spacing between adjacent contact structures 50, thereby affecting the storage performance of the semiconductor memory.

[0094] In view of this, the manufacturing method of the semiconductor structure provided by the embodiment of the present invention forms a plurality of mutually independent grooves in the substrate. During the groove formation process, based on the structural density of the first region being different from the structural density of the second region, the characteristic size of the grooves in the first region is different from the characteristic size of the grooves in the second region. Then, by adjusting the process conditions, when forming word lines in the grooves, it is possible to ensure that the characteristic size of the word lines in the first region is different from the characteristic size of the word lines in the second region. That is, the characteristic size of the word lines in the peripheral region is greater than the characteristic size of the word lines in the array region, and the word lines in the peripheral region with larger characteristic sizes are provided with contact structures, thereby reducing the difficulty of providing the contact structures on the word lines in the peripheral region, and at the same time increasing the contact area between the word lines and the contact structures, improving the connection stability between the two, and reducing the contact resistance at the connection between the two, so as to ensure that the contact structures can stably connect the word lines and the word line drivers, reduce the occurrence of short circuits and disconnections between the two, and improve the stability of signal transmission between the two, thereby ensuring the performance of the semiconductor structure.

[0095] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present invention will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present invention. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present invention, not all of them. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limitations on the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The embodiments of the present invention are described in detail below in conjunction with the drawings.

[0096] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present invention. Figure 4 A schematic diagram of a process for forming a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 5 A schematic diagram of a process of forming a trench mask layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 6 A schematic diagram of the process of etching a substrate along a trench mask layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 7 A schematic diagram of a process of forming a word line in a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 8 A schematic diagram of a process of forming a contact structure in a word line in a peripheral region of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Fig. 9 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention. Fig.10 A schematic structural diagram of a word line of a semiconductor structure provided by an embodiment of the present invention. Fig.11 A schematic structural diagram of a trench mask layer of a semiconductor structure provided in an embodiment of the present invention. Fig.12 A schematic diagram of a structure in which a groove is formed on a substrate of a semiconductor structure provided in an embodiment of the present invention. Fig.13 A schematic diagram of a structure in which a word line is formed in a trench of a semiconductor structure provided by an embodiment of the present invention. Fig.14 A schematic structural diagram of a word line in a trench of a semiconductor structure provided by an embodiment of the present invention. Fig.15 A cross-sectional view of a semiconductor structure provided in a first cutting direction according to an embodiment of the present invention. Fig.16 A cross-sectional view of a semiconductor structure provided in a second cutting direction according to an embodiment of the present invention. Fig.17 A schematic diagram of the structure of a single word line in the peripheral region of a semiconductor structure provided by an embodiment of the present invention. Fig.18 A schematic diagram of a structure in which a contact opening is formed on a word line in a peripheral region of a semiconductor structure provided by an embodiment of the present invention. Fig.19 A schematic diagram of a structure in which a contact structure is formed on a word line in a peripheral region of a semiconductor structure provided by an embodiment of the present invention.

[0097] Embodiment 1

[0098] Reference Figures 3 to 8 As shown, combined with Figures 9 to 19 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, referring to Figure 3 As shown, including:

[0099] S1: providing a substrate, wherein the substrate has a first region and a second region that are adjacently arranged.

[0100] S2: forming a plurality of grooves in both the first region and the second region of the substrate; wherein the plurality of grooves are arranged at intervals along the first direction.

[0101] S3: forming word lines in the trenches, wherein a characteristic size of the word lines in the first region is different from a characteristic size of the word lines in the second region.

[0102] S4: forming a contact structure on the word line with a larger feature size.

[0103] It should be noted that the semiconductor structure provided in this embodiment can generally be a semiconductor memory, and a plurality of active areas 60 arranged in an array will be provided on the substrate 10 of the semiconductor structure. The area where the plurality of active areas 60 are arranged forms an array area 11, and the position where the active area 60 is not provided on the periphery of the array area 11 forms a peripheral area 12, and the peripheral area 12 surrounds the periphery of the array area 11. A plurality of buried word lines 40 are provided on the substrate 10. Among them, the above-mentioned first area can correspond to the peripheral area 12, and the second area can correspond to the array area 11. The first area and the second area can be arranged side by side or in parallel adjacently, or the first area can surround the periphery of the second area, which is not limited here.

[0104] The formation of the word line 40 can be achieved through the above-mentioned steps 2 and 3. In step 2, a plurality of mutually independent grooves 30 are formed on the substrate 10, and the grooves 30 are sunk into the substrate 10. During the formation of the grooves 30, based on the pattern density loading effect, the characteristic size of the grooves 30 in the peripheral area 12 is larger than the characteristic size of the grooves 30 in the array area 11. Based on the size of the above-mentioned grooves 30, in step 3, the word lines 40 formed in the grooves 30 are distributed along the shape of the grooves 30, so that the characteristic size of the word lines 40 formed in the peripheral area 12 is larger than the characteristic size of the word lines 40 in the array area 11.

[0105] In step 4, the contact structure 50 is formed in the word line 40 of the peripheral region 12, so the contact area between the contact structure 50 and the word line 40 increases as the characteristic size of the word line 40 of the peripheral region 12 increases, thereby increasing the connection stability between the contact structure 50 and the word line 40 of the peripheral region 12 and reducing the contact resistance at the connection between the two to ensure that the contact structure 50 can stably connect the word line 40 and the word line driver to improve the stability of signal transmission between the two. Further, when the contact structure 50 is disposed in the peripheral region 12, refer to Figure 1 In the related art shown in FIG. 1 , the spacing between adjacent word lines 40 in the peripheral region is small, and the word lines 40 are arranged in a high density. Figure 3 In the structure shown in FIG. 1 , the spacing between adjacent word lines 40 in the peripheral region 12 is larger, and the arrangement density of the word lines 40 in the peripheral region 12 is smaller, which can reduce the short circuit between the contact structure 50 and the adjacent word lines 40, thereby ensuring the performance of the semiconductor structure.

[0106] Among them, refer to Figure 4 As shown, in step 2, a plurality of grooves are formed in both the first region and the second region of the substrate, and the plurality of grooves are arranged at intervals along the first direction, including:

[0107] S21: forming a trench mask layer on both the first region and the second region of the substrate, wherein the trench mask layer has a first trench mask pattern and a second trench mask pattern, and the first trench mask pattern and the second trench mask pattern are alternately arranged along a first direction.

[0108] S22: etching the first region and the second region of the substrate using the first trench mask pattern and the second trench mask pattern to form a first trench and a second trench in both the first region and the second region.

[0109] The etching rate of the first region of the substrate is greater than the etching rate of the second region of the substrate.

[0110] It should be noted that when forming the groove 30, the groove mask layer 20 may be firstly manufactured, and the substrate 10 may be etched along the groove mask pattern 21 of the groove mask layer 20, so as to form the groove 30 on the substrate 10. The etching method selected in the etching process may be dry etching or wet etching, such as plasma etching, laser etching and chemical liquid etching, etc., which is not limited in this embodiment. The first direction may be Fig. 9 The etching process includes the etching gas of sulfur fluoride gas, chlorine gas, difluoromethane, nitrogen gas and helium gas. The above-mentioned gases can physically collide with and chemically react with the substrate, respectively, so as to achieve etching of the substrate. In the multiple steps of the etching process, the types or proportions of gases used may be different. By adjusting the flow rate and flow velocity of the etching gas, the purpose of controlling the etching rate is achieved, thereby improving the controllability of the etching process.

[0111] The first trench mask pattern has a first mask protrusion relative to the second trench mask pattern, and the second trench mask pattern has a second mask protrusion relative to the first trench mask pattern. The first mask protrusion and the second mask protrusion are both located in the first region and at opposite sides of the second region.

[0112] In order to form the first mask protrusion and the second mask protrusion, refer to Figure 5 As shown, combined with Fig.11 As shown, in step 21, a trench mask layer is formed on both the first region and the second region of the substrate, the trench mask layer has a first trench mask pattern and a second trench mask pattern, and the first trench mask pattern and the second trench mask pattern are alternately arranged along the first direction, comprising:

[0113] S211: forming an array groove mask layer on the surface of the substrate in the second region, wherein the array groove mask layer has an array groove mask pattern, wherein the array groove mask pattern includes a plurality of first array groove mask patterns and a plurality of second array groove mask patterns, and the plurality of first array groove mask patterns and the plurality of second array groove mask patterns are alternately and spaced apart from each other along a first direction.

[0114] S212: A peripheral groove mask layer is formed on the surface of the substrate in the first region, the peripheral groove mask layer having a peripheral groove mask pattern, the peripheral groove mask pattern including a plurality of first peripheral groove mask patterns and a plurality of second peripheral groove mask patterns, the first peripheral groove mask pattern is located at a first end of the array groove mask pattern, the second peripheral groove mask pattern is located at a second end of the array groove mask pattern, the first end of the array groove mask pattern and the second end of the array groove mask pattern are respectively located on opposite sides of the second region.

[0115] It should be noted that the structure of the trench mask layer 20 can refer to Fig.11 As shown, a trench mask pattern 21 is formed on the trench mask layer 20. In this embodiment, the trench mask pattern 21 is divided into an array trench mask pattern located in the array area 11 and a peripheral trench mask pattern located in the peripheral area 12. The array trench mask pattern located in the array area 11 may include a plurality of first array trench mask patterns 211 and a plurality of second array trench mask patterns 212, and the plurality of array trench mask patterns 21 are arranged at intervals along the first direction, and there is a spacing between adjacent array trench mask patterns 21, and the spacing can be adjusted according to the spacing between adjacent word lines 40 formed in the end, and this embodiment is not limited to this. Among them, the first array trench mask pattern 211 can be a trench mask pattern arranged in odd rows, and correspondingly, the second array trench mask pattern 212 can be a trench mask pattern arranged in even rows, and the two are alternated and arranged at intervals.

[0116] Similar to the above array trench mask pattern, the peripheral trench mask pattern located in the peripheral area 12 may include a plurality of first peripheral trench mask patterns 213 and a plurality of second peripheral trench mask patterns 214, and the plurality of peripheral trench mask patterns are arranged at intervals along the first direction. The first peripheral trench mask pattern 213 and the second peripheral trench mask pattern 214 are respectively on opposite sides of the array area 11, and the first peripheral trench mask patterns 213 on the same side are arranged at intervals, and the second peripheral array mask patterns 214 on the same side are arranged at intervals.

[0117] The first peripheral trench mask pattern 213 is connected to the end of the first array trench mask pattern 211 located in the odd rows to form a first trench mask pattern, and the second peripheral array mask pattern 214 is connected to the end of the second array trench mask pattern 212 located in the even rows to form a second trench mask pattern. The first peripheral trench mask pattern 213 forms a first mask protrusion in the first trench mask pattern, and the second peripheral trench mask pattern 214 forms a second mask protrusion in the second trench mask pattern.

[0118] The first trench mask pattern has the same characteristic size in the first area and the second area of ​​the substrate 10. The second trench mask pattern has the same characteristic size in the first area and the second area of ​​the substrate 10. It should be noted that the above definition means that the characteristic size of the first array trench mask pattern 211 is equal to the characteristic size of the first peripheral trench mask pattern 213, and the characteristic size of the second array trench mask pattern 212 is equal to the characteristic size of the second peripheral trench mask pattern 214.

[0119] In actual use, the manufacturing method of the trench mask layer 20 can be selected from self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), and this embodiment does not limit this. The characteristic size of the first array trench mask pattern 211 and the first peripheral trench mask pattern 213 in the first trench mask pattern, and the characteristic size of the second array trench mask pattern 212 and the second peripheral trench mask pattern 214 in the second trench mask pattern 212 can be determined by the spacer in the etching process, so the above-mentioned limitation can reduce the difficulty of setting the spacer and help reduce the above-mentioned characteristic size. Of course, the manufacturing method of the groove mask layer 20 can also use photolithography. By adjusting the size of the photomask plate, the characteristic size of the first groove mask pattern and the second groove mask pattern can be limited. The above-mentioned limitation can also reduce the manufacturing difficulty of the photomask plate, and at the same time reduce the processing difficulty of optical proximity correction (OPC).

[0120] Further, refer to Figure 6 As shown, combined with Fig.12 As shown, in step 22, that is, the step of etching the substrate along the trench mask pattern, includes:

[0121] S221: etching the substrate along the array trench mask pattern, etching the substrate along the first array trench mask pattern to form a first array trench, and etching the substrate along the second array trench mask pattern to form a second array trench.

[0122] S222: etching the substrate along the peripheral trench mask pattern, etching the substrate along the first peripheral trench mask pattern to form a first peripheral trench, and etching the substrate along the second peripheral trench mask pattern to form a second peripheral trench.

[0123] The etching rate of the substrate 10 along the peripheral trench mask pattern is greater than the etching rate of the substrate 10 along the array trench mask pattern.

[0124] It should be noted that the structure of the groove 30 formed after etching can refer to Fig.12 As shown, based on the structure in which the active area 60 is provided in the array area 11, the structural density in the array area 11 is greater than the structural density in the peripheral area 12. According to the pattern density loading effect, in the etching process, the etching rate is lower in the area with a larger pattern density, and the etching rate is higher in the area with a smaller pattern density. Therefore, the etching rate of the substrate 10 in the peripheral trench mask pattern is higher, while the etching rate of the substrate 10 in the array trench mask pattern is lower, and the characteristic size of the first peripheral trench 33 and the second peripheral trench 34 finally formed is larger than the characteristic size of the first array trench 31 and the second array trench 32.

[0125] Among them, the etching rate is the etching rate of the substrate 10 in the first direction, that is, the etching rate in the groove width direction. The characteristic size of the first groove in the first region is greater than the characteristic size of the first groove in the second region, and the characteristic size of the second groove in the first region is greater than the characteristic size of the second groove in the second region. The above-mentioned first peripheral groove 33 and second peripheral groove 34 form the first groove in the first region, and the first array groove 31 and second array groove 32 form the second groove in the second region. That is, the etching rate of the first array groove 31 and the second array groove 32 in the array area 11 is less than the etching rate of the first peripheral groove 33 and the second peripheral groove 34 in the peripheral area 12.

[0126] The characteristic dimensions of the trench 30 may refer to the depth and width of the trench 30 .

[0127] In this embodiment, the pattern density loading effect mentioned above can be enhanced by controlling the parameters of the etching process, and the methods of adjusting the parameters may include but are not limited to the following methods: adjusting the etching power and the magnetic field strength, adjusting the etching gas composition, controlling the generation of etching by-products, adjusting the uniformity of etching in the array area and the peripheral area, controlling the ratio of chemical etching to physical etching, and controlling multiple etching steps.

[0128] Based on this, refer to Figure 7 As shown, combined with Figure 13 to Figure 14 As shown, in step 3, i.e., the step of forming a word line in the trench, the steps include:

[0129] S31: forming a first word line in a first trench.

[0130] S32: forming a second word line in the second trench.

[0131] The first word lines and the second word lines are alternately arranged along a first direction.

[0132] It should be noted that the word line 40 may be formed in the trench 30 by deposition. Based on the above-mentioned characteristic size of the trench 30, the shape and size of the word line 40 are limited by the trench 30. The word line 40 may include a first word line 41 and a second word line 42. The first word line 41 and the second word line 42 are alternately arranged. The first word line 41 may be located in an odd row, and the second word line 42 may be located in an even row. The first word line 41 may include a first word line protrusion 411 located in the peripheral area 12, and the second word line 42 may include a second word line protrusion 421 located in the peripheral area 12. The first word line protrusion 411 and the second word line protrusion 421 are respectively located on opposite sides of the array area 11. The characteristic size of the first word line protrusion 411 is greater than the characteristic size of the first word line 41 in the array area 11, and the characteristic size of the second word line protrusion 421 is greater than the characteristic size of the second word line 42 in the array area 11. The characteristic size of the word line 40 may refer to the thickness and width of the word line 40.

[0133] Combined with Fig.10 As shown, there is a spacing dimension a1 between adjacent first word line protrusions 411, and the spacing dimension a1 between adjacent first word line protrusions 421 can also be a1. The spacing dimension a1 is greater than Figure 2 The spacing dimension a0 between the adjacent first word lines 41 and the second word lines 42 in the related art.

[0134] Combination Fig.15 As shown, the word line 40 may include a second dielectric layer 45 formed in the trench 30, a word line metal layer 44 formed on the surface of the second dielectric layer 45, and a first dielectric layer 43 formed on the surface of the word line metal layer 44. Fig.16 As shown, an interlayer dielectric layer 46 is provided between the second dielectric layer 45 of the word line 40 and the substrate 10 to prevent the formation process of the word line 40 from affecting the structure of the active area 60 of the substrate 10. The word line metal layer 44 may be tungsten metal, the first dielectric layer 43 may be a silicon nitride layer, and the second dielectric layer 45 may be a silicon dioxide layer.

[0135] The word line 40 structure includes a first word line 41 and a second word line 42. The characteristic size of the first word line protrusion 411 is larger than the characteristic size of the first word line 41 in the array area, and the characteristic size of the second word line protrusion 421 is larger than the characteristic size of the second word line 42 in the array area. The first word line protrusion 411 of the first word line 41 can be distributed in the odd rows of the word line 40, and the second word line protrusion 421 of the second word line 42 can be distributed in the even rows of the word line 40. Therefore, compared with the related art Figure 1 The word line 40 structure in this embodiment has the following structural features and advantages:

[0136] 1) The distance between the adjacent first word line protrusions 411 and the adjacent second word line protrusions 421 is larger. The distance can be Fig.10 The part shown in a1 is compared with the related art Figure 1 The spacing a0 between the word lines 40 shown in the figure, the spacing a1 of the present embodiment is the spacing after removing the word lines 40 of the alternate rows (i.e., odd rows or even rows), so the spacing a1 is greater than the spacing a0. This arrangement can ensure that there is a larger space between adjacent word lines 40 in the peripheral area 12, so as to facilitate the arrangement of the contact structure 50 later.

[0137] 2) The characteristic size of the word line 40 in the peripheral area 12 is larger. The characteristic size may refer to the width and thickness of the word line 40. The width of the word line 40 in the peripheral area 12 may be Fig.14 Such a configuration can ensure that the contact area between the contact structure 50 and the word line 40 of the peripheral region 12 is larger, reduce the difficulty of electrical connection between the two, and improve the connection stability and signal transmission stability.

[0138] Further, refer to Figure 8 As shown, combined with Figures 16 to 19 As shown, in step 4, that is, the step of forming a contact structure on a word line with a larger feature size, includes:

[0139] S41: forming a first contact structure on a first word line in a first region.

[0140] S42: forming a second contact structure on the second word line in the first region.

[0141] The first contact structure and the second contact structure are respectively located at two opposite sides of the second region.

[0142] The above steps can be understood as forming a contact opening on the word line of the peripheral region, wherein the contact opening exposes the word line metal layer of the word line. The contact metal layer is filled in the contact opening, the contact metal layer abuts against the word line metal layer, and the contact metal layer forms a contact structure. Specifically, the first contact structure can be formed on the first word line protrusion 411, and the second contact structure can be formed on the second word line protrusion 421.

[0143] It should be noted that the contact structure 50 is located on the word line 40 in the peripheral area 12. Based on the increase in the characteristic size of the word line 40 in the peripheral area 12, the difficulty of setting the contact opening 51 in the peripheral area 12 will be reduced, and the contact opening 51 will expose more word line metal layer 44. Therefore, after the contact metal layer 52 is deposited, the contact area between the contact metal layer 52 and the word line metal layer 44 increases, thereby improving the stability of the electrical connection between the two and realizing signal transmission between the two. It should be pointed out that the contact structure 50 is connected to the word line driver through the connecting metal layer 80, and the connecting metal layer 80 is arranged in the peripheral area 12 of the substrate 10.

[0144] There are multiple first word line protrusions 411 and multiple second word line protrusions 421, and a contact structure 50 is disposed on each first word line protrusion 411 and each second word line protrusion 421. Fig. 9 As shown, based on the present embodiment, the spacing between adjacent word lines 40 in the peripheral region 12 is increased compared with that in the related art, and the spacing between the contact structures 50 on adjacent word lines 40 in the peripheral region 12 is correspondingly increased. In order to further ensure that the spacing between adjacent contact structures 50 is increased, the present embodiment arranges the contact structures 50 on the first word line protrusions 411 in an alternating manner along the first direction, and the contact structures 50 on the second word line protrusions 421 in an alternating manner along the first direction.

[0145] It should be noted that the staggered arrangement means that when two adjacent contact structures 50 are projected along the first direction, their projections do not completely overlap, or there is no overlapping portion at all, so as to minimize the degree of signal interference between adjacent contact structures 50.

[0146] Embodiment 2

[0147] Reference Figures 9 to 19 As shown, based on the above-mentioned embodiment 1, embodiment 2 of the present invention provides a semiconductor structure.

[0148] Specifically, the semiconductor structure includes a substrate 10 and a plurality of word lines 40 disposed on the substrate 10, the plurality of word lines 40 are arranged at intervals along a first direction, and the substrate 10 has a first region and a second region disposed adjacently. The first region may be a peripheral region 12, and the second region may be an array region 11. The above adjacent arrangement may be understood as the peripheral region 12 may surround the periphery of the array region 11, and the two may also be disposed in parallel or side by side.

[0149] The word line 40 includes a first word line 41 and a second word line 42, and the first word line 41 and the second word line 42 are arranged alternately. The first word line 41 has a first word line protrusion 411 relative to the second word line 42, and the second word line 42 has a second word line protrusion 421 relative to the first word line 41. The first word line protrusion 411 and the second word line protrusion 421 are respectively located at opposite sides of the second region, and are both located in the first region.

[0150] The characteristic size of the word line 40 in the first region is greater than that of the word line 40 in the second region. That is, the characteristic size of the first word line protrusion 411 is greater than that of the first word line 41 in the array region, and the characteristic size of the second word line protrusion 421 is greater than that of the second word line 42 in the array region.

[0151] Furthermore, a contact structure 50 is provided on the word line 40 with a larger characteristic size, and the contact structure 50 includes a first contact structure on the first word line 41 in the first region and a second contact structure on the second word line 42 in the first region. That is, the first contact structure is located on the first word line protrusion 411, and the second contact structure is located on the second word line protrusion 421.

[0152] It should be noted that, in this embodiment, referring to Fig. 9 As shown, the characteristic size of the word line 40 in the peripheral area 12 is greater than the characteristic size of the word line 40 in the array area 11, and the contact structure 50 is set on the word line 40 in the peripheral area 12, so that the difficulty of setting the contact structure 50 on the word line 40 in the peripheral area 12 can be reduced, and at the same time, the contact area between the word line 40 and the contact structure 50 is increased, the connection stability between the two is improved, and the contact resistance at the connection between the two is reduced to ensure that the contact structure 50 can stably connect the word line 40 and the word line driver to improve the stability of signal transmission between the two. The spacing between adjacent word lines 40 in the peripheral area 12 is increased, and the short circuit between the word line 40 and the word line driver is reduced, thereby ensuring the performance of the semiconductor structure.

[0153] Reference Fig.10As shown, the first word line 41 and the second word line 42 together form the word line 40, the first word line protrusion 411 is located at one end of the first word line 41 close to the peripheral area 12, and the second word line protrusion 421 is located at the other end of the second word line 42 close to the peripheral area 12. The first word line protrusion 411 and the second word line protrusion 421 are respectively located at opposite sides of the array area 11. The first word line protrusion 411 is located in the odd rows of the word line 40, that is, the 1st row, the 3rd row, and the 5th row, etc., and is located at one end of the first word line 41 in the odd row. The second word line protrusion 421 can be located in the even rows of the word line 40, that is, the 2nd row, the 4th row, and the 6th row, etc., and is located at the other end of the second word line 42 in the even row.

[0154] Specifically, the characteristic size of the word line 40 in the first region is less than 1.5 times the characteristic size of the word line 40 in the second region. Such a setting can prevent the characteristic size of the word line 40 in the peripheral region 12 from being too large, avoid reducing the distance between two adjacent word lines 40 in the peripheral region 12, and prevent the problem of short circuit when the distance between adjacent word lines 40 in the peripheral region 12 is too small.

[0155] Further, refer to Fig.10 As shown, the first contact structures are arranged in a staggered manner along the first direction. The second contact structures are arranged in a staggered manner along the first direction. There are multiple first contact structures located on the first word line protrusion 411, and there are multiple second contact structures located on the second word line protrusion 421. The multiple first contact structures and the multiple second contact structures are respectively located on opposite sides of the array area 11. The multiple first contact structures located on the same side of the array area 11 are arranged in a staggered manner along the first direction, and the multiple second contact structures located on the same side of the array area 11 are arranged in a staggered manner along the first direction. Such a setting can increase the spacing between adjacent contact structures 50 and reduce the problem of signal interference.

[0156] The width of the first contact structure is not less than the width of the first word line of the first region, and the length of the first contact structure is not greater than the length of the first word line of the first region. The width of the second contact structure is not less than the width of the second word line of the first region, and the length of the second contact structure is not greater than the length of the second word line of the first region.

[0157] It should be noted that the above definition can be understood as that the width of the contact structure 50 is not less than the width of the word line 40 in the peripheral region 12, that is, the width of the first contact structure is not less than the width of the first word line protrusion 411, and the width of the second contact structure is not less than the width of the second word line protrusion 421. The width of the contact structure 50 can be Fig.10In the portion shown by f, the appropriate increase in the width f of the contact structure 50 can reduce the difficulty of setting the contact structure 50, reduce the contact resistance at the connection between the contact structure 50 and the word line 42, and ensure the stability of the connection between the two. Such a setting can ensure the connection stability between the contact structure 50 and the word line 40 of the peripheral area 12, thereby ensuring the stability of the signal transmission of the word line 40. As an achievable implementation, the width range of the contact structure 50 is 10-80nm.

[0158] As an achievable implementation, the width of the word line 40 of the array area 11 ranges from 6 to 30 nm. The width of the word line 40 of the array area 11 can be Fig.14 The width of the word line 40 in the peripheral region 12 is in the range of 10-60 nm. The width of the word line 40 in the peripheral region 12 can be Fig.14 The part shown in b.

[0159] As an achievable implementation, the length of the word line 40 in the peripheral region 12 ranges from 90 nm to 350 nm. The length of the word line 40 in the peripheral region 12 can be Fig.10 The length of the contact structure 50 is not greater than the length of the word line 40 in the peripheral region 12, and the length of the contact structure 50 ranges from 90 to 350 nm. The length of the contact structure 50 can be Fig.10 The part shown in e.

[0160] Furthermore, in the present embodiment, blank word lines 40a are respectively provided at both ends of the word line 40 along the first direction. The blank word line 40a may be located at the outermost position of the plurality of word lines 40. The blank word line 40a is not used for the writing or reading process of storage data, but is used to imitate the word line 40 row structure in the semiconductor memory. The blank word line 40a may generally be used to provide reference and tracking signals for the driving circuit of the semiconductor memory.

[0161] In the above description, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0162] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first area and a second area adjacent to each other, the first area being a peripheral area of ​​the substrate, the second area being an array area of ​​the substrate, and the pattern density of the array area being higher than the pattern density of the peripheral area; A plurality of grooves are formed in both the first region and the second region of the substrate, and the plurality of grooves are arranged at intervals along a first direction, including: Forming a trench mask layer on both the first region and the second region of the substrate, wherein the trench mask layer has a first trench mask pattern and a second trench mask pattern, and the first trench mask pattern and the second trench mask pattern are alternately arranged along the first direction; Etching the first region and the second region of the substrate using the first trench mask pattern and the second trench mask pattern to form a first trench and a second trench in the first region and the second region, wherein an etching rate of etching the first region of the substrate is greater than an etching rate of etching the second region of the substrate; forming a word line in the trench, comprising: forming a first word line in the first trench; forming a second word line in the second trench; The characteristic size of the word lines in the first region is greater than the characteristic size of the word lines in the second region, and the first word lines and the second word lines are alternately arranged along the first direction; Forming a contact structure on the word line of the first region includes: forming a first contact structure on the first word line of the first region; forming a second contact structure on the second word line of the first region; Wherein, the first contact structure and the second contact structure are respectively located at two opposite sides of the second region; Wherein, the first contact structures are arranged in a staggered manner along a first direction, and / or the second contact structures are arranged in a staggered manner along the first direction; Wherein, the etching gas in the etching process for forming the plurality of grooves is sulfur fluoride gas, chlorine gas, difluoromethane, nitrogen gas and helium gas.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first trench mask pattern has a first mask protrusion relative to the second trench mask pattern; The second trench mask pattern has a second mask protrusion relative to the first trench mask pattern; The first mask protrusion and the second mask protrusion are both located in the first region and at two opposite sides of the second region.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The first trench mask pattern has the same feature size in the first region and the second region of the substrate; The second trench mask pattern has the same feature size in the first region and the second region of the substrate.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The etching rate is an etching rate of the substrate in a first direction; The characteristic size of the first trench in the first region is greater than the characteristic size of the first trench in the second region; A characteristic size of the second trench in the first region is greater than a characteristic size of the second trench in the second region.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: A characteristic size of the word line in the first region is less than 1.5 times a characteristic size of the word line in the second region.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The width of the first contact structure is not less than the width of the first word line of the first region, and the length of the first contact structure is not greater than the length of the first word line of the first region; And / or, a width of the second contact structure is not less than a width of the second word line in the first region, and a length of the second contact structure is not greater than a length of the second word line in the first region.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The first word line and / or the second word line in the second region have a characteristic size range of 6-30 nm, the first word line and / or the second word line in the first region have a characteristic size range of 10-60 nm, and the first contact structure and / or the second contact structure have a characteristic size range of 10-80 nm.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Two blank word lines are formed, the two blank word lines are respectively arranged on both sides of the word line along the first direction, the blank word lines are located at the edge of the word line, and the blank word lines are used to provide reference and tracking signals for the driving circuit of the semiconductor structure.

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