An improved single event upset tolerant flip-flop circuit and flip-flop

Abstract

The application discloses an improved structure anti-single event upset flip-flop circuit and a flip-flop, wherein the flip-flop circuit comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter in an electric circuit connection relationship. The application can solve the technical problem that the level of the prior art is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, and particularly relates to an improved structure anti-single event upset flip-flop circuit and flip-flop. BACKGROUND

[0002] In a radiation environment, the charged particles incident from outside can cause ionizing radiation to the digital circuit chip. A certain number of electron-hole pairs are generated around the trajectory of the particles. When the electron-hole pairs deposited along the incident direction of the particles are enough, the current caused by the electron-hole pairs collected by the depletion layer can cause the flip of the drain level, forming a single event upset.

[0003] The level occurring in the combinational logic unit is restored after the single event upset ends. When the particle upset occurs in the sequential logic unit (such as flip-flop) or the storage array, the upset is locked due to the existence of the internal feedback structure, the level cannot be restored, and the level of the circuit changes. SUMMARY

[0004] The embodiment of the present application provides an improved structure anti-single event upset flip-flop circuit and flip-flop, and solves the technical problem that the level is flipped and cannot be restored when the particle is incident on the circuit in the radiation environment in the prior art.

[0005] In one aspect, the embodiment of the present application provides a flip-flop circuit, which comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter, wherein:

[0006] The logic input circuit, the first main stage gate circuit and the first slave stage gate circuit are connected in sequence, the logic input circuit, the third main stage gate circuit and the third slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the second main stage gate circuit and the second slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the fourth main stage gate circuit and the fourth slave stage gate circuit are connected in sequence, the output terminals of the first main stage gate circuit, the second main stage gate circuit, the third main stage gate circuit and the fourth main stage gate circuit are connected with the main stage latch, and the output terminals of the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are connected with the slave stage latch;

[0007] The master level latch and the slave level latch each include a plurality of interlocking paths in an interlocking state with each other, and the interlocking paths are used to prevent the flip-flop circuit from level flip of feedback structure and being locked (unable to recover) when particles are incident in a radiation environment, resulting in a change in the output level of the flip-flop circuit.

[0008] Optionally, the logic input circuit, the first master level gate circuit, the master level latch, the first slave level gate circuit and the slave level latch form a first transmission channel, the logic input circuit, the third master level gate circuit, the master level latch, the third slave level gate circuit and the slave level latch form a third transmission channel, and the first transmission channel and the third transmission channel each correspond to the same signal transmission.

[0009] The logic input circuit, the first inverter, the second master level gate circuit, the master level latch, the second slave level gate circuit and the slave level latch form a second transmission channel, and the logic input circuit, the first inverter, the fourth master level gate circuit, the master level latch, the fourth slave level gate circuit and the slave level latch form a fourth transmission channel, and the second transmission channel and the fourth transmission channel each correspond to the same signal transmission.

[0010] The logic input circuit is configured to provide an input signal.

[0011] The first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each configured to perform signal transmission on the input signal according to an input clock signal.

[0012] Optionally,

[0013] When the clock signal is a low-level signal, the first master level gate circuit, the second master level gate circuit, the third master level gate circuit and the fourth master level gate circuit are opened respectively, and the first slave level gate circuit, the second slave level gate circuit, the third slave level gate circuit and the fourth slave level gate circuit are closed respectively, and the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each configured to perform signal transmission on the input signal and output a result signal transmitted at a previous transmission time.

[0014] Optionally,

[0015] When the clock signal is converted from low level to high level signal, i.e. clock rising edge, the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are opened respectively, and the first master stage gate circuit, the second master stage gate circuit, the third master stage gate circuit and the fourth master stage gate circuit are closed respectively, the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are used for signal transmission of the input signal respectively, and the result signal after signal transmission is output.

[0016] Optionally, the corresponding result signals of the first transmission channel and the third transmission channel are the same, the corresponding result signals of the second transmission channel and the fourth transmission channel are the same, and the corresponding result signals of the first transmission channel and the second transmission channel are opposite.

[0017] Optionally, the at least one inverter further comprises a second inverter and a third inverter, the second inverter is connected with the output end of the first slave stage gate circuit, and the third inverter is connected with the output end of the second slave stage gate circuit.

[0018] Optionally, the master stage latch and the slave stage latch comprise four interlocking paths in interlocking state, each of the interlocking paths comprises four series-connected transistors.

[0019] Optionally, the gate circuit comprises four series-connected transistors.

[0020] Optionally, the gate circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor and the second transistor are connected in series, the third transistor and the fourth transistor are connected in parallel, and an interconnection end after the series connection is connected with a connection end after the parallel connection.

[0021] In another aspect, an embodiment of the present application provides a flip-flop, which comprises the flip-flop circuit as described above.

[0022] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: the present application provides a flip-flop circuit, which includes a logic input circuit, a first main-stage gate circuit, a second main-stage gate circuit, a third main-stage gate circuit, a fourth main-stage gate circuit, a first slave-stage gate circuit, a second slave-stage gate circuit, a third slave-stage gate circuit, a fourth slave-stage gate circuit, a main-stage latch, a slave-stage latch and at least one inverter in a circuit connection relationship. The main-stage latch and the slave-stage latch are used to perform single event upset hardening on the circuit, to prevent single event effects from causing the output level of the circuit to change, that is, to resist single event upset. Thus, the technical problem that the level of the circuit is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment in the prior art is effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 is a structural schematic diagram of a GDICE hardened flip-flop circuit provided by the prior art.

[0025] Figure 2 is a structural schematic diagram of a latch in a GDICE hardened flip-flop circuit provided by the prior art.

[0026] Figure 3 is a structural schematic diagram of a flip-flop circuit provided by the embodiments of the present application.

[0027] Figure 4 is a working principle diagram of a flip-flop circuit provided by the embodiments of the present application.

[0028] Figure 5 (a)- Figure 5 (c) is a structural schematic diagram of several gate circuits provided by the embodiments of the present application.

[0029] Figure 6 is a structural schematic diagram of a latch hardened structure provided by the embodiments of the present application.

[0030] Figure 7 (a)- Figure 7 (d) is a logic input structural schematic diagram of several flip-flops provided by the embodiments of the present application.

[0031] Reference signs:

[0032] 11 - logic input circuit; 131 - first master stage gate circuit; 132 - second master stage gate circuit; 133 - third master stage gate circuit; 134 - fourth master stage gate circuit; 141 - first slave stage gate circuit; 142 - second slave stage gate circuit; 143 - third slave stage gate circuit; 144 - fourth slave stage gate circuit; 151 - master stage latch; 152 - slave stage latch; 12 - inverter; 15 - latch structure; 13 - gate circuit; 1 - first transistor; 2 - second transistor; 3 - third transistor; 4 - fourth transistor. DETAILED DESCRIPTION

[0033] The applicant has also found in the process of filing the present application that since the flip-flop is the most used timing device in digital circuits, the present application mainly aims at the hardening design of the single event upset effect of the flip-flop.

[0034] At present, the traditional flip-flop hardening scheme has a guard-gate double interlocking structure (GDICE), which is realized by adding a transmission channel and a storage node in the circuit and adopting an interlocking structure. The DICE is equivalent to a four-node storage unit, the input signal (also referred to as data) is written by two points, and the other two points are formed by feedback, finally forming a four-point interlocking structure. The GDICE structure adds a pair of guard gate structures to each storage node on the basis of the interlocking structure of the DICE structure. When the two inputs are different, the output is high impedance, so when a node has a flip-flop in the adjacent two points, the output remains unchanged.

[0035] Please refer to Figure 1 is a structural schematic diagram of a GDICE hardening flip-flop circuit provided by the prior art. As shown in the flip-flop circuit 100, it includes master and slave two-stage latch structures 15. The two-stage latch structures are the same, and are GDICE latches as shown in Figure 1 . The latches are realized by time-sharing control of the gate circuit to realize the latching of the clock signal in the high / low level stage. In the figure, c and cn are connected to the in-phase (c) and reverse (cn) ends of the clock signal CK circuit, respectively. The latch, as a structure with storage memory function in the flip-flop circuit, is the core of the single event upset hardening design of the flip-flop. Figure 2 Please refer to

[0036] is a structural schematic diagram of a GDICE hardening flip-flop circuit provided by the prior art. As shown in the flip-flop circuit 100, it includes master and slave two-stage latch structures 15. The two-stage latch structures are the same, and are GDICE latches as shown in Figure 2 . The latches are realized by time-sharing control of the gate circuit to realize the latching of the clock signal in the high / low level stage. In the figure, c and cn are connected to the in-phase (c) and reverse (cn) ends of the clock signal CK circuit, respectively. The latch, as a structure with storage memory function in the flip-flop circuit, is the core of the single event upset hardening design of the flip-flop. Figure 2

[0037] ​The working principle of the traditional GDICE hardened flip-flop circuit is as follows: first, data is copied into two paths, which are respectively controlled by clock signals to be transmitted to two input nodes of a latch, transmitted to two main stage output nodes through a main stage hardened latch feedback loop, and then respectively controlled by clock signals to be transmitted to a slave stage latch, transmitted to an output through a slave stage hardened latch feedback loop.

[0038] As can be seen, the traditional hardened mode causes the data transmission speed to slow down due to the interlocking structure.

[0039] To solve the above problems, the embodiment of the application provides a flip-flop circuit, and the general idea is as follows: the flip-flop circuit comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter, wherein:

[0040] The logic input circuit, the first main stage gate circuit and the first slave stage gate circuit are connected in sequence, the logic input circuit, the third main stage gate circuit and the third slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the second main stage gate circuit and the second slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the fourth main stage gate circuit and the fourth slave stage gate circuit are connected in sequence, and the output ends of the first main stage gate circuit, the second main stage gate circuit, the third main stage gate circuit and the fourth main stage gate circuit are connected with the main stage latch, and the output ends of the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are connected with the slave stage latch.

[0041] The main stage latch and the slave stage latch each comprise a plurality of interlocking paths in an interlocking state, and the interlocking paths are used to prevent the output level of the flip-flop circuit from changing when particles in the flip-flop circuit are flipped.

[0042] In order to better understand the above technical solutions, the above technical solutions will be described in detail in combination with the drawings in the specification and specific embodiments.

[0043] First of all, the term "and / or" appearing in this paper is only a description of the association relationship between the associated objects, which means that there are three kinds of relationships, for example, A and / or B, which means that there are three kinds of situations, such as A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents an "or" relationship between the front and rear associated objects.

[0044] Please refer to Figure 3 is a structural schematic diagram of a flip-flop circuit provided by an embodiment of the present application. As shown in Figure 3 The flip-flop circuit 300 includes a logic input circuit 11, a first master stage gate circuit 131, a second master stage gate circuit 132, a third master stage gate circuit 133, a fourth master stage gate circuit 134, a first slave stage gate circuit 141, a second slave stage gate circuit 142, a third slave stage gate circuit 143, a fourth slave stage gate circuit 144, a master stage latch 151, a slave stage latch 152, and at least one inverter 12, wherein:

[0045] The logic input circuit 11, the first master stage gate circuit 131, and the first slave stage gate circuit 141 are connected in sequence, the logic input circuit 11, the third master stage gate circuit 133, and the third slave stage gate circuit 143 are connected in sequence, the logic input circuit 11, a first inverter 121 of the at least one inverter, the second master stage gate circuit 132, and the second slave stage gate circuit 142 are connected in sequence, the logic input circuit 11, the first inverter 121 of the at least one inverter, the fourth master stage gate circuit 134, and the fourth slave stage gate circuit 144 are connected in sequence, the output terminals of the first master stage gate circuit 131, the second master stage gate circuit 132, the third master stage gate circuit 134, and the fourth master stage gate circuit 134 are connected to the master stage latch 151, and the output terminals of the first slave stage gate circuit 141, the second slave stage gate circuit 142, the third slave stage gate circuit 143, and the fourth slave stage gate circuit 144 are connected to the slave stage latch 152.

[0046] As shown in the figure, the logic input circuit 11, the first master stage gate circuit 131, the master stage latch 151, the first slave stage gate circuit 141, and the slave stage latch 152 form a first transmission channel, also referred to as a first transmission path, which is shown as transmission channel a1. The logic input circuit 11, the third master stage gate circuit 133, the master stage latch 151, the third slave stage gate circuit 143, and the slave stage latch 152 form a third transmission channel, also referred to as a third transmission path, which is shown as transmission channel a2. The first transmission channel and the third transmission channel each correspond to the same signal transmission, in other words, the signals transmitted by the two transmission channels are completely identical.

[0047] The logic input circuit 11, the first inverter 121, the second main stage gate circuit 132, the main stage latch 151, the second slave stage gate circuit 142 and the slave stage latch 152 form a second transmission channel, also called a second transmission path, which is shown as transmission channel b1. The logic input circuit 11, the first inverter 121, the fourth main stage gate circuit 134, the main stage latch 151, the fourth slave stage gate circuit 144 and the slave stage latch 152 form a fourth transmission channel, also called a fourth transmission path, which is shown as transmission channel b2. The second transmission channel and the fourth transmission channel each correspond to the same signal transmission, that is, the signals transmitted by the two transmission channels are exactly the same.

[0048] In the figure, the c and cn ends are respectively connected to clock signals, and cn represents the reverse signal corresponding to the input clock signal, which can be specifically referred to as the clock signal circuit CK shown in Figure 1 The logic input circuit is used to provide an input signal; the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each used to transmit the input signal according to an input clock signal.

[0049] The application Figure 3 The reinforced flip-flop circuit is an improved circuit of a conventional GDICE reinforced flip-flop circuit, which still comprises main and slave stage latches. Taking the main stage latch as an example, first, the input signal (also called data) is processed into two-way inverted data "1" and "0", and then four-way data "1010" is obtained through copying. The four-way data is respectively transmitted to four nodes INOUT1, INOUT2, INOUT3 and INOUT4 (that is, the input / output ends of 151 in the figure) of the latch by clock signals, and is controlled to be transmitted to the slave stage latch in time. The transmission mode of the slave stage latch is the same as that of the main stage, which will not be repeated here.

[0050] In actual application, taking a GDICE reinforced edge type (rising edge) D flip-flop as an example, please refer to Figure 4 The working principle diagram of an improved structure GDICE flip-flop circuit is shown. The figure is divided into the following two working stages:

[0051] Phase one: When the input clock signal is low signal (the dotted line is the starting point and the solid line is the ending point in the figure), the first main stage gate circuit 131, the second main stage gate circuit 132, the third main stage gate circuit 133 and the fourth main stage gate circuit 134 are opened, at this time, the main stage latch 151 is in the data signal transmission state, the input signal (also called data) is transmitted into the main stage output terminals INOUT31 and INOUT33 through the first transmission channel and the third transmission channel (the transmission channels a1 and a2 in the figure) respectively, and the input signal (also called data) is transmitted into the main stage output terminals INOUT32 and INOUT34 through the second transmission channel and the fourth transmission channel (the transmission channels b1 and b2 in the figure) respectively. At the same time, the input signal is transmitted into the main stage latch 151 (i.e. the main stage GDICE). At the same time, the first slave stage gate circuit 141, the second slave stage gate circuit 142, the third slave stage gate circuit 143 and the fourth slave stage gate circuit 144 are closed, the slave stage latch 152 (i.e. the slave stage GDICE) is in the data signal latching state (four-way interlocking), and the slave stage output terminals INOUT41, INOUT42, INOUT43 and INOUT44 maintain the result signal output at the last stage / previous time.

[0052] Phase two: When the input clock signal is converted from low level to high level signal, i.e. the clock rising edge (the solid line in the figure), the first slave stage gate circuit 141, the second slave stage gate circuit 142, the third slave stage gate circuit 143 and the fourth slave stage gate circuit 144 are opened, the slave stage latch 152 is in the data signal transmission state, the result signals output from the main stage output terminals INOUT31 and INOUT33 are transmitted into the slave stage output terminals INOUT41 and INOUT43 respectively through the first transmission channel and the third transmission channel (the transmission channels a1 and a2 in the figure) respectively, and are transmitted into the slave stage latch 152 (i.e. the slave stage GDICE). The result signals output from the main stage output terminals INOUT32 and INOUT34 are transmitted into the slave stage output terminals INOUT42 and INOUT44 respectively through the second transmission channel and the fourth transmission channel (the transmission channels b1 and b2 in the figure) respectively, and are transmitted into the slave stage latch 152 (i.e. the slave stage GDICE). At this time, the first main stage gate circuit 131, the second main stage gate circuit 132, the third main stage gate circuit 133 and the fourth main stage gate circuit 134 are closed, the main stage latch 151 (i.e. the main stage GDICE) is in the data signal latching state (four-way interlocking), and the main stage output terminals INOUT31, INOUT32, INOUT33 and INOUT34 maintain the result signal output at the last stage / previous time.

[0053] It should be noted that the above two stages complete a data signal transmission process from the input end to the output end of the circuit. Among them, the data signals transmitted by the first transmission channel and the third transmission channel (i.e. transmission channels a1 and a2) are completely consistent. The data signals transmitted by the second transmission channel and the fourth transmission channel (i.e. transmission channels b1 and b2) are completely consistent. The working principles of the two groups of transmission channels are consistent, and only the output result signal levels are opposite. The "reverse" in the figure refers to the opposite levels.

[0054] In an optional embodiment, the control ends of the master stage gate circuit and the slave stage gate circuit are reversed (c and cn are exchanged), that is, transformed into a falling edge D flip-flop.

[0055] In an optional embodiment, the at least one inverter 12 further includes a second inverter 122 and a third inverter 123. One end of the second inverter 122 is connected to the output end of the first slave stage gate circuit 141, and the other end of the second inverter 122 is an output end Qn of the entire flip-flop circuit. One end of the third inverter 123 is connected to the output end of the second slave stage gate circuit 142, and the other end of the third inverter 123 is another output end Q of the entire flip-flop circuit.

[0056] In an optional embodiment, please refer to Figure 5 (a)- Figure 5 (c) shows the structure of several possible gate circuits. Please refer to Figure 5 (a) is a symbol diagram of a gate circuit. In a specific embodiment, the gate circuit involved in the embodiments of the present application includes four transistors in series, for example, MOS transistors, as shown in Figure 5 (b). Among them, IN represents the input end of the gate circuit, and OUT represents the output end of the gate circuit. OEN and OE are connected to a pair of phase-opposed clock signals, OEN is connected to the inverse signal of the clock signal (also represented as cn), and OE is connected to the same direction signal of the clock signal (also represented as c); or OEN is connected to the same direction signal of the clock signal (c), and OE is connected to the inverse signal of the clock signal (cn).

[0057] In another specific embodiment, the gate circuit involved in the present application includes four transistors, namely a first transistor 1, a second transistor 2, a third transistor 3 and a fourth transistor 4. Among them, the first transistor 1 and the second transistor 2 are connected in series, and then connected in series with a combined device formed by the third transistor 3 and the fourth transistor 4 in parallel. In other words, an interconnection end after the series connection is connected to a connection end after the parallel connection, as shown in Figure 5 (c).

[0058] In an optional embodiment, the latch (particularly the master latch 151 or the slave latch 152) according to the present application is a latch with a hardened structure, which is used to prevent the level of the feedback structure of the entire flip-flop circuit from being flipped and locked (unable to recover) when particles are incident in a radiation environment, resulting in a change in the output level of the flip-flop circuit.

[0059] In an optional embodiment, the latch (particularly the hardened structure in the latch) includes a plurality of interlocking paths in an interlocking state with each other. In practical applications, the latch hardened structure usually includes four interlocking paths in an interlocking state with each other, and each of the interlocking paths includes four series-connected transistors. Please refer to Figure 6 A structure diagram of a GDICE latch hardened structure according to an embodiment of the present application is shown. As shown in the figure, Figure 6 The hardened structure includes four interlocking paths in an interlocking state with each other, and each of the interlocking paths includes four series-connected transistors, and there are a total of 16 transistors, which are connected in an interlocking manner by using the interlocking topology structure shown in the figure. Compared with the two-input and two-output structure of the conventional GDICE latch shown in the figure, Figure 2 As shown in the figure, the four storage nodes in the new GDICE latch are both inputs and outputs, and data is directly transmitted by the four channels of the flip-flop at the same time, without passing through the feedback structure of the master and slave latches, which can accelerate the transmission speed of the data signal.

[0060] It should be noted that the flip-flop circuit provided by the present application is an improved GDICE hardened flip-flop circuit, and the principle thereof is similar to that of the conventional GDICE structure. When a node on the feedback structure is flipped due to single particle incidence, the levels of the two adjacent nodes are restored after the ionizing radiation ends by the interlocking function. Moreover, compared with the conventional GDICE hardened flip-flop, data is directly transmitted by the four paths / channels at the same time, without passing through the feedback loop of the master and slave latches, which can improve the circuit speed.

[0061] The present application also provides a flip-flop, which includes the flip-flop circuit according to any one of the embodiments of the present application. Figures 3-6 The flip-flop includes but is not limited to an edge-type D flip-flop, a synchronous reset D flip-flop, a D scan flip-flop, a synchronous reset scan flip-flop, an RS flip-flop, or other types of flip-flops, etc.

[0062] For example, please refer to Figure 7 (a)- Figure 7 (d) shows the logic input structure diagrams of several possible flip-flops. Among them, Figure 7 (a) represents a D flip-flop, Figure 7 (b) represents a synchronous reset D flip-flop, Figure 7 (c) represents a D scan flip-flop, Figure 7(d) represents a synchronous reset scan D flip-flop.

[0063] The application is also applicable to anti-single event upset of other timing circuits such as latch circuits.

[0064] The one or more technical solutions provided in the embodiments of the application have at least the following technical effects or advantages:

[0065] The application provides a flip-flop circuit, which comprises a logic input circuit, a first main-stage gate circuit, a second main-stage gate circuit, a third main-stage gate circuit, a fourth main-stage gate circuit, a first slave-stage gate circuit, a second slave-stage gate circuit, a third slave-stage gate circuit, a fourth slave-stage gate circuit, a main-stage latch, a slave-stage latch and at least one inverter in a circuit connection relationship. The main-stage latch and the slave-stage latch are used to perform single event upset hardening on the circuit, so as to prevent the circuit output level from being changed due to the single event upset effect, that is, to resist single event upset. Thus, the technical problem that the level is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment in the prior art is effectively solved.

[0066] Although preferred embodiments of the application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to cover all changes and modifications falling within the scope of the application.

[0067] Obviously, those skilled in the art can make various modifications and variations to the application without departing from the spirit and scope of the application. Thus, if these modifications and variations of the application fall within the scope of the claims of the application and equivalent technologies thereof, the application is also intended to include these modifications and variations.

Claims

1. An improved structure single event upset trigger circuit, comprising: The trigger circuit comprises a logic input circuit, a first primary stage gate circuit, a second primary stage gate circuit, a third primary stage gate circuit, a fourth primary stage gate circuit, a first secondary stage gate circuit, a second secondary stage gate circuit, a third secondary stage gate circuit, a fourth secondary stage gate circuit, a primary stage latch, a secondary stage latch, and at least one inverter, wherein: The logic input circuit, the first primary stage gate circuit, and the first secondary stage gate circuit are connected in sequence, the logic input circuit, the third primary stage gate circuit, and the third secondary stage gate circuit are connected in sequence, the logic input circuit, a first inverter of the at least one inverter, the second primary stage gate circuit, and the second secondary stage gate circuit are connected in sequence, the logic input circuit, a first inverter of the at least one inverter, the fourth primary stage gate circuit, and the fourth secondary stage gate circuit are connected in sequence, the output terminals of the first primary stage gate circuit, the second primary stage gate circuit, the third primary stage gate circuit, and the fourth primary stage gate circuit are connected to the primary stage latch, and the output terminals of the first secondary stage gate circuit, the second secondary stage gate circuit, the third secondary stage gate circuit, and the fourth secondary stage gate circuit are connected to the secondary stage latch. The primary stage latch and the secondary stage latch each comprise a plurality of interlocking paths in an interlocking state, and the interlocking paths are used to prevent the trigger circuit from being flipped and locked when particles are incident in a radiation environment, so as to cause the output level of the trigger circuit to change.

2. The circuit of claim 1, wherein, The logic input circuit, the first primary stage gate circuit, the primary stage latch, the first secondary stage gate circuit, and the secondary stage latch form a first transmission channel, the logic input circuit, the third primary stage gate circuit, the primary stage latch, the third secondary stage gate circuit, and the secondary stage latch form a third transmission channel, and the first transmission channel and the third transmission channel each correspond to the same signal transmission. The logic input circuit, the first inverter, the second primary stage gate circuit, the primary stage latch, the second secondary stage gate circuit, and the secondary stage latch form a second transmission channel, the logic input circuit, the first inverter, the fourth primary stage gate circuit, the primary stage latch, the fourth secondary stage gate circuit, and the secondary stage latch form a fourth transmission channel, and the second transmission channel and the fourth transmission channel each correspond to the same signal transmission. The logic input circuit is configured to provide an input signal. The first transmission channel, the second transmission channel, the third transmission channel, and the fourth transmission channel are each configured to perform signal transmission on the input signal according to an input clock signal.

3. The circuit of claim 2, wherein When the clock signal is a low level signal, the first master stage gate circuit, the second master stage gate circuit, the third master stage gate circuit and the fourth master stage gate circuit are opened respectively, and the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are closed respectively, the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are used for signal transmission of the input signal respectively, and the result signal transmitted at a previous transmission time is outputted.

4. The circuit of claim 2, wherein, When the clock signal is converted from a low level to a high level signal, the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are opened respectively, and the first master stage gate circuit, the second master stage gate circuit, the third master stage gate circuit and the fourth master stage gate circuit are closed respectively, the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are used for signal transmission of the input signal respectively, and the result signal after the signal transmission is outputted.

5. A circuit according to claim 3 or 4, characterised in that, The corresponding result signals of the first transmission channel and the third transmission channel are the same, the corresponding result signals of the second transmission channel and the fourth transmission channel are the same, and the corresponding result signals of the first transmission channel and the second transmission channel are opposite.

6. The circuit of claim 1, wherein, The at least one inverter further comprises a second inverter and a third inverter, the second inverter is connected with the output end of the first slave stage gate circuit, and the third inverter is connected with the output end of the second slave stage gate circuit.

7. The circuit of claim 1, wherein, The master stage latch and the slave stage latch comprise four interlocking paths in an interlocking state, each of the interlocking paths comprises four series-connected transistors.

8. The circuit of claim 1, wherein, The gate circuit comprises four series-connected transistors.

9. The circuit of claim 1, wherein, The gate circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor and the second transistor are connected in series, the third transistor and the fourth transistor are connected in parallel, and an interconnection end after the series connection is connected with a connection end after the parallel connection.

10. A flip-flop, characterized by comprising: The flip-flop comprises the improved structure anti-single event upset flip-flop circuit in any one of claims 1-9.

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