Spike-timing-dependent plasticity weight update method for memristors

Abstract

The present invention discloses a spike timing-related plasticity weight updating method applicable to a memristor. The change in the conductance value of the memristor is calculated according to a preset pulse sequence, and then applied to the memristor to update the conductance value of the memristor; specifically, each pulse signal in the pulse sequence is first processed to obtain the voltage of the spike pulse signal input to the memristor, and then the change in the conductance value of the memristor is simulated according to the voltage difference of the spike pulse signal at both ends of the memristor, and the change in the conductance value of the memristor is applied to the memristor to achieve weight update. Compared with the traditional weight updating method, the present invention has two significant advantages: it enables the pulse neural network to achieve a higher recognition accuracy and lower power consumption during the training process.

Description

Technical Field

[0001] The invention relates to an internal processing method in the field of memristors, in particular to a spike timing-related plasticity weight updating method applicable to memristors. Background Art

[0002] The spiking neural network is a third-generation neural network whose input and output information is encoded by spike sequences. The spiking neural network is very suitable for brain-like chips, and it is closer to the characteristics of the human brain neural network than the second-generation neural network that relies on activation functions and gradient descent algorithms.

[0003] Different types of supervised and unsupervised spiking neural network algorithms have been proposed, among which unsupervised learning algorithms based on spike timing-dependent plasticity have attracted much attention. Spike timing-dependent plasticity is a biological feature of synapses connecting different neurons, which describes the relationship between the strength of synaptic connections and the spikes generated by pre- and post-synaptic neurons, enabling spiking neural networks to be trained and learned.

[0004] The conductance of a memristor can be adjusted according to the voltage across its two electrodes, so it can act as an artificial synapse to achieve spike timing-dependent plasticity. Brain-like chips based on a crossbar array of memristors can achieve in-memory computing, which is more efficient than chips based on traditional semiconductor devices.

[0005] Many researchers have studied spike timing-dependent plasticity weight update methods based on memristor crossbar arrays, but the transmission signals targeted by the existing methods are mostly simplified to square wave signals rather than spike pulse signals. The performance of spike timing-dependent plasticity weight update methods for spike pulse signals is often not verified by circuit simulation, or the circuit scale targeted is too small. Summary of the invention

[0006] Aiming at the shortcomings of the existing spike timing-related plasticity weight update method, the present invention proposes a spike timing-related plasticity weight update method suitable for memristors. The method targets spike pulse signals and is suitable for large-scale circuits. Circuit simulation verification shows that the method has the advantages of high recognition accuracy and low power consumption compared with traditional methods.

[0007] The technical solution of the present invention is as follows:

[0008] The method mainly includes spike timing related plasticity weight update target and the implementation of spike timing related plasticity weight update target at the hardware level.

[0009] The method is directed to a brain-like chip memristor array, which is composed of a plurality of memristor arrays arranged according to a neural network chip architecture of rows and columns.

[0010] Set the following spike timing-dependent plasticity weight update target, expressed as:

[0011]

[0012] Δt=t1-t2

[0013] Wherein, Δt represents the time difference between the pulse input at the data input side of the memristor and the pulse input at the data output side of the memristor, Δw represents the change in the conductance value of the memristor under the action of the two pulses, and τ pre and τ post Respectively represent the positive time constant and the negative time constant, A pre Represents the positive amplitude, A post represents the negative amplitude, and k represents the offset.

[0014] The forward time constant τ pre and negative time constant τ post are all positive numbers, A pre is a positive constant, A post is a negative constant, and k is a positive constant. That is, when Δt tends to positive infinity, Δw is less than 0; when Δt is less than 0, Δw is always less than 0.

[0015] The synapse described in the present invention refers to a single memristor.

[0016] The memristor receives pulse signals from both the data input side and the data output side, and the pulse signals are peak pulse signals.

[0017] The implementation method of the spike timing-related plasticity weight update target at the hardware level is based on a memristor and a specific spike pulse signal. The conductance value of the memristor changes with the voltage difference across the memristor, simulating the synaptic weight.

[0018] According to the preset pulse sequence, the change in the conductance value of the memristor is calculated in the following manner, and then applied to the memristor to update the conductance value of the memristor:

[0019] Each pulse signal in the pulse sequence is first processed according to the following formula to obtain the voltage of the spike pulse signal input to the memristor, which is expressed by the following formula:

[0020]

[0021] Among them, A mp + and A mp - are the positive and negative amplitude values ​​of the pulse signal, respectively, t ail + and t ail- are the positive and negative time lengths of the pulse signal, τ + and τ - are the positive and negative time constants of the pulse signal; spk(t) represents the voltage of the pulse signal at time t;

[0022] Then, according to the voltage difference of the spike pulse signal at both ends of the memristor, the change in the conductance value of the memristor is simulated according to the following formula, and the conductance value of the memristor changes with the voltage difference at both ends:

[0023]

[0024] v MR =spk1(t1)-spk2(t2)

[0025] Among them, v MR Represents the voltage across the memristor, v th + and v th - Represent the positive and negative voltage thresholds at which the conductance of the memristor changes, G0 and v o + and v o - are the first, second and third characteristic parameters of the memristor; f(v MR ) represents the change in the conductance value of the memristor; spk1(t1) represents the voltage of the pulse signal input from the data input side of the memristor at time t1, and spk2(t2) represents the voltage of the pulse signal input from the data output side of the memristor at time t2. The pulse signal input from the data input side and the pulse signal input from the data output side have different timings. t represents the timing of the peak pulse signal. When the amplitude value of the peak pulse signal is zero, t=0;

[0026] Thereby, the change in the conductance value of the memristor is applied to the memristor to achieve weight update.

[0027] The first, second and third characteristic parameters G0, v o + and v o - All of them are trained in advance using unsupervised learning.

[0028] The relationship between the positive and negative voltage thresholds of the memristor model used satisfies:

[0029] The relationship between the positive and negative amplitude values ​​of the spike pulse signal used and the positive and negative voltage thresholds of the memristor satisfies:

[0030]

[0031]

[0032] The spike pulse signal only includes one spike located above the amplitude value of zero and one spike located below the amplitude value of zero.

[0033] In a specific implementation, the voltage difference across the memristor is expressed as:

[0034] v MR (t,Δt)=spk(t)-spk(t+Δt)

[0035] Among them, t represents the time when a signal is input to the front end of the memristor, and t+Δt represents the time when a signal is input to the back end of the memristor.

[0036] The total amount of change in the memristor conductance is obtained by integration:

[0037] Δw(Δt)=∫f(v MR (t,Δt))dt

[0038] This formula is approximately consistent with the spike timing-related plasticity weight update method proposed in the present invention through parameter fitting of the memristor and the pulse signal.

[0039] The present invention can actually be defined in a spiking neural network code through differential equations and can be implemented on a memristor crossbar array by using a specific spike pulse signal.

[0040] The beneficial effects of the present invention are:

[0041] Compared with the traditional spike timing-dependent plasticity updating method, the proposed invention has significant advantages:

[0042] 1. The pulse neural network of the present invention can achieve a higher recognition accuracy after training;

[0043] Second, the corresponding brain-like chip memristor cross array of the present invention has lower power consumption during training;

[0044] 3. The corresponding brain-like chip memristor cross array of the present invention is less affected by static voltage drop and parasitic current during training, and therefore has better circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram of the method of the present invention;

[0046] Figure 2 A schematic diagram of the present invention and the traditional updating method implemented by a memristor and a spike pulse signal;

[0047] Figure 3 This is a schematic diagram of the memristor array of the brain-like chip;

[0048] Figure 4 A comparison chart of the recognition accuracy of the present invention and the traditional updating method when applied to handwritten digit recognition;

[0049] Figure 5 This is a power comparison diagram between the present invention and the traditional updating method during the memristor array training process. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention and make the above-mentioned objects, features and advantages of the present invention clearer and easier to understand, the present invention is further described in detail below in conjunction with embodiments.

[0051] The embodiments fully implemented according to the content of the present invention are as follows:

[0052] like Figure 1 The figure shows a schematic diagram of the spike timing-dependent plasticity weight update method for memristors proposed in the present invention. The two curves represent the spike timing-dependent plasticity weight update target and the hardware-level fitting result, respectively. It can be seen that the update method proposed in the present invention can be approximately realized by fitting the memristor and the spike pulse signal. The schematic diagram of the present invention and the traditional update method implemented by the memristor and the spike pulse signal is shown in FIG. Figure 2 As shown, the four groups of figures from left to right represent the four conditions of the voltage at the front and rear ends of the memristor:

[0053] 1. The input side generates a pulse signal before the output side, the voltage difference between the two ends of the memristor is greater than the positive voltage threshold, and the conductance of the memristor will increase;

[0054] 2. After the input side generates a pulse signal on the output side, the voltage difference between the two ends of the memristor is less than the negative voltage threshold, and the conductance value of the memristor will decrease;

[0055] 3. The input side generates a pulse signal alone, and the conductance value of the memristor remains unchanged;

[0056] 4. The output side generates a pulse signal alone. In the updating method of the present invention, the voltage difference between the two ends of the memristor is less than the negative voltage threshold, and the conductance value of the memristor will decrease; while in the traditional updating method, the conductance value of the memristor remains unchanged at this time.

[0057] Based on memristor devices, a brain-like chip memristor array can be designed to train the spiking neural network based on the spike timing-related plasticity weight update method of the present invention and the traditional update method, so as to compare the performance of the two. Figure 3As shown. The task targeted by this embodiment is handwritten digit recognition, and the data set used is a large handwritten digit database (MNIST) collected and compiled by the National Institute of Standards and Technology of the United States. The data set contains 60,000 training set images, each of which contains 784 pixels, and the pixel value ranges from 0 to 255. Each pixel value is encoded as a 500-millisecond pulse sequence as input, and its pulse frequency is one-quarter of the pixel value Hertz, and satisfies the Poisson distribution. The pulse neural network training process is as follows: the size of the memristor array is 784×100, and 784 voltage pulse sequences are input from the input side. The output side integrates the received current, and after reaching the output side threshold, a pulse signal for external output and a pulse signal for reverse input are issued. The pulse input on the output side and the pulse on the input side work together to change the corresponding memristor conductance value, thereby achieving learning. The initial value of the conductance value of the memristor is normally distributed around 1 microSiemens, and its range of variation during the training process, that is, its maximum conductance value and minimum conductance value are 10 microSiemens and 0.1 microSiemens. The spike timing-related plasticity weight update target, that is, the corresponding pulse signal and the parameters of the memristor model are adjusted so that the final recognition rate reaches the highest. The final parameter values ​​trained based on the present invention and the traditional method are shown in Table 1.

[0058] Table 1

[0059]

[0060] The 60,000 training sets were trained three times, and the recognition rate was calculated once for each 10,000 sets of data. The recognition accuracy comparison between the two during 18 training iterations was obtained, as shown in the figure below: Figure 4 As shown. The memristor array based on the update method of the present invention achieved a handwritten digit recognition rate of 91.7%, while the memristor array based on the traditional update method achieved a recognition rate of 87.2%. The present invention improved the recognition rate by 4.5%. In addition, the power consumed by the memristor array training based on the update method of the present invention was 180.4 milliwatts, while the power consumed by the traditional method was 216.8 milliwatts. The present invention achieved a 16.8% power reduction.

[0061] Based on this embodiment, it can be seen that the spike timing-related plasticity update method of the present invention has two significant advantages over the traditional update method: the pulse neural network under the present invention can achieve a higher recognition accuracy after training; the corresponding brain-like chip memristor cross array of the present invention has lower power consumption during the training process. The advantages of the present invention mainly come from Figure 2The difference between the fourth case in the above example is that the memristor output side generates a pulse signal alone. In the updating method of the present invention, the voltage difference between the two ends of the memristor is less than the negative voltage threshold, and the memristor conductance value will decrease; while in the traditional updating method, the memristor conductance value remains unchanged at this time. This difference makes the conductance value of most memristors continue to decrease until it reaches the minimum conductance value when the updating method of the present invention is used, thereby highlighting the change characteristics of the conductance value of the remaining memristors and improving the recognition rate; and because the conductance value of most memristors decreases, that is, the resistance value increases, the power consumption of the memristor array is also lower when the input voltage signal is the same.

[0062] The above embodiments are implementation modes of the present invention, but the implementation modes of the present invention are not limited by the embodiments. Any other changes, modifications, substitutions, combinations and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope defined by the claims.

Claims

1. A spike timing-dependent plasticity weight updating method for a memristor, characterized in that: The method mainly includes spike timing-dependent plasticity weight update target and the implementation of spike timing-dependent plasticity weight update target at the hardware level; Set the following spike timing-dependent plasticity weight update target, expressed as: Wherein, Δt represents the time difference between the pulse input at the data input side of the memristor and the pulse input at the data output side of the memristor, Δw represents the change in the conductance value of the memristor under the action of the two pulses, and τ pre and τ post Respectively represent the positive time constant and the negative time constant, A pre Represents the positive amplitude, A post represents the negative amplitude, and k represents the offset; The memristor receives pulse signals from both the data input side and the data output side, and the pulse signals are spike pulse signals; According to the preset pulse sequence, the change in the conductance value of the memristor is calculated in the following manner, and then applied to the memristor to update the conductance value of the memristor: Each pulse signal in the pulse sequence is first processed according to the following formula to obtain the voltage of the spike pulse signal input to the memristor: Among them, A mp + and A mp - are the positive and negative amplitude values ​​of the pulse signal, respectively, t ail + and t ail - are the positive and negative time lengths of the pulse signal, τ + and τ - are the positive and negative time constants of the pulse signal; spk(t) represents the voltage of the pulse signal at time t; Then, according to the voltage difference of the spike pulse signal at both ends of the memristor, the change in the conductance value of the memristor is simulated according to the following formula: v MR =spk1(t1)-spk2(t2) Among them, v MR Represents the voltage across the memristor, v th + and v th - Respectively represent the positive and negative voltage thresholds at which the conductance value of the memristor changes, G0, vo+ and vo- are the first, second and third characteristic parameters of the memristor; f(v MR ) represents the change in the conductance value of the memristor; spk1(t1) represents the voltage of the pulse signal input from the data input side of the memristor at time t1, spk2(t2) represents the voltage of the pulse signal input from the data output side of the memristor at time t2, t represents the time of the peak pulse signal, and t=0 when the amplitude value of the peak pulse signal is zero; Thus, the change in the conductance value of the memristor is applied to the memristor to achieve weight update; The relationship between the positive and negative amplitude values ​​of the spike pulse signal used and the positive and negative voltage thresholds of the memristor satisfies:

2. A spike timing-dependent plasticity weight updating method applicable to a memristor according to claim 1, characterized in that: The method is directed to a brain-like chip memristor array, which is composed of multiple memristor arrays.

3. The method for updating spike timing-related plasticity weights applicable to a memristor according to claim 1, characterized in that: The relationship between the positive and negative voltage thresholds of the memristor model used satisfies:

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