Display panel and display device using the same

Abstract

The present disclosure relates to a display panel and a display device using the display panel. The display panel includes: a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are arranged; a first gate driver configured to provide a gate signal to a gate line connected to a pixel arranged in a first area of ​​the pixel array; and a second gate driver configured to receive a carry signal from the first gate driver and provide the gate signal to a gate line connected to a pixel arranged in a second area of ​​the pixel array. The second gate driver includes a signal transmission unit arranged in the pixel array to receive the carry signal from the first gate driver.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0145199, filed on November 3, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display panel that reproduces an image in a pixel array and a display device using the display panel. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include self-luminous organic light-emitting diodes (hereinafter referred to as "OLED"), and have the advantages of fast response speed and large luminous efficiency, brightness and viewing angle. In the organic light-emitting display device, OLED is formed in each pixel. The organic light-emitting display device has a fast response speed, excellent luminous efficiency, brightness and viewing angle, and has excellent contrast and color reproducibility because it can represent black grayscale in full black.

[0005] The multimedia functions of mobile terminals have been improved. For example, cameras are built into smartphones by default, and the resolution of cameras is increasing to the level of conventional digital cameras. The front camera of smartphones limits screen design, making screen design difficult. In order to reduce the space occupied by the camera, a screen design including a notch or a perforation is adopted in smartphones, but the screen size is still limited due to the camera, making it impossible to achieve full-screen display. Summary of the invention

[0006] In order to achieve full-screen display, the camera module can be set to overlap with the screen of the display panel. Compared with other normal display areas, some display areas of the screen overlapping with the camera module can increase their transmittance by reducing the resolution or pixels per inch (PPI). In this case, a brightness difference may occur between some display areas where the camera module is provided and the normal display area. In order to solve this problem, the brightness difference can be reduced by setting the data voltage differently between the areas of the screen (i.e., the pixel array), but the grayscale expression of each area may be different, and the grayscale expression may be degraded. In addition, in order to set the data voltage differently for each area of ​​the pixel array, a plurality of programmable gamma ICs (P-GMAICs) are used to set the gamma compensation voltage independently for each area, and therefore, the circuit cost increases.

[0007] The object of the present disclosure is to address the above-mentioned needs and / or problems.

[0008] The present disclosure provides a display panel capable of achieving full-screen display and uniform brightness over the entire full-screen display, and a display device using the display panel.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] A display panel according to an embodiment of the present disclosure includes: a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are arranged; a first gate driver configured to provide a gate signal to a gate line connected to a pixel arranged in a first region of the pixel array; and a second gate driver configured to receive a carry signal from the first gate driver and provide the gate signal to a gate line connected to a pixel arranged in a second region of the pixel array. The second gate driver includes a signal transmission unit arranged in the pixel array to receive the carry signal from the first gate driver.

[0011] The resolution or pixels per inch (PPI) of the first region and the second region may be different from each other. For example, the resolution or PPI of the second region may be lower than the resolution or PPI of the first region.

[0012] A display device according to an embodiment of the present disclosure includes: a display panel including a pixel array in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are arranged; a data voltage control unit configured to output a first voltage control data during a first scanning period of scanning a first area of ​​the pixel array and to output a second voltage control data during a second scanning period of scanning a second area of ​​the pixel array, the first voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the first area, the second voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the second area; a gamma compensation voltage generator configured to output a first gamma compensation voltage in response to the first voltage control data during the first scanning period of the first area, and and outputs a second gamma compensation voltage in response to second voltage control data during a second scanning period in the second area; a data driver configured to: during a first scanning period, convert pixel data into a first gamma compensation voltage to output a data voltage to be provided to pixels set in the first area, and during a second scanning period, convert pixel data into a second gamma compensation voltage to output a data voltage to be provided to pixels set in the second area; a first gate driver configured to provide a gate signal to a gate line connected to the pixels set in the first area during the first scanning period; and a second gate driver configured to receive a carry signal from the first gate driver during the second scanning period and provide the gate signal to the gate line connected to the pixels set in the second area.

[0013] According to the present disclosure, since the sensor is provided in the screen on which an image is displayed, full screen display can be achieved.

[0014] According to the present disclosure, the gamma compensation voltage output from the gamma compensation voltage generator is individually controlled for each of the high PPI area and the low PPI area to control the dynamic range of the data voltage applied to the pixel of the low PPI area to be greater than the dynamic range of the data voltage applied to the pixel of the high PPI area. As a result, in the present disclosure, the brightness difference between the high PPI area and the low PPI area can be reduced (e.g., minimized) to achieve uniform brightness characteristics across the entire screen.

[0015] Furthermore, according to the present disclosure, the dynamic range of the data voltage may be controlled differently for each region of the pixel array by using one programmable gamma IC.

[0016] According to the present disclosure, a brightness difference between regions having different PPIs may be reduced by increasing a voltage range of a data voltage applied to a low PPI region or increasing a channel ratio of a driving element disposed in a pixel of the low PPI region.

[0017] According to the present disclosure, by dispersively arranging at least some of the circuit elements of a gate driver constituting a gate line for driving a low PPI area in a pixel array, the increase in the border area of ​​the display panel can be reduced (for example, the increase in the border area is minimized) without reducing the transmittance of the low PPI area.

[0018] The effects that can be achieved by the present disclosure are not limited to the above-mentioned effects. That is, according to the following description, those skilled in the art to which the present disclosure belongs can clearly understand other purposes that are not mentioned. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1A and Figure 1B is a cross-sectional view schematically showing a display panel according to an embodiment of the present disclosure;

[0021] Figure 2 is a plan view showing an area in which a sensor module is provided in a screen of a display panel;

[0022] Figure 3 is a diagram showing pixel arrangement in a high PPI area;

[0023] Figure 4 is a diagram showing pixel arrangement in a low PPI area;

[0024] Figure 5 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0025] Figure 6 is a diagram showing an example in which a display device according to an embodiment of the present disclosure is applied to a mobile device;

[0026] Figure 7 is a diagram showing the brightness difference between regions due to PPI difference;

[0027] Figure 8 is a diagram showing one frame period of a display device;

[0028] Fig. 9 is a circuit diagram showing an example of a pixel circuit;

[0029] Fig.10 Is shown driving Fig. 9 A waveform diagram of the pixel circuit method shown;

[0030] Fig.11is a plan view schematically showing a channel of a driving element;

[0031] Fig.12 is a block diagram schematically illustrating a shift register of a gate driver;

[0032] Fig.13 It is shown Fig.12 The waveform diagram of the output signal and the control node voltage of the nth signal transmission unit shown;

[0033] Fig.14 is a block diagram showing a data voltage control unit;

[0034] Fig.15 is a circuit diagram showing a gamma compensation voltage generator according to an embodiment of the present disclosure;

[0035] Fig.16 is a diagram showing a gamma compensation voltage output from a gamma compensation voltage generator and a data voltage of each region;

[0036] Fig.17 is a diagram showing gate lines and gate drivers separated for each region of a pixel array;

[0037] Fig.18 and Fig.19 is a diagram showing a carry signal transmission path between gate drivers;

[0038] Fig. 20 is a diagram showing a scanning period for each area of ​​a pixel array and lookup table data selected according to the scanning period; and

[0039] Figure 21 to Figure 26 2 is a diagram showing various connection structures of a gate driver that drives a gate line in a low PPI region. DETAILED DESCRIPTION

[0040] The advantages and features of the present disclosure and the methods for achieving these advantages and features will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. However, this embodiment is provided to improve the present disclosure and to fully inform the scope of the present disclosure to those of ordinary skill in the art to which the present disclosure belongs, and the present disclosure is limited only by the scope of the claims.

[0041] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings for explaining the embodiments of the present disclosure are exemplary, and thus the present disclosure is not limited to the matters shown. The same reference numerals used herein refer to the same parts. In addition, when describing the present disclosure, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present disclosure, its detailed description will be omitted.

[0042] When terms such as "including", "having", and "consisting of" are used herein, other parts may be added unless "only" is used. In the case of expressing a component in the singular, it includes the case of including the plural unless otherwise specifically stated.

[0043] When interpreting a part, interpret it as including a margin of error even if it is not explicitly described.

[0044] In the case of describing a positional relationship, for example, if the positional relationship of two parts is described using terms such as "on," "above," "below," or "beside," unless "just" or "directly" is used, one or more other parts may be located between the two parts.

[0045] In the description of the embodiments, various components are described using first, second, etc., but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present disclosure, the first component mentioned below may be the second component.

[0046] Like reference numerals used herein refer to like parts.

[0047] The features of various embodiments may be coupled or combined with each other partially or in whole, and may be variously interlocked and driven technically, and the embodiments may be implemented independently of each other or together in a related relationship.

[0048] In the display device of the present disclosure, the pixel circuit and the gate driver may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, LTPS TFTs including low temperature polysilicon (LTPS), etc. Each of the transistors may be implemented as a p-channel TFT or an n-channel TFT.

[0049] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), because the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure will not be limited by the source and drain of the transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0050] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, and the transistor is turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH and VEH, and the gate-off voltage may be a gate low voltage VGL and VEL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL and VEL, and the gate-off voltage may be a gate high voltage VGH and VEH.

[0051] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Reference Figure 1A and Figure 2 The screen of the display panel 100 according to the embodiment of the present disclosure includes a pixel array that reproduces an input image. The pixel array includes a first area DA and a second area CA having different resolutions or pixels per inch (PPI).

[0053] The first area DA is a main display area occupying most of the screen. In the second area CA, pixels are arranged at a PPI lower than that of the first area DA and display pixel data.

[0054] One or more sensor modules SS1 and SS2 may be disposed at a lower portion of the rear surface of the display panel 100. The sensor modules SS1 and SS2 face the second area CA. The sensor modules SS1 and SS2 may include various sensors, such as, for example, an imaging module (or camera module) including an image sensor, an infrared sensor module, and a brightness sensor module. The sensor modules SS1 and SS2 perform photoelectric conversion on the light received through the second area CA to output an electrical signal. An image may be obtained from the output signals of the sensor modules SS1 and SS2. The second area CA may include a light-transmitting portion disposed at a portion obtained by lowering the PPI so as to increase the transmittance of light directed to the sensor modules SS1 and SS2.

[0055] Since the first area DA and the second area CA include pixels, the input image may be displayed in the first area DA and the second area CA.

[0056] like Figure 1B As shown, the pixel array may further include a third area SA. The resolution or PPI of the display pixels in the third area SA may be lower than the resolution or PPI of the first area DA, and may be the same as or different from the resolution or PPI of the second area CA. The third area SA displays pixel data in display mode. In the third area SA, in fingerprint recognition mode, a light sensor S is used to sense the user's fingerprint. The pixels R, G, and B of the third area SA may share at least some of the signal lines and power lines with the light sensor S. In the text, for convenience, the areas DA, CA, and SA of the pixel array may be referred to as "pixel arrays DA, CA, and SA."

[0057] Each of the pixels of the pixel arrays DA, CA, and SA includes sub-pixels having different colors to reproduce the color of an image. The sub-pixels include a red sub-pixel (hereinafter referred to as an "R sub-pixel"), a green sub-pixel (hereinafter referred to as a "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as a "B sub-pixel"). Although not shown, each pixel may also include a white sub-pixel (hereinafter referred to as a "W sub-pixel"). Each sub-pixel may include a pixel circuit that drives a light-emitting element.

[0058] The image quality compensation algorithm for compensating the brightness and color coordinates of the pixels may be applied to the second area CA and the third area SA having a lower PPI than that of the first area DA.

[0059] In the display device of the present disclosure, since the sensor module is disposed in the second area CA and the light sensor is embedded in the pixel array of the third area SA, full screen display may be achieved.

[0060] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a circuit layer 12 disposed on a substrate 10 and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and an encapsulating glass 20 may be disposed on the polarizing plate 18.

[0061] The circuit layer 12 may include pixel circuits connected to wirings such as data lines, gate lines, and power lines, and gate drivers connected to the gate lines. The circuit layer 12 may include transistors implemented as thin film transistors (TFTs) and circuit elements such as capacitors. The wiring and circuit elements of the circuit layer 12 may be implemented using multiple insulating layers, two or more metal layers separated by insulating layers interposed therebetween, and an active layer including a semiconductor material.

[0062] The light-emitting element layer 14 may include a light-emitting element driven by a pixel circuit. The light-emitting element may be implemented using an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the light-emitting layer EML to form excitons, and as a result, visible light is emitted from the light-emitting layer EML. The light-emitting element layer 14 may be disposed on pixels that selectively emit red wavelengths, green wavelengths, and blue wavelengths, and may also include a color filter array.

[0063] The light emitting element layer 14 may be covered by a passivation layer, and the passivation layer may be covered by an encapsulation layer. The passivation layer and the encapsulation layer may have a structure in which an organic film and an inorganic film are alternately stacked. The inorganic film prevents the penetration of moisture or oxygen. The organic film smoothes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen becomes longer than the movement path in a single layer, thereby effectively blocking the penetration of moisture / oxygen that affects the light emitting element layer 14.

[0064] The polarizing plate 18 may be adhered to the encapsulation layer. The polarizing plate 18 improves outdoor visibility of the display device. The polarizing plate 18 reduces light reflected from the surface of the display panel 100 and blocks light reflected from the metal of the circuit layer 12 to improve the brightness of the pixel. The polarizing plate 18 may be implemented as a polarizing plate in which a linear polarizing plate and a phase delay film are bonded, or as a circular polarizing plate.

[0065] Figure 3 is a diagram showing an example of pixel arrangement in a high PPI area. Figure 4 is a diagram showing an example of a pixel and a light-transmitting portion in a low PPI region. Figure 3 and Figure 4 , the wiring connected to the pixels is omitted.

[0066] Reference Figure 3 , the first area DA includes pixels PIX1 and PIX2 arranged with a high PPI. Each of the pixels PIX1 and PIX2 may be implemented as a real type pixel, in which an R sub-pixel, a G sub-pixel, and a B sub-pixel of three primary colors constitute one pixel. Each of the pixels PIX1 and PIX2 may also include a W sub-pixel omitted from the drawings.

[0067] Using the sub-pixel rendering algorithm, each pixel can be composed of two sub-pixels. For example, the first pixel PIX1 can be composed of an R sub-pixel and a first G sub-pixel, and the second pixel PIX2 can be composed of a B sub-pixel and a second G sub-pixel. The insufficient color representation in each of the first pixel PIX1 and the second pixel PIX2 can be compensated by the average value of the corresponding color data between adjacent pixels. White can be represented by combining the R sub-pixels, G sub-pixels and B sub-pixels of the first pixel PIX1 and the second pixel PIX2.

[0068] The pixels in the first area DA may be defined as unit pixel groups PG1 and PG2 having a predetermined size. The unit pixel groups PG1 and PG2 are pixel areas of a predetermined size including four sub-pixels. The unit pixel groups PG1 and PG2 are repeatedly arranged in a first direction (X axis), in a second direction (Y axis) perpendicular to the first direction, and in an inclined direction (θx axis and θy axis) between the first direction and the second direction. θx and θy respectively represent directions of inclined axes formed by rotating the X axis and the Y axis by 45°.

[0069] The unit pixel groups PG1 and PG2 may be a parallelogram-shaped pixel region PG1 or a rhombus-shaped pixel region PG2. The unit pixel groups PG1 and PG2 should be interpreted as including a rectangular shape, a square shape, or the like.

[0070] The sub-pixels of the unit pixel groups PG1 and PG2 include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, including two sub-pixels of any one of the first color sub-pixel to the third color sub-pixel. For example, the unit pixel groups PG1 and PG2 may include one R sub-pixel, two G sub-pixels, and one B sub-pixel. In the sub-pixels in the unit pixel groups PG1 and PG2, the luminous efficiency of the light-emitting element may be different for each color. In view of this, the size of the sub-pixel may vary for each color. For example, among the R sub-pixel, the G sub-pixel, and the B sub-pixel, the B sub-pixel may be the largest, and the G sub-pixel may be the smallest.

[0071] Reference Figure 4 , the second area CA includes pixel groups PG spaced apart by a predetermined distance and a light-transmitting portion AG disposed between adjacent pixel groups PG. External light is received by the lens of the sensor module through the light-transmitting portion AG. The light-transmitting portion AG may include a transparent medium having a high transmittance without containing metal, so that light can be incident with minimal light loss. In other words, the light-transmitting portion AG may be formed of a transparent insulating material without including metal lines or pixels. Due to the light-transmitting portion AG, the PPI of the second area CA is lower than the PPI of the first area DA.

[0072] The pixel group PG of the second area CA may include one or two pixels. Each pixel in the pixel group may include two to four sub-pixels. For example, one pixel in the pixel group may include an R sub-pixel, a G sub-pixel, and a B sub-pixel, or may include two sub-pixels and also include a W sub-pixel. Figure 4 In the example, the first pixel PIX1 is composed of an R sub-pixel and a G sub-pixel, and the second pixel PIX2 is composed of a B sub-pixel and a G sub-pixel, but the present disclosure is not limited thereto.

[0073] The first pixel PIX1 and the second pixel PIX2 may be arranged in a pixel group PG arranged in the second region. The first pixel PIX1 may be composed of an R sub-pixel and a first G sub-pixel, and the second pixel PIX2 may be composed of a B sub-pixel and a second G sub-pixel. Insufficient color representation in each of the first pixel PIX1 and the second pixel PIX2 may be compensated by an average value of corresponding color data between adjacent pixels. White may be represented by combining the R sub-pixels, the G sub-pixels, and the B sub-pixels of the first pixel PIX1 and the second pixel PIX2.

[0074] exist Figure 4 , the shape of the light-transmitting portion AG is shown as a circle, but is not limited thereto. For example, the light-transmitting portion AG may be designed in various shapes such as a circle, an ellipse, and a polygon.

[0075] Due to the process deviation and component characteristic deviation caused in the manufacturing process of the display panel, there may be differences in the electrical characteristics of the driving element between pixels, and this difference may increase as the driving time of the pixel passes. In order to compensate for the deviation of the electrical characteristics of the driving element between pixels, an internal compensation technology or an external compensation technology can be applied to the organic light-emitting display device. In the internal compensation technology, the threshold voltage of the driving element of each sub-pixel is sensed using an internal compensation circuit implemented in each pixel circuit, and the gate-source voltage Vgs of the driving element is compensated by the threshold voltage. In the external compensation technology, the current or voltage of the driving element is sensed in real time using an external compensation circuit, and the current or voltage of the driving element changes according to the electrical characteristics of the driving element. The external compensation technology modulates the pixel data (digital data) of the input image to a degree similar to the deviation (or change) of the electrical characteristics of the driving element sensed for each pixel, thereby compensating the electrical characteristic deviation (or change) of the driving element in each pixel in real time. The display panel driver can drive pixels using external compensation technology and / or internal compensation technology.

[0076] Figure 5 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0077] Reference Figure 5 According to an embodiment of the present disclosure, a display device includes: a display panel 10; a display panel driver 110, 112, 120 for writing pixel data of an input image into a pixel P of the display panel 100; a timing controller 130 for controlling the display panel driver; and a power supply unit for generating power required to drive the display panel 100.

[0078] The display panel 100 includes a pixel array that displays an input image on a screen. As described above, the pixel array may be divided into a first area DA and a second area CA having a resolution or PPI lower than that of the first area DA. Since the first area DA includes pixels P with a high PPI and is therefore larger in size than the second area CA, most of the image information is displayed on the first area DA. A sensor module overlapping the second area CA may be provided at a lower portion of the display panel 100.

[0079] The pixel array may further include a third area SA having a resolution or PPI lower than that of the first area DA. The third area SA includes pixels arranged with a low PPI and a plurality of light sensors for sensing a user's fingerprint.

[0080] The touch sensor may be provided on the screen of the display panel 100. The touch sensor may be provided on the screen of the display panel in an on-cell type or an additional type, or may be implemented as an in-cell type touch sensor incorporated in a pixel array.

[0081] The display panel 100 may be implemented as a flexible display panel in which the pixels P are arranged on a flexible substrate such as a plastic substrate or a metal substrate. In a flexible display, the size and shape of the screen may be changed by winding, folding or bending the flexible display panel. The flexible display may include a slideable display, a rollable display, a bendable display, a foldable display, and the like.

[0082] The display panel driver may drive the pixels P by applying an internal compensation technique.

[0083] The display panel driver reproduces an input image on the screen of the display panel 100 by writing pixel data of the input image into sub-pixels. The display panel driver includes a data driver 110, a first gate driver 120, a second gate driver 123, and a third gate driver 124. The display panel driver may further include a demultiplexer 112 disposed between the data driver 110 and the data lines DL.

[0084] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. In the low-speed drive mode, the input image is analyzed, and when the input image does not change within a preset time period, the power consumption of the display device can be reduced. In the low-speed drive mode, when a still image is input within a specific time period or longer, the refresh rate of the pixel P is reduced to control the data write period of the pixel P to be longer, thereby reducing power consumption. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in a standby mode, or when no user command or input image is input to the display panel drive circuit within a predetermined time period or longer, the display panel drive circuit can operate in a low-speed drive mode.

[0085] The data driver 110 samples pixel data to be written into the pixels of the pixel arrays DA, CA, and SA from the pixel data received from the timing controller 130. The data driver 110 converts the pixel data to be written into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as "DAC") and outputs a data voltage Vdata.

[0086] During the first scanning period when the gate signal is applied to the first area DA, the data driver 110 outputs a first data voltage synchronized with the gate signal. Due to the difference in density (i.e., PPI) of the pixels turned on, when the same data voltage as the data voltage for each grayscale of the first area DA is applied to the pixels in the second area CA and the third area SA, the brightness of the second area CA and the third area SA may be lower than the brightness of the first area DA. In order to compensate for the brightness difference of each area of ​​the pixel array, the data driver 110 outputs a first data voltage synchronized with the gate signal during the first scanning period when the gate signal is applied to the first area DA, and outputs a second data voltage and a third data voltage synchronized with the gate signal during the second scanning period and the third scanning period when the gate signal is applied to the second area CA and the third area SA. The second data voltage and the third data voltage are set to be in a voltage range larger than the voltage range of the first data voltage to increase the brightness of the pixels in the second area CA and the third area SA. According to the voltage control data of the gamma compensation voltage generator 150, the voltage level of the data voltage is determined for each grayscale.

[0087] The gamma compensation voltage generator 150 may be implemented with a programmable gamma IC in which an output voltage may vary according to voltage control data input from the timing controller 130. The gamma compensation voltage output from the gamma compensation voltage generator 150 is input to the DAC of the data driver 110. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage Vdata. Therefore, as described above, the data voltage of each region of the pixel array may vary according to the output voltage of the gamma compensation voltage generator 150, which varies under the control of the timing controller 130.

[0088] The demultiplexer 112 distributes the data voltage Vdata output through the channels of the data driver 110 to the plurality of data lines DL in a time division manner. Due to the demultiplexer 112, the number of channels of the data driver 110 may be reduced. The demultiplexer 112 may be omitted.

[0089] The first gate driver 120 may be implemented as a gate-in-panel (GIP) circuit that is directly formed on the bezel region BZ of the display panel 100 together with the TFT arrays of the pixel arrays DA, CA, and SA. The bezel region BZ is a non-display region disposed on an edge outside the pixel arrays DA, CA, and SA on the display panel 100.

[0090] The first gate driver 120 applies a gate signal to the gate lines GL of the pixels connected to the first area DA under the control of the timing controller 130. The first gate driver 120 may shift the gate signal using a shift register to sequentially provide the signal to the gate lines GL of the pixels connected to the first area DA. The voltage of the gate signal swings between a gate-off voltage VGH and a gate-on voltage VGL. The gate signal may include a pulse of a scan signal (hereinafter referred to as a "scan pulse") and a pulse of a light emission control signal (hereinafter referred to as an "EM pulse"). The gate line may include a scan line to which the scan pulse is applied and an EM line to which the EM pulse is applied.

[0091] The first gate driver 120 may further include a shift register which provides gate signals to some gate lines GL connected to the pixels of the second area CA and the third area SA.

[0092] The first gate driver 120 may be disposed on each of the left frame BZ and the right frame BZ of the display panel 100 to provide a gate signal to the gate line GL in a dual-feed method. In the dual-feed method, the gate drivers 120 disposed on the two frames of the display panel 100 are synchronized by the timing controller 130 so that the gate signal can be applied to both ends of one gate line at the same time. In another embodiment, the first gate driver 120 may be disposed on one of the left frame and the right frame of the display panel 100 to provide a gate signal to the gate line GL in a single-feed method.

[0093] The first gate driver 120 may include a scan driver 121 and an EM driver 122. The scan driver 121 outputs scan pulses, shifts the scan pulses according to a shift clock, and sequentially supplies the scan pulses to the scan lines. The EM gate driver 122 outputs EM pulses, shifts the EM pulses according to a shift clock, and sequentially supplies the EM pulses to the EM lines.

[0094] The second gate driver 123 applies a gate signal to the gate line GL of the pixel connected to the second area CA. The gate signal output from the second gate driver 123 includes a scan pulse applied to the scan line of the second area CA and an EM pulse applied to the EM line of the second area CA. The third gate driver 124 applies a gate signal to the gate line GL of the pixel connected to the third area SA. The gate signal output from the third gate driver 124 includes a scan pulse applied to the scan line of the third area SA and an EM pulse applied to the EM line of the third area SA.

[0095] like Figure 5 and Figure 6As shown in , at least some of the transistors and wirings of the second gate driver 123 and the third gate driver 124 may be implemented as a gate-in-array (GIA) circuit provided in the pixel arrays DA, CA, and SA. Each of the second gate driver 123 and the third gate driver 124 receives a carry signal from the first gate driver 120 to start outputting a gate signal, and includes a shift register that shifts the gate signal.

[0096] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from a host system. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, etc. A period of the vertical synchronization signal Vsync is a frame period. A period of the horizontal synchronization signal Hsync and the data enable signal DE is a horizontal period 1H. The pulse of the data enable signal DE is synchronized with a row of data (one line data) of a pixel P to be written into a pixel line. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0097] The timing controller 130 may multiply the input frame frequency by i (i is a natural number) to control the operation timing of the display panel drivers 110, 112, and 120 at a frame frequency of the input frame frequency×i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the Phase Alternating Line (PAL) system. In the low-speed driving mode, the timing controller 130 may reduce the frame frequency to a frequency between 1 Hz and 30 Hz so as to reduce the refresh rate of the pixel P.

[0098] The timing controller 130 transmits pixel data of an input image to the data driver 120, and controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer 112, and the gate drivers 120, 123, and 124. The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a switch control signal for controlling the operation timing of the demultiplexer 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0099] The gate timing control signal may include a start pulse, a shift clock, etc. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-off voltage VGH / VEH or a gate-on voltage VGL / VEL by a level shifter omitted from the drawing, and may be provided to the gate driver 120. The level shifter may convert a low-level voltage of the gate timing control signal into a gate-on voltage VGL, and may convert a high-level voltage of the gate timing control signal into a gate-off voltage VGH.

[0100] The power supply unit may include a charge pump, a regulator, a buck converter, a boost converter, a gamma compensation voltage generator 150, etc. The power supply unit receives a DC input voltage from a host system and generates power required to drive the display panel driver and the display panel 100. The power supply unit may output DC voltages such as a gamma reference voltage, a gate cut-off voltage VGH / VEH, a gate-on voltage VGL / VEL, a pixel driving voltage ELVDD, a low potential power voltage ELVSS, and an initialization voltage Vini. The gamma compensation voltage generator 150 includes a programmable gamma IC that changes the gamma compensation voltage according to voltage control data received from the timing controller 130. The gamma compensation voltage is provided to the data driver 110. The gate cut-off voltage VGH / VEH and the gate-on voltage VGL / VEL are provided to the level shifter and the gate driver 120. DC voltages such as the pixel driving voltage ELVDD, the low potential power voltage ELVSS, and the initialization voltage Vini are commonly provided to the pixel circuit through the power line. The pixel driving voltage ELVDD is set to a voltage higher than the low potential power voltage ELVSS and the initialization voltage Vini.

[0101] The host system may be a main circuit board of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a transportation system, a home theater system, a mobile device, or a wearable device.

[0102] like Figure 6 As shown in , in a mobile device or a wearable device, the timing controller 130, the data driver 110, and the power supply unit may be integrated into one driver integrated circuit (D-IC). Figure 6 , reference numeral '200' denotes a host system.

[0103] The PPI of the second area CA and the third area SA is lower than the PPI of the first area DA. Therefore, if the data voltage Vdata applied to the pixels P of the second area CA and the third area SA is equal to the data voltage Vdata applied to the pixels P of the first area DA at the same grayscale, then Figure 7 As shown in , the brightness of the second area CA and the third area SA may be lower than the brightness of the first area DA.

[0104] In order to compensate for the brightness difference between the areas DA, CA, and SA of the pixel array, the gamma compensation voltage generator 150 outputs a gamma compensation voltage as a voltage for each area defined by the voltage control data under the control of the timing controller 130 .

[0105] The timing controller 130 includes a data voltage control unit that controls the dynamic range of the data voltage of each region so that the brightness difference between the regions DA, CA, and SA of the pixel array is not visually recognized. The data voltage control unit outputs first voltage control data for controlling the dynamic range of the data voltage applied to the pixels in the region DA with high PPI during the scanning period of the high PPI region DA, and outputs second voltage control data for controlling the dynamic range of the data voltage applied to the pixels in the regions CA and SA with low PPI during the scanning period of the low PPI regions CA and SA.

[0106] The gamma compensation voltage generator 150 outputs a first gamma compensation voltage in response to first voltage control data during a scan period of the high PPI area DA, and outputs a second gamma compensation voltage in response to second voltage control data during a scan period of the low PPI areas CA and DA by using one programmable gamma IC. The data driver 110 converts pixel data into a first gamma compensation voltage during a scan period of the high PPI area DA, and outputs a data voltage charged to the pixel of the high PPI area. In addition, the data driver 110 converts pixel data into a second gamma compensation voltage during a scan period of the low PPI areas CA and SA, and outputs a data voltage charged to the pixel of the low PPI areas CA and SA.

[0107] The first gate driver 120 provides gate signals to the gate lines GL of the high PPI area DA. The second and third gate drivers 123 and 124 may receive the carry signal from the first gate driver 120 and provide gate signals to the gate lines GL of the low PPI areas CA and SA.

[0108] Figure 8 is a diagram showing one frame period of a display device. Figure 8 In the embodiment, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync and the data enable signal DE are timing signals synchronized with the pixel data of the input image.

[0109] Reference Figure 8 , one frame period is divided into an active interval AT in which pixel data of an input image is written into pixels and a vertical blank period VB having no pixel data.

[0110] The vertical blank period VB is a blank period during which the timing controller 130 does not receive pixel data between the effective interval AT of the (N-1)th frame period and the effective interval AT of the Nth frame period. The vertical blank period VB includes a vertical synchronization time VS, a vertical front porch FP, and a vertical back porch BP.

[0111] The vertical synchronization signal Vsync defines a frame period. The horizontal synchronization signal Hsync defines a horizontal period 1H. The data enable signal DE defines an effective data section including pixel data to be written into the pixel. The pulse of the data enable signal DE is synchronized with the pixel data to be written into the pixel of the display panel 100. One pulse period of the data enable signal DE is one horizontal period 1H.

[0112] Fig. 9 is a circuit diagram showing an example of a pixel circuit. Fig.10 Is shown driving Fig. 9 The waveform diagram of the pixel circuit method is shown.

[0113] Reference Fig. 9 and Fig.10 The pixel circuit includes a light emitting element OLED, a driving element DT for supplying current to the light emitting element OLED, and a switch circuit for switching voltages applied to the light emitting element OLED and the driving element DT.

[0114] The switch circuit is connected to the power lines PL1, PL2 and PL3, the data line DL and the gate lines GL1, GL2 and GL3 to which the pixel driving voltage ELVDD, the low potential power voltage ELVSS and the initialization voltage Vini are applied, and switches the voltage applied to the light emitting element OLED and the driving element DT in response to the scan pulses SCAN(N-1) and SCAN(N) and the EM pulse EM(N). The switch circuit includes an internal compensation circuit that samples the threshold voltage Vth of the driving element DT using the first switching element M1 to the sixth switching element M6 and applies the data voltage Vdata of the pixel data to the driving element DT. Each of the driving element DT and the switching elements M1 to M6 can be implemented using a p-channel TFT.

[0115] like Fig.10 As shown in , the driving period of the pixel circuit may be divided into an initialization period Tini, a sampling period Tsam, and a light emission period Tem. The initialization period Tini and the sampling period Tsam are defined by a scan pulse synchronized with a data voltage Vdata.

[0116] The Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL during the sampling period Tsam and is applied to the Nth scan line GL1. The Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the pixels applied to the Nth pixel line. The (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL during the initialization period Tini before the sampling period and is applied to the (N-1)th scan line GL2. The (N-1)th scan pulse SCAN(N-1) is generated before the Nth scan pulse SCAN(N) and is synchronized with the data voltage Vdata of the pixels applied to the (N-1)th pixel line. The EM pulse EM(N) is generated as the gate-off voltage VGH during the initialization period Tini and the sampling period Tsam and is applied to the EM line GL3. The EM pulse EM(N) may be simultaneously applied to the pixels of the (N-1)th pixel line and the Nth pixel line.

[0117] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) of the gate-on voltage VGL is applied to the (N-1)th scan line GL2, and the EM pulse of the gate-off voltage VGH is applied to the EM line GL3. In this case, the voltage of the Nth scan line GL1 is the gate-off voltage VGH. During the initialization period Tin, the fifth switching element M5 is turned on according to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to initialize the pixel circuit of the first area DA.

[0118] During the sampling period Tsam, the Nth scan pulse SCAN(N) of the gate-on voltage VGL is applied to the Nth scan line GL1. In this case, the voltages of the (N-1)th scan line GL2 and the EM line GL3 are gate-off voltages. During the sampling period Tsam, the first switching element M1 and the second switching element M2 are turned on according to the gate-on voltage VGL of the Nth scan pulse SCAN(N), so that the driving element DT is turned on, thereby sampling the threshold voltage Vth of the driving element DT and storing the data voltage Vdata compensated by the threshold voltage Vth in the capacitor Cst1. At the same time, the sixth switching element M6 is turned on during the sampling period Tsam to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the light emission of the light emitting element OLED.

[0119] When the light emission period Tem begins, the EM line GL3 is inverted to the gate-on voltage VGL. During the light emission period Tem, the scan lines GL1 and GL2 maintain the gate-off voltage VGH. During the light emission period Tem, the third switch element M3 and the fourth switch element M4 are turned on so that the light emitting element OLED can emit light. During the light emission period Tem, in order to accurately represent the brightness of low grayscale, the voltage level of the EM pulse EM(N) can be inverted between the gate-on voltage VGL and the gate-off voltage VGH at a predetermined duty cycle. In this case, the third switch element M3 and the fourth switch element M4 can be repeatedly turned on / off according to the duty cycle of the EM pulse EM(N) during the light emission period Tem.

[0120] The anode electrode of the light emitting element OLED is connected to the fourth node n4 between the fourth switch element M4 and the sixth switch element M6. The fourth node n4 is connected to the anode electrode of the light emitting element OLED, the second electrode of the fourth switch element M4, and the second electrode of the sixth switch element M6. The cathode electrode of the light emitting element OLED is connected to the VSS line PL3 to which the low potential power voltage ELVSS is applied. The light emitting element OLED emits light by the current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the light emitting element OLED is switched by the third switch element M3 and the fourth switch element M4.

[0121] The capacitor Cst1 is connected between the VDD line PL1 and the second node n2.

[0122] After the sampling period Tsam ends, the data voltage Vdata compensated by the sampled threshold voltage Vth of the driving element DT is charged into the capacitor Cst1. Since the data voltage Vdata is compensated by the threshold voltage Vth of the driving element DT in each subpixel, the deviation of the electrical characteristics of the driving element DT is compensated in the subpixel.

[0123] The first switch element M1 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the second node n2 to the third node n3. The second node n2 is connected to the gate electrode of the driving element DT, the first electrode of the capacitor Cst1, and the first electrode of the first switch element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switch element M1, and the first electrode of the fourth switch element M4. The gate electrode of the first switch element M1 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the first switch element M1 is connected to the second node n2, and the second electrode of the first switch element M1 is connected to the third node n3.

[0124] Since the first switching element M1 is turned on only in a very short horizontal period 1H, in which the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL in one frame period, leakage current may occur in the off state. In order to suppress the leakage current in the first switching element M1, the first switching element M1 can be implemented using a transistor having a dual-gate structure in which two transistors are connected in series.

[0125] The second switching element M2 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to provide the data voltage Vdata to the first node n1. The gate electrode of the second switching element M2 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the second switching element M2 is connected to the first node n1. The second electrode of the second switching element M2 is connected to the data line DL of the first area DA to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0126] The third switch element M3 is turned on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. The gate electrode of the third switch element M3 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the third switch element M3 is connected to the VDD line PL1. The second electrode of the third switch element M3 is connected to the first node n1.

[0127] The fourth switch element M4 is turned on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the third node n3 to the anode electrode of the light emitting element OLED. The gate electrode of the fourth switch element M4 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the fourth switch element M4 is connected to the third node n3, and the second electrode thereof is connected to the fourth node n4.

[0128] The fifth switch element M5 is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the second node n2 to the Vini line PL2. The gate electrode of the fifth switch element M5 is connected to the (N-1)th scan line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the fifth switch element M5 is connected to the second node n2, and the second electrode thereof is connected to the Vini line PL2. In order to suppress leakage current in the fifth switch element M5, the fifth switch element M5 is implemented using a transistor having a dual-gate structure in which two transistors are connected in series.

[0129] The sixth switching element M6 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode thereof is connected to the fourth node n4.

[0130] In another embodiment, the gate electrodes of the fifth switching element M5 and the sixth switching element M6 may be commonly connected to the (N-1)th scan line GL2 to which the (N-1)th scan pulse SCAN(N-1) is applied. In this case, the fifth switching element M5 and the sixth switching element M6 may be simultaneously turned on in response to the (N-1)th scan pulse SCAN(N-1).

[0131] The driving element DT drives the light emitting element OLED by controlling a current flowing through the light emitting element OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0132] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL. The Nth scan pulse SCAN(N) and the EM pulse EM(N) maintain the gate-off voltage VGH during the initialization period Tini. Therefore, during the initialization period Tini, the fifth switching element M5 is turned on, so that the second node n2 and the fourth node n4 are initialized to Vini. A holding period may be set between the initialization period Tini and the sampling period Tsam. During the holding period, the voltages of the scan lines GL1 and GL2 and the EM line GL3 are the gate-off voltages.

[0133] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL. The Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel line. The (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) maintain the gate-off voltage VGH during the sampling period Tsam. Therefore, the first switching element M1 and the second switching element M2 are turned on during the sampling period Tsam.

[0134] During the sampling period Tsam, the gate voltage DTG of the driving element DT rises due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is turned off, the gate voltage DTG of the driving element DT is Vdata-|Vth|, and the source voltage of the driving element DT is ELVDD-|Vth|. Therefore, when the sampled threshold voltage Vth of the driving element DT is stored in the capacitor Cst1, the gate-source voltage Vgs of the driving element DT is ELVDD-Vdata. As a result, the current Ioled flowing through the light emitting element OLED during the light emission period Tem is not affected by the threshold voltage Vth of the driving element DT.

[0135] During the light emission period Tem, when the EM pulse EM(N) is the gate-on voltage VEL, current flows between the pixel driving voltage ELVDD and the light emitting element OLED, so that the light emitting element OLED can emit light. During the light emission period Tem, the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) maintain the gate-off voltage VGH. During the light emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on according to the gate-on voltage of the EM pulse EM(N). When the EM pulse EM(N) is the gate-on voltage VGL, the third switching element M3 and the fourth switching element M4 are turned on, so that current flows through the light emitting element OLED. At this time, the current Ioled flowing to the light emitting element OLED through the driving element DT is K(ELVDD-Vdata) 2 K is a constant determined by the charge mobility, parasitic capacitance, channel ratio W / L, etc. of the driving element DT.

[0136] In order to reduce the brightness difference between the regions DA, CA and SA of the pixel array, the channel ratio W / L of the driving element DT arranged in the second region CA and the third region SA is further increased compared with the channel ratio of the driving element DT arranged in the first region DA, thereby increasing the current driving the light emitting element OLED. Fig.11 In the example of , "DT(DA)" is the driving element DT disposed in the first area DA. "DT(CA / SA)" is the driving element DT disposed in the second area CA and the third area SA. In order to increase the brightness of the second area CA and the third area SA, the channel width W' of the driving element DT disposed in the second area CA and the third area DA may be made greater than the channel width of the driving element DT in the first area DA, or alternatively, the channel ratio W' / L' of the driving element DT in the second area CA and the third area DA may be set to be greater than the channel ratio of the driving element DT in the first area DA by reducing the channel length L'. In addition, in Fig.11, ACT represents an active region of the driving element DT, G represents a gate of the driving element DT, D represents a drain of the driving element DT, and S represents a source of the driving element DT.

[0137] Fig.12 is a block diagram schematically showing a shift register that outputs a scan pulse. Fig.13 It is shown Fig.12 , which is a waveform diagram of the output signal of the nth signal transmission unit and the control node voltage.

[0138] Reference Fig.12 and Fig.13 , the shift register includes signal transmission units ST(n-1) to ST(n+2) connected dependently. Each of the signal transmission units ST(n-1) to ST(n+2) includes: a VST node through which a start pulse VST is input; a CLK node through which shift clocks CLK1 to CLK4 are input; and an output node through which scan pulses SRO(n-1) to SRO(n+2) are output. The start pulse VST is basically input to the first signal transmission unit. The shift clocks CLK1 to CLK4 may be 4-phase clocks, but are not limited thereto.

[0139] exist Fig.12 In the example of , the (n-1)th signal transmission unit ST(n-1) may be the first signal transmission unit. The signal transmission units ST(n) to ST(n+2) dependently connected to the (n-1)th signal transmission unit ST(n-1) receive the carry signal CAR from the previous signal transmission unit and begin to be driven. The carry signal CAR may be the scan pulse SRO(n-1) to SRO(n+2) output from the previous signal transmission unit. Each of the signal transmission units ST(n-1) to ST(n+2) may output the carry signal CAR through a separate carry signal output node. The carry signal CAR is output simultaneously with the scan pulses SRO(n-1) to SRO(n+2) output from the previous signal transmission unit.

[0140] Each of the signal transmission units ST(n-1) to ST(n+2) includes a first control node Q, a second control node QB, and a buffer BUF. The buffer BUF outputs a gate signal to a gate line through an output node using a pull-up transistor Tu and a pull-down transistor Td.

[0141] When the voltage of the first control node Q is charged and the shift clocks CLK1 to CLK4 are input, the pull-up transistor Tu is turned on to charge the voltage of the output node to the gate-on voltage VGL. At this time, the scan pulses SRO (n-1) to SRO (n+2) and the carry signal CAR rise to the gate-on voltage VGL. When the voltage of the shift clocks CLK1 to CLK4 becomes the gate-on voltage VGL, the voltage of the first control node Q is bootstrapped to increase to a gate-on voltage of about 2VGL. When the voltage of the first control node Q becomes substantially higher than the threshold voltage of the pull-up transistor, the pull-up transistor Tu is turned on.

[0142] When the first control node Q is charged to a voltage equal to or higher than the gate-on voltage VGL, the voltage of the second control node QB is set to the gate-off voltage VGH. When the voltage of the second control node QB is charged to the gate-on voltage VGL, the pull-down transistor Td is turned on to provide the gate-off voltage VGH to the output node. At this time, the scan pulses SRO(n-1) to SRO(n+2) and the carry signal CAR drop to the gate-off voltage VGH.

[0143] The shift register outputting the EM pulse has the same Fig.19 The structure of the shift register shown is similar to that of the shift register shown in FIG. When a start pulse or a carry signal is input, the signal transmission unit of the shift register starts to be driven and sequentially outputs EM pulses.

[0144] The timing controller 130 includes a data voltage control unit 131 for controlling a data voltage of each region of the pixel arrays DA, CA, and SA. The data voltage control unit 131 determines a region in the pixel arrays DA, CA, and SA where pixel data is written, and selects voltage control data for controlling an output voltage of the gamma compensation voltage generator 150 for each region.

[0145] when Fig.12 When the signal transmission unit shown is implemented as a GIA circuit, transistors of the signal transmission unit may be dispersedly arranged in the pixel arrays DA, CA, and SA.

[0146] Fig.14 is a block diagram showing the data voltage control unit 131 .

[0147] Reference Fig.14 The data voltage control unit 131 includes a region determination unit 141, a first lookup table 142, a second lookup table 143, and a data selection unit 144. Fig.14 , “LUT1” is the first lookup table 142 , and “LUT2” is the second lookup table 143 .

[0148] The region determining unit 141 receives pixel data DATA and a data enable signal DE synchronized with the pixel data DATA. The region determining unit 141 counts the data enable signal DE as a clock for sampling data bits and determines a region in which pixel data in the pixel arrays DA, CA, and SA is to be written.

[0149] The first lookup table 142 and the second lookup table 143 are stored in a memory. The first lookup table 142 includes first voltage control data in which the data voltage of the first area DA is set for each grayscale. The second lookup table 143 includes second voltage control data in which the data voltage of the second area CA and the third area SA is set for each grayscale. The second voltage control data can be determined by an experimental method so that for each grayscale, the brightness of the second area CA and the third area SA is equal to the brightness of the first area DA. In particular, the second voltage control data can be set to data for selecting a voltage higher than the first voltage control data in a high grayscale.

[0150] The efficiency of the light-emitting element OLED may vary according to the color of the sub-pixel. Voltage control data may be independently set in each of the first lookup table 142 and the second lookup table 143 for each color of the sub-pixel, so that a gamma compensation voltage optimized for each color of the light-emitting element OLED may be output in response to the efficiency difference of each color. For example, the first lookup table 142 may include: a first-first lookup table in which first-first voltage control data for determining the data voltage applied to the R sub-pixel has been set; a first-second lookup table in which first-second voltage control data for determining the data voltage applied to the G sub-pixel has been set; and a first-third lookup table in which first-third voltage control data for determining the data voltage applied to the B sub-pixel has been set. The second lookup table 143 may include: a second-first lookup table, in which second-first voltage control data for determining the data voltage applied to the R sub-pixel has been set; a second-second lookup table, in which second-second voltage control data for determining the data voltage applied to the G sub-pixel has been set; and a second-third lookup table, in which second-third voltage control data for determining the data voltage applied to the B sub-pixel has been set.

[0151] The data selection unit 144 selects the voltage control data output from the first lookup table 142 and the second lookup table 143 in response to the selection signal input from the area determination unit 141. During a scanning period in which a gate signal is applied to pixels of the first area DA, the data selection unit 144 selects the first voltage control data from the first lookup table 142 and provides the first voltage control data to the gamma compensation voltage generator 150. During a scanning period in which a gate signal is applied to pixels of the second area CA and the third area SA, the data selection unit 144 selects the second voltage control data from the second lookup table 142 and provides the second voltage control data to the gamma compensation voltage generator 150. The data selection unit 144 may be implemented with a multiplexer.

[0152] The gamma compensation voltage generator 150 outputs a gamma compensation voltage for each grayscale at a voltage level indicated by the voltage control data from the data voltage control unit 131. Therefore, the display device of the present disclosure can use one gamma compensation voltage generator 150 to change the data voltage applied to the area having different resolutions or PPIs, thereby uniformly controlling the brightness over the entire screen of the full screen display.

[0153] Fig.15 is a circuit diagram illustrating a gamma compensation voltage generator according to an embodiment of the present disclosure.

[0154] Reference Fig.15 , the gamma compensation voltage generator 150 receives a high potential reference voltage VRH and a low potential reference voltage VRL.

[0155] when Fig. 9 When the driving element DT of the pixel circuit shown is implemented with a p-channel transistor, the amount of current flowing to the light emitting element OLED through the driving element DT increases as the data voltage decreases. Fig. 9 In the pixel circuit shown, the data voltage is set to an inverse gamma compensation voltage. Fig.15 The gamma compensation voltage generator 150 shown is an example of generating a negative gamma compensation voltage. The data voltage may be set to a positive gamma compensation voltage according to the pixel circuit. In this case, Fig.15 In the embodiment, the application node of the high potential reference voltage VRH and the application node of the low potential reference voltage VRL can be switched.

[0156] The gamma compensation voltage generator 150 includes a plurality of voltage divider circuits and a plurality of multiplexers MUX01 to MUX03 and MUX10 to MUX18. The voltage divider circuit divides the voltage between the high potential voltage and the low potential voltage using resistors connected in series to output voltages with different voltage levels. Each of the multiplexers MUX01 to MUX18 selects a voltage indicated by the voltage control data REG01 to REG03 and REG10 to REG18 from the voltage divided by the voltage divider circuit.

[0157] The data voltage control unit 131 determines the area where the pixel data in the pixel arrays DA, CA and SA are written. The data voltage control unit 131 controls the multiplexers MUX01 to MUX03 and MUX11 to MUX18 to select the output voltage of the multiplexers MUX01 to MUX03 and MUX11 to MUX18 for each area of ​​the pixel array. During the scanning period of the first area DA, the first voltage control data is input to the control nodes of the multiplexers MUX01 to MUX03 and MUX11 to MUX18. During the scanning period of the second area CA and the third area SA, the second voltage control data is input to the control nodes of the multiplexers MUX01 to MUX03 and MUX11 to MUX18.

[0158] Each of the multiplexers MUX01 to MUX18 selects any one of the divided voltages in response to the first voltage control data during the scan period of the high PPI area DA, and selects any one of the divided voltages in response to the second voltage control data during the scan period of the low PPI areas CA and SA.

[0159] The gamma compensation voltage generator 150 includes an input voltage selection unit, a gray voltage generation unit 151 that generates a gamma compensation voltage, and a light source driving voltage generation unit 152 .

[0160] The input voltage selection unit includes: a voltage divider circuit RS01; a multiplexer MUX01 that selects the highest grayscale voltage V255 according to the voltage control data REG01; a multiplexer MUX02 that selects a lower gamma compensation voltage according to the voltage control data REG02; and a multiplexer MUX03 that outputs the lowest gamma compensation voltage V0 according to the voltage control data REG03. The voltage output from the multiplexer MUX01 is provided to the voltage divider circuits of the light source driving voltage generating unit 152 and the grayscale voltage generating unit 151. During the scanning period of the first area DA of the pixel array, the first voltage control data is input to the control nodes of the multiplexers MUX01, MUX02 and MUX03 of the input voltage selection unit. During the scanning period of the second area CA and the third area SA of the pixel array, the second voltage control data is input to the control nodes of the multiplexers MUX01, MUX02 and MUX03 of the input voltage selection unit.

[0161] In the fingerprint recognition mode, at least some pixels of the third area SA are driven to serve as a light source. The light source of the third area SA may emit light having a brightness higher than the maximum brightness of the pixels disposed in the first area DA and the second area CA. The light source driving voltage generating unit 152 generates a driving voltage for the light source in the fingerprint recognition mode.

[0162] The light source driving voltage generating unit 152 includes a tenth voltage divider circuit RS10 connected between the VRL node and the V255 node and multiplexers MUX10 and MUX20. The voltage divider circuit RS10 divides the voltage between the low potential reference voltage VRL and the highest grayscale voltage V255. The output voltage of the voltage divider circuit RS10 has a voltage level of a grayscale higher than the highest grayscale V255. The multiplexer MUX10 selects and outputs any one of the voltages divided by the voltage divider circuit RS10 according to the voltage control data REG10. The voltage D256' output from the multiplexer MUX10 can be linked to a display brightness value (DBV) so that its voltage level can be changed. For example, when DBV is high, a voltage close to the low potential reference voltage VRL is output from the multiplexer MUX10. DBV is brightness setting data for changing the brightness according to a brightness sensor output signal of the host system 200 or a brightness input value of the user. The host system 200 or the timing controller 130 may change the voltage control data REG10 in association with DBV. The output voltage of the multiplexer MUX10 may be selected within a voltage range of grayscales higher than the highest grayscale voltage V255. Therefore, in the fingerprint recognition mode, the pixels used as the light source in the third area SA may emit light having a higher brightness than the brightness of the pixels in the first area DA and the second area CA.

[0163] The multiplexer MUX20 selects any one of the separate light source driving voltage D256 set independently of the DBV and the DBV interlock voltage D256' output from the multiplexer MUX10 under the control of the host system 200 to output the light source driving voltage V256. The DBV non-interlock voltage D256 is a voltage preset within a voltage range of grayscale higher than the highest grayscale voltage V255. In the fingerprint recognition mode, the host system 200 can use the enable signal EN to select the output voltage of the multiplexer MUX20.

[0164] The gray voltage generating unit 151 includes a plurality of voltage divider circuits RS11 to RS17 and a plurality of multiplexers MUX11 to MUX18 .

[0165] The first-first voltage divider circuit RS11 divides the voltage between the output voltage of the first multiplexer MUX01 and the output voltage of the second multiplexer MUX02. The first-first multiplexer MUX11 selects any one of the voltages divided by the voltage divider circuit RS11 according to the voltage control data REG11. The output voltage of the first-first multiplexer MUX11 is output through a buffer and may be a gamma compensation voltage V191 corresponding to grayscale 191. The first-second voltage divider circuit RS12 divides the voltage between the output voltage of the first-first multiplexer MUX11 and the output voltage of the second multiplexer MUX02. The first-second multiplexer MUX12 selects any one of the voltages divided by the voltage divider circuit RS12 according to the voltage control data REG12. The output voltage of the first-second multiplexer MUX12 is output through a buffer and may be a gamma compensation voltage V127 corresponding to grayscale 127.

[0166] The first-third voltage divider circuit RS13 divides the voltage between the output voltage of the first-second multiplexer MUX12 and the output voltage of the second multiplexer MUX02. The first-third multiplexer MUX13 selects any one of the voltages divided by the voltage divider circuit RS13 according to the voltage control data REG13. The output voltage of the first-third multiplexer MUX13 is output through a buffer and may be a gamma compensation voltage V63 corresponding to grayscale 63. The first-fourth voltage divider circuit RS14 divides the voltage between the output voltage of the first-third multiplexer MUX13 and the output voltage of the second multiplexer MUX02. The first-fourth multiplexer MUX14 selects any one of the voltages divided by the voltage divider circuit RS14 according to the voltage control data REG14. The output voltage of the first-fourth multiplexer MUX14 is output through a buffer and may be a gamma compensation voltage V31 corresponding to grayscale 31.

[0167] The first-fifth voltage divider circuit RS15 divides the voltage between the output voltage of the first-fourth multiplexer MUX14 and the output voltage of the second multiplexer MUX02. The first-fifth multiplexer MUX15 selects any one of the voltages divided by the voltage divider circuit RS15 according to the voltage control data REG15. The output voltage of the first-fifth multiplexer MUX15 is output through a buffer and may be a gamma compensation voltage V15 corresponding to grayscale 15. The first-sixth voltage divider circuit RS16 divides the voltage between the output voltage of the first-fifth multiplexer MUX15 and the output voltage of the second multiplexer MUX02. The first-sixth multiplexer MUX16 selects any one of the voltages divided by the voltage divider circuit RS16 according to the voltage control data REG16. The output voltage of the first-sixth multiplexer MUX16 is output through a buffer and may be a gamma compensation voltage V7 corresponding to grayscale 7.

[0168] The first to seventh voltage divider circuit RS17 divides the voltage between the output voltage of the first to sixth multiplexers MUX16 and the output voltage of the second multiplexer MUX02. The first to seventh multiplexers MUX17 select any one of the voltages divided by the voltage divider circuit RS17 according to the voltage control data REG17. The output voltage of the first to seventh multiplexers MUX17 is output through a buffer and may be a gamma compensation voltage V4 corresponding to grayscale 4. The first to eighth multiplexers MUX18 select any one of the voltages divided by the voltage divider circuit RS17 according to the voltage control data REG18. The output voltage of the first to eighth multiplexers MUX18 is output through a buffer and may be a gamma compensation voltage V1 corresponding to grayscale 1.

[0169] The gray voltage generating unit 151 further includes a plurality of voltage divider circuits RS21 to RS28. The second-first voltage divider circuit RS21 divides the voltage between the highest gamma compensation voltage V255 and the voltage V191 of gray 191 to output the gamma compensation voltage between the highest gray and gray 191. The second-second voltage divider circuit RS22 divides the voltage between the voltage V191 of gray 191 and the voltage V127 of gray 127 to output the gamma compensation voltage between gray 191 and gray 127. The second-third voltage divider circuit RS23 divides the voltage between the voltage V127 of gray 127 and the voltage V63 of gray 63 to output the gamma compensation voltage between gray 127 and gray 63. The second-fourth voltage divider circuit RS24 divides the voltage between the voltage V63 of gray 63 and the voltage V31 of gray 31 to output the gamma compensation voltage between gray 63 and gray 31. The second-fifth voltage divider circuit RS25 divides the voltage between the voltage V31 of gray 31 and the voltage V15 of gray 15 to output the gamma compensation voltage between gray 31 and gray 15. The second-sixth voltage divider circuit RS26 divides the voltage between the voltage V15 of gray 15 and the voltage V7 of gray 7 to output the gamma compensation voltage between gray 15 and gray 7. The second-seventh voltage divider circuit RS27 divides the voltage between the voltage V7 of gray 7 and the voltage V4 of gray 4 to output the gamma compensation voltage between gray 7 and gray 4. The second-eighth voltage divider circuit RS28 divides the voltage between the voltage V4 of gray 4 and the voltage V1 of gray 1 to output the gamma compensation voltage between gray 4 and gray 1.

[0170] The gamma compensation voltage generator 150 may include an R gamma compensation voltage generator, a G gamma compensation voltage generator, and a B gamma compensation voltage generator to obtain an optimal gamma compensation voltage for each color of the sub-pixel. Each of the first voltage control data and the second voltage control data is independently set for each color to select different voltages from the R gamma compensation voltage generator, the G gamma compensation voltage generator, and the B gamma compensation voltage generator. The gamma compensation voltage output from the R gamma compensation voltage generator is a grayscale voltage of the data voltage to be provided to the R sub-pixel. The gamma compensation voltages V0 to V256 output from the G gamma compensation voltage generator are grayscale voltages of the data voltage to be provided to the G sub-pixel. The gamma compensation voltage output from the B gamma compensation voltage generator is a grayscale voltage of the data voltage to be provided to the B sub-pixel.

[0171] The gamma compensation voltages V0 to V255 and the light source driving voltage V256 for each grayscale are input to the DAC of the data driver 110. The DAC of the data driver 110 converts the pixel data received from the timing controller 130 into a gamma compensation voltage having a different voltage for each grayscale, and outputs a data voltage Vdata for driving the display. In the fingerprint recognition mode, the data driver 110 converts the light source driving data received from the timing controller 130 into the light source driving voltage V256, and provides the light source driving voltage V256 to the pixels used as the light source in the third area SA through the data line.

[0172] The PPI of the second area CA and the third area SA is lower than that of the first area DA. Therefore, when the pixels of the first area DA and the pixels of the second area CA and the third area SA are driven by the same data voltage at the same grayscale, the brightness of the second area CA and the third area SA may be reduced. In the present disclosure, the first voltage control data is input to the gamma compensation voltage generator 150 during the scanning period of the first area DA, and the second voltage data is input to the gamma compensation voltage generator 150 during the scanning period of the second area CA and the third area SA, so that the data voltage applied to the second area CA and the third area SA is controlled within a dynamic range larger than the dynamic range of the data voltage applied to the first area DA. In the present disclosure, a programmable gamma IC can be used to independently control the dynamic range of the data voltage for each area of ​​the pixel array. Therefore, in the present disclosure, the brightness of the second area CA and the third area SA with low PPI increases, so that the brightness difference between the areas DA, CA and SA of the pixel array is not visually recognized, thereby achieving uniform brightness over the entire screen.

[0173] Fig.16 is a diagram showing a gamma compensation voltage output from a gamma compensation voltage generator and a data voltage of each region. Fig.16 In FIG. 1 , “PGMA range” indicates the gamma compensation voltage output from the gamma compensation voltage generator 150. Fig.16 As shown, the dynamic range of the data voltage Vdata applied to the second and third areas CA and SA with low PPI is greater than the data voltage range applied to the first area DA with high PPI. In particular, since the dynamic range of the data voltage Vdata is larger at high grayscale, the pixel brightness of low PPI can be increased compared with the pixel brightness of high PPI.

[0174] Fig.17 is a diagram showing gate lines and gate drivers separated for each region of the pixel arrays DA, CA, and SA. Fig.17In FIG. 1 , “GIP” indicates a first gate driver 120 disposed in a border area BZ outside the pixel arrays DA, CA, and SA. “GIA” indicates at least a portion of a second gate driver 123 and / or a third gate driver 124 disposed in the pixel arrays DA, CA, and SA.

[0175] Reference Fig.17 The gate lines GL (DA) and GL (CA / SA) are separated between the first area DA of high PPI and the second and third areas CA and SA of low PPI. The data lines DL are connected between the areas DA, CA, and SA without separation.

[0176] The gate driver GIP is connected to the gate line GL (DA) during the scanning period of the first area DA, and sequentially applies the gate signal to the gate line GL (DA). The nth (n is a natural number) signal transmission unit of the gate driver GIP applies the gate signal to the gate line connected to the nth pixel line, and provides the carry signal to the (n+1)th signal transmission unit of the gate driver GIA provided in the pixel arrays DA, CA and SA. To this end, the gate drivers GIP and GIA are connected to the gate control line CL. The gate control line CL includes a carry line to which the carry signal CAR is applied and a clock line to which the shift clocks CLK1 to CLK4 are applied.

[0177] During the scanning period of the second area CA or the third area SA, the gate driver GIA provided in the pixel arrays DA, CA and SA is connected to the gate line GL (CA / SA), and the gate signal is sequentially applied to the gate line GL (CA / SA). At least a portion of the gate control line CL of the signal transmission unit connected to the gate driver GIA is provided in the pixel arrays DA, CA and SA. The gate control line CL in the pixel arrays DA, CA and SA may overlap with the signal lines DL and GL or the power lines PL1 and PL2 in the pixel arrays DA, CA and SA. As an example, at least a portion of the carry line is formed in the pixel arrays DA, CA and SA as a wiring parallel to the data line DL, the VDD line PL1 and the Vini line PL2, and overlaps with the lines DL, PL1 and PL2.

[0178] Fig.18 and Fig.19 is a diagram showing a carry signal transmission path between gate drivers. Fig.18 and Fig.19 In the example, "ST1 to STm" are signal transmission units. Fig.18 and Fig.19 , the third area SA is omitted, but the second area CA may be interpreted as the third area SA.

[0179] Reference Fig.18, the second area CA may be disposed at a position close to a pixel line of the first area DA where scanning is completed. For example, the second area CA may be disposed at the top or bottom of the pixel arrays DA, CA, and SA.

[0180] The first gate driver GIP may include first to nth (n is a natural number) signal transmission units ST1 to STn connected to the gate lines of the first area DA. The first gate driver GIP sequentially provides gate signals to the gate lines of the first area DA on a pixel line basis to sequentially scan pixels in the first area DA.

[0181] The second gate driver GIA may include an (n+1)th signal transmission unit STn+1 to an mth (m is a natural number greater than n) signal transmission unit STm connected to the gate lines of the second area CA. The (n+1)th signal transmission unit STn+1 receives a carry signal CAR from the first gate driver GIP. The second gate driver GIA starts to be driven when the carry signal is input from the first gate driver GIP, and sequentially provides gate signals to the gate lines of the second area CA on a pixel line basis to sequentially scan the pixels in the second area CA.

[0182] Reference Fig.19 , the second area CA may be disposed in a middle portion of the pixel arrays DA, CA, and SA.

[0183] The first gate driver GIP may include first to nth signal transmission units ST1 to STn and (m+1)th to STm+1 to (m+4)th signal transmission units STm+4 connected to gate lines of the first area DA. The first to nth signal transmission units ST1 to STn sequentially provide gate signals to gate lines connected to first to nth pixel lines in the first area DA. The nth signal transmission unit STn may provide a carry signal CAR to the (n+1)th signal transmission unit STn+1, which is the first signal transmission unit of the second gate driver GIA. The (m+1)th signal transmission unit STm+1 may receive the carry signal CAR from the mth signal transmission unit STm, which is the last signal transmission unit of the second gate driver GIA. After the carry signal CAR is input to the (m+1)th signal transmission unit STm+1, the (m+1)th signal transmission unit STm+1 to the (m+4)th signal transmission unit STm+4 sequentially provide gate signals to the gate lines of the (m+1)th pixel line to the (m+4)th pixel line connected to the first area DA.

[0184] The second gate driver GIA may include the (n+1)th signal transmission unit STn+1 to the mth signal transmission unit STm connected to the gate line of the second area CA. The (n+1)th signal transmission unit STn+1 receives the carry signal CAR from the nth signal transmission unit STn of the first gate driver GIP. After the carry signal CAR is input to the (n+1)th signal transmission unit STn+1, the (n+1)th signal transmission unit STn+1 to the mth signal transmission unit STm sequentially provide gate signals to the gate lines of the pixel lines connected to the second area CA.

[0185] Fig. 20 is a diagram showing a scanning period of each area of ​​a pixel array and lookup table data selected according to the scanning period.

[0186] Reference Fig. 20 , during the scanning period of the first area DA, the first voltage control data recorded in the first lookup table LUT1 is selected. Therefore, during the scanning period of the first area DA, as Fig.16 The data voltage Vdata shown having a relatively small dynamic range is applied to the pixels of the first area DA.

[0187] During the scanning period of the second area CA or the third area SA, the second voltage control data recorded in the second lookup table LUT2 is selected. Fig.16 The data voltage Vdata shown having a relatively large dynamic range is applied to the pixels of the second area CA or the third area SA.

[0188] The gate driver driving the gate lines of the second area CA and the third area SA is partially disposed in the pixel arrays DA, CA, and SA so that a portion of the gate signal can be applied to the gate lines in the pixel arrays. In another embodiment, the gate driver driving the gate lines of the low PPI areas CA and SA is disposed in the pixel arrays DA, CA, and SA to apply the gate signal to the gate lines in the pixel arrays DA, CA, and SA.

[0189] like Fig. 9 As shown in , each of the pixel circuits of the high PPI area DA and the low PPI areas CA and SA can receive a first scan pulse, a second scan pulse, and an EM pulse. In this case, the gate driver for driving the gate lines of the low PPI areas CA and SA, for example, the second gate driver may include a second-first gate driver that outputs a first scan pulse, a second-second gate driver that outputs a second scan pulse, and a second-third gate driver that outputs an EM control pulse. Figure 21 to Figure 26As shown, at least one of the second-first gate driver, the second-second gate driver, and the second-third gate driver may be provided in the pixel arrays DA, CA, and SA.

[0190] Figure 21 to Figure 26 2 is a diagram showing various connection structures of a gate driver that drives a gate line in a low PPI region. Figure 21 to Figure 26 The gate driver shown is a second gate driver or a third gate driver for driving the gate lines GL of the low PPI areas CA and SA. Fig.21 and Fig. 22 , “PIXn-1” and “PIXn” are pixel lines in the second area CA or the third area SA.

[0191] Reference Fig.21 and Fig. 22 The gate driver may include a GIA circuit GIA disposed in the pixel arrays DA, CA, and SA and a GIP circuit GIP disposed in a border region outside the pixel arrays DA, CA, and SA. The GIA circuit GIA and the GIP circuit GIP include a signal transmission unit.

[0192] The (n-1)th GIP circuit GIP applies the (N-1)th scan pulse SCAN(N-1) to the (N-1)th scan line of the (n-1)th pixel line PIXn-1, and applies the EM pulse EM(N) to the N EM line. The (n-1)th GIA circuit GIA applies the (N-2)th scan pulse SCAN(N-2) to the (N-2)th scan line of the (n-1)th pixel line PIXn-1.

[0193] The nth GIP circuit GIP applies the Nth scan pulse SCAN(N) to the Nth scan line of the nth pixel line PIXn and applies the EM pulse EM(N) to the Nth EM line. The nth GIA circuit GIA applies the (N-1)th scan pulse SCAN(N-1) to the (N-1)th scan line of the nth pixel line PIXn.

[0194] Reference Figure 23 to Figure 26 In this embodiment, the gate driver for driving the gate lines of the low PPI areas CA and SA is configured with only a GIA circuit without a GIP circuit. The GIA circuit GIA includes a signal transmission unit. The GIA circuit GIA applies gate signals SCAN(N-2) to SCAN(N) and EM(N) to the gate lines of the pixel lines PIXn-1 and PIXn.

[0195] like Fig. 22 and Fig.23As shown, the GIA circuit GIA is located at the center of the gate line GL of the low PPI area CA and SA, and applies the gate signal to the gate line GL in a single feeding method, but the present disclosure is not limited thereto. For example, two GIA circuits GIA are connected to both ends of the gate lines of the low PPI area CA and SA, and as shown in FIG. Fig.25 As shown in , a dual feeding method is used to simultaneously apply gate signals on both sides of the gate line GL. In addition, three or more GIA circuits GIA are connected to both sides and the center of the gate lines of the low PPI areas CA and SA, and as shown in FIG. Fig.26 As shown, the gate signal is simultaneously applied at a plurality of points of the gate line GL using a dual feeding method, thereby compensating for the RC delay of the gate signal.

[0196] The gate driver of the present disclosure can be applied not only to pixel arrays with partially different resolutions or PPIs, but also to pixel arrays without resolution or PPI differences. For example, the display panel includes a first gate driver and a second gate driver, the first gate driver being configured to provide a gate signal to a gate line connected to a pixel arranged in a first area of ​​the pixel array, and the second gate driver being configured to receive a carry signal from the first gate driver and provide a gate signal to a gate line connected to a pixel arranged in a second area of ​​the pixel array. The second gate driver includes a signal transmission unit arranged in the pixel array to receive a carry signal from the first gate driver.

[0197] The display panel and the display device according to the embodiments of the present disclosure may be described using the following various embodiments.

[0198] Embodiment 1: A display panel comprises: a pixel array, in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are arranged; a first gate driver, which is configured to provide a gate signal to the gate lines connected to the pixels arranged in a first area of ​​the pixel array; and a second gate driver, which is configured to receive a carry signal from the first gate driver and provide the gate signal to the gate lines connected to the pixels arranged in a second area of ​​the pixel array, wherein the second gate driver comprises a first signal transmission unit arranged in the pixel array for receiving the carry signal from the first gate driver.

[0199] Embodiment 2: The resolutions or pixels per inch (PPI) of the first area and the second area are different from each other.

[0200] Embodiment 3: The resolution or PPI of the second region is lower than the resolution or PPI of the first region.

[0201] Embodiment 4: the second region includes a first low PPI region, and the first low PPI region includes a plurality of light-transmitting portions.

[0202] Embodiment 5: The second area further includes a second low PPI area, and a plurality of light sensors are disposed in the second low PPI area.

[0203] Embodiment 6: Gate lines connected to pixels arranged in the second region are separated from gate lines connected to pixels arranged in the first region.

[0204] Embodiment 7: The first gate driver includes a plurality of third signal transmission units arranged in a border area outside the pixel array, for sequentially providing gate signals to gate lines connected to pixels arranged in the first area, and the second gate driver also includes a plurality of second signal transmission units dependently connected to the first signal transmission unit receiving the carry signal from the first gate driver, for sequentially providing gate signals to gate lines connected to pixels arranged in the second area.

[0205] Embodiment 8: The display panel further includes: a gate control line configured to transmit a carry signal from the first gate driver to the second gate driver, wherein at least a portion of the gate control line is disposed in the pixel array.

[0206] Embodiment 9: The first gate driver further includes a fourth signal transmission unit configured to receive the carry signal from the second gate driver and sequentially provide gate signals to some gate lines connected to some pixels disposed in the first region.

[0207] Embodiment 10: Each of the pixels in the first area and the second area includes a sub-pixel having a pixel circuit, and the pixel circuit receives a first scanning pulse, a second scanning pulse, and a light emission control pulse.

[0208] Embodiment 11: The second gate driver includes: a second-first gate driver, which is configured to output a first scanning pulse; a second-second gate driver, which is configured to output a second scanning pulse; and a second-third gate driver, which is configured to output a light emission control pulse, and at least one of the second-first gate driver, the second-second gate driver and the second-third gate driver is arranged in the pixel array.

[0209] Embodiment 12: A display device, comprising: a display panel including a pixel array provided with a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels; a data voltage control unit configured to output first voltage control data during a first scanning period of scanning a first area of ​​the pixel array and to output second voltage control data during a second scanning period of scanning a second area of ​​the pixel array, the first voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the first area, and the second voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the second area; a gamma compensation voltage generator configured to output a first gamma compensation voltage in response to the first voltage control data during a first scanning period of the first area, and outputting a second gamma compensation voltage in response to second voltage control data during a second scanning period in the second area; a data driver configured to: during a first scanning period, convert pixel data into a first gamma compensation voltage to output a data voltage to be provided to pixels set in the first area, and during a second scanning period, convert pixel data into a second gamma compensation voltage to output a data voltage to be provided to pixels set in the second area; a first gate driver configured to provide a gate signal to a gate line connected to the pixels set in the first area during the first scanning period; and a second gate driver configured to receive a carry signal from the first gate driver during the second scanning period and provide the gate signal to the gate line connected to the pixels set in the second area.

[0210] Embodiment 13: The resolution or PPI of the second region is lower than that of the first region, and the dynamic range of the data voltages applied to the pixels of the second region is greater than the dynamic range of the data voltages applied to the pixels of the first region.

[0211] Embodiment 14: The data voltage control unit includes: an area determination unit, which is configured to receive pixel data and a timing signal synchronized with the pixel data, and determine an area of ​​the pixel array that displays the pixel data; a first lookup table, in which first voltage control data has been set; a second lookup table, in which second voltage control data has been set; and a data selection unit, which is configured to select the first voltage control data during a first scanning period and select the second voltage control data during a second scanning period under the control of the area determination unit.

[0212] Embodiment 15: A gamma compensation voltage generator includes a plurality of multiplexers that select one of the divided voltages in response to first voltage control data during a first scan period and select one of the divided voltages in response to second voltage control data during a second scan period.

[0213] Embodiment 16: The second region includes a first low PPI region, the first low PPI region includes a plurality of light-transmitting portions, and the display device further includes: a sensor module disposed at a lower portion of a rear surface of the display panel to face the first low PPI region.

[0214] Embodiment 17: The second region further includes a second low PPI region including a plurality of light sensors disposed in at least a portion of the second region.

[0215] Embodiment 18: The first gate driver includes a plurality of third signal transmission units arranged in a border area outside the pixel array, for sequentially providing gate signals to gate lines connected to pixels arranged in the first area, and the second gate driver arranged in the pixel array includes a plurality of second signal transmission units dependently connected to the first signal transmission unit that receives a carry signal from the first gate driver, for sequentially providing gate signals to gate lines connected to pixels arranged in the second area.

[0216] Embodiment 19: The display panel further includes a gate control line configured to transmit a carry signal from the first gate driver to the second gate driver, and at least a portion of the gate control line is disposed in the pixel array.

[0217] Embodiment 20: The first gate driver further includes a fourth signal transmission unit configured to receive the carry signal from the second gate driver and sequentially provide gate signals to some gate lines connected to some pixels of the first region.

[0218] The object to be achieved by the present disclosure, means for achieving the object, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0219] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display panel, comprising: A pixel array, in which a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels are arranged; a first gate driver configured to provide a gate signal to a gate line connected to a pixel disposed in a first region of the pixel array; as well as a second gate driver configured to receive a carry signal from the first gate driver and provide a gate signal to a gate line connected to a pixel disposed in a second area of ​​the pixel array, The second gate driver includes a first signal transmission unit disposed in the pixel array, configured to receive the carry signal from the first gate driver. wherein a channel ratio of a driving element disposed in the first region is smaller than a channel ratio of a driving element disposed in the second region, and The resolution or PPI of the second area is lower than the resolution or PPI of the first area.

2. The display panel according to claim 1, wherein: The second region includes a first low PPI region, and the first low PPI region includes a plurality of light-transmitting portions.

3. The display panel according to claim 1 or 2, wherein: The second area further includes a second low PPI area, and a plurality of light sensors are disposed in the second low PPI area.

4. The display panel according to claim 1, wherein: Gate lines connected to pixels disposed in the second region are separated from gate lines connected to pixels disposed in the first region.

5. The display panel according to claim 1, wherein: The first gate driver includes a plurality of third signal transmission units disposed in a border area outside the pixel array, for sequentially providing the gate signals to gate lines connected to pixels disposed in the first area, and The second gate driver further includes a plurality of second signal transmission units dependently connected to the first signal transmission unit receiving the carry signal from the first gate driver to sequentially provide the gate signal to gate lines connected to pixels disposed in the second area.

6. The display panel according to claim 5, further comprising: a gate control line configured to transmit the carry signal from the first gate driver to the second gate driver, wherein At least a portion of the gate control line is disposed in the pixel array.

7. The display panel according to claim 5, wherein: The first gate driver further includes a fourth signal transmission unit configured to receive a carry signal from the second gate driver and sequentially provide gate signals to some gate lines connected to some pixels disposed in the first region.

8. The display panel according to claim 5, wherein: Each of the pixels in the first area and the second area includes a sub-pixel having a pixel circuit, and The pixel circuit receives a first scanning pulse, a second scanning pulse, and a light emission control pulse.

9. The display panel according to claim 8, wherein: The second gate driver comprises: a second-first gate driver configured to output the first scanning pulse; a second-second gate driver configured to output the second scanning pulse; and a second-third gate driver configured to output the light emission control pulse, and At least one of the second-first gate driver, the second-second gate driver, and the second-third gate driver is disposed in the pixel array.

10. A display device, comprising: The display panel includes a pixel array having a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixels; a data voltage control unit configured to output first voltage control data during a first scanning period for scanning a first area of ​​the pixel array and to output second voltage control data during a second scanning period for scanning a second area of ​​the pixel array, the first voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the first area, and the second voltage control data being used to control a dynamic range of a data voltage applied to a pixel arranged in the second area; a gamma compensation voltage generator configured to output a first gamma compensation voltage in response to the first voltage control data during a first scan period of the first area, and to output a second gamma compensation voltage in response to the second voltage control data during a second scan period of the second area; a data driver configured to: during the first scanning period, convert pixel data into the first gamma compensation voltage to output a data voltage to be provided to pixels arranged in the first area, and during the second scanning period, convert pixel data into the second gamma compensation voltage to output a data voltage to be provided to pixels arranged in the second area; a first gate driver configured to supply a gate signal to a gate line connected to a pixel disposed in the first area during the first scanning period; as well as a second gate driver configured to receive a carry signal from the first gate driver during the second scanning period and to provide a gate signal to a gate line connected to a pixel provided in the second area, The second gate driver includes a first signal transmission unit disposed in the pixel array, configured to receive the carry signal from the first gate driver, and The resolution or PPI of the second area is lower than the resolution or PPI of the first area.

11. The display device according to claim 10, wherein: A dynamic range of the data voltages applied to the pixels of the second region is greater than a dynamic range of the data voltages applied to the pixels of the first region.

12. The display device according to claim 10, wherein: The data voltage control unit includes: an area determination unit configured to receive the pixel data and a timing signal synchronized with the pixel data, and determine an area of ​​the pixel array displaying the pixel data; a first lookup table, in which the first voltage control data has been set; a second lookup table, in which the second voltage control data has been set; and A data selection unit is configured to select the first voltage control data during the first scanning period and select the second voltage control data during the second scanning period under the control of the area determination unit.

13. The display device according to claim 10, wherein: The gamma compensation voltage generator includes a plurality of multiplexers that select one of the divided voltages in response to the first voltage control data during the first scan period and select one of the divided voltages in response to the second voltage control data during the second scan period.

14. The display device according to claim 10, wherein: The second region includes a first low PPI region, wherein the first low PPI region includes a plurality of light-transmitting portions, The display device further includes: A sensor module is disposed at a lower portion of a rear surface of the display panel to face the first low PPI area.

15. The display device according to claim 10 or 14, wherein: The second area further includes a second low PPI area including a plurality of light sensors disposed in at least a portion of the second area.

16. The display device according to claim 10, wherein: The first gate driver includes a plurality of third signal transmission units disposed in a border region outside the pixel array, for sequentially providing the gate signals to gate lines connected to pixels disposed in the first region, and The second gate driver provided in the pixel array includes a plurality of second signal transmission units dependently connected to the first signal transmission unit to sequentially provide the gate signals to gate lines connected to the pixels provided in the second area.

17. The display device according to claim 16, wherein: The display panel further includes a gate control line configured to transmit the carry signal from the first gate driver to the second gate driver, and At least a portion of the gate control line is disposed in the pixel array.

18. The display device according to claim 10, wherein: The first gate driver further includes a fourth signal transmission unit configured to receive a carry signal from the second gate driver and sequentially provide gate signals to some gate lines connected to some pixels of the first area.

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