Non-volatile storage device, method of programming operation thereof, and storage system

Abstract

This application provides a non-volatile memory device and its programming operation method and memory system. The programming operation method of the non-volatile memory device includes: performing a second programming operation on a first memory cell among a plurality of memory cells connected to a first word line and having already undergone a first programming operation; performing the first programming operation on a second memory cell connected to a second word line at least one third word line spaced from the first word line, wherein the first memory cell and the second memory cell are located on a first memory string; and performing a first sub-step on memory cells located on the same memory string other than the first memory string, until the plurality of memory cells connected to the first word line complete the second programming operation and the plurality of memory cells connected to the second word line complete the first programming operation, wherein the first sub-step includes: sequentially performing the second programming operation on the memory cells connected to the first word line and performing the first programming operation on the memory cells connected to the second word line.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a programming operation method for a non-volatile memory device, a non-volatile memory device, and a non-volatile memory system. Background Technology

[0002] Non-volatile memory systems retain stored data even after power loss and are widely used in computers, cellular phones, smartphones, personal digital assistants, and other electronic device systems. A non-volatile memory system typically includes a non-volatile memory device as the storage medium and a control device for controlling the non-volatile memory device. The non-volatile memory device further includes an array formed by multiple memory cells.

[0003] The structure of a memory cell typically includes a tunneling layer, a charge trapping layer, and a charge blocking layer from the channel layer to the gate. During programming (data writing), charge is injected into the charge trapping layer from the channel layer through the tunneling layer under the influence of a strong electric field. The charge trapping layer contains numerous traps, trapping the charge within them. The deeper the trap's energy level, the better the charge retention. However, in some real-world scenarios, the trap energy levels vary in depth; traps at shallow energy levels exhibit poor charge retention and are prone to charge leakage. In other scenarios, the charge is trapped in the tunneling layer's traps. These traps also have poor charge retention, and within a short time after the programming operation ends, the charge detaches from the tunneling layer and returns to the channel layer, causing the threshold voltage to drift downwards. Summary of the Invention

[0004] This application provides a programming operation method for a non-volatile memory device. The programming operation method includes: performing a second programming operation on a first memory cell among a plurality of memory cells connected to a first word line and having already undergone a first programming operation; performing the first programming operation on a second memory cell connected to a second word line at least one third word line spaced from the first word line, wherein the first and second memory cells are located on a first memory string; and performing a first sub-step on memory cells located on the same memory string other than the first memory string, until the plurality of memory cells connected to the first word line complete the second programming operation and the plurality of memory cells connected to the second word line complete the first programming operation, wherein the first sub-step includes: sequentially performing the second programming operation on the memory cells connected to the first word line and performing the first programming operation on the memory cells connected to the second word line.

[0005] In some embodiments, a plurality of memory cells connected to a third word line have performed a first programming operation. The programming operation method further includes: performing a second sub-step on memory cells located on the same memory string until the plurality of memory cells connected to the third word line have completed the second programming operation. The second sub-step includes: alternately performing the second programming operation on memory cells connected to each third word line, performing the first programming operation on memory cells connected to each fourth word line adjacent to the second word line, and performing the second programming operation on the second memory cells.

[0006] In some implementations, after performing a first programming operation on the second memory cell and then performing programming operations on 2n(m+1)-2 memory cells, a second programming operation is performed on the second memory cell, where m is the number of third word lines and n is the number of memory cells connected to each word line.

[0007] In some implementations, the first sub-step is executed sequentially on memory cells located on the same memory string other than the first memory string, in a predetermined order.

[0008] In some implementations, the second sub-step is performed sequentially on memory cells located on the same memory string in a predetermined order.

[0009] In some implementations, the storage unit includes one of QLC, TLC or MLC.

[0010] In some implementations, the first programming operation is a coarse programming operation, and the second programming operation is a fine programming operation.

[0011] This application also provides a non-volatile memory device, which includes: a first word line, a second word line, a third word line, a plurality of memory strings including a first memory string, and peripheral circuitry. The peripheral circuitry is electrically connected to the first word line, the second word line, the third word line, and the plurality of memory strings, and is configured to: perform a second programming operation on a first memory cell among a plurality of memory cells connected to the first word line and having undergone a first programming operation; perform a first programming operation on a second memory cell connected to a second word line at least one third word line away from the first word line, wherein the first memory cell and the second memory cell are located on a first memory string; and perform a first sub-step on memory cells located on the same memory string other than the first memory string, until the plurality of memory cells connected to the first word line complete the second programming operation and the plurality of memory cells connected to the second word line complete the first programming operation, wherein the first sub-step includes: sequentially performing the second programming operation on the memory cells connected to the first word line and performing the first programming operation on the memory cells connected to the second word line.

[0012] In some embodiments, the non-volatile memory device further includes a fourth word line adjacent to the first word line, wherein a plurality of memory cells connected to the third word line have performed a first programming operation, and the peripheral circuitry is further configured to: perform a second sub-step on memory cells located on the same memory string until the plurality of memory cells connected to the third word line have completed a second programming operation, wherein the second sub-step includes: alternately performing a second programming operation on memory cells connected to each third word line, performing a first programming operation on memory cells connected to each fourth word line; and performing a second programming operation on second memory cells.

[0013] In some implementations, the storage unit includes one of QLC, TLC or MLC.

[0014] This application also provides a non-volatile storage system, which includes: at least one non-volatile storage device; and a control device electrically connected to the non-volatile storage device and controlling the non-volatile storage device to perform the programming operation method as described in any of the embodiments above.

[0015] According to the embodiments of the present application, the non-volatile memory device and its programming operation method and non-volatile memory system, by increasing the interval between the first programming operation and the second programming operation performed by the memory cell (i.e., the interval between other memory cells performing programming operations), more charges located in shallow energy levels can retreat back into the channel layer after the first programming operation, thereby making more charges in the memory cell located in deep energy levels after the second programming operation. This is beneficial to weakening the tendency of the threshold voltage to drift in the direction of decreasing and to increasing the read window size. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0017] Figure 1 This is a functional block diagram of a non-volatile storage device according to an embodiment of this application;

[0018] Figure 2 This is an equivalent circuit diagram of a storage block according to an embodiment of this application;

[0019] Figure 3 This is a schematic cross-sectional view of the storage string according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the threshold voltage distribution of a QLC memory cell according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram showing the change of threshold voltage drift of a memory cell over time according to an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the threshold voltage drift of a QLC memory cell according to an embodiment of this application;

[0023] Figure 7 This is a flowchart of a programming operation method for a non-volatile memory device according to an embodiment of this application;

[0024] Figures 8A to 8E This is a schematic diagram showing the sequence of programming operations performed by each storage unit in the programming operation method according to the embodiments of this application;

[0025] Figure 9 This is a schematic diagram of the threshold voltage distribution after the QLC memory cell performs the first programming operation and the second programming operation according to the embodiments of this application;

[0026] Figure 10 This is a schematic diagram illustrating the sequence of programming operations performed by each storage unit in the programming operation method of related technologies;

[0027] Figure 11 This is a schematic diagram illustrating the threshold voltage drift of a memory cell after performing a second programming operation according to the programming operation method of the present application and related technologies; and

[0028] Figure 12A and 12B This is a functional block diagram of a non-volatile storage system according to an embodiment of this application. Detailed Implementation

[0029] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0030] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0031] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0032] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0033] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is a functional block diagram of a non-volatile storage device 100 according to an embodiment of this application. For example... Figure 1 As shown, the non-volatile memory device 100 may include a memory cell array 110 and peripheral circuitry such as a page buffer 121, a row decoder 122, a column decoder 123, a voltage generator 124, a logic control module 125, an I / O module 126, and a data bus 127. It should be understood that the operations performed by the circuit modules described above in this application can be executed by processing circuitry. Optionally, the processing circuitry may include, but is not limited to, hardware logic circuitry or a hardware / software combination of a processor executing software.

[0035] The memory cell array 110 is connected to the row decoder 122 via, for example, word lines (WL), and to the column decoder 123 via, for example, bit lines (BL), and may be, for example, a NAND architecture. Exemplarily, the memory cell array 110 may include a plurality of dies (LUNs), each die being a basic unit for receiving and executing, for example, programming commands and read commands. Each die may include a plurality of planes, each plane may include a plurality of blocks, and each block may include a plurality of pages corresponding to word lines.

[0036] Page buffer (or "sensing amplifier") 121 can be configured to read data from or program (write) data to memory cell array 110 based on control signals from logic control module 125. In one example, page buffer 121 can store data to be programmed into a page of memory cell array 110. In another example, page buffer 121 can sense low-power signals of data stored in memory cells of memory cell array 110 during a read operation and amplify small voltage swings to a recognizable logic level.

[0037] The row decoder 122 can be configured to be controlled by the logic control module 125 and to select memory blocks in the memory cell array 110, and further select pages within those memory blocks. For example, the row decoder 122 can be configured to select pages using a voltage generated by the voltage generator 124 via a drive word line.

[0038] The column decoder 123 can be configured to be controlled by the logic control module 125 and to select one or more memory strings by applying a bit line voltage generated by the voltage generator 124.

[0039] The voltage generator 124 can be configured to be controlled by the logic control module 125 and generate word line voltages (e.g., charging voltage, ground voltage, read voltage, programming voltage, pass voltage, verification voltage, etc.), bit line voltages, and source line voltages, etc., to be supplied to the memory cell array 110.

[0040] The logic control module 125 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The logic control module 125 can execute the programming operation methods described below.

[0041] I / O module 126 can be coupled to logic control module 125 to forward control commands received from host or control device (not shown) to logic control module 125, and to forward status information received from logic control module 125 to host or control device. I / O module 126 can also be coupled to column decoder 123 via data bus 127 to buffer and forward data to and from memory cell array 110.

[0042] Figure 2 This is an equivalent circuit diagram of the storage block 200 according to an embodiment of this application. For example... Figure 2 As shown, storage block 200 can be Figure 1 An example of a portion of the storage cell array 110 shown in the figure.

[0043] In some embodiments, the memory block 200 may include multiple memory strings, such as MS1 to MS4. The multiple memory strings MS1 to MS4 may be arranged in a two-dimensional array on the xy plane. Each memory string (e.g., MS1) may extend along the z-direction and may sequentially include a top selection transistor TST1, a memory cell MC, and a bottom selection transistor BST connected to each other at their source and drain terminals. It should be noted that the number of selection transistors TST / BST and memory cells MC in each memory string (e.g., MS1) is merely exemplary, and this application does not specifically limit the number of the above structures.

[0044] In some implementations, multiple memory strings (e.g., MS1 to MS4) in memory block 200 may be connected to a common source line CSL. For example, the source terminal of the bottom select transistor BST located at the end of each memory string (e.g., MS1 to MS4) may be connected to the common source line CSL.

[0045] In some implementations, the gate terminals of memory cells (e.g., MC11 to MC41) located at the same or similar height from the common source line CSL in multiple memory strings (e.g., MS1 to MS4) can be connected to the same word line (e.g., WL1).

[0046] In some implementations, the gates of top-select transistors (e.g., TST1 and TST2) in memory strings MS1 and MS2 arranged in the x-direction, located at the same or similar height from the common source line CSL, can be connected to the same top-select line TSL1. Similarly, the gates of top-select transistors (e.g., TST3 and TST4) in memory strings MS3 and MS4 arranged in the x-direction, located at the same or similar height from the common source line CSL, can be connected to the same top-select line TSL2.

[0047] In some embodiments, the gates of bottom selection transistors (BSTs) in multiple memory strings (e.g., MS1–MS4) located at the same or similar height from the common source line (CSL) can be connected to the same bottom select line (BSL). In other embodiments, similar to top select lines (TSL1 and TSL2), the gates of bottom selection transistors (BSTs) in memory strings arranged in the x-direction, such as MS1 and MS2, located at the same or similar height from the common source line (CSL), can be connected to the same bottom select line (BSL1, not shown). The gates of bottom selection transistors (BSTs) in memory strings arranged in the x-direction, such as MS3 and MS4, located at the same or similar height from the common source line (CSL), can be connected to the same bottom select line (BSL2, not shown).

[0048] In some implementations, the drain terminals of the top select transistors TST1 and TST3, located at the same or similar height from the common source line CSL in memory strings MS1 and MS3 arranged in the y-direction, can be connected to the same bit line BL1. Similarly, the drain terminals of the top select transistors TST2 and TST4, located at the same or similar height from the common source line CSL in memory strings MS2 and MS4 arranged in the y-direction, can be connected to the same bit line BL2.

[0049] In some implementations, according to the structure described above, the extension direction of the bit lines (e.g., BL1 and BL2) may be perpendicular or substantially perpendicular to the extension direction of the top selection lines (e.g., TSL1 and TSL2). It should be noted that... Figure 2 The number of storage strings, word lines, bit lines, and select lines in the storage block 200 shown is merely exemplary, and this application does not specifically limit the number of the above structures.

[0050] In some implementations, such as Figure 2 As shown, when performing a programming operation on a memory cell MC11 connected to, for example, word line WL1, a programming voltage (e.g., 15–21V) can be applied to word line WL1, and the bottom select transistor BST and top select transistor TST1 on the memory string MS1 containing memory cell MC11 can be turned on. A ground voltage, for example, can be applied to bit line BL1 connected to the memory string MS1 containing memory cell MC11. Under the influence of the high voltage on word line WL1, charge is trapped in the charge trapping layer according to the tunneling effect, thereby causing memory cell MC11 to reach a predetermined threshold voltage. Optionally, the top select transistor TST3 and / or the bottom select transistor BST in MS3 can be turned off to suppress programming of memory cell M31 in memory string MS3. Optionally, a programmable disable voltage (e.g., 2V) can be applied to bit line BL2 to prevent charge tunneling, thereby suppressing programming of memory cell M21 in memory string MS2. The programming operation will be described in detail below in conjunction with the physical structure of the memory cell.

[0051] In some implementations, such as Figure 2 As shown, when performing a read operation on a memory cell, such as M11, which has already been programmed, the bit line BL1 connected to the memory string MS1 containing memory cell MC11 can be charged to a threshold value and then left floating. Then, an on-state voltage (e.g., 5V) can be applied to the word line WL, excluding word line WL1. This turns on the bottom select transistor BST and top select transistor TST1 on the memory string MS1 containing memory cell MC11, and turns off the top select transistor TST3 and bottom select transistor BST on the memory string MS3 containing MC31. By applying a read voltage to word line WL1 and sensing the current value at the bit line BL1, the threshold voltage range of the memory cell M11 after the programming operation is determined, thus identifying the data stored in memory cell MC11. The read operation will be described in detail below in conjunction with the physical structure of the memory cell.

[0052] Figure 3 This is a schematic cross-sectional view of the storage string 300 according to an embodiment of this application. Figure 3 As shown, storage string 300 can be Figure 2 An example of a portion of any of the storage strings MS1 to MS4 shown in the figure.

[0053] The memory string 300 includes a plurality of memory cells (e.g., 350) disposed in the z-direction. Each memory cell may have the same physical structure. Optionally, the memory cell 350 may be a charge-trapping memory cell. For example, the memory cell 350 may include a gate 360-1, a charge blocking layer 310, a charge trapping layer 320, a tunneling layer 330, and a channel layer 340. The material of the charge trapping layer 320 may be, for example, silicon nitride. Optionally, a word line 360-2 may be physically connected to the gate 360-1 of the memory cell 350 on the memory string 300, and the word line 360-2 may also be physically connected to the gates of memory cells in other memory strings (not shown) located at the same height (e.g., in the z-direction) or approximately the same height.

[0054] When programming the memory cell 350, the charge trapping layer 320 can trap the charge from the channel layer 340 and through the tunneling layer 330 under the voltage control of the gate 360-1 according to the tunneling effect. Depending on the amount of charge in the charge trapping layer 320 of the memory cell 350, the memory cell 350 can be made to have different threshold voltages, i.e., predetermined threshold voltage ranges, and thus be in different programming states.

[0055] The number of threshold voltage ranges that the storage cell 350 can reach is related to the size of the data stored in the storage cell 350. For example, the storage cell 350 may be one of the following: SLC that can reach 2 threshold voltage ranges and store 1 bit of data, MLC that can reach 4 threshold voltage ranges and store 2 bits of data, TLC that can reach 8 threshold voltage ranges and store 8 bits of data, or QLC that can reach 16 threshold voltage ranges and store 16 bits of data.

[0056] Figure 4 This is a schematic diagram of the threshold voltage distribution of a QLC memory cell according to an embodiment of this application. For example... Figure 4 As shown, the horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. Before the QLC memory cell performs a programming operation, its threshold voltage is in the L0 range. After the programming operation, the threshold voltage of the QLC memory cell can be in any range from L1 to L15. The ranges L0 to L15 correspond to the data stored in the QLC memory cell. For example, when the threshold voltage of the QLC memory cell is in the L0 range, it means that the data stored in the QLC memory cell is 1111; when the threshold voltage of the QLC memory cell is in the L15 range, it means that the data stored in the QLC memory cell is 1110.

[0057] QLC storage cells can have, for example Figure 3 The physical structure shown, if the charge trapping layer 320 of the QLC memory cell (reference) Figure 2If the amount of charge stored in a QLC memory cell falls within a certain range, then the threshold voltage of the QLC memory cell is within a certain range. Figure 3 The diagram shows a certain threshold voltage range. It should be noted that due to differences in the physical structure of each QLC memory cell, not all QLC memory cells have a charge trapping layer 320 capable of trapping the exact same amount of charge. This results in the threshold voltage of the QLC memory cell exhibiting a centrally symmetrical Gaussian distribution, rather than an ideal linear distribution.

[0058] When performing a read operation on a QLC memory cell, the gate 360-1 of the QLC memory cell (reference) is accessed. Figure 2 A read voltage (e.g., Vr1) is applied between two intervals (e.g., L1 and L2 intervals) to determine whether the QLC memory cell is turned on, thereby determining the L0 to L15 interval in which the QLC memory cell is located, and further determining the data stored in the QLC memory cell.

[0059] As described above, during the programming operation of a memory cell (e.g., a QLC memory cell), numerous traps exist in the charge trapping layer 320, trapping charges within them. The deeper the energy level of the traps in the charge trapping layer 320, the better the charge retention characteristics. Conversely, the shallower the energy level of the traps in the charge trapping layer 320, the worse the charge retention characteristics. On the other hand, some shallower traps may also exist in the tunneling layer 330, where charges may become trapped as they pass through. Shortly after the programming operation (from microseconds to seconds), charges trapped in shallow traps can more easily escape and return to the channel layer 340, causing the threshold voltage of the memory cell to drift in a decreasing direction.

[0060] Figure 5 This is a schematic diagram showing the change of the threshold voltage drift of a memory cell over time according to an embodiment of this application. Figure 6 This is a schematic diagram of the threshold voltage drift of a QLC memory cell according to an embodiment of this application. Figure 5 As shown, the solid line represents the threshold voltage distribution at the end of the programming operation of the memory cell, and the dashed line represents the gradual shift of the threshold voltage of the memory cell in the direction of decreasing (arrow direction) as the waiting time after the programming operation ends.

[0061] like Figure 6As shown, for QLC memory cells, in order to enable the QLC memory cell to store 16 bits of data, i.e., to achieve 16 threshold voltage ranges, it is usually necessary to compress the distribution width of each threshold voltage range to increase the read voltage distribution width (read window) between adjacent threshold voltage ranges. Thus, when a QLC memory cell is in a larger threshold voltage range L15, it is more prone to charge loss as described above, causing the threshold voltage of the QLC memory cell in the larger threshold voltage range L15 to drift more easily in the decreasing direction (arrow direction). Similarly, for TLC and MLC memory cells, the aforementioned threshold voltage drift problem due to charge loss may also occur when TLC and MLC memory cells are in a larger threshold voltage range.

[0062] This application provides a programming operation method for a non-volatile storage device. Figure 7 This is a flowchart of a programming operation method 1000 for a non-volatile memory device according to an embodiment of this application. For example... Figure 7 As shown, programming operation method 1000 includes the following steps:

[0063] S110, perform a second programming operation on the first memory cell among a plurality of memory cells connected to the first word line and which has already undergone a first programming operation;

[0064] S120, performing a first programming operation on a second memory cell connected to a second word line that is at least one third word line apart from the first word line, wherein the first and second memory cells are located on a first memory string; and

[0065] S130, perform a first sub-step on the storage cells located on the same storage string other than the first storage string, until the multiple storage cells connected to the first word line complete the second programming operation and the multiple storage cells connected to the second word line complete the first programming operation, wherein the first sub-step includes: sequentially performing the second programming operation on the storage cells connected to the first word line and performing the first programming operation on the storage cells connected to the second word line.

[0066] Figures 8A to 8E This is a schematic diagram showing the sequence of programming operations performed by each storage unit in the programming operation method 1000 according to the embodiments of this application. Figures 8A to 8E The word lines, memory strings, and individual memory cells shown can be Figure 2 An example of a portion of storage block 200 is shown below. (The following is in conjunction with...) Figures 8A to 8E The programming operation method 1000 for a non-volatile memory device is further explained.

[0067] In implementation method one, Figure 8A Four word lines WL are shown. n+1WL n WL n-1 and WL n-2 And four memory strings Str0, Str1, Str2, and Str3. The intersection of each word line and each memory string is a memory cell. Optionally, the memory cell may be, for example, a QLC memory cell.

[0068] A method for performing programming operations on, for example, a QLC memory cell may include sequentially performing a first programming operation and a second programming operation on the QLC memory cell. It should be noted that, in this application, after performing a first programming operation on a QLC memory cell, the second programming operation can be performed again on the QLC memory cell that has already undergone the first programming operation after performing either the first or second programming operation on any number of other QLC memory cells.

[0069] Figure 9 This is a schematic diagram of the threshold voltage distribution after the QLC memory cell performs the first programming operation and the second programming operation according to the embodiments of this application. Figure 9 As shown, after performing a first programming operation, a QLC memory cell can form a (approximate) threshold voltage range distribution. Further, after performing a second programming operation on the QLC memory cell that has already undergone the first programming operation, the formed (approximate) threshold voltage range distribution can be finely narrowed. Therefore, the first programming operation can be called a coarse programming operation, and the second programming operation can be called a fine programming operation. For example, the first programming operation or the second programming operation can be performed on the QLC memory cell based on Incremental Step Pulse Program (ISPP). For example, by controlling the step size of the ISPP, the QLC memory cell can be controlled to reach a predetermined threshold voltage range after performing the first programming operation and the second programming operation, respectively. For example, a first verification voltage V' can be used... vfy To verify that the QLC memory cell reaches the target threshold voltage range L1' after the first programming operation, a second verification voltage V is used. vfy This is used to verify the target threshold voltage range L1 reached by the QLC memory cell after the second programming operation. Optionally, the first verification voltage V' vfy Less than the second verification voltage V vfy .

[0070] Refer again Figure 8A , with the first character line WL n-2 The connected memory cells MC0, MC2, MC4, and MC6 and the third word line WL n-1 The connected storage units MC8, MC10, MC12 and MC14 have completed the first programming operation.

[0071] In step S110, the first word line WL is... n-2 The connected, first memory cell MC0, which has already undergone the first programming operation, performs the second programming operation. Figure 8A MC0 (2) The representation of other memory cells performing the first or second programming operation is the same as that of MC0. (2) resemblance.

[0072] In step S120, the second word line WL is located on the storage string Str0. n The connected second memory cell MC1 performs the first programming operation. In this embodiment, the first word line WL n-2 Second letter WL n There is a third letter WL between them. n-1 .

[0073] In step S130, the first sub-step is performed three times on the storage cells located on storage strings Str1, Str2, and Str3 (excluding storage string Str0). For example, firstly, the storage cells located on storage string Str1 and connected to the first word line WL are processed. n-2 The connected memory cell MC2 performs a second programming operation on the memory string Str1 and the second word line WL. n The connected memory cell MC3 performs the first programming operation. Then, the program is applied to the memory string Str2 and connected to the first word line WL. n-2 The connected memory cell MC5 performs a second programming operation on the memory string Str2 and the second word line WL. n The connected memory cell MC4 performs the first programming operation. Next, the program is applied to the memory string Str3 and connected to the first word line WL. n-2 The connected memory cell MC6 performs a second programming operation on the memory string Str3 and the second word line WL. n The connected memory cell MC7 performs the first programming operation. By executing the first sub-step three times, the first word line WL is made compatible. n-2 The connected memory cells MC0, MC2, MC4, and MC6 complete the second programming operation, and connect with the second word line WL. n The connected storage units MC1, MC3, MC5 and MC7 complete the first programming operation.

[0074] It should be noted that in this step, the first sub-step can be performed in a numbering order different from that of storage strings Str1, Str2, and Str3, and this application does not specifically limit this. For example, the first sub-step can be performed sequentially on storage cells MC4 and MC5 on storage string Str2, storage cells MC6 and MC7 on storage string Str3, and storage cells MC2 and MC3 on storage string Str1.

[0075] It is worth noting that the first, second, and third word lines described in the above programming operation method 1000 are merely examples and are not intended to limit specific positions. For example, word line WL can be... n-1 As the first letter, WL n+1 As the second letter line and WL n As the third word line, and using the programming operation method 1000 described above, after completing steps S110 to S130, a first programming operation or a second programming operation is performed on the memory cells connected to the re-determined word lines.

[0076] For clarity, the following description of WL will still follow the approach described in Implementation Method 1. n-2 As the first letter, WL n As the second letter line and WL n-1 As a third line, the subsequent steps of steps S110 to S130, such as S140 and S150, are further described.

[0077] For example, in step S140, the fourth word line WL n+1 Can be used with the second letter WL n Adjacent settings, and the fourth word line WL n+1 With the third letter line WL n-1 The quantities are equal. And the fourth letter line WL n+1 The connected memory cells MC9, MC11, MC13, and MC15 did not undergo the first programming operation. In this step, the second sub-step can be performed four times on memory cells located on the same memory strings Str0, Str1, Str2, and Str3. For example, firstly, the memory cells located on memory string Str0 and connected to the third word line WL... n-1 The connected memory cell MC8 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+1 The connected memory cell MC9 performs the first programming operation. Then, the program is applied to the memory string Str1 and the third word line WL. n-1 The connected memory cell MC10 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+1 The connected memory cell MC11 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-1 The connected memory cell MC12 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+1 The connected memory cell MC13 performs the first programming operation. Finally, the program is applied to the memory string Str3 and the third word line WL. n-1 The connected memory cell MC14 performs a second programming operation on the memory string Str3 and the fourth word line WL.n+1 The connected memory cell MC15 performs the first programming operation. By performing four second sub-steps, the third word line WL is connected... n-1 The connected storage units MC8, MC10, MC12, and MC14 complete the second programming operation. It should be noted that the second sub-step can be executed in a numbering order different from that of the storage strings Str0, Str1, Str2, and Str3; this application does not specifically limit this.

[0078] For example, in step S150, a second programming operation is performed on the second storage unit MC1, which has already completed the first programming operation in step S110. It is understood that the first programming operation or the second programming operation of the second storage unit MC1 is spaced 14 storage units apart.

[0079] In implementation method two, Figure 8B Six word lines WL are shown. n+2 WL n+1 WL n WL n-1 WL n-2 and WL n-3 And four memory strings: Str0, Str1, Str2, and Str3. The intersection of each word line and each memory string is a memory cell. (This is related to the first word line WL.) n-3 The connected memory cells MC0, MC2, MC4, and MC6, and the third word line WL n-2 The connected memory cells MC8, MC10, MC12, and MC14, and the third word line WL n-1 The connected storage units MC16, MC18, MC20 and MC22 have completed the first programming operation.

[0080] In step S110, for the first word line WL n-3 The first memory cell MC0, which is connected and has already undergone the first programming operation, performs the second programming operation.

[0081] In step S120, the second word line WL is located on the storage string Str0. n The connected second memory cell MC1 performs the first programming operation. In this embodiment, the first word line WL n-3 Second letter WL n Two third-letter lines WL are spaced between them. n-1 and WL n-2 .

[0082] In step S130, the first sub-step is performed once for storage cells MC2 and MC3 located on storage string Str1 (excluding storage string Str0), and the first sub-step is performed once for storage cells MC4 and MC5 on storage string Str2, until the first word line WL is reached. n-3 The connected memory cells MC0, MC2, MC4, and MC6 complete the second programming operation, and connect with the second word line WL. n The connected storage units MC1, MC3, MC5, and MC7 complete the first programming operation. Similar to Embodiment 1, the first sub-step can be executed in a numbering order different from that of the storage strings Str1, Str2, and Str3; this application does not specifically limit this.

[0083] For example, in the subsequent step S140, the fourth word line WL n+1 and WL n+2 Can be used with the second letter WL n Adjacent settings, and the fourth word line WL n+1 and WL n+2 With the third letter line WL n-1 and WL n-2 The quantities are equal. And the fourth letter line WL n+1 and WL n+2 The connected storage units MC9, MC11, MC13, MC15, MC17, MC19, MC21 and MC23 did not perform the first programming operation.

[0084] For example, in this step, the second sub-step can be performed eight times on the memory cells located on the same memory strings Str0, Str1, Str2, and Str3. For instance, firstly, the memory cells located on memory string Str0 and connected to the third word line WL are processed. n-2 The connected memory cell MC8 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+1 The connected memory cell MC9 performs the first programming operation. Then, the program is applied to the memory string Str1 and the third word line WL. n-2 The connected memory cell MC10 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+1 The connected memory cell MC11 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-2 The connected memory cell MC12 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+1 The connected memory cell MC13 performs the first programming operation. Finally, the program is applied to the memory string Str3 and the third word line WL. n-2The connected memory cell MC14 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+1 The connected storage unit MC15 performs the first programming operation.

[0085] Furthermore, for the storage string Str0 and the third word line WL n-1 The connected memory cell MC16 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+2 The connected memory cell MC17 performs the first programming operation. Then, the program is applied to the memory string Str1 and the third word line WL. n-1 The connected memory cell MC18 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+2 The connected memory cell MC19 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-1 The connected memory cell MC20 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+2 The connected memory cell MC21 performs the first programming operation. Finally, the program is applied to the memory string Str3 and the third word line WL. n-1 The connected memory cell MC22 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+2 The connected memory cell MC23 performs the first programming operation. By executing the second sub-step eight times, the third word line WL is then connected. n-2 The connected memory cells MC8, MC10, MC12, and MC14, as well as the third word line WL n-1 The connected storage units MC16, MC18, MC20, and MC22 complete the second programming operation. Optionally, the second sub-step can be executed in a numbering order different from that of the storage strings Str0, Str1, Str2, and Str3; this application does not specifically limit this.

[0086] For example, when the number of third or fourth word lines is greater than one, the second sub-step can be performed alternately on each memory cell located on the same memory string and connected to the third and fourth word lines respectively, for example, according to the method described above. Optionally, the multiple third and fourth word lines described in the above programming operation method 1000 are merely examples and are not intended to limit their specific locations. For example, such as Figure 8C and 8D As shown, when the second sub-step is executed alternately on each memory cell located on the same memory string and connected to the third word line and the fourth word line respectively, the specific position of any one of the multiple third word lines or multiple fourth word lines is not restricted.

[0087] For example, in step S150, a second programming operation is performed on the second storage unit MC1, which has already completed the first programming operation in step S110. It is understood that the first programming operation or the second programming operation of the second storage unit MC1 is spaced 22 storage units apart.

[0088] In implementation method three, Figure 8E Eight word lines WL are shown. n+3 WL n+2 WL n+1 WL n WL n-1 WL n-2 WL n-3 and WL n-3 And five memory strings: Str0, Str1, Str2, Str3, and Str4. The intersection of each word line and each memory string is a memory cell. The first word line WL... n-4 The connected memory cells MC0, MC2, MC4, MC6 and MC8, and the third word line WL n-3 The connected memory cells MC10, MC12, MC14, MC16 and MC18, and the third word line WL n-2 The connected memory cells MC20, MC22, MC24, MC26, and MC28, as well as the third word line WL, n-1 The connected storage units MC30, MC32, MC34, MC36 and MC38 have completed the first programming operation.

[0089] In step S110, for the first word line WL n-4 The first memory cell MC0, which is connected and has already undergone the first programming operation, performs the second programming operation.

[0090] In step S120, the second word line WL is located on the storage string Str0. n The connected second memory cell MC1 performs the first programming operation. In this embodiment, the first word line WL n-4 Second letter WL n There are 3 third-letter lines WL between them n-1 WL n-2 and WL n- 3.

[0091] In step S130, the first sub-step is performed once for storage cells MC2 and MC3 located on storage string Str1 (excluding storage string Str0), once for storage cells MC4 and MC5 on storage string Str2, once for storage cells MC4 and MC5 on storage string Str3, and once for storage cells MC8 and MC9 on storage string Str4, until the first word line WL is reached. n-4 The connected memory cells MC0, MC2, MC4, MC6, and MC8 complete the second programming operation, and connect with the second word line WL. n The connected storage units MC1, MC3, MC5, MC7, and MC9 complete the first programming operation. Similar to Embodiment 1, the first sub-step can be executed in a numbering order different from that of the storage strings Str1, Str2, Str3, and Str4; this application does not specifically limit this.

[0092] For example, in the subsequent step S140, the fourth word line WL n+1 WL n+2 and WL n+3 Can be used with the second letter WL n Adjacent settings, and the fourth word line WL n+1 WL n+2 and WL n+3 With the third letter line WL n-1 WL n-2 and WL n-3 The quantities are equal. And the fourth letter line WL n+1 WL n+2 and WL n+3 The connected storage units MC11, MC13, MC15, MC17, MC19, MC21, MC23, MC25, MC27, MC29, MC31, MC33, MC35, MC37, and MC39 did not perform the first programming operation.

[0093] For example, in this step, the second sub-step can be performed 15 times on memory cells located on the same memory strings Str0, Str1, Str2, Str3, and Str4. For instance, firstly, the memory cells located on memory string Str0 and connected to the third word line WL are processed. n-3 The connected memory cell MC10 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+1 The connected memory cell MC11 performs the first programming operation. Then, the program is applied to the memory string Str1 and the third word line WL. n-3 The connected memory cell MC12 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+1The connected memory cell MC13 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-3 The connected memory cell MC14 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+1 The connected memory cell MC15 performs the first programming operation. Next, the program is applied to the memory string Str3 and the third word line WL. n-3 The connected memory cell MC16 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+1 The connected memory cell MC17 performs the first programming operation. Finally, the program is applied to the memory string Str4 and the third word line WL. n-3 The connected memory cell MC18 performs a second programming operation on the memory string Str4 and the fourth word line WL. n+1 The connected storage unit MC19 performs the first programming operation.

[0094] Furthermore, for the storage string Str0 and the third word line WL n-2 The connected memory cell MC20 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+2 The connected memory cell MC21 performs the first programming operation. Then, the program located on memory string Str1 and connected to the third word line WL... n-2 The connected memory cell MC22 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+2 The connected memory cell MC23 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-2 The connected memory cell MC24 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+2 The connected memory cell MC25 performs the first programming operation. Next, the program is applied to the memory string Str3 and the third word line WL. n-2 The connected memory cell MC26 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+2 The connected memory cell MC27 performs the first programming operation. Next, the program is applied to the memory string Str4 and connected to the third word line WL. n-2 The connected memory cell MC28 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+2 The connected storage unit MC29 performs the first programming operation.

[0095] Furthermore, for the storage string Str0 and the third word line WL n-1The connected memory cell MC30 performs a second programming operation on the memory string Str0 and the fourth word line WL. n+3 The connected memory cell MC31 performs the first programming operation. Then, the program is applied to the memory string Str1 and the third word line WL. n-1 The connected memory cell MC32 performs a second programming operation on the memory string Str1 and the fourth word line WL. n+3 The connected memory cell MC33 performs the first programming operation. Next, the program is applied to the memory string Str2 and connected to the third word line WL. n-1 The connected memory cell MC34 performs a second programming operation on the memory string Str2 and the fourth word line WL. n+3 The connected memory cell MC35 performs the first programming operation. Next, the program is applied to the memory string Str3 and the third word line WL. n-1 The connected memory cell MC36 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+3 The connected memory cell MC37 performs the first programming operation. Finally, the program is applied to the memory string Str3 and the third word line WL. n-1 The connected memory cell MC38 performs a second programming operation on the memory string Str3 and the fourth word line WL. n+3 The connected storage unit MC38 performs the first programming operation.

[0096] For example, by performing the second sub-step 15 times, the third word line WL is made possible. n-3 The connected memory cells MC10, MC12, MC14, MC16 and MC18, and the third word line WL n-2 The connected memory cells MC20, MC22, MC24, MC26, and MC28, as well as the third word line WL, n-1 The connected storage units MC30, MC32, MC34, MC36, and MC38 complete the second programming operation. Optionally, the second sub-step can be performed in a numbering order different from that of the storage strings Str0, Str1, Str2, Str3, and Str4; this application does not specifically limit this.

[0097] For example, when the number of third or fourth word lines is greater than one, the second sub-step can be performed alternately on each memory cell located on the same memory string and connected to the third and fourth word lines respectively, as described above. Optionally, the multiple third and fourth word lines described in the above programming operation method are merely examples and are not intended to limit their specific positions. For example, when the second sub-step is performed alternately on each memory cell located on the same memory string and connected to the third and fourth word lines respectively, the specific position of any one of the multiple third or fourth word lines is not limited.

[0098] For example, in step S150, a second programming operation is performed on the second storage unit MC1, which has already completed the first programming operation in step S110. It is understood that the first programming operation or the second programming operation of the second storage unit MC1 is spaced 38 storage units apart.

[0099] According to the programming operation methods provided in Embodiments 1 to 3, the programming operation of the second storage unit (e.g., MC1) is spaced 2n(m+1)-2 storage units apart (including the first and second programming operations). Here, m is the number of third word lines, and n is the number of storage units connected to each word line. It should be noted that the number of storage units connected to each word line (including the first, second, third, and fourth word lines) is the same.

[0100] Figure 10 This is a schematic diagram illustrating the sequence of programming operations performed by each storage unit in the programming operation method of related technologies. Figure 10 Two word lines WL' are shown. n and WL' n-1 And four storage strings Str0', Str1', Str2', and Str3'. The intersection of each word line and each storage string is a storage unit.

[0101] like Figure 10 As shown, in related technologies, firstly, the word line WL' n-1 The connected memory cells MC0', MC1', MC2', and MC3' are programmed sequentially according to the numbering order of their respective memory strings. Further, the word line WL'... n-1 Adjacent word line WL' n The connected memory cells MC4', MC5', MC6', and MC7' are programmed sequentially according to the numbering order of their respective memory strings. Further, the word line WL' is then programmed again. n-1The connected memory cell, such as MC0', performs a second programming operation. Thus, the first programming operation of memory cell, such as MC0', is spaced 7 memory cells apart from the first programming operation and the second programming operation.

[0102] Based on the programming operation method described above, it is easy to deduce that the first programming operation and the second programming operation of a memory cell (e.g., MC'0) are separated by a programming operation of 2n-1 memory cells (i.e., the first programming operation). Here, n is the number of memory cells connected by each word line.

[0103] When the number of memory cells connected to each word line is the same, the difference in the interval between the first and second programming operations performed on a memory cell (i.e., the interval between programming operations performed on other memory cells) in the programming operation method 1000 provided in this application, compared with related technologies, is [2n(m+1)-2]-(2n-1)=2nm-1. Based on the physical meaning of n and m, both n and m are positive integers greater than 1, thus the above difference is a positive integer greater than 1. In other words, compared with the prior art, the programming operation method 1000 for non-volatile memory devices provided in this application is advantageous in increasing the interval between the first and second programming operations performed on a memory cell (i.e., the interval between programming operations performed on other memory cells).

[0104] Figure 11 This is a schematic diagram illustrating the threshold voltage drift after performing a second programming operation on a memory cell according to the programming operation method of the embodiments of this application. Figure 11 As shown, the thick solid line represents the threshold voltage distribution when the memory cell performs the second programming operation, the dashed line represents the threshold voltage distribution after the memory cell performs the second programming operation using related techniques (e.g., within 1 second), and the thin solid line represents the threshold voltage distribution after the memory cell performs the second programming operation using the programming operation method 1000 provided in this application (e.g., within 1 second). It is understood that after a memory cell performs the first programming operation, the charge (e.g., electrons) located in the shallow energy level will retreat back into the channel layer over time. The programming operation method 1000 for the non-volatile memory device provided in this application, by increasing the interval between the first and second programming operations of the memory cell (i.e., the interval between programming operations of other memory cells), enables more charge (e.g., electrons) located in the shallow energy level to retreat back into the channel layer after the first programming operation. This results in more charge (e.g., electrons) in the memory cell after the second programming operation being located in the deep energy level, which helps to weaken the tendency of the threshold voltage to decrease and helps to increase the read window size.

[0105] Figure 12A and Figure 12BThese are functional block diagrams of non-volatile storage systems 2000a and 2000b according to embodiments of this application. Figure 12A and 12B As shown, the non-volatile storage system 2000a or 2000b includes at least one non-volatile storage device 2100 and a control device 2200.

[0106] The non-volatile storage device 2100 may be the same as the non-volatile storage device described in any of the embodiments above, and will not be described again in this application.

[0107] Control device 2200 can control non-volatile memory device 2100 via, for example, a channel (not shown), and non-volatile memory device 2100 can perform operations based on the control of control device 2200. Non-volatile memory device 2100 can receive commands and addresses from control device 2200 via the channel and access memory cell array 110 (see reference 110) in response to the address. Figure 1 The region selected by the address. In other words, the non-volatile storage device 2100 can perform internal operations corresponding to the command on the region selected by the address. More specifically, the control device 2200 can send a command and an address to execute the programming operation method 1000 described in any of the above embodiments via a channel, causing the non-volatile storage device 2100 to execute the programming operation method.

[0108] In some examples, the control device 2200 and one or more non-volatile storage devices 2100 can be integrated into various types of storage systems; in other words, storage systems 2000a and 2000b can be implemented and packaged into different types of final electronic products. Figure 12A In one example shown, the control device 2200 and a single non-volatile storage device 2100 may be integrated into a non-volatile storage system 2200a in the form of a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The non-volatile storage system 2200a in the form of a memory card may also include a memory card connector 2300a that couples it to a host (not shown).

[0109] In such Figure 12BIn another example shown, the control device 2200 and multiple non-volatile storage devices 2100 may be integrated into a non-volatile storage system 2000b formed by a solid-state drive (SSD). The SSD may also include an SSD connector 2300b that couples it to the host. In some embodiments, the storage capacity and / or operating speed of the SSD may be higher than that of a memory card.

[0110] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for programming a non-volatile memory device, including: A second programming operation is performed on the first memory cell among a plurality of memory cells connected to the first word line, wherein the plurality of memory cells connected to the first word line have already undergone a first programming operation; The first programming operation is performed on a second memory cell connected to a second word line that is at least one third word line apart from the first word line, wherein the first memory cell and the second memory cell are located on a first memory string; and The first sub-step is performed on the storage cells located on the same storage string other than the first storage string until the plurality of storage cells connected to the first word line complete the second programming operation and the plurality of storage cells connected to the second word line complete the first programming operation. The first sub-step includes: sequentially performing the second programming operation on the storage cells connected to the first word line and performing the first programming operation on the storage cells connected to the second word line.

2. The programming operation method according to claim 1, wherein, The plurality of memory cells connected to the third word line have performed a first programming operation, the programming operation method further comprising: A second sub-step is performed on memory cells located on the same memory string until multiple memory cells connected to the third word line complete the second programming operation, wherein the second sub-step includes: alternately performing the second programming operation on memory cells connected to each third word line, and performing a first programming operation on memory cells connected to each fourth word line adjacent to the second word line; and Perform a second programming operation on the second storage unit.

3. The programming operation method according to claim 2, wherein, After performing the first programming operation on the second storage unit and performing programming operations on 2n(m+1)-2 storage units, the second programming operation is performed on the second storage unit, where m is the number of the third word lines and n is the number of storage units connected to each word line.

4. The programming operation method according to claim 2, wherein, The first sub-step is executed sequentially on storage cells located on the same storage string other than the first storage string, according to a predetermined order.

5. The programming operation method according to claim 4, wherein, The second sub-step is performed sequentially on the storage cells located on the same storage string in the predetermined order.

6. The programming operation method according to any one of claims 1 to 5, wherein, The storage unit includes one of QLC, TLC or MLC.

7. The programming operation method according to any one of claims 1 to 5, wherein, The first programming operation is a coarse programming operation, and the second programming operation is a fine programming operation.

8. A non-volatile storage device, comprising: The first word line, the second word line, the third word line, multiple memory strings including the first memory string, and peripheral circuitry. The peripheral circuit is electrically connected to the first word line, the second word line, the third word line, and the plurality of memory strings, and is configured as follows: A second programming operation is performed on the first memory cell among a plurality of memory cells connected to the first word line, wherein the plurality of memory cells connected to the first word line have already undergone a first programming operation; The first programming operation is performed on a second memory cell connected to a second word line that is spaced at least one third word line from the first word line, wherein the first memory cell and the second memory cell are located on a first memory string; and The first sub-step is performed on the storage cells located on the same storage string other than the first storage string until the plurality of storage cells connected to the first word line complete the second programming operation and the plurality of storage cells connected to the second word line complete the first programming operation. The first sub-step includes: sequentially performing the second programming operation on the storage cells connected to the first word line and performing the first programming operation on the storage cells connected to the second word line.

9. The non-volatile storage device according to claim 8, further comprising a fourth word line adjacent to the first word line, wherein, The plurality of memory cells connected to the third word line have performed the first programming operation, and the peripheral circuitry is further configured as follows: A second sub-step is performed on memory cells located on the same memory string until multiple memory cells connected to the third word line complete the second programming operation, wherein the second sub-step includes: alternately performing the second programming operation on memory cells connected to each third word line and performing the first programming operation on memory cells connected to each fourth word line; and Perform a second programming operation on the second storage unit Perform a second programming operation on the second storage unit.

10. The non-volatile storage device according to claim 8, wherein, The storage unit includes one of QLC, TLC or MLC.

11. Non-volatile memory systems, including: At least one non-volatile storage device; as well as A control device is electrically connected to the non-volatile storage device and controls the non-volatile storage device to perform the programming operation method as described in any one of claims 1 to 7.

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