High voltage decoupling capacitor and integration method

Abstract

The present invention relates to high voltage decoupling capacitors and integration methods. A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers above the first isolation region. The plurality of dielectric layers can include an interlayer dielectric (ILD) layer and an intermetal dielectric (IMD) layer. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is disposed above the plurality of dielectric layers, where the second conductive layer is a top plate of the capacitor and at least partially overlaps the first conductive layer.

Description

TECHNICAL FIELD

[0001] The disclosed embodiments relate generally to isolation structures in semiconductor devices, and more particularly to decoupling capacitors capable of operating at high voltages and methods of manufacturing the same. BACKGROUND

[0002] Electrical systems often contain several circuits that can communicate with each other but operate at different voltages. For example, a microwave oven that operates at 110V / 220V alternating current (AC) can generate up to 2800V inside it. The high voltage must be isolated from the user or other circuits within the system while still allowing exchange of information between different circuits. Galvanic isolation can be used to prevent direct current from flowing between different circuits while still allowing exchange of signals or energy to enable communication between different circuits.

[0003] Decoupling capacitors can be used to galvanically isolate different circuits of an electrical system to prevent stray current flow. Physical space limitations can make it difficult to implement decoupling capacitors with sufficiently high breakdown voltages in integrated circuits. For example, decoupling capacitors can be fabricated in the metallization layers or back end of line (BEOL) layers of an integrated circuit. However, due to large voltage differences that can occur between the circuits being isolated, on the order of thousands of volts, decoupling capacitors with higher breakdown voltages than those fabricated using this technology are needed. Therefore, there is a need for an improved decoupling capacitor to overcome the above challenges. SUMMARY

[0004] In one aspect of the disclosure, a capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate. A plurality of dielectric layers is disposed above the first isolation region. A second conductive layer is disposed above the plurality of dielectric layers, wherein the second conductive layer at least partially overlaps the first conductive layer.

[0005] In another aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a substrate including an insulating layer and an active layer above the insulating layer. A first isolation region is disposed in the active layer and the insulating layer. A second isolation region is disposed in the active layer laterally adjacent to the first isolation region. A capacitor is provided. The capacitor includes a first conductive layer in the first isolation region. The first conductive layer is a bottom plate of the capacitor. A plurality of dielectric layers is disposed above the first isolation region. A second conductive layer is disposed above the plurality of dielectric layers. The second conductive layer is a top plate of the capacitor, and the second conductive layer at least partially overlaps the first conductive layer.

[0006] In yet another aspect of the disclosure, a method of fabricating a semiconductor device is provided. The method includes providing a substrate including an insulating layer and an active layer located above the insulating layer. A first isolation region is disposed in the insulating layer and the active layer. A second isolation region is disposed in the active layer, wherein the second isolation region is laterally adjacent to an upper portion of the first isolation region. A capacitor is disposed. The capacitor includes a first conductive layer disposed in the first isolation region. A plurality of dielectric layers is disposed above the first isolation region. A second conductive layer is disposed above the plurality of dielectric layers, wherein the second conductive layer at least partially overlaps the first conductive layer.

[0007] Many advantages are provided in the embodiments described below. The embodiments provide a decoupling capacitor capable of operating at high voltages. The decoupling capacitor can be fabricated with existing substrate and metallization stacks, without requiring additional metallization layers. The first conductive layer of the decoupling capacitor can be integrated into an isolation region in a substrate layer, thereby freeing up space for overlying metallization stacks. An upper portion of the first isolation region is located within a shallow trench isolation (STI) layer of an active layer. Thus, no additional lateral space is taken up in the device layout. BRIEF DESCRIPTION OF DRAWINGS

[0008] The disclosed embodiments will be better understood from reading the following detailed description in conjunction with the drawings, in which:

[0009] Figure 1 is a semiconductor device having a decoupling capacitor according to embodiments of the disclosure.

[0010] Figures 2 to 11 shows a method for fabricating a semiconductor device according to some embodiments of the disclosure. Figure 1 shows a fabrication process flow for a semiconductor device.

[0011] For illustrative simplicity, the drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques can be omitted in order to avoid unnecessarily obscuring the discussion of the embodiments of the devices being described. Additionally, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings can be exaggerated relative to other elements to help improve the understanding of the embodiments of the devices. Like reference numerals designate like elements throughout the drawings, while similar reference numerals can, but do not necessarily, designate similar elements. DETAILED DESCRIPTION

[0012] The following detailed description is exemplary in nature and is not intended to limit the scope or application of the devices or utility of the devices. Furthermore, there is no intention to be bound by any theory of operation presented in the preceding background or the following detailed description.

[0013] Figure 1is a semiconductor device 100 having a decoupling capacitor 300 according to embodiments of the present disclosure. Referring to Figure 1 The semiconductor device 100 can include a substrate 186 having an insulating layer 106 and an active layer 108 located above the insulating layer 106. A first isolation region 112 can be disposed in the insulating layer 106 and the active layer 108. The decoupling capacitor 300 can include the first conductive layer 110, the first isolation region 112, a plurality of dielectric layers 126, 128, and 132, and the second conductive layer 162. In one embodiment, the first conductive layer 110 can be located in the first isolation region 112, and in a preferred embodiment, can be located in a lower portion of the first isolation region 112. The plurality of dielectric layers 126, 128, and 132 can be located above the first isolation region 112. The second conductive layer 162 can be located above the plurality of dielectric layers 126, 128, and 132. In one embodiment, the second conductive layer 162 can at least partially overlap the first conductive layer 110. In another embodiment, the second conductive layer 162 can completely overlap the first conductive layer 110. The decoupling capacitor 300 is enclosed by a dashed outline. The first conductive layer 110 can serve as a bottom plate of the decoupling capacitor 300, and the second conductive layer 162 can serve as a top plate of the decoupling capacitor 300. The first isolation region 112 and the plurality of dielectric layers 126, 128, and 132 can serve as dielectric layers of the decoupling capacitor 300 between the first conductive layer 110 and the second conductive layer 162.

[0014] A top surface of the first isolation region 112 can be at least flush with a top surface of the active layer 108. The second isolation region 118 can be disposed laterally adjacent to an upper portion of the first isolation region 112, whereby a width x of the second isolation region 118 can be greater than the first isolation region 112. In one embodiment, the second isolation region 118 can be shallower than the first isolation region 112. In one embodiment, the first isolation region 112 can be a deep trench isolation (DTI) and the second isolation region 118 can be a shallow trench isolation (STI). Since the upper portion of the first isolation region 112 can be disposed in the second isolation region 118, the decoupling capacitor 300 does not occupy additional lateral space in the semiconductor device 100. In one embodiment, the second isolation region 118 can at least partially surround the upper portion of the first isolation region 112. In another embodiment, the second isolation region 118 can completely surround the upper portion of the first isolation region 112. The first isolation region 112 can be made of a suitable dielectric material, such as high-density plasma (HDP) silicon dioxide (SiO2) or any other suitable dielectric material. The second isolation region 118 can be made of a suitable dielectric material, such as borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material. In one embodiment, the first isolation region 112 and the second isolation region 118 can be made of the same dielectric material. In another embodiment, the first isolation region 112 and the second isolation region 118 can be made of different dielectric materials.

[0015] In one embodiment, the dielectric layer 126 can be an interlayer dielectric (ILD) layer. The dielectric layers 128 and 132 can be intermetal dielectric (IMD) layers of the first metallization layer 150 and the second metallization layer 156, respectively. The dielectric layer 126 can be made of a suitable dielectric material, such as silicon dioxide (SiO2), high-density plasma (HDP) undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material. The dielectric layers 128 and 132 can be made of a suitable dielectric material, such as silicon dioxide, undoped silicate glass (USG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), or any other suitable dielectric material.

[0016] The first isolation region 112 can extend through the active layer 108 and an upper portion of the insulating layer 106. The first isolation region 112 can be disposed above a lower portion of the insulating layer 106. In one embodiment, the first conductive layer 110 can be disposed in a lower portion of the first isolation region 112. In another embodiment, the first conductive layer 110 can be disposed above a bottom surface of the first isolation region 112. In another embodiment, the first conductive layer 110 can be located in an upper portion of the first isolation region 112. The substrate 186 can include a base layer 102 located below the insulating layer 106. In one embodiment, the substrate 186 can be a silicon-on-insulator (SOI) substrate. The lower portion of the insulating layer 106 and the lower portion of the first isolation region 112 can be located between the first conductive layer 110 and the base layer 102 to electrically isolate the first conductive layer 110 of the decoupling capacitor 300 from the base layer 102 of the substrate 186.

[0017] The decoupling capacitor 300 can include a first interconnect 200 located above the first conductive layer 110, whereby the first interconnect 200 extends through a portion of the first isolation region 112 above the first conductive layer 110 and through the plurality of dielectric layers 126, 128, 132, and 136 to couple to the first bonding pad 170. In an alternative embodiment, the first interconnect 200 can extend through a portion of the first isolation region 112 and through the plurality of dielectric layers 126, 128, 132, and 136 to couple to a metallization line. The decoupling capacitor 300 can include a second interconnect 166 located above the second conductive layer 162, whereby the second interconnect 166 can extend through the dielectric layer 136 to couple to the second bonding pad 168. In an alternative embodiment, the second interconnect 166 can extend through the dielectric layer 136 to couple to another metallization line. In one embodiment, the dielectric layer 136 can be an intermetallic dielectric (IMD) layer. The first bonding pad 170 and the second bonding pad 168 can be connected to separate external input terminals or separate circuits. The first interconnect 200 can include a plurality of contact pillars 116, 152, 158, and 188 and metallization layers 150, 156, and 160. The second interconnect 166 can include a contact pillar.

[0018] The third interconnect 400 can extend from the base layer 102 through the insulating layer 106, the active layer 108, and the dielectric layer 126 to electrically bias the base layer 102. In one embodiment, the third interconnect 400 can be coupled to a ground terminal to ground the base layer 102 of the substrate 186. The third interconnect 400 can include a contact pillar 120 and a metallization layer 190.

[0019] The above embodiments provide a semiconductor device 100 including a decoupling capacitor 300 having a high breakdown voltage due to the thick dielectric layer between the first conductive layer 110 and the second conductive layer 162. In one embodiment, the first isolation region 112 can be made of a suitable dielectric layer, such as a silicon dioxide (Si02) layer. A portion of the first isolation region 112 located above the first conductive layer 110 can have a thickness ranging from about 3 to 4 micrometers (pm). In one embodiment, the dielectric layers 126, 128, and 132 can be made of a suitable dielectric material, such as silicon dioxide (Si02). The dielectric layer 126 can have a thickness ranging from about 0.55 to 0.95 micrometers (pm). The dielectric layers 128 and 132 can have a thickness ranging from about 0.6 to 1 micrometers (pm). Thus, the total thickness of the dielectric layers between the first conductive layer 110 and the second conductive layer 162 is between 4 to 10 micrometers (pm). In one embodiment, the first conductive layer 110 and the second conductive layer 162 can be metal layers.

[0020] Figures 2 to 11 A flow diagram illustrating a method for fabricating a semiconductor device 100 according to some embodiments of the present disclosure is shown. Figure 1 A flow diagram illustrating a method for fabricating a semiconductor device 100 according to some embodiments of the present disclosure is shown. Figure 2 is a partially completed semiconductor device 100 having an opening 192 in the active layer 108 of the substrate 186 according to embodiments of the present disclosure. Reference is made to Figure 2 A suitable substrate 186, such as a silicon-on-insulator (SOI) substrate, can be provided. The substrate 186 can include a base layer 102, an insulating layer 106 located above the base layer 102, and an active layer 108 located above the insulating layer 106. The base layer 102 can include silicon. The insulating layer 106 can include silicon dioxide. The active layer 108 can include single-crystal silicon. A sacrificial silicon dioxide layer 196 and a silicon nitride layer 198 can be deposited on a top surface of the active layer 108 of the substrate 186 and patterned by a conventional photolithography process and a wet or dry etching process. The conventional photolithography process can include depositing a photoresist layer above the sacrificial silicon dioxide layer 196 and the silicon nitride layer 198, followed by exposure and development to form a suitable photoresist pattern. The wet or dry etching process can be used to remove a portion of the sacrificial silicon dioxide layer 196 and the silicon nitride layer 198 not covered by the photoresist pattern, and leave another portion of the sacrificial silicon dioxide layer 196 and the silicon nitride layer 198 as a hard mask layer 216. The photoresist layer can then be removed. A portion of the active layer 108 not covered by the hard mask layer 216 can be removed using a wet or dry etching process to form the opening 192 in the active layer 108. The hard mask layer 216 can then be removed.

[0021] Figure 3is a partially completed semiconductor device 100 according to embodiments of the present disclosure after forming the second isolation region 118 in the active layer 108 of the substrate 186. Referring to Figure 3 A suitable dielectric material layer, such as a silicon dioxide (Si02) layer, can be deposited in the opening 192 by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. A portion of the silicon dioxide layer above the top surface of the active layer 108 can be planarized by a suitable planarization process, such as chemical mechanical planarization (CMP), to leave another portion of the silicon dioxide layer in the opening 192, thereby forming the second isolation region 118.

[0022] Figure 4 is a partially completed semiconductor device 100 according to embodiments of the present disclosure after forming the openings 208 and 210. Referring to Figure 4 The opening 208 extends through the second isolation region 118, the active layer 108, and an upper portion of the insulating layer 106. The opening 210 extends through the active layer 108 and a portion of the insulating layer 106. Formation of the openings 208 and 210 can include depositing a photoresist layer and patterning the photoresist layer by a conventional photolithography process to form a suitable photoresist pattern having openings over a portion of the second isolation region 118 and a portion of the active layer 108 of the substrate 186. A portion of the second isolation region 118, a portion of the active layer 108, and a portion of the insulating layer 106 not covered by the photoresist pattern can be removed using a wet etching or dry etching process, thereby forming the opening 208. Similarly, a portion of the active layer 108 and a portion of the insulating layer 106 not covered by the photoresist pattern can be removed using a wet etching or dry etching process, thereby forming the opening 210. The photoresist pattern can be subsequently removed after the etching process.

[0023] Figure 5 is a partially completed semiconductor device 100 according to embodiments of the present disclosure after forming the first isolation region 112 and the third isolation region 122. In embodiments, the first isolation region 112 and the third isolation region 122 can be deep trench isolation (DTI) regions. Referring to Figure 5The upper portion of the first isolation region 112 is formed in the second isolation region 118 and the lower portion of the first isolation region 112 extends through the active layer 108 and a portion of the insulating layer 106. The third isolation region 122 is formed in the active layer 108 and a portion of the insulating layer 106. The formation of the first and third isolation regions 112 and 122 can respectively include depositing a layer of a suitable dielectric material, such as a layer of silicon dioxide, in the openings 208 and 210, respectively, by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. A portion of the layer of silicon dioxide can be removed from the top surface of the second isolation region 118 using a suitable planarization process, such as chemical mechanical planarization (CMP), to leave another portion of the layer of silicon dioxide in the opening 208 to form the first isolation region 112. Similarly, a portion of the layer of silicon dioxide can be removed from the top surface of the active layer 108 using a suitable planarization process, such as chemical mechanical planarization (CMP), to leave another portion of the layer of silicon dioxide in the opening 210 to form the third isolation region 122. The upper portion of the first isolation region 112 is formed in the second isolation region 118, resulting in a compact semiconductor device 100 because the first isolation region 112 does not occupy additional lateral area in the active layer 108 of the substrate 186.

[0024] Figure 6 is a partially completed semiconductor device 100 after forming a gate structure 176 and a dielectric liner 178 over the active layer 108 according to embodiments of the present disclosure. The formation of the gate structure 176 is well known in the art and will not be further elaborated. Although not shown, doped semiconductor regions can be formed in the active layer 108 to form source and drain regions adjacent to the gate structure 176. The formation of the dielectric liner 178 can include depositing a layer of a suitable dielectric material, such as a layer of silicon nitride (Si3N4), over the top surface of the active layer 108, over the top surfaces of the third and first isolation (DTI) regions 122 and 112, over the top surface of the second isolation region 118, and over the gate structure 176 by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process, to form the dielectric liner 178. The dielectric liner 178 can be used as an etch stop layer to stop the etch removal process of overlying layers.

[0025] Figure 7 is a partially completed semiconductor device 100 after forming a dielectric layer 126 and openings 180 and 182 according to embodiments of the present disclosure. In one embodiment, the dielectric layer 126 can be an interlayer dielectric (ILD) layer. Reference is made to Figure 7A dielectric layer 126 can be formed over the dielectric liner 178. Formation of the dielectric layer 126 can include depositing a layer of a suitable dielectric material, such as a layer of silicon dioxide, over the dielectric liner 178 by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process, thereby forming the dielectric layer 126. An opening 180 can be formed in the dielectric layer 126, in the dielectric liner 178, and in the third isolation region 122. An opening 182 can be formed in the dielectric layer 126, in the dielectric liner 178, and in the first isolation region 112. Formation of the openings 180 and 182 can include depositing a photoresist layer and patterning the photoresist layer to form a suitable photoresist pattern by a conventional photolithography process. A portion of the dielectric layer 126, a portion of the dielectric liner 178, and a portion of the third isolation region 122 that are not covered by the photoresist pattern can be removed using a wet etching or dry etching process, thereby forming the opening 180. The photoresist layer can then be removed. Similarly, a portion of the dielectric layer 126, a portion of the dielectric liner 178, and a portion of the first isolation region 112 can be removed using a wet etching or dry etching process, thereby forming the opening 182.

[0026] Figure 8 is a partially completed semiconductor device 100 after formation of the first conductive layer 110, the third and first isolation regions 122 and 112, and the dielectric layer 126 according to embodiments of the present disclosure. Reference is made to Figure 8The formation of the first conductive layer 110 can include depositing a layer of a suitable conductive material, such as a layer of aluminum (Al), a layer of tungsten (W), a layer of titanium nitride (TiN), a layer of cobalt (Co), or any other suitable layer of conductive material, in the opening 182 over the lower portion of the first isolation region 112 by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. A layer of photoresist can be deposited on the layer of aluminum and patterned by a conventional photolithography process to form a suitable photoresist pattern. A portion of the layer of aluminum not covered by the photoresist pattern can be removed using a wet etching or dry etching process, leaving another portion of the layer of aluminum over the lower portion of the first isolation region 112, thereby forming the first conductive layer 110. The photoresist pattern can be subsequently removed.

[0027] Figure 9 is a partially completed semiconductor device 100 according to embodiments of the present disclosure after the formation of the openings 220 and 222. Referring to Figure 9 The opening 220 extends through the dielectric layer 126, the third isolation region 122, the insulating layer 106, and the upper portion of the base layer 102. The opening 222 extends through the dielectric layer 126 and a portion of the first isolation region 112 to expose a portion of the first conductive layer 110. The formation of the openings 220 and 222 can include depositing a layer of photoresist over the dielectric layer 126 and patterning the deposited layer of photoresist by a conventional photolithography process to form a suitable photoresist pattern. A portion of the dielectric layer 126, a portion of the third isolation region 122, a portion of the insulating layer 106, and a portion of the base layer 102 not covered by the photoresist pattern can be removed using a wet etching or dry etching process, thereby forming the opening 220. Similarly, a portion of the dielectric layer 126 and a portion of the first isolation region 112 over the first conductive layer 110 not covered by the photoresist pattern can be removed using a wet etching or dry etching process, thereby forming the opening 222. The photoresist pattern can be subsequently removed.

[0028] Figure 10 is a partially completed semiconductor device 100 after formation of contact pillars 116 and 120 according to embodiments of the present disclosure. Referring to Figure 10 , contact pillar 116 can extend through dielectric layer 126 and a portion of first isolation region 112 to contact first conductive layer 110. Contact pillar 120 can extend through dielectric layer 126, third isolation region 122, insulating layer 106, and an upper portion of base layer 102. Contact pillars 116 and 120 can be formed by depositing a layer of a suitable conductive material, such as a tungsten (W) layer or any other suitable conductive material layer, in openings 220 and 222 by a suitable deposition method, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. A portion of the tungsten layer can be removed from a top surface of dielectric layer 126 using a suitable planarization process, such as chemical mechanical planarization (CMP), leaving another portion of the tungsten layer in openings 220 and 222 to form contact pillars 120 and 116, respectively. Although not shown, in one embodiment, second conductive layer 162 of decoupling capacitor 300 can be formed over contact pillar 116 and dielectric layer 126.

[0029] Figure 11 is a partially completed semiconductor device 100 after formation of metallization layers 150 and 190 over contact pillars 116 and 120, respectively, according to embodiments of the present disclosure. Referring to Figure 11 , formation of metallization layer 150 can include depositing a photoresist layer over dielectric layer 126 and over contact pillar 116. The photoresist layer can be patterned using a conventional photolithography process to form an opening over contact pillar 116. A layer of a suitable conductive material, such as a copper (Cu) layer, an aluminum (Al) layer, or any other suitable conductive material layer, can be deposited in the opening over contact pillar 116 by a suitable deposition process, such as electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. The photoresist layer can be removed in a lift-off process to leave a portion of the copper layer over contact pillar 116 to form metallization layer 150. Metallization layer 190 and metallization layer 130 over gate structure 176 can also be formed by a conventional photolithography process, conductive layer deposition, and subsequent lift-off process similar to the formation of metallization layer 150.

[0030] Referring back to Figure 1wherein semiconductor device 100 is shown after forming dielectric layers 128, 132, 136, and 138, contact pillars 152, 158, 188, 140, 146, 184, and 166, metallization layers 156, 160, 142, 148, second conductive layer 162, and bonding pads 168, 170, and 172, in accordance with an embodiment of the present disclosure. Reference is made to FIG. 1 for a description of semiconductor device 100. Figure 1 Dielectric layer 128 can be formed over metallization layers 150, 130, and 190, and over dielectric layer 126. In one embodiment, dielectric layer 128 can be an intermetal dielectric (IMD) layer. Contact pillar 152 can be formed in dielectric layer 128 and over metallization layer 150. Contact pillar 140 can be formed in dielectric layer 128 and over metallization layer 130. Formation of contact pillars 152 and 140 can include forming openings in dielectric layer 128 over metallization layers 150 and 130, respectively. A suitable conductive material, such as tungsten or any other suitable conductive material, can be deposited in the openings. A suitable planarization process, such as chemical mechanical planarization, can be used to remove the tungsten from the top surface of dielectric layer 128 to leave another layer of tungsten in the openings over metallization layers 150 and 130, respectively, thereby forming contact pillars 152 and 140, respectively. Metallization layers 156 and 142 can be formed over contact pillars 152 and 140, respectively. Dielectric layer 132 can be formed over dielectric layer 128, and over metallization layers 156 and 142. In one embodiment, dielectric layer 132 can be an intermetal dielectric (IMD) layer. Contact pillar 158 can be formed in dielectric layer 132 and over metallization layer 156. Contact pillar 146 can be formed in dielectric layer 132 over metallization layer 142. Formation of contact pillars 158 and 146 can include forming openings in dielectric layer 132 over metallization layers 156 and 142, respectively. A suitable conductive material, such as tungsten or any other suitable conductive material, can be deposited in the openings. A suitable planarization process, such as chemical mechanical planarization, can be used to remove the tungsten from the top surface of dielectric layer 132 to leave another layer of tungsten in the openings over metallization layers 156 and 142, respectively, thereby forming contact pillars 158 and 146, respectively.

[0031] Metallization layers 160 and 148 can be formed over contact pillars 158 and 146, respectively. A second conductive layer 162 of decoupling capacitor 300 can be formed over a portion of first isolation region 112 over first conductive layer 110, over dielectric layers 126, 128, and 132. Second conductive layer 162 of decoupling capacitor 300, as well as metallization layers 160 and 148, can be made of the same conductive material. A dielectric layer 136 can be formed over second conductive layer 162, as well as over metallization layers 160 and 148. In one embodiment, dielectric layer 136 can be an intermetal dielectric (IMD) layer. Contact pillars 166, 188, and 184 can be formed in dielectric layer 136 over second conductive layer 162 of decoupling capacitor 300, as well as over metallization layers 160 and 148. Formation of contact pillars 166, 188, and 184 can include forming openings in dielectric layer 136 over second conductive layer 162, as well as over metallization layers 160 and 148, respectively. A suitable conductive material, such as tungsten or any other suitable conductive material, can be deposited in the openings. A suitable planarization process, such as chemical mechanical planarization, can be used to remove the tungsten from the top surface of dielectric layer 136, leaving another layer of tungsten in the openings over second conductive layer 162, as well as over metallization layers 160 and 148, respectively, thereby forming contact pillars 166, 188, and 184, respectively. Bonding pads 168, 170, and 172 can be formed over contact pillars 166, 188, and 184, respectively. Formation of bonding pads 168, 170, and 172 can include conventional photolithography processes, conductive layer deposition, and subsequent stripping processes similar to those used in the formation of second conductive layer 162, as well as metallization layers 160 and 148. A dielectric layer 138 can be formed over bonding pads 168, 170, and 172. Openings can be formed in dielectric layer 138 to expose bonding pads 168, 170, and 172. In one embodiment, contact pillars 140, 146, and 184, as well as metallization layers 130, 142, and 148, can be used to connect gate structure 176 to an input or output terminal.

[0032] Dielectric layers 128, 132, 136, and 138 can be made of the same dielectric material as dielectric layer 126 and deposited using the same deposition process. In one embodiment, second conductive layer 162 of decoupling capacitor 300, as well as metallization layers 156, 142, 160, and 148, can be made of the same conductive material as metallization layers 150, 130, and 190 and fabricated using the same deposition and patterning processes. In another embodiment, second conductive layer 162 of decoupling capacitor 300 can be made of a different conductive material than metallization layers 150, 130, 190, 156, 142, 160, and 148.

[0033] The terms “first,” “second,” “third,” etc., if any, in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the devices described herein are, for example, capable of accomplishing functionalities in a different order than that which is shown in the figures or recited in the description. The terminology used in the description and the claims of the application are for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. It will be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the devices described herein are, for example, capable of accomplishing functionalities in a different order than other embodiments. Similarly, if a method is described herein as comprising a series of steps, the order in which such steps are presented is not necessarily the order in which they are performed on practicing the method. The particular steps presented in the description and claims of the application are susceptible to modification and / or substitution for other steps, and not all steps that are useful for the method have necessarily been presented or described. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0034] While several exemplary embodiments have been set forth above, it should be understood that there are many variations that fall within the scope of the present disclosure. It should also be understood that the embodiments are only examples and are not intended to limit the scope, applicability, or configuration of the devices in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the devices, it being understood that various changes can be made in the function and arrangement of elements described in the exemplary embodiments without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A capacitor, comprising: a first conductive layer in a first isolation region in a substrate; a plurality of dielectric layers over the first isolation region; a first interconnect over the first conductive layer, wherein the first interconnect extends through a portion of the first isolation region over the first conductive layer and through the plurality of dielectric layers to couple to a first bond pad; and a second conductive layer over the plurality of dielectric layers, wherein the second conductive layer at least partially overlaps the first conductive layer.

2. The capacitor of claim 1, wherein the substrate comprises an insulating layer and an active layer over the insulating layer, and the first isolation region extends through an upper portion of the insulating layer and the active layer.

3. The capacitor of claim 1, wherein the first conductive layer is disposed in a lower portion of the first isolation region.

4. The capacitor of claim 1, wherein the first conductive layer is disposed over a bottom surface of the first isolation region.

5. The capacitor of claim 1, wherein the plurality of dielectric layers comprises an interlayer dielectric (ILD) layer and an intermetal dielectric (IMD) layer.

6. The capacitor of claim 1, further comprising: a second interconnect over the second conductive layer, wherein the second interconnect extends through a dielectric layer to couple to a second bond pad.

7. The capacitor of claim 1, wherein the first interconnect comprises a plurality of contact pillars and a metallization layer.

8. The capacitor of claim 1, wherein the second conductive layer completely overlaps the first conductive layer.

9. The capacitor of claim 6, wherein the second interconnect comprises a contact pillar.

10. A semiconductor device, comprising: a substrate comprising an insulating layer and an active layer over the insulating layer; a first isolation region in the active layer and the insulating layer; a second isolation region in the active layer laterally adjacent to an upper portion of the first isolation region; and a capacitor having a first conductive layer in the first isolation region, wherein the first conductive layer is a bottom plate of the capacitor, a plurality of dielectric layers over the first isolation region; a first interconnect over the first conductive layer, wherein the first interconnect extends through a portion of the first isolation region over the first conductive layer and through the plurality of dielectric layers to couple to a first bond pad, and a second conductive layer over the plurality of dielectric layers, wherein the second conductive layer is a top plate of the capacitor and the second conductive layer at least partially overlaps the first conductive layer.

11. The semiconductor device of claim 10, wherein the second isolation region is shallower than the first isolation region.

12. The semiconductor device of claim 10, wherein the capacitor further comprises: a second interconnect over the second conductive layer, wherein the second interconnect couples to a second bond pad. ​ ​ 13. The semiconductor device of claim 10, wherein the plurality of dielectric layers comprises an interlayer dielectric (ILD) layer and an intermetal dielectric (IMD) layer.

14. The semiconductor device of claim 10, wherein the substrate further comprises a base layer, and a lower portion of the first isolation region and a lower portion of the insulating layer are between the first conductive layer of the capacitor and the base layer of the substrate.

15. The semiconductor device of claim 14, further comprising: a third interconnect extending through the insulating layer and the active layer from the base layer, wherein the third interconnect is coupled to a ground terminal.

16. A method of manufacturing a semiconductor device, comprising: providing a substrate comprising an insulating layer and an active layer above the insulating layer; providing a first isolation region in the insulating layer and the active layer; providing a second isolation region in the active layer, wherein the second isolation region is laterally adjacent to an upper portion of the first isolation region; and providing a capacitor comprising a first conductive layer in the first isolation region, a plurality of dielectric layers above the first isolation region, a first interconnect above the first conductive layer, and a second conductive layer above the plurality of dielectric layers, wherein the first interconnect extends through a portion of the first isolation region above the first conductive layer and through the plurality of dielectric layers to couple to a first bond pad, wherein the second conductive layer at least partially overlaps the first conductive layer.

17. The method of manufacturing a semiconductor device of claim 16, wherein providing a second isolation region in the active layer further comprises: forming an opening in the active layer; forming a layer of dielectric material in the opening to form a second isolation region in the active layer; forming an opening in the second isolation region, the active layer, and the insulating layer; and forming an isolation layer material in the opening to form a first isolation region in the active layer and the insulating layer, wherein the second isolation region is laterally adjacent to an upper portion of the first isolation region.

18. The method of manufacturing a semiconductor device of claim 17, wherein providing a capacitor further comprises: forming an opening in the first isolation region and a first conductive layer in the opening in the first isolation region; forming an isolation layer material above the first conductive layer to form the first conductive layer in the first isolation region; forming a plurality of dielectric layers above the first isolation region; and forming a second conductive layer above the plurality of dielectric layers, wherein the second conductive layer at least partially overlaps the first conductive layer. ​ ​

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