Four - transistor static random access memory cell circuit based on a stacked nanosheet structure

Abstract

The present invention discloses a four-transistor static random access memory cell circuit based on a stacked nanosheet structure, which mainly solves the problem of poor read / write stability of existing memory cells. It includes two N-type access transistors AXL and AXR, two N-type pull-down transistors PL and PR, two storage nodes QL and QR, one word line WL, and two bit lines BL and BLB. The sources of PL and PR are both grounded, the drains are respectively connected to QL and QR, and the gates are respectively connected to QR and QL; the lower gates of AXL and AXR are both connected to WL, the drains are respectively connected to BL and BLB, and the sources and upper gates are respectively connected to QL and QR. The metal work functions of the upper gates of the two access transistors are both lower than the metal work functions of the gates of the two pull-down transistors, and the metal work functions of the lower gates are both higher than the metal work functions of the gates of the pull-down transistors. The present invention improves the read / write stability of the memory circuit and can be used for the preparation of large-scale integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic circuits, and particularly relates to a four-transistor static random access memory cell circuit, which can be used to fabricate large-scale integrated circuits. Background Art

[0002] With the development of integrated circuits, the feature size of devices is continuously shrinking. In order to alleviate a series of non-ideal effects caused by the size reduction, advanced structures such as double-gate structures, fin structures, nanowire structures, and stacked nanosheet structures have been proposed one after another. Figure 1 Shown is a schematic diagram of a stacked nanosheet structure. Due to its excellent gate control performance and compatible process flow, this stacked nanosheet structure is considered to be the most promising candidate device for process nodes below 5nm. The channel of this stacked nanosheet is composed of several stacked nanosheets, and is surrounded by gate metal materials on all four sides. The channels of several vertically stacked nanosheets connect the source and drain regions, and isolate the source and drain regions from the gate metal through isolation sidewalls. However, due to the continuous shrinking of the feature size of such devices, the problem of device reliability has become increasingly prominent. Researchers have long found that when the device is in a continuous bias state at a high temperature, aging phenomena such as threshold voltage increase and drive current decrease will occur, resulting in bias temperature instability. Moreover, the negative bias temperature instability that occurs in PMOS is much more significant than the positive bias temperature instability that occurs in NMOS.

[0003] Currently, the 6-transistor static random access memory 6T SRAM cell structure widely used in memory arrays, as Figure 2 shown, is composed of 4 NMOS transistors and 2 PMOS transistors. Since PMOS transistors are significantly affected by negative bias temperature instability, it is very easy to occur the mismatch between PMOS and NMOS inside the static random access memory SRAM cell, thereby affecting the read and write stability of the SRAM cell. And as the device process size continues to shrink below the 5nm process node, the degradation of the read and write stability of this SRAM circuit unit based on the stacked nanosheet structure caused by negative bias temperature instability becomes more and more serious, resulting in serious transistor mismatch phenomena inside this circuit structure during long-term use, and reducing the noise margin of the memory cell in the read and write states. Summary of the Invention

[0004] The purpose of the present invention is to propose a four-transistor static random access memory cell circuit based on a stacked nanosheet structure in view of the above-mentioned deficiencies of the prior art, so as to improve the read and write stability of the static random access memory SRAM cell and enhance the noise margin of the memory cell in the read and write states.

[0005] To achieve the above object, the unit circuit of the four-transistor static random access memory cell based on the stacked nanosheet structure of the present invention includes two N-type access transistors, AXL and AXR, two N-type pull-down transistors PL and PR, two storage nodes QL and QR, one word line WL, and two bit lines BL and BLB. The source of the first pull-down transistor PL is grounded, the drain is connected to the storage node QL, and the gate is connected to the storage node QR; the source of the second pull-down transistor PR is grounded, the drain is connected to the storage node QR, and the gate is connected to the storage node QL. Its characteristics are as follows;

[0006] Both of the two access transistors AXL and AXR include a plurality of stacked channels. The lower layer of the channel is wrapped with a lower gate, and the upper layer of the channel not wrapped by the lower gate is wrapped with an upper gate. The metal work functions of the materials used for the upper gates of these two access transistors AXL and AXR are both lower than the metal work functions of the materials used for the gates of the two pull-down transistors PL and PR, and the metal work functions of the materials used for the lower gates of the access transistors AXL and AXR are higher than the metal work functions of the materials used for the gates of the pull-down transistors PL and PR;

[0007] For the first access transistor AXL, its lower gate is connected to the word line WL, the drain is connected to the first bit line BL, and the source and the upper gate are connected to the first storage node QL;

[0008] For the second access transistor AXR, its lower gate is connected to the word line WL, the drain is connected to the second bit line BLB, and the source and the upper gate are connected to the second storage node QR.

[0009] Preferably, the number of channels wrapped by the lower gates of the two access transistors AXL and AXR is less than the number of channels wrapped by the upper gates, and the metal work function of the gate material used for the lower gate is higher than the metal work function of the gate material used for the upper gate, and the difference in their work functions is more than 0.2 eV. The metal work function of the lower gate is 4.6 eV to 4.7 eV, and the work function of the upper gate is 4.4 to 4.5 eV.

[0010] Preferably, an isolation layer is provided between the upper gate and the lower gate to avoid short circuits between the two gates.

[0011] Preferably, both of the two pull-down transistors PL and PR include a plurality of stacked channels, and the channels are wrapped by gates. The number of channels included in the two pull-down transistors is less than the number of channels included in the access transistors AXL and AXR.

[0012] Compared with the prior art, the present invention has the following advantages:

[0013] First, since the present invention adopts a fully N-type stacked nanosheet structure, it avoids the influence of the device on negative bias temperature instability, thus improving the read / write stability of the circuit.

[0014] Second, the access transistor included in the circuit of the present invention adopts an upper and lower layer gate structure, and controls the metal work function of the materials used for the upper and lower layer gates of the access transistor and the gate of the pull-down transistor, that is, the metal work function of the material used for the upper layer gate is lower than the metal work function of the materials used for the gates of the two transistors, and the metal work function of the material used for the lower layer gate is higher than the metal work function of the material used for the gate of the pull-down transistor, which can not only ensure the data stability of the storage node in the read state of the circuit, but also ensure the writing stability of the storage node in the write state, thus improving the read / write stability of the circuit.

[0015] Third, since the present invention uses a stacked nanosheet structure with upper and lower layer gates, the number of transistors used is reduced, so its integration is greatly improved compared with the traditional six-transistor static random access memory cell circuit. Description of the Drawings

[0016] Figure 1 is a structural diagram of a conventional stacked nanosheet transistor;

[0017] Figure 2 is a circuit diagram of a conventional 6-transistor static random access memory cell;

[0018] Figure 3 is a circuit diagram of a 4-transistor static random access memory cell based on a stacked nanosheet structure according to the present invention;

[0019] Figure 4 is a schematic diagram of the structure of a stacked nanosheet access transistor with upper and lower layer gates in the present invention;

[0020] Figure 5 is a simulation diagram of the read noise margin curve of the present invention;

[0021] Figure 6 is a simulation diagram of the write noise margin curve of the present invention. Detailed Embodiments

[0022] Refer to Figure 3, the 4T-SRAM cell circuit based on the stacked nanosheet structure of the present invention includes two N-type access transistors, AXL and AXR, two N-type pull-down transistors PL and PR, two storage nodes QL and QR, a word line WL, and two bit lines BL and BLB. Among them, the source of the first pull-down transistor PL is grounded, the drain is connected to the first storage node QL, and the gate is connected to the second storage node QR; the source of the second pull-down transistor PR is grounded, the drain is connected to the second storage node QR, and the gate is connected to the first storage node QL; both access transistors AXL and AXR are stacked nanosheet transistors with upper and lower layer gates. For the first access transistor AXL, its lower layer gate is connected to the word line WL, the drain is connected to the first bit line BL, and the source and upper layer gate are connected to the first storage node QL; for the second access transistor AXR, its lower layer gate is connected to the word line WL, the drain is connected to the second bit line BLB, and the source and upper layer gate are connected to the second storage node QR, realizing data reading and writing in the read state and write state and data storage in the hold state.

[0023] Refer to Figure 4 , each stacked nanosheet access transistor with upper and lower layer gates includes a substrate 1a and source-drain regions 3a located on both sides of the upper part of the substrate. A conduction control region is provided between the source-drain regions. The conduction control region is provided with several stacked channels 2a from bottom to top. Each side of the stacked channels is provided with isolation sidewalls 4a. The surface of the channels between the isolation sidewalls is covered with a gate dielectric layer 21a. The lower layer of the channels is wrapped with a lower layer gate 22a, and the channels not wrapped by the lower layer gate are wrapped with an upper layer gate 23. A gate isolation layer 24 is provided between the upper layer gate 23 and the lower layer gate 22a. The number of channels 2a wrapped by the lower layer gate 22a is less than the number of channels 2a wrapped by the upper layer gate 23, and the metal work function of the gate material used for the lower layer gate 22a is higher than the metal work function of the gate material used for the upper layer gate 23, and the difference in work function is more than 0.2 eV. The metal work function of the lower layer gate 22a is 4.6 eV to 4.7 eV, and the work function of the upper layer gate 23 is 4.4 to 4.5 eV.

[0024] Refer to Figure 1 , both pull-down transistors adopt transistors with the stacked nanosheet structure having only one gate in the prior art. The structure includes a substrate 1b and source-drain regions 3b located on both sides of the upper part of the substrate. A conduction control region is provided between the source-drain regions. The conduction control region is provided with several stacked channels 2b from bottom to top. Each side of the stacked channels is provided with isolation sidewalls 4b. The surface of the channels between the isolation sidewalls is covered with a gate dielectric layer 21b, and the channels are wrapped by the gate 22b.

[0025] The metal work function of the material selected for the gate 22b of each of the above pull-down transistors is greater than the metal work function of the material selected for the upper gate 23 of each of the above access transistors and less than the metal work function of the material selected for the lower gate 22a of each of the above access transistors. The number of channels 2b included in each of the above pull-down transistors is less than the number of channels 2a included in each of the above access transistors.

[0026] In this example, the metal work function of the material selected for the upper gate 23 of each access transistor is selected but not limited to 4.4 eV, the metal work function of the material selected for the lower gate 22a is selected but not limited to 4.6 eV, the number of channels 2a wrapped by the upper gate 23 is selected but not limited to 2, and the number of channels 2a wrapped by the lower gate 22a is selected but not limited to 1; the metal work function of the material selected for the gate 22b of each pull-down transistor is selected but not limited to 4.5 eV, and the number of included channels is selected but not limited to 2, so as to improve the read and write stability of the static random access memory cell circuit.

[0027] The circuit of this example has three working states, namely the hold state, the read state, and the write state. Among them:

[0028] The hold state is to stably store the level information in the two storage nodes QL and QR in this circuit to wait for external circuits to read or write.

[0029] The read state is to read the level information of the two storage nodes QL and QR through the two bit lines BL and BLB, and the level information of the two storage nodes QL and QR cannot change. The external circuit realizes the reading of the level information stored in this circuit by detecting the changes of the two bit lines BL and BLB.

[0030] The write state is to write level information to the two storage nodes QL and QR through the two bit lines BL and BLB, so that the level information of the first storage node QL is the same as that of the first bit line BL, and the level information of the second storage node QR is the same as that of the second bit line BLB. The external circuit will specify the level information to be written to the two bit lines BL and BLB, and the level information to be written to the two bit lines BL and BLB must be opposite.

[0031] In the above three operating states, since the first storage node QL is connected to the upper gate of the first access transistor AXL and the gate of the second pull-down transistor PR, and the second storage node QR is connected to the upper gate of the second access transistor AXR and the gate of the first pull-down transistor PL, and the upper gate of the first access transistor AXL controls the charging of the first storage node QL, and the first pull-down transistor PL controls the discharging of the first storage node QL; the upper gate of the second access transistor AXR controls the charging of the second storage node QR, and the second pull-down transistor PR controls the discharging of the second storage node QR; therefore, the level information stored in the two storage nodes QL and QR is always opposite.

[0032] In the hold state, the word line WL is at a low level, and the two bit lines BL and BLB are at a high level. The lower channels of the two access transistors AXL and AXR controlled by the lower gates are turned off by the word line WL, and the state of the upper channels controlled by the upper gates is related to the level state of the storage node connected to the upper gate. The working principle is as follows:

[0033] When the level of the first storage node QL is "1" and the level of the second storage node QR is "0", the upper channel of the first access transistor AXL is turned on by the feedback of the first storage node QL, and the first pull-down transistor PL is turned off by the feedback of the second storage node QR. The first bit line BL is connected to the first storage node QL through the first access transistor AXL, so that the level of the first storage node QL is maintained at "1"; the upper channel of the second access transistor AXR is turned off by the feedback of the second storage node QR, and the second pull-down transistor PR is turned on by the feedback of the first storage node QL. The second storage node QR is connected to the ground wire through the second pull-down transistor PR, so that the level of the second storage node QR is maintained at "0";

[0034] When the level of the first storage node QL is "0" and the level of the second storage node QR is "1", due to the symmetric structure of the four-transistor static random access memory cell circuit, both the first storage node QL and the second storage node QR will be maintained at their original levels.

[0035] In the read state, the word line WL remains at a high level, and the two bit lines BL and BLB are pre-charged to a high level. The lower channels of the access transistors controlled by the lower gates are turned on by the word line WL, and the state of the upper channels controlled by the upper gates is related to the level state of the storage node connected to the upper gate. The working principle is as follows:

[0036] When the level of the first storage node QL is "1" and the level of the second storage node QR is "0", the upper channel of the first access transistor AXL is turned on by the feedback of QL. The first bit line BL is connected to the first storage node QL through the first access transistor AXL. Since both the first bit line BL and the first storage node QL have a level of "1", the levels of the bit line BL and the QL node remain unchanged.

[0037] The upper channel of the second access transistor AXR is turned off by the feedback of the second storage node QR. The second pull-down transistor PR is turned on by the feedback of the first storage node QL. The second bit line BLB is connected to the second storage node QR through the second access transistor AXR. Since the level of the second bit line BLB is "1", which is higher than the level of the second storage node QR, the second bit line BLB charges the second QR node through the second access transistor AXR, and the level of the second bit line BLB drops.

[0038] The second storage node QR is not only connected to the second bit line BLB through the second access transistor AXR but also connected to the ground wire through the second pull-down transistor PR. Therefore, while the second storage node QR is being charged by the second bit line BLB, it also discharges to the ground wire. Since the metal work function of the material used for the gate of the second pull-down transistor PR is less than the metal work function of the material used for the lower gate of the second access transistor, the discharge current of the second storage node QR is greater than the charging current, and the stored "0" level remains unchanged.

[0039] When the level of the first storage node QL is "0" and the level of the second storage node QR is "1", due to the symmetric structure of the four-transistor static random access memory cell circuit, the level of the first bit line BL drops, and the levels of the second bit line BLB, the first storage node QL, and the second storage node QR remain unchanged.

[0040] The sense amplifier in the external circuit reads the data stored in the two nodes QL and QR by detecting the changes in the levels of the two bit lines BL and BLB, completing the read operation.

[0041] In the write state, the word line WL is at a high level. The two bit lines BL and BLB are set to the levels to be written. The lower channels of the access transistors controlled by the lower gates are turned on by the word line WL. The states of the upper channels controlled by the upper gates are related to the level states of the storage nodes connected to the upper gates. The working principle is as follows:

[0042] When the level of the first storage node QL is "1", the level of the second storage node QR is "0", the first bit line BL is set at the "1" level, and the second bit line BLB is set at the "0" level, the upper channel of the first access transistor AXL is turned on by the feedback of the first storage node QL, and the first pull-down transistor PL is turned off by the feedback of the second storage node QR. The first storage node QL is connected to the first bit line BL through the first access transistor AXL. Since the levels of both the first storage node QL and the first bit line BL are "1", the level of the first storage node QL remains "1", the same as that of the bit line BL; the upper channel of the second access transistor AXR is turned off by the feedback of the second storage node QR, and the second pull-down transistor PR is turned off by the feedback of the first storage node QL. The first storage node QL is connected to the first bit line BL through the first access transistor AXL. The second storage node QR is not only connected to the second bit line BLB through the second access transistor AXR but also connected to the ground wire through the second pull-down transistor PR. Therefore, while the second storage node QR is being charged by the second bit line BLB, it also discharges to the ground wire. Because the metal work function of the material used for the gate of the second pull-down transistor PR is less than the metal work function of the material used for the lower gate of the second access transistor AXR, the discharge current of the second storage node QR is greater than the charging current, and the stored "0" level remains unchanged, the same as that of the second bit line BLB.

[0043] When the level of the first storage node QL is "1", the level of the second storage node QR is "0", the first bit line BL is set at the "0" level, and the second bit line BLB is set at the "1" level, at the start of the write state, the upper channel of the first access transistor AXL is turned on by the feedback of the first storage node QL, and the first pull-down transistor PL is turned off by the feedback of the second storage node QR. The first storage node QL is connected to the first bit line BL through the first access transistor AXL. Since the level of the first bit line BL is lower than the level of the first storage node QL, the first storage node QL starts to discharge to the first bit line BL, and the level of the first storage node QL starts to decrease;

[0044] At the start of the write state, the upper channel of the second access transistor AXR is turned off by the feedback of the second storage node QR. The first pull-down transistor PL is turned on by the feedback of the first storage node QL. The second storage node QR is connected to the ground wire through the second pull-down transistor PR and is connected to the second bit line BLB through the second access transistor AXR. Due to the decrease in the level of the first storage node QL, the second pull-down transistor PR gradually turns off, the discharge current of the second storage node QR starts to decrease, the voltage of the second storage node QR starts to show an upward trend, and the upper channel of the second access transistor AXR is gradually turned on by the feedback of the second storage node QR. When both the second access transistor AXR and the second pull-down transistor PR are in the subthreshold state, since the metal work function of the material used for the upper gate of the second access transistor AXR is less than the metal work function of the material used for the gate of the second pull-down transistor PR, the second access transistor AXR has a larger subthreshold current compared to the second pull-down transistor PR, which promotes the increase in the level of the second storage node QR. The increase in the level of the second storage node QR will cause the first pull-down transistor PL to turn on, promoting the decrease in the level of the first storage node QL, making the level of the QL node drop to "0", the same as the first bit line BL, and the level of the second storage node QR node rises to "1", the same as the second bit line BLB;

[0045] When the level of the first storage node QL is "0", the level of the second storage node QR is "1", the first bit line BL is set at the "1" level, and the second bit line BLB is set at the "0" level, due to the symmetric structure of the four-transistor static random access memory cell circuit, the level of the first storage node QL will rise to "1", the same as the first bit line BL, and the level of the second storage node QR will drop to "0", the same as the second word line BLB.

[0046] The advantages of this example can be further illustrated by the following simulation experiments.

[0047] 1. Simulation parameters:

[0048] Parameter 1: Set the working voltages of the word line WL and the two bit lines BL and BLB to 0.65V. The metal work function of the material used for the upper gate of each access transistor is 4.4eV, the metal work function of the material selected for the lower gate is 4.6eV, the number of channels wrapped by the upper gate is 2, and the number of channels wrapped by the lower gate is 1; the metal work function of the material selected for the gate of each pull-down transistor is 4.5eV, and the number of channels included is 2.

[0049] Parameter 2: Set the working voltages of the word line WL and the second bit line BL to 0.65V, the working voltage of the first bit line BL to 0V, and the remaining parameters are the same as in Simulation 1.

[0050] 2. Simulation content:

[0051] Simulation 1: Under the simulation conditions of the above Parameter 1, the read stability of the circuit of the present invention was simulated and compared with the read stability of the existing six-transistor random static memory cell circuit. The results are as Figure 5 , where the side length of the solid-line square represents the read stability of the 4T-SRAM cell circuit of the present invention based on the stacked nanosheet structure, and the side length of the dashed-line square represents the read stability of the traditional 6T-SRAM cell circuit.

[0052] From Figure 5 it can be seen that the read stability of the 4T-SRAM cell circuit of the present invention based on the stacked nanosheet structure is higher than that of the traditional 6T-SRAM cell circuit.

[0053] Simulation 2: Under the simulation conditions of the above Parameter 2, the write stability of the circuit of the present invention was simulated and compared with the read stability of the existing six-transistor random static memory cell circuit. The results are as Figure 6 , where the side length of the solid-line square represents the write stability of the 4T-SRAM cell circuit of the present invention based on the stacked nanosheet structure, and the side length of the dashed-line square represents the write stability of the traditional 6T-SRAM cell circuit.

[0054] From Figure 6 it can be seen that the write stability of the 4T-SRAM cell circuit based on the stacked nanosheet structure is significantly higher than that of the traditional 6T-SRAM cell circuit.

[0055] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. However, these corrections and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A four-transistor static random access memory cell circuit based on a stacked nanosheet structure, comprising two N-type access transistors AXL and AXR, two N-type pull-down transistors PL and PR, two storage nodes QL and QR, a word line WL, and two bit lines BL and BLB. The source of the first pull-down transistor PL is grounded, the drain is connected to the storage node QL, and the gate is connected to the storage node QR; the source of the second pull-down transistor PR is grounded, the drain is connected to the storage node QR, and the gate is connected to the storage node QL, characterized in that ； The two access transistors AXL and AXR each include a plurality of stacked channels. The lower layer of the channel is wrapped with a lower gate, and the upper layer of the channel not wrapped by the lower gate is wrapped with an upper gate. The metal work function of the material used for the upper gates of the two access transistors AXL and AXR is lower than the metal work function of the material used for the gates of the two pull-down transistors PL and PR, and the metal work function of the material used for the lower gates of the access transistors AXL and AXR is higher than the metal work function of the material used for the gates of the pull-down transistors PL and PR; For the first access transistor AXL, its lower gate is connected to the word line WL, its drain is connected to the first bit line BL, and its source and upper gate are connected to the first storage node QL; for the second access transistor AXR, its lower gate is connected to the word line WL, its drain is connected to the second bit line BLB, and its source and upper gate are connected to the second storage node QR, realizing data reading and writing in the read state and the write state and data storage in the hold state.

2. The circuit according to claim 1, characterized in that, The number of channels wrapped by the lower gates of the two access transistors AXL and AXR is less than the number of channels wrapped by the upper gates, and the metal work function of the gate material used for the lower gates is higher than the metal work function of the gate material used for the upper gates, with a difference in work function of more than 0.2 eV. The metal work function of the lower gate is 4.6 eV - 4.7 eV, and the work function of the upper gate is 4.4 - 4.5 eV.

3. The circuit according to claim 1, wherein An isolation layer is provided between the upper gate and the lower gate to avoid short circuits between the two gates.

4. The circuit according to claim 1, wherein Both of the two pull-down transistors PL and PR include a plurality of stacked channels, and the channels are wrapped by gates. The number of channels included in both of the two pull-down transistors is less than the number of channels included in the access transistors AXL and AXR.

5. The circuit according to claim 1 is provided with three working states, namely a hold state, a read state, and a write state. The hold state is the initial state of this circuit, used to keep the level information of the two bit lines BL and BLB and the two storage nodes QL and QR from changing. The read state is the state in which the external circuit reads the level information of the two storage nodes QL and QR through the two bit lines BL and BLB. The write state is the state in which the external circuit writes level information to the two storage nodes QL and QR through the two bit lines BL and BLB.

6. The circuit according to claim 5, wherein In the hold state, the word line WL is at a low level, the two bit lines BL and BLB are at a high level, and the levels of the two storage nodes QL and QR will both remain stable.

7. The circuit according to claim 5, characterized in that, In the read state, the word line WL remains at a high level, and the two bit lines BL and BLB are pre-charged to a high level to enable the level information of the two bit lines BL and BLB to change according to the level information of the two storage nodes QL and QR. This change is output to the sense amplifier of the external circuit, and the levels of the storage nodes QL and QR will remain stable, thereby realizing the reading of the data stored in the two storage nodes QL and QR by the external circuit.

8. The circuit according to claim 5, wherein In the write state, the word line WL is at a high level, and the two bit lines BL and BLB are set to the levels to be written, so as to realize the inversion of the level information stored in the first storage node QL into the level information of the first bit line BL, and the inversion of the level information stored in the second storage node QR into the level information of the second bit line BLB.

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