A wafer-level packaging structure and packaging method for a sensor

Abstract

The present invention discloses a wafer-level packaging structure of a sensor and its packaging method. The packaging method includes: providing a first structure, the first structure including: a substrate with a first cavity formed therein; a detection structure disposed above the substrate to cover the first cavity, the detection structure including a sensitive unit and an electrical lead-out terminal; forming a first annular cofferdam on the detection structure, the first annular cofferdam at least surrounding a part of the sensitive unit, and the electrical lead-out terminal being located outside the first annular cofferdam; providing a cover substrate and forming a second annular cofferdam on the cover substrate; bonding the cover substrate to the detection structure through the first annular cofferdam and the second annular cofferdam, and forming a second cavity between the detection structure and the cover substrate, and there is an overlapping part between the projection of the second cavity in the direction of the substrate surface and the projection of the first cavity in the direction of the substrate surface. Placing the electrical lead-out terminal outside the first annular cofferdam, the electrical connection method can be diversified, avoiding the complex process of TSV leads and saving costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and particularly to a wafer-level packaging structure and a packaging method for a sensor. Background Art

[0002] With the continuous development of MEMS sensing technology, higher performance is pursued in sensor packaging. Sensors with a thermopile as the core component have been widely used in fields such as infrared temperature measurement, infrared detection, infrared alarm, infrared imaging, and infrared guidance. The basic principle of the sensor is based on the Seebeck effect of thermoelectric materials. Generally, multiple pairs of thermocouples are connected into a "pile" to convert the infrared radiation signal absorbed from the outside into an electrical signal to achieve temperature measurement. Among the two ends, the end that absorbs infrared is called the hot zone, and the substrate end is called the cold zone. Most traditional sensors use TO packaging. With the increasing demand for integrated temperature measurement chips in electronic products such as mobile phones and wearable devices, there is also a demand for miniaturization of the chip volume.

[0003] However, in the traditional TO packaging process, the thermopile chip is attached to the packaging base, and then the chip pads and the pins of the base are connected by wire bonding. Finally, the cap and the base are hermetically packaged. Its packaging size is very large (5×5×3 mm), and the pins are very long, which seriously restricts its application in miniaturized devices.

[0004] Therefore, how to improve the sensor packaging method, reduce the manufacturing cost, reduce the packaging size of the chip, and meet the application requirements in miniaturized devices is the problem faced at present. Summary of the Invention

[0005] The purpose of the present invention is to provide a wafer-level packaging structure and a packaging method for a sensor, which can solve the problem that the packaging size of the sensor is large and cannot meet the application requirements in miniaturized devices.

[0006] To achieve the above purpose, the present invention provides a wafer-level packaging method for a sensor, including:

[0007] Providing a first structure, the first structure includes:

[0008] A substrate, in which a first cavity is provided; a detection structure, disposed above the substrate to cover the first cavity, the detection structure including a sensitive unit and an electrical lead-out end;

[0009] Forming a first annular cofferdam on the detection structure, the first annular cofferdam at least surrounding part of the sensitive unit, and the electrical lead-out end being located outside the first annular cofferdam;

[0010] Providing a cover substrate, and forming a second annular cofferdam on the cover substrate;

[0011] Bond the capping substrate to the detection structure through the first annular cofferdam and the second annular cofferdam, and form a second cavity between the detection structure and the capping substrate. A part of the projection of the second cavity in the substrate surface direction overlaps with the projection of the first cavity in the substrate surface direction.

[0012] The present invention also provides a wafer-level packaging structure for a sensor, including:

[0013] A substrate, in which a first cavity is provided;

[0014] A detection structure, disposed above the substrate to cover the first cavity, the detection structure includes a sensitive unit and an electrical lead-out terminal;

[0015] A sealing ring, disposed above the detection structure, at least surrounding part of the sensitive unit, the electrical lead-out terminal is located outside the sealing ring; the sealing ring includes a first sealing ring and a second sealing ring and a soldering aid layer disposed between the first sealing ring and the second sealing ring, wherein the first sealing ring is close to the detection structure;

[0016] A capping substrate, covering the sealing ring to form a second cavity, and a part of the projection of the second cavity in the substrate surface direction overlaps with the projection of the first cavity in the substrate surface direction.

[0017] The beneficial effects of the present invention are as follows:

[0018] The wafer-level manufacturing method forms the first cavity and the second cavity, and can fabricate small-sized sensor devices. The capping substrate is bonded to the detection structure through the first annular cofferdam and the second annular cofferdam to form a sealed second cavity, reducing the packaging volume. At the same time, the electrical lead-out terminal is placed outside the first annular cofferdam, and the connection method between the electrical lead-out terminal and the external circuit can be diversified, avoiding the complex process of TSV leads and saving costs.

[0019] Further, an annular groove is formed on the capping substrate, and the second annular cofferdam is disposed in the annular groove to prevent solder overflow during bonding, improving the yield and reliability of the wafer-level packaging of the sensor.

[0020] Further, the material of the capping substrate is silicon, and the silicon material can pass through infrared radiation, eliminating the need to provide a window on the capping, simplifying the process flow. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figures 1 to 13 The schematic structural diagrams corresponding to different steps in the wafer-level packaging method of the sensor according to Embodiment 1 of the present invention are shown.

[0023] Figure 14 The schematic diagram of the wafer-level packaging structure of the sensor according to Embodiment 2 of the present invention is shown.

[0024] Explanation of reference numerals:

[0025] 100 - Substrate; 200 - Capping substrate; 10 - First substrate; 11 - Dielectric layer; 20 - Electrical lead-out terminal; 21 - First thermoelectric strip; 22 - Isolation layer; 24 - Passivation layer; 221 - Through hole; 25 - Silicon oxide layer; 26 - Second substrate; 27 - First cavity; 28 - Third substrate; 29 - Bonding layer; 31 - First annular cofferdam; 311 - First annular metal layer; 312 - First soldering aid layer; 32 - Second annular cofferdam; 321 - Second annular metal layer; 322 - Second soldering aid layer; 301 - First sealing ring; 302 - Second sealing ring; 303 - Soldering aid layer; 320 - Annular groove; 33 - Second cavity; 34 - Third cavity. Detailed implementation manners

[0026] The following further elaborates on the present invention in detail in conjunction with the drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will be clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0027] The terms "first", "second", etc. in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological order. It is to be understood that, in appropriate circumstances, these terms so used may be interchanged, for example, so that the embodiments of the present invention described herein can be operated in an order different from that described or shown herein. Similarly, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps may be omitted and / or some other steps not described herein may be added to the method. If the components in a certain drawing are the same as those in other drawings, although these components can be easily recognized in all the drawings, for the sake of clearer illustration of the drawings, the present specification will not label the reference numerals of all the same components in each drawing.

[0028] The present invention provides a wafer-level packaging structure and a packaging method for a sensor, and the detection structure serves as the sensing structure of the sensor, such as a MEMS cantilever structure, a thermopile structure, a filter structure, etc.

[0029] Example 1

[0030] Embodiment 1 of the present invention provides a wafer-level packaging method for a sensor, including the following steps:

[0031] S01: Provide a first structure, and the first structure includes:

[0032] A substrate, in which a first cavity is provided; a detection structure, disposed above the substrate to cover the first cavity, and the detection structure includes a sensitive unit and an electrical lead-out end;

[0033] S02: Form a first annular cofferdam on the detection structure, and the first annular cofferdam at least surrounds part of the sensitive unit, and the electrical lead-out end is located outside the first annular cofferdam;

[0034] S03: Provide a cover substrate, and form a second annular cofferdam on the cover substrate;

[0035] S04: Bond the cover substrate to the detection structure through the first annular cofferdam and the second annular cofferdam, and form a second cavity between the detection structure and the cover substrate, and the projection of the second cavity in the direction of the substrate surface and the projection of the first cavity in the direction of the substrate surface have an overlapping part.

[0036] It should be noted that S0N in this specification does not represent the sequence of manufacturing processes.

[0037] Figures 1 to 13The structural schematic diagrams corresponding to different steps of the wafer-level packaging method of the sensor according to this embodiment are shown. Please refer to Figures 1 to 13 , and each step will be described in detail.

[0038] Refer to Figure 1 , a first structure is provided, and the first structure includes: a substrate 100, in which a first cavity 27 is provided; a detection structure, disposed above the substrate 100 to cover the first cavity 27, and the detection structure includes a sensitive unit and an electrical lead-out end 20.

[0039] In this embodiment, the detection structure is a thermopile structure, and the sensitive unit is a first thermoelectric strip 21 and a second thermoelectric strip (not shown in the figure) connected to each other. In this embodiment, the first thermoelectric strip 21 and the second thermoelectric strip are horizontally arranged. In other embodiments, the two thermoelectric strips can also be stacked vertically. After the sensitive unit receives infrared radiation, its temperature rises, and the first cavity 27 in the substrate 100 is used for heat insulation. In this embodiment, the substrate 100 includes a third substrate 28, and a first substrate 10 bonded to the third substrate through a bonding layer 29. The first cavity 27 is located in the first substrate 10 and penetrates the first substrate 10. The material of the first substrate 10 includes semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, etc. An isolation layer 22 is provided between and above the two thermoelectric strips, and the material of the isolation layer 22 includes dielectric materials such as silicon dioxide, silicon nitride, and aluminum oxide. A passivation layer 24 is further formed on the upper surface of the thermopile structure. In this embodiment, a dielectric layer 11 is further formed above the first substrate 10. The dielectric layer 11 covers the first cavity 27. The dielectric layer 11 prevents the sensitive unit from transferring heat in the direction of the first cavity 27, ensures the sensitivity of the sensor, and supports the thermosensitive unit. The material of the dielectric layer 11 includes silicon nitride or silicon dioxide.

[0040] Refer to Figure 2, a first annular cofferdam 31 is formed on the detection structure. The first annular cofferdam 31 surrounds part of the sensitive unit, and the electrical lead-out end 20 is located outside the first annular cofferdam 31. In this embodiment, forming the first annular cofferdam 31 includes: forming a first annular metal layer 311 on the thermopile structure, and forming a first soldering layer 312 on the first annular metal layer 311. The material of the first annular metal layer 311 is metal, such as copper. In this embodiment, the material of the first soldering layer 312 is tin. In other embodiments, the material of the first soldering layer 312 can also be Au, Ge, etc. The first annular metal layer 311 can be formed by deposition or electroplating processes. In this embodiment, the first annular cofferdam 31 is a continuous and sealed ring. The first annular cofferdam 31 surrounds the area enclosed by the thermal junctions of the thermopile. The electrical lead-out end 20 is placed outside the first annular cofferdam 31, and the connection method between the electrical lead-out end 20 and the external circuit can be diversified, avoiding the complex process of TSV leads and saving costs.

[0041] In this embodiment, with the substrate 100 as the support, a bonding cofferdam is fabricated above the detection structure for subsequent bonding. There is a first cavity in the substrate. The size of the first cavity is 300 - 3000 μm in length or width, such as 500 μm, 800 μm, 1000 μm, 2000 μm, and the depth of the first cavity is 10 - 400 microns, such as 20 μm, 50 μm, 100 μm, 200 μm; the width range of the first annular cofferdam is 10 - 1000 μm, such as 20 μm, 40 μm, 60 μm, 500 μm, 800 μm, and the height of the first annular cofferdam is 2 - 50 μm, such as 4 μm, 8 μm, 15 μm, 25 μm, etc., thereby overcoming the technical difficulties of using a cavity substrate as the support and forming a second cavity during bonding, ensuring the feasibility of the cofferdam process, and ensuring the product yield.

[0042] Reference Figure 3 and Figure 4, a capping substrate 200 is provided, and a second annular cofferdam 32 is formed on the capping substrate 200. In this embodiment, forming the second annular cofferdam 32 includes: forming an annular groove 320 in the capping substrate 200, and forming the second annular cofferdam 32 in the annular groove 320, and a gap is provided between the outer periphery of the second annular cofferdam 32 and the annular groove 320. The size and shape of the second annular cofferdam 32 correspond to those of the first annular cofferdam 31. The annular groove 320 can be formed by an etching process. The second annular cofferdam 32 includes: a second annular metal layer 321 close to the thermopile structure, and a second solder layer 322 on the second annular metal layer 321. A gap is provided between the outer periphery of the second annular cofferdam 32 and the annular groove 320, so that when the first solder layer 312 and the second solder layer 322 are heated and welded, the flowing solder can flow into the annular groove 320. This prevents the solder from contacting other circuits and causing a short circuit, improving the yield and reliability of the wafer-level packaging of the sensor.

[0043] To better prevent the solder from flowing out of the annular groove 320, in this embodiment, the depth of the annular groove 320 is greater than the height of the second annular cofferdam 32. When welding the second annular cofferdam 32 and the first annular cofferdam 31, the welding position is within the annular groove 320, which better prevents the solder from flowing out of the annular groove 320. The structure, material, and forming method of the second annular cofferdam 32 refer to the relevant description of the first annular cofferdam 31. In this embodiment, a third cavity 34 is provided on the lower surface of the capping substrate 200, the annular groove 320 surrounds the third cavity 34, and the annular groove 320 and the third cavity 34 are independent of each other to avoid solder contamination of the third cavity 34. The material of the capping substrate 200 can be a semiconductor material or a dielectric material, and the semiconductor material can refer to the material of the first substrate 10. In this embodiment, the material of the capping substrate 200 is silicon, and the silicon material can pass infrared radiation without opening a window on the capping, simplifying the process flow.

[0044] Reference Figure 5 , the capping substrate 200 is bonded to the detection structure through the first annular cofferdam 31 and the second annular cofferdam 32, and a second cavity 33 is formed between the detection structure and the capping substrate 200. The projection of the second cavity 33 in the substrate surface direction and the projection of the first cavity 27 in the substrate surface direction have an overlapping part. In this embodiment, the second annular cofferdam 31 and the second annular cofferdam 32 are welded together through the first solder layer 312 and the second solder layer 322 to form a sealed second cavity 33. In this embodiment, before bonding the capping substrate 200 to the detection structure, it further includes removing part of the passivation layer to expose the electrical lead-out terminal 20. Reference Figure 6, in this embodiment, it further includes removing the cover substrate vertically above the electrical lead-out terminal 20 to expose the upper area of the electrical lead-out terminal 20, facilitating the later process to perform wire bonding on the electrical lead-out terminal 20 to achieve electrical connection with external signals.

[0045] In this embodiment, the projection of the second annular cofferdam in the direction of the substrate surface surrounds the projection of the first cavity in the direction of the substrate surface. In this way, when bonding the cover substrate, the position of the second annular cofferdam is supported by the substrate, preventing cracking caused by uneven stress during bonding of the detection structure or the cover substrate.

[0046] In this embodiment, the method for forming the first structure is as follows: providing a first substrate, forming the thermopile structure on the first substrate; forming a second substrate on the thermopile structure; forming the heat insulation cavity penetrating the first substrate; forming a third substrate on the first substrate to cover the heat insulation cavity, and removing the second substrate; the substrate includes the first substrate and the third substrate.

[0047] Specifically, referring to Figure 7 , a first substrate 10 is provided, and a dielectric layer 11 is formed on the first substrate. The material of the first substrate 10 is silicon, and the material of the dielectric layer 11 includes silicon nitride or silicon oxide. The dielectric layer 11 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In another embodiment, the first substrate is an SOI structure, and the thermopile structure can be directly formed on the first substrate, and the top silicon layer can be used as at least one of the materials of the thermocouple. Referring to Figure 8 , a thermocouple structure is formed on the dielectric layer 11. The thermocouple structure includes a first thermoelectric strip 21 and a second thermoelectric strip. The first thermoelectric strip 21 and the second thermoelectric strip can be distributed vertically or horizontally. In this embodiment, the two are distributed horizontally, Figure 8 and only the first thermoelectric strip 21 is shown in the cross-section of. The material combinations of the first thermoelectric strip 21 and the second thermoelectric strip include: p-type single-crystalline silicon and n-type single-crystalline silicon, single-crystalline silicon and polycrystalline silicon, single-crystalline silicon and metal, polycrystalline silicon and metal, p-type polycrystalline silicon and n-type polycrystalline silicon. The metal includes aluminum, copper, gold, titanium, or tungsten. An isolation layer 22 is formed between and above the thermoelectric strips. The material of the isolation layer 22 includes dielectric materials such as silicon dioxide, silicon nitride, and aluminum oxide. A through hole 221 is formed on the isolation layer 22 to expose part of the first thermoelectric strip 21 and the second thermoelectric strip.

[0048] Referring to Figure 9, a conductive material is formed in the through hole to form an electrical lead-out terminal 20 that electrically connects the first thermoelectric strip 21 and the second thermoelectric strip. The electrical lead-out terminal 20 is also used to connect to an external electrical signal. The conductive material is such as aluminum, copper, gold, titanium or tungsten. In this embodiment, the number of the first thermoelectric strips 21 and the second thermoelectric strips is equal, and the second thermoelectric strips and the corresponding first thermoelectric strips 21 are electrically connected to each other to form a plurality of thermocouples, and the plurality of thermocouples are connected in series.

[0049] Reference Figure 10 , in this embodiment, after forming the thermocouple, it further includes forming a passivation layer 24 to cover the thermocouple and the electrical lead-out terminal 20. The material of the passivation layer 24 includes single-layer or laminated insulating films such as silicon nitride, silicon dioxide, phosphosilicate glass, borophosphosilicate glass or polyimide film. The passivation layer 24 can be formed by methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, laser ablation deposition or molecular beam deposition. The passivation layer 24 can play a role of dielectric isolation and can also be used as an absorption layer for absorbing infrared rays, effectively transferring the heat generated by absorbing infrared rays to the sensitive unit, thereby improving the sensor sensitivity. An oxide layer 25 is deposited on the surface of the passivation layer 24, and a second substrate 26 is fusion-bonded on the oxide layer 25. In this embodiment, the material of the second substrate 26 is silicon.

[0050] Reference Figure 11 , flip the formed structure, and form a first cavity 27 in the first substrate 10 through an etching process. The first cavity 27 penetrates the first substrate 10 to expose the dielectric layer 11, and the first cavity 27 at least surrounds the region surrounded by the thermocouple thermal junctions. Reference Figure 12 , bond a third substrate 28 on the first substrate 10 through a bonding layer 29. Reference Figure 13 , remove the oxide layer and the second substrate 26, and etch the passivation layer 24 to expose a partial surface of the electrical lead-out terminal 20.

[0051] Embodiment 2

[0052] Figure 14 shows a schematic diagram of the wafer-level packaging structure of the sensor in this embodiment. Please refer to Figure 14 , the packaging structure includes:

[0053] A substrate 100, in which a first cavity 27 is provided;

[0054] A detection structure, disposed above the substrate 100 to cover the first cavity 27, and the detection structure includes a sensitive unit and an electrical lead-out terminal 20;

[0055] A sealing ring is disposed above the detection structure, at least surrounding part of the sensitive unit, and the electrical lead-out terminal 20 is located outside the sealing ring; the sealing ring includes a first sealing ring 301 and a second sealing ring 302, and a soldering aid layer 303 disposed between the first sealing ring 301 and the second sealing ring 302, wherein the first sealing ring 301 is close to the detection structure;

[0056] A cover substrate 200 covers the sealing ring to form a second cavity 33, and the projection of the second cavity 33 in the surface direction of the substrate 100 and the projection of the first cavity 27 in the surface direction of the substrate 100 have an overlapping part.

[0057] Specifically, in this embodiment, the detection structure is a thermopile structure, and the sensitive unit is a first thermoelectric strip 21 and a second thermoelectric strip connected to each other. In this embodiment, the first thermoelectric strip 21 and the second thermoelectric strip 23 are arranged in parallel. Only the first thermoelectric strip 21 is shown in the cross-section in the figure. In other embodiments, the two thermoelectric strips can also be stacked one above the other. In this embodiment, the substrate 100 includes a third substrate 28, and a first substrate 10 bonded to the third substrate 28 through a bonding layer 29. The first cavity 27 is located in the first substrate 10 and penetrates the first substrate 10. The material of the first substrate 10 includes a semiconductor material, and the selection of the semiconductor material refers to the method embodiment. A passivation layer 24 is formed on the upper surface of the thermopile structure, and the passivation layer 24 exposes at least part of the electrical lead-out terminal 20, and the electrical lead-out terminal 20 is used for electrical connection with an external signal. In this embodiment, a dielectric layer 11 is further formed above the first substrate 10. The dielectric layer 11 covers the first cavity 27, and the dielectric layer 11 prevents the sensitive unit from transferring heat in the direction of the first cavity 27, ensuring the sensitivity of the sensor. The material of the dielectric layer 11 includes silicon nitride or silicon oxide.

[0058] The sealing ring is disposed above the detection structure and encloses a second cavity 33. The sealing ring includes three parts: a first sealing ring 301 close to the detection structure, a second sealing ring 302 close to the cover substrate 200, and a soldering aid layer 303 disposed between the first sealing ring 301 and the second sealing ring 302. In this embodiment, the materials of the first sealing ring 301 and the second sealing ring 302 are both copper. In other embodiments, the materials of the first sealing ring 301 and the second sealing ring 302 can also be at least one of other metal materials, dielectric materials, or polymers. The soldering aid layer 303 can be a single-layer structure or a double-layer structure. When the soldering aid layer is a double-layer structure, the two layers of materials can be the same or different. In this embodiment, the soldering aid layer is a double-layer material, and both materials are tin. The electrical lead-out terminal 20 is placed outside the sealing ring, and the connection method between the electrical lead-out terminal 20 and the external circuit can be diversified, avoiding the complex process of TSV leads and saving costs.

[0059] In this embodiment, an annular groove 320 is provided in the cover substrate 200, and the second sealing ring 302 is located in the annular groove 320. The depth of the annular groove 320 is greater than the height of the second sealing ring, and solder is filled between the outer periphery of the second sealing ring 302 and the annular groove 320. In this embodiment, the solder assisting layer 303 is also located in the annular groove 320. For the reason of the above setting, please refer to the method embodiment and details will not be described here. In this embodiment, a third cavity 34 is provided in the cover substrate 200 to increase the distance between the thermopile and the upper cover, thereby reducing the heat dissipation rate of the hot end of the thermopile to the upper cover and maintaining the temperature of the hot end. The annular groove 320 surrounds the outer periphery of the third cavity 34. The material of the cover substrate is silicon, and the silicon material can radiate infrared rays, eliminating the need to provide a window on the cover and simplifying the process flow. The sealing ring structure of this embodiment is equivalent to the combination of the first annular cofferdam and the second annular cofferdam in the method embodiment, and its structure and positional relationship refer to the relevant description in the method embodiment.

[0060] It should be noted that each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment.

[0061] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A wafer-level packaging method for a sensor, characterized in that, Comprising: Providing a first structure, the first structure comprising: A substrate having a first cavity therein; a detection structure disposed above the substrate covering the first cavity, the detection structure comprising a sensitive unit and an electrical lead-out end; Forming a first annular cofferdam on the detection structure, the first annular cofferdam surrounding at least a part of the sensitive unit, and the electrical lead-out end being located outside the first annular cofferdam; Providing a capping substrate and forming a second annular cofferdam on the capping substrate; Bonding the capping substrate to the detection structure through the first annular cofferdam and the second annular cofferdam, and forming a second cavity between the detection structure and the capping substrate, and a part of the projection of the second cavity in the direction of the substrate surface overlaps with the projection of the first cavity in the direction of the substrate surface; Forming the second annular cofferdam includes: forming an annular groove in the capping substrate, and forming the second annular cofferdam in the annular groove, and there is a gap between the outer periphery of the second annular cofferdam and the annular groove; The depth of the annular groove is greater than the height of the second annular cofferdam.

2. The wafer-level packaging method of the sensor according to claim 1, characterized in that Forming the first annular cofferdam includes: forming a first annular metal layer on the detection structure and forming a first solder assist layer on the first annular metal layer; and / or forming the second annular cofferdam includes: forming a second annular metal layer on the capping substrate and forming a second solder assist layer on the second annular metal layer.

3. The wafer-level packaging method of the sensor according to claim 1, characterized in that, The method further includes: removing the capping substrate directly above the electrical lead-out end.

4. The wafer-level packaging method of the sensor according to claim 3, characterized in that, The method further includes connecting the electrical lead-out end to an external signal through a wire bonding process.

5. The wafer-level packaging method of the sensor according to claim 1, wherein The projection of the second annular cofferdam in the direction of the substrate surface surrounds the projection of the first cavity in the direction of the substrate surface.

6. The wafer-level packaging method of the sensor according to claim 1, wherein A passivation layer covering the sensitive unit and the electrical lead-out end is formed on the upper surface of the detection structure. Before bonding the capping substrate to the detection structure, it further includes: removing a part of the passivation layer to expose the electrical lead-out end.

7. The wafer-level packaging method of the sensor according to claim 1, characterized in that The material of the capping substrate includes a semiconductor.

8. The wafer-level packaging method of the sensor according to claim 1, characterized in that, Forming the first structure includes: providing a first substrate, forming the detection structure on the first substrate; forming a second substrate on the detection structure; forming the first cavity penetrating the first substrate; forming a third substrate on the first substrate to cover the first cavity, and removing the second substrate; the substrate includes the first substrate and the third substrate.

9. The wafer-level packaging method of the sensor according to claim 2, wherein The first annular cofferdam includes a first solder assist layer, and the material of the first solder assist layer includes tin; and / or, the second annular cofferdam includes a second solder assist layer, and the material of the second solder assist layer includes tin.

10. The wafer-level packaging method of the sensor according to claim 1, characterized in that, The sensitive unit includes a first thermoelectric strip and a second thermoelectric strip connected to each other, and the first thermoelectric strip and the second thermoelectric strip are stacked or arranged side by side.

11. The wafer-level packaging method of the sensor according to claim 1, characterized in that, The material of the first annular cofferdam and / or the second annular cofferdam includes one or a combination of a metal material, a dielectric material, and a polymer.

12. A wafer-level packaging structure of a sensor, characterized in that, Comprising: a substrate having a first cavity therein; The detection structure is disposed above the substrate to cover the first cavity, and the detection structure includes a sensitive unit and an electrical lead-out terminal; The sealing ring is disposed above the detection structure to surround part of the sensitive unit, and the electrical lead-out terminal is located outside the sealing ring; the sealing ring includes a first sealing ring, a second sealing ring, and a soldering aid layer disposed between the first sealing ring and the second sealing ring, wherein the first sealing ring is close to the detection structure; The cover substrate covers the sealing ring to form a second cavity, and an overlapping part is provided between the projection of the second cavity in the direction of the substrate surface and the projection of the first cavity in the direction of the substrate surface; An annular groove is provided in the cover substrate, the second sealing ring is located in the annular groove, and solder is filled between the outer periphery of the second sealing ring and the annular groove; The depth of the annular groove is greater than the height of the second sealing ring.

13. The wafer-level package structure of the sensor according to claim 12, wherein The soldering aid layer is located in the annular groove.

14. The wafer-level package structure of the sensor according to claim 12, wherein, The material of the first sealing ring and / or the second sealing ring includes one or a combination of a metal material, a dielectric material, and a polymer.

15. The wafer-level packaging structure of the sensor according to claim 12, characterized in that, The material of the cover substrate includes a semiconductor.

16. The wafer-level packaging structure of the sensor according to claim 12, wherein The sensitive unit includes a first thermoelectric strip and a second thermoelectric strip connected to each other, and the first thermoelectric strip and the second thermoelectric strip are stacked or arranged side by side.

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