Conduction Time Timing Circuit of Polyphase Power Supply and Polyphase Power Supply

Abstract

Embodiments of the present invention relate to the field of electronic technologies, and disclose a conduction time timing circuit for a multi-phase power supply and a multi-phase power supply. The conduction time timing circuit for the multi-phase power supply includes: a timing circuit and a regulation circuit; the timing circuit is configured to start timing after receiving a power conduction trigger signal sent by a control loop, and output a conduction time end signal when the accumulated time reaches a preset duration; the regulation circuit is configured to reduce the preset duration according to a pre-stored attenuation factor when the control loop enters a saturation state. This solution can meet the requirements of a wide range of operating frequencies without occupying too many register resources, and at the same time solve the over-compensation problem caused by the saturation of the control loop in the multi-phase power supply system.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a conduction time timing circuit for a multi-phase power supply and a multi-phase power supply. Background Art

[0002] Currently, the performance of Intel microprocessors (CPUs) is getting better and better, and the computing processing speed is getting faster and faster. However, the rate of change and magnitude of the current required during their operation have also increased simultaneously. This poses more stringent requirements and challenges to the power management platform that supplies power to the microprocessor, such as a voltage regulator module (VRM) that can control the output of a multi-phase power supply, also known as a "VRM multi-phase power supply". That is, regardless of the operating state of the microprocessor, the power supply system needs to provide appropriate voltage and current to meet the requirements of the microprocessor's operation. Among them, when the frequency of sudden changes in the load current is in a relatively high frequency band, such as 200KHz to 250KHz, it is very easy to cause overshoot in the power supply system, resulting in the output voltage being too high and exceeding the specification range of the CPU.

[0003] Currently, the conventional solution to the problem of excessive voltage bounce caused by overshoot in the power supply system is to increase the blank time between the conduction of each phase in the VRM multi-phase power supply. As Figure 1 shown, the VRM multi-phase power supply usually has multiple parallel outputs, and these outputs all output a specified working current through pulse width modulation (PWM). Taking 4 outputs as an example: in the steady state, the current amplitudes of the 4-phase outputs are the same, and they work alternately in turn ( Figure 1 in

[0004] When there is a transient change in the load current, especially when the magnitude of the instantaneous increase in the load current is very large, the internal control loop will enter saturation, and it is required that each phase output respond to this sudden change at the fastest speed, manifested as the PWM currents of each phase output working at a high level almost simultaneously. This reaction does not pose too much of a problem when the load change frequency is relatively low, such as 30 Hz. However, when the load change frequency switches to 200 KHz, since the PWM currents of each phase output are simultaneously high and the load changes from large to small very quickly, too much energy will impact the output capacitor of the power supply, causing the output voltage to bounce to a very high level. This phenomenon is called overcompensation. To prevent this overcompensation phenomenon, the existing technical solution is to insert a fixed minimum interval conduction time (tblank) for each phase. Even when the control loop is saturated, a time interval of tblank duration is maintained before allowing the next phase to conduct, so as to prevent too much energy from reaching the output end and causing the voltage to bounce too high.

[0005] However, the VRM supports a very wide operating frequency range, which can be from 200 KHz to 5 MHz. The required interval time tblank is different for different operating frequencies. Generally, the lower the frequency, the longer the required interval time tblank, and the higher the frequency, the shorter the required interval time tblank. The interval time tblank is set through the registers inside the power supply system. To support the interval time tblank for a wide range of operating frequencies, relatively more register resources are occupied. Summary of the Invention

[0006] The purpose of the embodiment of the present invention is to provide a conduction time timing circuit and a multi-phase power supply for a multi-phase power supply, which can meet the requirements of a wide range of operating frequencies without occupying too many register resources, and at the same time solve the overcompensation problem caused by the saturation of the control loop in the multi-phase power supply system.

[0007] To solve the above technical problems, the embodiment of the present invention provides a conduction time timing circuit for a multi-phase power supply, including: a timing circuit and a regulation circuit;

[0008] The timing circuit is used to start timing after receiving a power conduction trigger signal sent by the control loop and output a conduction time end signal when the accumulated time reaches a preset duration;

[0009] The regulation circuit is used to reduce the preset duration according to a pre-stored attenuation factor when the control loop enters a saturation state.

[0010] The embodiment of the present invention also provides a multi-phase power supply, including: a control loop, and the conduction time timing circuit for the multi-phase power supply as described above;

[0011] The control loop is used to send a power-on trigger signal to the timing circuit in the on-time timing circuit of the multi-phase power supply according to the load operating frequency and operating current of the current multi-phase power supply, and the operating frequency is inversely proportional to the preset duration;

[0012] The on-time timing circuit of the multi-phase power supply is used to start timing after receiving the power-on trigger signal and output an on-time end signal when the accumulated time reaches the preset duration; and when the control loop enters the saturation state, the preset duration is reduced according to the pre-stored attenuation factor.

[0013] Compared with the prior art, the embodiment of the present invention sets an on-time timing circuit for a multi-phase power supply including a timing circuit and a regulation circuit. The timing circuit is used to start timing after receiving a power-on trigger signal sent by the control loop and output an on-time end signal when the accumulated time reaches the preset duration; the regulation circuit is used to shorten the preset duration according to the pre-stored attenuation factor when the control loop enters the saturation state to reduce the total output energy. In this solution, when the control loop enters the saturation state, by shortening the on-time of each phase of the power supply, the energy impacting the output capacitor of the power supply is effectively reduced, and the output voltage is prevented from bouncing to a very high level. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the figures in the drawings do not constitute a scale limitation.

[0015] Figure 1 is the output timing diagram of the multi-phase power supply in the prior art;

[0016] Figure 2 is the structure of the on-time timing circuit of the multi-phase power supply according to the embodiment of the present invention Figure 1 ;

[0017] Figure 3 is the structure of the on-time timing circuit of the multi-phase power supply according to the embodiment of the present invention Figure 2 ;

[0018] Figure 4 is the structure of the on-time timing circuit of the multi-phase power supply according to the embodiment of the present invention Figure 3 ;

[0019] Figure 5 is the structure of the on-time timing circuit of the multi-phase power supply according to the embodiment of the present invention Figure 4 。 DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, each embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that in each embodiment of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0021] One embodiment of the present invention relates to a multi-phase power supply on-time timing circuit, which can be applied to an existing multi-phase VRM power supply to control the power on time of each phase VRM power supply, such as Figure 2 As shown, the on-time timing circuit of the multi-phase power supply includes: a timing circuit 1 and a control circuit 2.

[0022] Among them, the timing circuit 1 is used to start timing after receiving the power-on trigger signal issued by the control loop (not shown in the figure) and output a conduction time end signal when the accumulated time reaches the preset duration; the control circuit 2 is used to shorten the preset duration according to the pre-stored attenuation factor when the control loop enters the saturation state.

[0023] Specifically, the function of the timing circuit 1 in this embodiment is to control the on-time of the PWM output power (voltage or current) of each phase in the multi-phase VRM power supply. That is, when each phase PWM changes to a high level based on the control loop to supply external power, the timing circuit 1 will also simultaneously receive the power on trigger signal issued by the control loop and start timing. When the accumulated time of the timing circuit 1 reaches a preset duration, it outputs an on-time end signal. After receiving the on-time end signal, the control loop controls the output of the current phase PWM to a low level and stops supplying external power. The specific circuit structure of the timing circuit 1 is not limited in this embodiment; in principle, any circuit structure that can achieve the above functions is acceptable.

[0024] The control loop controls the on / off switching of each phase of PWM based on the current load operating frequency and operating current (or operating voltage) of the power supply system, and enters a saturated state under specific operating conditions. The so-called saturated state of the control loop means that in order to cater to the transient changes in the large operating current (or operating voltage) at a certain high load operating frequency, the control loop controls each phase of PWM to respond to this sudden change as quickly as possible. This is manifested as the PWM output of each phase operating at a high level almost simultaneously. This reaction is not a big problem when the load change frequency is low, such as 30Hz. However, when the load change frequency switches to 200kHz, because each phase of PWM is simultaneously high and the load changes from large to small very quickly, excessive energy will impact the output capacitor, causing the output voltage to jump to a very high level, which can easily lead to unstable operating conditions or even collapse of the power supply.

[0025] As a way to solve this problem, in this embodiment, when the control loop enters the saturation state, the regulation circuit 2 can adjust the above-mentioned preset duration according to the attenuation factor pre-stored in the power supply system, so that it is reduced to a specified multiple of the original duration according to the preset attenuation factor. In this way, since the conduction time corresponding to each phase PWM being at a high level is shortened, the energy impacting the output capacitor is greatly reduced, thereby controlling the output voltage from bouncing to a very high level.

[0026] The advantage of adopting this method is that for the control architecture of the conventional conduction time timing circuit in the prior art, after the frequency is fixed, its PWM high-level time Ton is also fixed accordingly (the lower the load operating frequency, the longer the Ton time; the higher the load operating frequency, the shorter the Ton time). When it is detected that the control loop enters the saturation state, the Ton time can be immediately shortened by the regulation circuit 2, for example, to 0.75 times the original. In this way, the conduction time of each phase PWM is shortened, and the total output energy will ultimately become less, thus avoiding the problem of overcompensation.

[0027] The shortened conduction time (Ton_new) = the original conduction time (Ton) * attenuation factor.

[0028] In this embodiment, the original conduction time is the above-mentioned preset duration, and the shortened conduction time (Ton_new) is the duration obtained by reducing the preset duration according to the pre-stored attenuation factor.

[0029] It can be seen from the above formula that the shortened conduction time follows the original conduction time (by multiplying by an attenuation factor), and the original conduction time follows the operating frequency, so the shortened conduction time also follows the frequency, thus completing the "followability" of the operating frequency. That is, whether the operating frequency is 200KHz, 5MHz, or a higher frequency, only by multiplying by an attenuation factor. Theoretically, this attenuation factor only occupies one bit of the register, rather than requiring a relatively long register bit like setting tblank. This saves register resources.

[0030] Compared with the related art, in the embodiment of the present invention, by setting a conduction time timing circuit for a multi-phase power supply including a timing circuit and a regulation circuit, the timing circuit is used to start timing after receiving a power conduction trigger signal sent by the control loop and output a conduction time end signal when the accumulated time reaches the preset duration; the regulation circuit is used to shorten the preset duration according to the pre-stored attenuation factor when the control loop enters the saturation state, so as to reduce the total output energy. In this solution, when the control loop enters the saturation state, by shortening the conduction duration of each phase power supply, the energy impacting the output capacitor of the power supply is effectively reduced, and the output voltage is prevented from bouncing to a very high level.

[0031] Another embodiment of the present invention relates to a conduction time timing circuit for a multi-phase power supply. This conduction time timing circuit is an improvement on the Figure 2 conduction time timing circuit shown, and the improvement lies in: refining the timing circuit 1 and elaborating on the principle of reducing the preset duration of the regulation circuit 2.

[0032] Continuing to refer to Figure 2 , the timing circuit 1 may include: a comparator A, a first current mirror M1, a first capacitor C1, and a first switch S1; the inverting input terminal ("-") of the comparator A is connected to the first current mirror M1 and then connected to the power supply VCC; the circuit formed by the parallel connection of the first capacitor C1 and the first switch S1 is connected in series between the inverting input terminal of the comparator A and the ground GND; the non-inverting input terminal ("+") of the comparator A is connected to the reference voltage Vref; the output terminal of the comparator A is used to output a conduction time end signal (when Ton is at a high level, it is a conduction time start signal, and when Ton is at a low level, it is a conduction time end signal).

[0033] The working principle of the timing circuit 1 is as follows: when the power supply system is in a steady-state operation, after the control loop issues a power conduction trigger signal, the timing circuit 1 starts, and the first current mirror M1 starts to charge the first capacitor C1. During the charging process, the first switch S1 is disconnected; a ramp voltage is generated on the first capacitor C1. When the ramp voltage rises to Vref, the output of the comparator A flips from a high level to a low level, that is, the conduction time (Ton) end signal is output (the start signal is generated by the control loop). At the same time, S1 closes, discharging the voltage on the first capacitor C1 to 0V to clear it for the next cycle of charging. When the voltage on the first capacitor C1 is discharged to 0V, the first switch S1 is disconnected, and the timing circuit 1 stops working and waits for the next trigger to start. Assuming the current of the first current mirror M I is I1, the capacitance value of the first capacitor C1 is C1, and the reference voltage value is Vref, then Ton1 = Vref * C1 / I1 can be obtained.

[0034] It can be seen from this that the duration required for the above ramp voltage to rise to Vref is the power conduction duration of the power supply and is also the above preset duration. The key factors for shortening this duration are included in the charging process of the first current mirror M1 to the first capacitor C1. For example, by increasing the charging current of the first capacitor C1 (such as adding a charging current on the basis of the first current mirror M1), and / or reducing the charging capacitance corresponding to the first current mirror M1 (such as setting a controllable charging capacitance on the basis of the first capacitor C1), and / or reducing the reference voltage input to the non-inverting input terminal of the comparator A (such as attenuating Vref), the time required for the above ramp voltage to rise to Vref can be shortened, thereby controlling the comparator A to quickly flip and output the conduction time end signal, and thus shortening the power conduction duration.

[0035] The control circuit 2 in this embodiment is based on the various principles of shortening the power-on duration listed above. After being connected to the timing circuit 1, by controlling its own circuit, when the control loop enters the saturation state, it increases the charging current of the first capacitor C1, and / or reduces the charging capacitor corresponding to the first current mirror M1, and / or reduces the reference voltage input to the non-inverting input terminal of the comparator A, so as to reduce the preset duration, and the reduction multiple can be controlled based on the pre-stored attenuation factor.

[0036] It should be noted that the specific circuit structure of the control circuit 2 and its connection relationship with the timing circuit 1 in this embodiment are not limited. In principle, as long as it can start from at least one of the above principles to achieve shortening the power-on duration.

[0037] In this embodiment, the following specific structures of the control circuit 2 that can achieve shortening the power-on duration will be listed.

[0038] As Figure 3 shown, from the perspective of the principle of increasing the charging current of the first capacitor C1, the structure of the control circuit 2 will be described in detail. Specifically, the control circuit 2 may include: a second current mirror M2 and a second switch S2. The circuit after the second current mirror M2 and the second switch S2 are connected in series is connected in parallel with the first current mirror M1; the second switch S2 switches from open to closed when the control loop enters the saturation state, so as to control the charging of the first capacitor C1 from the first current mirror M1 to the charging of the first capacitor C1 by the first current mirror M1 and the second current mirror M2 together.

[0039] The specific working process is as follows: When the power supply system is in a steady-state operation, after the control loop issues a power-on trigger signal, the timing circuit 1 starts, and the first current mirror M1 starts to charge the first capacitor C1. During the charging process, both the first switch S1 and the second switch S2 are open; a ramp voltage is generated on the first capacitor C1. When the ramp voltage rises to Vref, the output of the comparator A flips from high level to low level, that is, an end signal of the conduction time (Ton) is output (the start signal is generated by the control loop). At the same time, S1 closes, discharging the voltage on the first capacitor C1 to 0V to clear 0 for the next cycle of charging. When the voltage on the first capacitor C1 is discharged to 0V, the first switch S1 opens, and the timing circuit 1 stops working and waits for the next trigger to start. Assuming the current of the first current mirror M1 is I1, the capacitance value of the first capacitor C1 is C1, and the reference voltage value is Vref, then Ton1 = Vref * C1 / I1 can be obtained.

[0040] When receiving the saturation signal of the control loop, the second switch S2 immediately closes, and the second current mirror M2 participates in the charging process of the first capacitor C1 together with the first current mirror M1. By setting the magnitude of the output current of the second current mirror M2, the degree of shortening of the power-on duration can be set.

[0041] For example, when the regulation circuit 2 only includes the second current mirror M2 and the second switch S2, the output current ratio of the first current mirror M1 to the second current mirror M2 is T1, and the corresponding attenuation factor is T1 / (T1 + 1).

[0042] Assume that the current magnitude of the second current mirror M2 is 1 / 3I1, that is, T1 = 3. Then it can be obtained that Ton2 = 0.75 * Ton1, thus completing the shortening of Ton with an attenuation factor of 3 / 4.

[0043] As Figure 4 shown, from the perspective of the principle of reducing the charging capacitance corresponding to the first current mirror M1, the structure of the regulation circuit 2 will be described in detail. Specifically, the regulation circuit 2 may include: a second capacitor C2 and a third switch S3. The circuit formed by the series connection of the second capacitor C2 and the third switch S3 is connected in parallel with the first capacitor C1; the third switch S3 switches from closed to open when the control loop enters the saturation state, so as to switch from controlling the first current mirror M1 to charge the first capacitor C1 and the second capacitor C2 to controlling the first current mirror M1 to only charge the first capacitor C1.

[0044] The specific working process is as follows: When the power supply system is in the steady-state operation, after the control loop issues a power-on trigger signal, the timing circuit 1 starts, and the first current mirror M1 starts to charge the first capacitor C1 and the second capacitor C2. During the charging process, the first switch S1 is disconnected and the third switch S3 is closed; a ramp voltage is generated on the first capacitor C1 and the second capacitor C2. When the ramp voltage rises to Vref, the output of the comparator A flips from high level to low level, that is, an end signal of the conduction time (Ton) is output (the start signal is generated by the control loop). At the same time, S1 is closed, and the voltages on the first capacitor C1 and the second capacitor C2 are discharged to 0V to clear 0 for the next cycle of charging. When the voltages on the first capacitor C1 and the second capacitor C2 are discharged to 0V, the first switch S1 is disconnected, and the timing circuit 1 stops working and waits for the next trigger to start. Assume that the current of the first current mirror M1 is I1, the capacitance value of the first capacitor C1 is C1, the capacitance value of the second capacitor C2 is C2, and the reference voltage value is Vref. Then it can be obtained that Ton3 = Vref * (C1 + C2) / I1.

[0045] When receiving the saturation signal of the control loop, the third switch S3 immediately disconnects, and the first current mirror M1 only charges the first capacitor C1. By setting the capacitance value of the second capacitor C2, the shortening degree of the power-on duration can be set.

[0046] For example, when the regulation circuit 2 only includes the second capacitor C2 and the third switch S3, the capacitance ratio of the first capacitor C1 to the second capacitor C2 is T2, and the corresponding attenuation factor is T2 / (T2 + 1).

[0047] Assume that the capacitance value C2 of the second capacitor C2 is 1 / 3C1, that is, T2 = 3, then Ton4 = 0.75 * Ton3 can be obtained, thus completing the shortening of Ton with a decay factor of 3 / 4.

[0048] As Figure 5 shown, from the perspective of the principle of reducing the reference voltage input to the non-inverting input terminal of comparator A, the structure of the regulation circuit 2 will be described in detail. Specifically, the regulation circuit 2 may include: a proportional attenuation unit X scale and a fourth switch S4. The circuit after the parallel connection of the proportional attenuation unit X scale and the fourth switch S4 is connected in series between the reference voltage Vref and the non-inverting input terminal of comparator A; the fourth switch S4 switches from closed to open when the control loop enters the saturation state, so as to switch from directly inputting the control reference voltage Vref to the non-inverting input terminal of comparator A to inputting the reference voltage Vref after being attenuated by the proportional attenuation unit Xscale to the non-inverting input terminal of comparator A.

[0049] The specific working process is as follows: When the power supply system is in the steady-state operation, after the control loop issues a power-on trigger signal, the timing circuit 1 starts, and the first current mirror M1 starts to charge the first capacitor C1. During the charging process, the first switch S1 is disconnected and the fourth switch S4 is closed; a ramp voltage is generated on the first capacitor C1. When the ramp voltage rises to Vref, the output of comparator A flips from high level to low level, that is, an end signal of the conduction time (Ton) is output (the start signal is generated by the control loop). At the same time, S1 is closed, and the voltage on the first capacitor C1 is discharged to 0V to clear 0 for the next cycle of charging. When the voltage on the first capacitor C1 is discharged to 0V, the first switch S1 is disconnected, and the timing circuit 1 stops working and waits for the next trigger to start. Assume that the current of the first current mirror M1 is I1, the capacitance value of the first capacitor C1 is C1, and the reference voltage value is Vref, then Ton1 = Vref * C1 / I1 can be obtained.

[0050] When receiving the saturation signal of the control loop, the fourth switch S4 immediately disconnects, and the reference voltage input to the non-inverting input terminal of comparator A changes from the original Vref to the Vref after being attenuated by the proportional attenuation unit X scale. By setting the size of the attenuation factor X of the proportional attenuation unit X scale, the shortening degree of the power-on duration can be set.

[0051] For example, when the regulation circuit 2 only includes the proportional attenuation unit X scale and the fourth switch S4, the voltage ratio of the reference voltage after being attenuated by the proportional attenuation unit Xscale to the original reference voltage is T3, and the corresponding attenuation factor is T3.

[0052] Assume that when the voltage ratio of the reference voltage after attenuation by the proportional attenuation unit X_scale to the original reference voltage is 3 / 4, i.e., T3 = 3 / 4, then it can be obtained that Ton5 = 0.75 * Ton1, thus completing the shortening of Ton with an attenuation factor of 3 / 4.

[0053] In addition, for the on-time timing circuit of the multi-phase power supply described in any of the above embodiments, the corresponding attenuation factor can be stored in the register of the power supply, and the storage space occupied has a length of 2 bits.

[0054] Moreover, for the three schemes of shortening the preset duration shown above, any 2 or all three of the schemes can be arbitrarily selected and combined for use.

[0055] Compared with the related art, in this embodiment, the timing circuit includes: a comparator, a first current mirror, a first capacitor, and a first switch; the reverse input terminal of the comparator is connected to the first current mirror and then connected to the power supply; the circuit formed by the parallel connection of the first capacitor and the first switch is connected in series between the reverse input terminal of the comparator and the ground; the non-inverting input terminal of the comparator is connected to the reference voltage; the output terminal of the comparator is used to output an on-time end signal; the regulation circuit is connected to the timing circuit, and when the control loop enters the saturation state, by increasing the charging current of the first capacitor, and / or reducing the charging capacitor corresponding to the first current mirror, and / or reducing the reference voltage input to the non-inverting input terminal of the comparator, to shorten the preset duration, thereby also giving a construction plan guidance for enriching the circuit structure of the regulation circuit.

[0056] Another embodiment of the present invention relates to a multi-phase power supply, which can be a multi-phase VRM power supply. The multi-phase power supply includes: a control loop, and the on-time timing circuit of the multi-phase power supply described in any of the above embodiments;

[0057] Among them, the control loop is used to send a power-on trigger signal to the on-time timing circuit of the multi-phase power supply according to the load operating frequency and operating current of the current multi-phase power supply, and the operating frequency is inversely proportional to the preset duration;

[0058] The on-time timing circuit of the multi-phase power supply is used to start timing after receiving the power-on trigger signal and output an on-time end signal when the accumulated time reaches the preset duration; and when the control loop enters the saturation state, it shortens the preset duration according to the pre-stored attenuation factor.

[0059] Specifically, in this embodiment, for the specific structure and working principle of the control loop and the on-time timing circuit of the multi-phase power supply, reference can be made to the corresponding embodiments of the on-time timing circuit of the multi-phase power supply above, and details will not be elaborated here.

[0060] In this embodiment, the multi-phase power supply replaces the method in the prior art of preventing over-compensation of the multi-phase output power supply by increasing the blanking time tblank, reduces the occupation of register resources, and saves storage resources.

[0061] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention.

Claims

1. A conduction time timing circuit for a multiphase power supply, characterized in that, Comprising: A timing circuit and a regulation circuit; The timing circuit is configured to start timing after receiving a power-on trigger signal sent by a control loop, and output a conduction time end signal when the accumulated time reaches a preset duration; The regulation circuit is configured to reduce the preset duration according to a pre-stored attenuation factor when the control loop enters a saturation state; Wherein, the preset duration is the conduction time of the output power of each phase in the multi-phase power supply, and the control loop entering the saturation state means that the control loop caters to the transient change of the working current or working voltage at a high load working frequency; The timing circuit includes: a comparator, a first current mirror, a first capacitor, and a first switch; the reverse input terminal of the comparator is connected to the first current mirror and then connected to a power supply; the circuit formed by the parallel connection of the first capacitor and the first switch is connected in series between the reverse input terminal of the comparator A and the ground; the non-inverting input terminal of the comparator is connected to a reference voltage; the output terminal of the comparator is configured to output the conduction time end signal; The regulation circuit is connected to the timing circuit, and is configured to increase the charging current of the first capacitor, and / or reduce the charging capacitor corresponding to the first current mirror, and / or reduce the reference voltage input to the non-inverting input terminal of the comparator when the control loop enters a saturation state, so as to reduce the preset duration.

2. The conduction time timing circuit of the polyphase power supply according to claim 1, wherein The regulation circuit includes: a second current mirror and a second switch, and the circuit formed by the series connection of the second current mirror and the second switch is connected in parallel with the first current mirror; The second switch switches from an open state to a closed state when the control loop enters a saturation state, so as to control the charging of the first capacitor from the first current mirror to the charging of the first capacitor by the first current mirror and the second current mirror together.

3. The conduction time timing circuit of the polyphase power supply according to claim 2, wherein When the regulation circuit only includes the second current mirror and the second switch, the output current ratio of the first current mirror to the second current mirror is T1, and the corresponding attenuation factor is T1 / (T1 + 1).

4. The conduction time timing circuit of the polyphase power supply according to claim 1, wherein The regulation circuit includes: a second capacitor and a third switch, and the circuit formed by the series connection of the second capacitor and the third switch is connected in parallel with the first capacitor; The third switch switches from a closed state to an open state when the control loop enters a saturation state, so as to control the charging of the first capacitor and the second capacitor by the first current mirror to the charging of only the first capacitor by the first current mirror.

5. The conduction time timing circuit of the polyphase power supply according to claim 4, characterized in that, When the regulation circuit only includes the second capacitor and the third switch, the capacitance ratio of the first capacitor to the second capacitor is T2, and the corresponding attenuation factor is T2 / (T2 + 1).

6. The conduction time timing circuit of the polyphase power supply according to claim 1, wherein The regulation circuit includes: a proportional attenuation unit and a fourth switch, and the circuit formed by the parallel connection of the proportional attenuation unit and the fourth switch is connected in series between the reference voltage and the non-inverting input terminal of the comparator; The fourth switch switches from a closed state to an open state when the control loop enters a saturation state, so as to control the direct input of the reference voltage to the non-inverting input terminal of the comparator to the input of the reference voltage to the non-inverting input terminal of the comparator after being attenuated by the proportional attenuation unit.

7. The turn-on time timing circuit of the polyphase power supply according to claim 6, wherein When the regulation circuit only includes the proportional attenuation unit and the fourth switch, the voltage ratio of the reference voltage after attenuation by the proportional attenuation unit to the original reference voltage is T3, and the corresponding attenuation factor is T3.

8. The conduction time timing circuit of the polyphase power supply according to any one of claims 1-7, characterized in that, The attenuation factor is stored in the register of the power supply, and the occupied storage space length is 2 bits.

9. A polyphase power supply, characterized in that, Comprising: a control loop, and a conduction time timing circuit of the multi-phase power supply as described in any one of claims 1-8; The control loop is configured to send a power conduction trigger signal to the conduction time timing circuit of the multi-phase power supply according to the load operating frequency and operating current of the current multi-phase power supply, and the operating frequency is inversely proportional to a preset duration; The conduction time timing circuit of the multi-phase power supply is configured to start timing after receiving the power conduction trigger signal and output a conduction time end signal when the accumulated time reaches the preset duration; and when the control loop enters a saturation state, reduce the preset duration according to the pre-stored attenuation factor.

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