Power conversion device, abnormality detection method for power conversion device, abnormality detection method for power transmission unit

Abstract

Provided is a power conversion device, an abnormality detection method for a power conversion device, and an abnormality detection method for a power transmission unit, which appropriately detect an abnormality of a current detector even if a 3-phase load is unbalanced or contains a current pulsation component. The power conversion device has any one of a converter, an inverter, and an AC converter, and has: a plurality of current detectors that detect currents of a plurality of phases flowing between a power source and the power conversion device or between the power conversion device and a load device; an abnormality determiner that determines an abnormality of the plurality of current detectors, the abnormality determiner having: a summer that calculates a sum of current detection values of the plurality of phases detected by the plurality of current detectors; a plurality of multipliers that respectively calculate products of the current detection value of each phase and an output of the summer; a plurality of filters that have a function of reducing or removing a harmonic component of the outputs of the plurality of multipliers; and an abnormality determination section that determines an abnormality of the current detector based on the outputs of the plurality of filters, respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to a power conversion device, an abnormality detection method for a power conversion device, and an abnormality detection method for a power transmission unit. BACKGROUND

[0002] A power conversion device that converts power of an alternating-current power source into power of variable voltage and variable frequency is known. In the power conversion device, a current detector that detects a current flowing between a power source and the power conversion device is provided, and control is performed so that the current becomes a predetermined value. In addition, a current detector that detects a current flowing between the power conversion device and a load device is provided, and control is performed so that the current becomes a predetermined value.

[0003] For example, as a technique for confirming the soundness of a current detector that detects a current flowing between a power converter and a motor, a method is known in which currents of respective phases are detected, and the current effective values of the respective phases are compared with the current effective values of the other phases, thereby determining a phase in which an abnormality has occurred (for example, refer to Patent Literature 1).

[0004] In addition, a method is known in which it is first determined whether the sum of the 3-phase current detection values is zero, and in the case where the sum of the 3-phase currents is not zero in the determination result, a phase in which a current detector abnormality has occurred is determined by current value comparison or sign determination of the respective phases (for example, refer to Patent Literature 2, Patent Literature 3).

[0005] In addition, a method is known in which, in the case where a current detector abnormality of one phase is determined, operation is switched to using a current estimation value estimated from the current detection values of the other phases instead of the current detection value of the phase determined to be abnormal (for example, refer to Patent Literature 1, Patent Literature 2, Patent Literature 3).

[0006] The current detector that detects a current flowing between a power converter and a motor, and the current detector that detects a current flowing between a power converter and a power source are necessary in order to control the current of the power conversion device, and a current detector abnormality can cause instability of the system operation, and in the worst case, can cause an unexpected stop of the system, and can cause a large damage.

[0007] The technique of Patent Literature 1 can determine a phase in which an abnormality has occurred in the case where a balanced 3-phase load is connected, but in the case where the 3-phase load is unbalanced, a large current flows in a phase in which the load is small, and thus the 3-phase current effective values are not consistent, and thus there is a problem in which a current detector abnormality can be erroneously detected in the case where the current detector is normal or abnormal.

[0008] In addition, in the technologies of Patent Literature 2 and Patent Literature 3, in a case where the current ripple of a size that cannot be ignored compared to the size of the fundamental wave component of the current waveform is included in the current waveform, it is possible that the current detector abnormality is erroneously detected due to the current ripple.

[0009] In order to avoid erroneous detection of the current detector abnormality, a filter having a characteristic of removing only the current ripple component without removing the current fundamental wave component is required, but in a case where the frequency of the current ripple is close to the fundamental wave frequency of the current waveform, there is a problem that it is difficult to remove only the current ripple by the filter.

[0010] As described above, in the methods of Patent Literature 1, Patent Literature 2, and Patent Literature 3, the imbalance of the 3-phase load or the current ripple included in the current waveform can cause erroneous detection of the current detector abnormality or a decrease in the abnormality determination accuracy, and thus the abnormality of the current detector cannot be properly detected.

[0011] In particular, in a case where the current detector abnormality is erroneously detected, there is a problem that, instead of the normal current detection value determined to be abnormal, a current estimation value estimated from the current detection value of the other phase including the abnormal current detection value is used for the operation, which causes further instability of the system operation, and in the worst case, causes unexpected stop of the system, and can cause great damage.

[0012] Patent Literature 1: Japanese Patent No. 3737370

[0013] Patent Literature 2: Japanese Patent Application Laid-Open No. 2005-94912

[0014] Patent Literature 3: Japanese Patent Application Laid-Open No. 2006-50702 SUMMARY

[0015] The present application has been achieved in view of the above-described circumstances, and an object thereof is to provide a power conversion device capable of properly detecting a current detector abnormality even in a case where a 3-phase load imbalance or a current ripple component is included.

[0016] In order to solve the above-described object, the present application is configured as follows.

[0017] That is, the power conversion device of the present application, which has at least any one of a converter that converts alternating current into direct current, an inverter that converts direct current into alternating current, and an AC converter that converts alternating current into alternating current, has: a plurality of current detectors that detect currents of a plurality of phases flowing between a power source and the power conversion device or between the power conversion device and a load device; and an abnormality determiner that determines an abnormality of the plurality of current detectors, the abnormality determiner having: a summer that calculates a sum of current detection values of the plurality of phases detected by the plurality of current detectors; a plurality of multipliers that respectively calculate products of the current detection value of each of the plurality of phases and an output of the summer; a plurality of filters that have a function of reducing or removing harmonic components in the respective outputs of the plurality of multipliers; and an abnormality determination section that determines an abnormality of the current detectors based on the respective outputs of the plurality of filters.

[0018] Further, other means are described in the embodiments for carrying out the invention.

[0019] According to the present application, it is possible to provide a power conversion device that can appropriately detect a current detector abnormality even in a case where a 3-phase load connected to the power conversion device is unbalanced or a case where a large current pulsation component is included in an alternating current. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A circuit structure example of a power conversion device of the first embodiment of the present application, and a connection structure example with an alternating current power source and a motor.

[0021] Figure 2A and Figure 2B A circuit structure example of a converter-side abnormality determiner and an inverter-side abnormality determiner of the power conversion device of the first embodiment of the present application.

[0022] Figure 3 An example of a flowchart of an abnormality determination process performed by an abnormality determination section of the inverter-side abnormality determiner of the first embodiment of the present application.

[0023] Figure 4 An example of a current waveform of current detection values when all of the current detectors are normal and a 3-phase load of a motor is balanced, and an example of a summer output, a multiplier output, and a filter output of the inverter-side abnormality determiner.

[0024] Figure 5 An example of a current waveform of current detection values when a current detector of a U phase is abnormal (G U = 125%) and a 3-phase load of a motor is balanced, and an example of a summer output, a multiplier output, and a filter output of the inverter-side abnormality determiner.

[0025] Figure 6 This indicates an abnormality in the current detector of phase U (G). U Examples of current waveforms of the current detection value when the three-phase load of the motor is balanced (75%), and the adder output, multiplier output, and filter output of the inverter-side fault detector.

[0026] Figure 7 Examples of current waveforms representing the current detection values ​​when all current detectors are normal and the three-phase load of the motor is unbalanced, as well as the adder output, multiplier output, and filter output of the inverter-side fault detector.

[0027] Figure 8 This indicates an abnormality in the current detector of phase V (G). V Examples of current waveforms of the current detection value when the 3-phase load of the motor is unbalanced (=110%), and examples of adder output, multiplier output, and filter output of the inverter-side fault detector.

[0028] Figure 9 This indicates an abnormality in the current detector of phase V (G). V =110%), the three-phase load of the motor is unbalanced, and the current waveform of the fundamental current waveform contains the current detection value when the current pulsates, as well as the adder output, multiplier output and filter output of the inverter side abnormal judgment unit.

[0029] Figure 10 An example flowchart illustrating the abnormality judgment process performed by the abnormality judgment unit of the inverter-side abnormality judgment unit in a modified example of the first embodiment of the present invention.

[0030] Figure 11 An example flowchart illustrating the abnormal judgment process performed by the abnormal judgment unit of the inverter-side abnormal judgment device according to the second embodiment of the present invention.

[0031] Figure 12 This illustrates a circuit structure example of the converter-side fault detector in Modification 1 of the second embodiment of the present invention.

[0032] Figure 13 This illustrates a circuit structure example of an inverter-side fault detector in Modification 1 of the second embodiment of the present invention.

[0033] Figure 14 This illustrates a circuit structure example of the converter-side fault detector in Modification 2 of the second embodiment of the present invention.

[0034] Figure 15 This illustrates a circuit structure example of an inverter-side fault detector in Modification 2 of the second embodiment of the present invention.

[0035] Figure 16 A circuit configuration example of a converter-side abnormality determiner and an inverter-side abnormality determiner of the power conversion device of the third embodiment of the present application.

[0036] Figure 17 A calculation example of a current waveform by a filter and an adder / subtracter in the inverter-side abnormality determiner of the power conversion device of the third embodiment of the present application.

[0037] Figure 18 A circuit configuration example of the power conversion device of the fourth embodiment of the present application, and a connection structure example with an alternating current power supply and a motor.

[0038] Figure 19 A circuit configuration example of the power conversion device of the fifth embodiment of the present application, and a connection structure example with an alternating current power supply and a motor.

[0039] Figure 20 A circuit configuration example of a part including a converter-side output estimator of the power conversion device of the fifth embodiment of the present application.

[0040] Figure 21 An example of an abnormality determination method of a three-phase alternating current wiring not via a power converter.

[0041] Figure 22 A circuit configuration example of a three-shunt method in which a shunt resistor is provided on the direct current power supply side of an inverter unit in a power conversion device as a current detector. DETAILED DESCRIPTION

[0042] Hereinafter, modes for carrying out the present application (hereinafter, referred to as "embodiments") will be described with appropriate reference to the accompanying drawings.

[0043] The embodiments described below are not intended to limit the scope of the application dealt with in the scope of the claims, and furthermore, each element and all combinations thereof described in the embodiments are not necessarily essential to the means for solving the invention.

[0044] <1st Embodiment: Power Conversion Device>

[0045] Reference Signs Figures 1-9 A power conversion device of the first embodiment of the present application will be described.

[0046] The following description not only describes a power conversion device, but also describes an abnormality detection method of a power conversion device.

[0047] Circuit Configuration of Power Conversion Device, and Connection Structure with Alternating Current Power Supply and Motor

[0048] Figure 1A circuit configuration example of the power conversion device 100 of the first embodiment of the present application, and a connection structure example with the alternating current power source 1, the motor 4.

[0049] In Figure 1 The power conversion device 100 is configured to include the converter unit 2, the inverter unit 3, the converter control device 5, and the inverter control device 6.

[0050] In addition, the power conversion device 100 includes a converter-side abnormality determiner 71, an inverter-side abnormality determiner 72, and a display 73.

[0051] The power conversion device 100 inputs alternating current power from the alternating current power source 1, and outputs converted alternating current power to the motor 4 via the converter unit 2 and the inverter unit 3. The power conversion device 100 includes a speed detector 7 that detects the speed of the motor 4 and outputs the same.

[0052] The converter unit (also referred to as a converter) 2 inputs alternating current power from the alternating current power source 1, and converts the same to direct current power.

[0053] The inverter unit (also referred to as an inverter) 3 converts the direct current power output from the converter unit 2 to alternating current power of a desired voltage and frequency. The motor 4 is driven using the converted alternating current power.

[0054] The converter control device 5 controls the converter unit 2.

[0055] The inverter control device 6 controls the inverter unit 3.

[0056] Converter Unit 2

[0057] The converter unit 2 is configured to include three converter power conversion sections 21 (first to third converter power conversion sections 21), a P wiring 40, a C wiring 41, an N wiring 42, a converter P-side smoothing capacitor 22 (smoothing capacitor), a converter N-side smoothing capacitor 23 (smoothing capacitor), a converter P-side direct current voltage detector 24, a converter N-side direct current voltage detector 25, an R-phase current detector 26, an S-phase current detector 27, and a T-phase current detector 28.

[0058] The converter unit 2 is a so-called 3-level converter that converts alternating current power input to the converter power conversion sections 21 to direct current power of a positive potential (first potential) level, a neutral point (zero) potential (second potential) level, and a negative potential (third potential) level.

[0059] The positive potential level is connected via the P wiring 40, the neutral point potential level is connected via the C wiring 41, and the negative potential level is connected via the N wiring 42.

[0060] Further, the converter P-side smoothing capacitor 22 suppresses variation in the direct current voltage between the P-wire 40 and the C-wire 41. The converter N-side smoothing capacitor 23 suppresses variation in the direct current voltage between the C-wire 41 and the N-wire 42.

[0061] The converter P-side direct current voltage detector 24 measures the voltage between the terminals of the converter P-side smoothing capacitor 22. The converter N-side direct current voltage detector 25 measures the voltage between the terminals of the converter N-side smoothing capacitor 23.

[0062] The converter power conversion section 21 is composed of four transistors and six diodes, and the transistors are composed of IGBTs (Insulated Gate Bipolar Transistors).

[0063] Four transistors (first to fourth transistors) are connected in series between the P-wire 40 and the N-wire 42. Inverse-parallel diodes (first to fourth diodes) are connected to the first to fourth transistors, respectively.

[0064] The collector of the first transistor is connected to the P-wire 40.

[0065] The emitter of the fourth transistor is connected to the N-wire 42.

[0066] The fifth diode and the sixth diode are connected in series, the cathode of the fifth diode is connected to the connection point of the first transistor and the second transistor, and the anode of the sixth diode is connected to the connection point of the third transistor and the fourth transistor.

[0067] The connection point of the anode of the fifth diode and the cathode of the sixth diode is connected to the C-wire 41.

[0068] When there are parasitic diodes built in the first to fourth transistors, the above-mentioned inverse-parallel diodes (first to fourth diodes) can also function as the parasitic diodes.

[0069] In the Figure 1 , for convenience of description, only one of the converter power conversion sections 21 is described, but actually, three converter power conversion sections (first to third converter power conversion sections 21) corresponding to the R-phase, the S-phase, and the T-phase of the three-phase alternating current are provided.

[0070] In the Figure 1 , the power line of the S-phase is connected to the connection point of the second transistor and the third transistor of the converter power conversion section 21 (the second converter power conversion section 21), and the power of the S-phase is input to the converter power conversion section 21 (the second converter power conversion section 21).

[0071] Further, although in the Figure 1The power line of the R phase is connected to the connection points of the second transistor and the third transistor of the converter power conversion section 21 (the first converter power conversion section 21) and inputs the power of the R phase to the converter power conversion section 21 (the first converter power conversion section 21), although not directly shown in FIG. 1.

[0072] In addition, although not directly shown in FIG. 1, the power line of the S phase is connected to the connection points of the second transistor and the third transistor of the converter power conversion section 22 (the second converter power conversion section 22) and inputs the power of the S phase to the converter power conversion section 22 (the second converter power conversion section 22). Figure 1 In addition, although not directly shown in FIG. 1, the power line of the T phase is connected to the connection points of the second transistor and the third transistor of the converter power conversion section 21 (the third converter power conversion section 21) and inputs the power of the T phase to the converter power conversion section 21 (the third converter power conversion section 21).

[0073] However, the power lines of the direct current of the first to third converter power conversion sections 21, that is, the P line 40, the C line 41, and the N line 42 are shared among the first to third converter power conversion sections 21.

[0074] The R phase, the S phase, and the T phase of the three-phase alternating current are respectively input to the three converter power conversion sections 21 (the first to third converter power conversion sections 21), but are shared on the side of the direct current power converted by the converter power conversion sections 21. That is, the three-phase alternating current power (voltage) of the R phase, the S phase, and the T phase is converted into one direct current power (voltage).

[0075] In addition, the first to third converter power conversion sections 21 are collectively controlled by the converter control device 5.

[0076] As described above, the R-phase current detector 26 (current detector, current detection unit), the S-phase current detector 27 (current detector, current detection unit), and the T-phase current detector 28 (current detector, current detection unit) are provided in the converter unit 2 and respectively detect the currents flowing in the R phase, the S phase, and the T phase of the three-phase alternating current.

[0077] The signals (output signals) of the current detection values detected by the current detectors 26, 27, and 28 are input to the converter-side abnormality determiner 71 (abnormality determiner) and the converter control device 5.

[0078] In addition, the signals (output signals) of the voltage detection values detected by the direct current voltage detectors 24 and 25 are input to the converter control device 5.

[0079] "Inverter Unit 3"

[0080] In Figure 1In the present embodiment, the inverter unit 3 is configured to include three inverter power conversion sections 31 (first to third inverter power conversion sections 31), a P-wire 40, a C-wire 41, an N-wire 42, an inverter P-side smoothing capacitor 32 (smoothing capacitor), an inverter N-side smoothing capacitor 33 (smoothing capacitor), a U-phase current detector 34 (current detector, current detection unit), a V-phase current detector 35 (current detector, current detection unit), and a W-phase current detector 36 (current detector, current detection unit).

[0081] The inverter unit 3 is a so-called 3-level inverter that converts direct-current power of positive potential (first potential) level, neutral point (zero) potential (second potential) level, and negative potential (third potential) level into alternating-current power for the motor 4.

[0082] The positive potential levels of the inverter unit 3 and the converter unit 2 are connected by the P-wire 40, the neutral point potential levels are connected by the C-wire 41, and the negative potential levels are connected by the N-wire 42.

[0083] The inverter power conversion section 31 is configured by four transistors and six diodes, and the transistors are configured by IGBTs.

[0084] The configuration of the inverter power conversion section 31, which is configured by four transistors and six diodes, is substantially the same as the configuration of the converter power conversion section 21, which is configured by four transistors and six diodes. Repetitive descriptions are omitted.

[0085] The three converter power conversion sections 21 generate direct-current power (voltage) from three-phase alternating-current power (voltage), and, in contrast, the three inverter power conversion sections 31 generate three-phase (U-phase, V-phase, and W-phase) alternating-current power (voltage) from direct-current power (voltage).

[0086] The three-phase alternating-current power (voltage) of the R-phase, S-phase, and T-phase is different in voltage and frequency from the three-phase alternating-current power (voltage) of the U-phase, V-phase, and W-phase.

[0087] In addition, the three inverter power conversion sections 31 are collectively controlled by the inverter control device 6.

[0088] As described above, the inverter unit 3 includes the U-phase current detector 34, the V-phase current detector 35, and the W-phase current detector 36, which respectively detect currents flowing through the U-phase, V-phase, and W-phase of the three-phase alternating current.

[0089] The signals (output signals) of the current detection values detected by the current detectors 34, 35, and 36 are input to the inverter-side abnormality determiner 72 (abnormality determiner) and the inverter control device 6.

[0090] The outputs of the three inverter power conversion sections 31 are output as the output of the power conversion device 100.

[0091] The output of the power conversion device 100 is directly linked to the motor 4 as a three-phase motor.

[0092] Converter control device 5

[0093] In Figure 1 The converter control device 5 is configured to include a direct current voltage command generator 51, a direct current voltage controller 52, a current controller 53, and a pulse generator 54.

[0094] The direct current voltage command generator 51 generates a direct current voltage command value indicating the voltage value of the direct current voltage output from the converter unit 2, and outputs it to the direct current voltage controller 52.

[0095] The direct current voltage controller 52 is inputted with the voltage between the terminals of the converter P-side smoothing capacitor 22 and the voltage between the terminals of the converter N-side smoothing capacitor 23 detected by the direct current voltage detectors 24, 25.

[0096] The direct current voltage controller 52 calculates a converter output current command value based on the direct current voltage command value inputted from the direct current voltage command generator 51 and the detected values of the direct current voltages inputted from the direct current voltage detectors 24, 25, and outputs it to the current controller 53.

[0097] Specifically, the direct current voltage controller 52 calculates the converter output current command value so that the sum of the detected values of the direct current voltages inputted from the direct current voltage detectors 24, 25 respectively coincides with the direct current voltage command value.

[0098] The current controller 53 calculates a converter voltage command value and outputs it to the pulse generator 54 so that the current detected value (converter output current detected value) corresponding to the converter output current outputted from the current detectors 26, 27, 28 for detecting the input current of the three-phase alternating current coincides with the converter output current command value inputted from the direct current voltage controller 52.

[0099] The pulse generator 54 calculates a pulse signal for on / off control of each switching element of the converter power conversion section 21, and outputs the pulse signal to the converter power conversion section 21 so that the output voltage of the converter power conversion section 21 coincides with the converter output voltage command value inputted from the current controller 53.

[0100] That is, the converter control device 5 performs the above-described various calculation processes in the converter unit 2 so that the direct current power converted from the alternating current power becomes a desired value, and outputs a signal for controlling the converter power conversion section 21.

[0101] Inverter control device 6

[0102] In Figure 1 In this embodiment, the inverter control device 6 is configured to include a speed command generator 61, a speed controller 62, a current controller 63, and a pulse generator 64.

[0103] The speed command generator 61 outputs a speed command value for indicating a speed at which the motor 4 is to be operated to the speed controller 62.

[0104] The speed detector 7 detects a speed of the motor 4 and outputs the speed detection value to the speed controller 62.

[0105] The speed controller 62 calculates an inverter output current command value and outputs the inverter output current command value to the current controller 63 so that the speed detection value input from the speed detector 7 attached to the motor 4 coincides with the speed command value input from the speed command generator 61.

[0106] The current controller 63 calculates an inverter voltage command value and outputs the inverter voltage command value to the pulse generator 64 so that the inverter output current detection value input from the current detectors 34, 35, and 36 for detecting the output current of the 3-phase alternating current coincides with the inverter output current command value input from the speed controller 62.

[0107] The pulse generator 64 calculates a pulse signal for on / off control of each switching element of the inverter power conversion section 31 and outputs the pulse signal to the inverter power conversion section 31 so that the output voltage of the inverter power conversion section 31 coincides with the inverter output voltage command value input from the current controller 63.

[0108] The inverter control device 6 controls the inverter power conversion section 31 in the inverter unit 3 so that the output torque and the speed of the motor 4 satisfy a desired characteristic.

[0109] Structure related to abnormality determination in power conversion device 100

[0110] Next, a structure related to abnormality determination in the power conversion device 100 will be described.

[0111] In Figure 1 In this embodiment, the power conversion device 100 includes a converter-side abnormality determiner 71, an inverter-side abnormality determiner 72, and a display 73.

[0112] Converter-side abnormality determiner 71

[0113] The converter-side abnormality determiner 71 calculates the sum of the current values (detection values) input from the current detectors 26, 27, 28 of the three-phase AC of the R phase, the S phase, and the T phase and the product of the current detection values of the respective phases. Then, based on the filter output after removing the AC component contained in the calculated product, it determines whether the current detectors 26, 27, 28 are abnormal via the abnormality determination section 714 of the converter-side abnormality determiner 71. Figure 2A

[0114] The output signal of the converter-side abnormality determiner 71 is input to the display 73.

[0115] The detailed structure of the converter-side abnormality determiner 71 will be described later.

[0116] 《Inverter-side Abnormality Determiner 72》

[0117] The inverter-side abnormality determiner 72 calculates the sum of the current values (detection values) input from the current detectors 34, 35, 36 of the three-phase AC of the U phase, the V phase, and the W phase and the product of the current detection values of the respective phases. Then, based on the filter output after removing the AC component contained in the calculated product, it determines whether the current detectors 34, 35, 36 are abnormal via the abnormality determination section 724 of the inverter-side abnormality determiner 72. Figure 2B

[0118] The output signal of the inverter-side abnormality determiner 72 is input to the display 73.

[0119] The detailed structure of the inverter-side abnormality determiner 72 will be described later.

[0120] 《Display 73》

[0121] The display 73 is, for example, a display device such as a liquid crystal display that can display information, and displays information of the converter-side abnormality determiner 71 and the inverter-side abnormality determiner 72 and other various information.

[0122] <About Abnormality Determination by Abnormality Determiners 71, 72>

[0123] Next, the abnormality determination by the abnormality determiners (the converter-side abnormality determiner 71 and the inverter-side abnormality determiner 72) of the first embodiment will be described in detail.

[0124] Figure 2A 、 Figure 2B The circuit structure example of the converter-side abnormality determiner 71 and the inverter-side abnormality determiner 72 of the power conversion device 100 of the first embodiment of the present application is shown.

[0125] Figure 2A The drawing shown is the converter-side abnormality determiner 71,​​ Figure 2B The illustrated diagram is the inverter-side abnormality determiner 72.

[0126] Figure 2A The illustrated converter-side abnormality determiner 71 is composed of an adder (addition unit) 711, three multipliers (multiplication units) 712 (712R, 712S, 712T), three filters (filter units) 713 (713R, 713S, 713T), and an abnormality determination section (abnormality determination unit) 714.

[0127] The detection currents I R , I S , and I T detected by the current detectors 26, 27, and 28 Figure 1 are input to the adder 711 and to the first input terminals of the multipliers 712R, 712S, and 712T, respectively. R S T

[0128] The current I C0 (= I R + I S + I T ) obtained by the addition operation by the adder 711 is input to the second input terminals of the multipliers 712R, 712S, and 712T, respectively. C0 R S T

[0129] The outputs D R , D S , and D T of the products obtained by the multiplication operations by the multipliers 712R, 712S, and 712T, respectively, are input to the filters 713R, 713S, and 713T, respectively. R S T

[0130] In the filters 713R, 713S, and 713T, high-frequency components (periodic variation amounts of trigonometric functions) are removed.

[0131] The outputs F R , F S , and F T of the filters 713R, 713S, and 713T, respectively, are input to the abnormality determination section 714. R S T

[0132] In the abnormality determination section 714, the outputs F R , F S , and F T are comprehensively judged for abnormalities of the current detectors 26, 27, and 28, respectively. R S T

[0133] Details of the comprehensive judgment of abnormalities in the abnormality determination section 714 will be described later.

[0134] Figure 2BThe inverter-side fault detector 72 shown consists of an adder (adding unit) 721, three multipliers (multiplication units) 722 (722U, 722V, 722W), three filters (filtering units) 723 (723U, 723V, 723W), and a fault detection unit (fault detection unit) 724.

[0135] The current detectors 34, 35, and 36 will be used. Figure 1 The detected current I U I V I W The input is fed into adder 721 and into the first input terminal of multipliers 722U, 722V, and 722W respectively.

[0136] The current I obtained by addition operation by adder 721 I0 (=I U +I V +I W The inputs are fed into the second input terminal of each of the multipliers 722U, 722V, and 722W.

[0137] The output D obtained by multiplying by multipliers 722U, 722V, and 722W respectively U D V D W The inputs are respectively fed into filters 723U, 723V, and 723W.

[0138] In filters 723U, 723V, and 723W, high-frequency components are removed (the periodic changes of trigonometric functions are removed).

[0139] The output F of filters 723U, 723V, and 723W U F V F W The values ​​are input into the exception detection unit 724.

[0140] In the anomaly detection unit 724, based on the above-mentioned output F U F V F W A comprehensive assessment of the abnormalities in current detectors 34, 35, and 36 is conducted.

[0141] The detailed content of the comprehensive judgment of anomalies in the anomaly judgment section 724 will be described later.

[0142] The relation that holds true in the circuits associated with anomaly detectors 71 and 72

[0143] First, before the detailed operation of the abnormality determiners (converter-side abnormality determiner 71, inverter-side abnormality determiner 72) is described, the relationship established in the circuit and the current detector will be described.

[0144] Figure 2A The illustrated converter-side abnormality determiner 71 is an abnormality determiner related to the R phase, S phase, and T phase of the 3-phase alternating current. The circuit structure of the converter-side abnormality determiner 71 is as described above, for example.

[0145] The relationship between each detection value (I * ) of the converter-side current detector (26: R phase, 27: S phase, 28: T phase) and the true value (I *T ) is represented by equations (1) to (3).

[0146] I R = I RT × G R ... (1)

[0147] I S = I ST × G S ... (2)

[0148] I T = I TT × G T ... (3)

[0149] Figure 2B The illustrated inverter-side abnormality determiner 72 is an abnormality determiner related to the U phase, V phase, and W phase of the 3-phase alternating current. The circuit structure of the inverter-side abnormality determiner 72 is as described above, for example.

[0150] The relationship between each detection value (I * ) of the inverter-side current detector (34: U phase, 35: V phase, 36: W phase) and the true value (I *T ) is represented by equations (4) to (6).

[0151] I U = I UT × G U ... (4)

[0152] I V = I VT × G V ... (5)

[0153] I W = I WT × G W ... (6)

[0154] I *the detection value of the current detector representing the position corresponding to the subscript *, G * the detection gain of the current detector representing the position corresponding to the subscript *, I *T the true value of the current detector representing the position corresponding to the subscript *.

[0155] In addition, according to the Kirchhoff's current law, with respect to the actually flowing current (current true value), the equations (7) to (8) hold.

[0156] I RT +I ST +I TT = 0... (7)

[0157] I UT +I VT +I WT = 0... (8)

[0158] In addition, with respect to the amplitude of the current true value, when 3 phases are all I, the current true values of the U phase, the V phase, and the W phase are represented by the equations (9) to (11).

[0159] I UT = I x cos (ωt)... (9)

[0160] I VT = I x cos (ωt - 2π / 3)... (10)

[0161] I WT = I x cos (ωt - 4π / 3)... (11)

[0162] where, as described above, I is the current amplitude, t is the time (time, the passage of time), and ω = 2πf is the angular frequency (f is the frequency).

[0163] In the case where all the current detectors (34, 35, 36) are normal, the detection value I * of each current detector is equal to the true value I *T , and thus the value of the detection gain G is 1.

[0164] On the other hand, in the case where the current detectors 34, 35, 36 are abnormal (for example, in the case where a detection gain abnormality has occurred), the detection value I * is not consistent with the true value I *T , and the value of the detection gain G is not 1 (for example, 0.9, 1.1).

[0165] Action and Principle of Inverter-Side Abnormality Judge 72

[0166] The action and principle of the inverter-side abnormality judge 72 and the converter-side abnormality judge 71 will be described below, as described above, Figure 2A The converter-side fault detector 71 and shown Figure 2B The inverter-side fault detector 72 shown has a very similar structure, so the inverter-side fault detector 72 will be used as an example for explanation.

[0167] The following explanation uses the abnormality of the inverter-side current detectors (34, 35, 36) as an example to illustrate the operation and principle of the inverter-side abnormality detector 72. However, by replacing the subscripts U, V, W with R, S, T, the operation and principle of the converter-side abnormality detector 71 can also be explained in the same way.

[0168] Here, the degree of anomaly A is defined as information indicating the degree of anomaly of the current detector, as follows. * .

[0169] Abnormality level A * Defined as for the detection gain G * G * =1+A * Established.

[0170] In A * When the detection gain G is 0, * A value of 1 indicates normal operation.

[0171] In A * When the detection gain G is a value other than 0, * A value other than 1 indicates an anomaly.

[0172] Therefore, A * It means A * The further the value is from 0, the greater the impact of the anomaly, indicating the degree of anomaly.

[0173] Assuming the U-phase current detector 34 is malfunctioning (detection gain G) U =1+A U ≠1), V-phase current detector 35 and W-phase current detector 36 are normal (detection gain G) V =1+A V =1, detection gain G W =1+A W =1).

[0174] At this time, for the current flowing through the above equations (9) to (11), the output of adder 721 and the output of multiplier 722 (722U, 722V, 722W) (D) U D V D W The output (F) of the 723 filter (723U, 723V, 723W) U F V F W) will be described.

[0175] When each detection gain is G U ≠ 1, G V = 1, G W = 1, the current detection value (I U , I V , I W ) is represented by the following formulas (12) to (14) according to the above formulas (4) to (6) and formulas (9) to (11). U is the abnormality degree of the U phase.

[0176] I U = (1 + A U ) I x cos (ωt)... (12)

[0177] I V = I x cos (ωt - 2π / 3)... (13)

[0178] I W = I x cos (ωt - 4π / 3)... (14)

[0179] At this time, the sum of the current detection values of the three phases I I0 = I U + I V + I W becomes the following formula (15).

[0180] I I0 of the formula (15) becomes the output of the adder 721.

[0181] I I0 = A U I x cos (ωt)... (15)

[0182] The product D U = I U x I I0 , D V = I V x I I0 , D W = I W x I I0 of each phase current detection value and the sum of the three phase current detection values is represented by the following formulas (16) to (18).

[0183] D U , D V , D W of the formulas (16) to (18) are the outputs of the multiplier 722.

[0184] In the calculation process of equations (16) to (18) which are omitted, the addition theorem of trigonometric functions, the formula for double angles, and the formula for half angles are used.

[0185] D U =A U (1+A U )I 2 (1+cos(2ωt)) / 2...(16)

[0186] D V =﹣A U I 2 (1+cos(2ωt)) / 4+√3 / 4×A U I 2 ×sin(2ωt) ...(17)

[0187] D W =﹣A U I 2 (1+cos(2ωt)) / 4﹣√3 / 4×A U I 2 ×sin(2ωt) ...(18)

[0188] In equations (17) and (18), the symbol “√3” is used for convenience. 3 1 / 2 、SQRT(3).

[0189] If we consider the D represented by equations (16) to (18) above... U D V D W Apply removal D U D V D W If the high-frequency components are filtered (removing the periodic variations of the trigonometric functions), then the output F of filter 723 will be... U F V F W It becomes equations (19) to (21) as shown below.

[0190] F U =(A U 2 +A U )I 2 / 2...(19)

[0191] F V =﹣A U I 2 / 4...(20)

[0192] F W =﹣A U I2 / 4...(21)

[0193] In addition, the value of A U , F U +F V +F W becomes the formula (22).

[0194] F U +F V +F W =A U 2 I 2 / 2...(22)

[0195] The filter 723 (723U, 723V, 723W) preferably has a function of extracting a direct current component included in the filter input by removing or greatly reducing an alternating current component included in the filter input.

[0196] For example, the filter 723 (723U, 723V, 723W) is a low pass filter such as a 1st order lag filter.

[0197] Alternatively, the filter 723 (723U, 723V, 723W) can also output an average value or a central value of the input waveform in a predetermined time range.

[0198] Alternatively, the filter 723 (723U, 723V, 723W) can also output an intermediate value of the maximum value and the minimum value of the input waveform in a predetermined time range.

[0199] In addition, the inverter-side abnormality determiner 72 can change the setting of the filter 723 (723U, 723V, 723W) depending on the frequency of the current flowing through the inverter-side current detector (34, 35, 36).

[0200] <Flowchart of the abnormality determination processing by the abnormality determination section of the first embodiment: one>

[0201] Figure 3 An example of a flowchart showing the abnormality determination processing by the abnormality determination section 724 of the inverter-side abnormality determiner 72 of the first embodiment of the present application.

[0202] However, first, the mathematical formula and the calculation example appearing in the flowchart of Figure 3 will be described.

[0203] 《Calculation example related to F U , F V , F W of step S105, step S106》

[0204] In the description Figure 3 The abnormality determination section 724 performs the abnormality determination process shown above before G U ≠ 1 (A U ≠ 0) and G V = G W = 1 (A V = A W = 0) are used in step S105 and step S106. U , F V , F W , the absolute values |F U |, |F V |, |F W |, and |F U | + |F V | + |F W | are calculated.

[0205] The absolute values |F U |, |F V |, |F W | of F U , F V , F W may be calculated by hardware or by software. In either case, the function or means for calculating the absolute values is referred to as an "absolute value calculator".

[0206] In addition, there can be multiple absolute value calculators, or one absolute value calculator can be shared among the phases. In the case of sharing one absolute value calculator, it is sometimes convenient to consider multiple absolute value calculators.

[0207] When A U ≥ 0 (with respect to the detection gain G U , G U ≥ 1), the absolute values |F U |, |F V |, |F W | of F U , F V , F W become the following expressions (23) to (25).

[0208] |F U | = (A U 2 + A U ) I 2 / 2... (23)

[0209] |F V | = A U I 2 / 4... (24)

[0210] |F W |=A U I 2 / 4...(25)

[0211] According to the above-described formulae (23) to (25), when A U ≥ 0 (G U ≥ 1), |F U | + |F V | + |F W | becomes the following formula (26).

[0212] |F U | + |F V | + |F W | = (A U 2 + 2A U )I 2 / 2...(26)

[0213] When -1 ≤ A U ≤ 0 (0 ≤ G U ≤ 1 with respect to the detection gain G U ), the absolute values |F U |, |F V |, and |F W | of F U , F V , and F W become the following formulae (27) to (29).

[0214] |F U | = - (A U 2 + A U )I 2 / 2...(27)

[0215] |F V | = - A U I 2 / 4...(28)

[0216] |F W | = - A U I 2 / 4...(29)

[0217] According to the above-described formulae (27) to (29), when -1 ≤ A U ≤ 0 (0 ≤ G U ≤ 1), |F U | + |F V | + |F W | becomes the following formula (30).

[0218] |F U |+|F V |+|F W |=﹣(A U 2 +2A U )I 2 / 2...(30)

[0219] In A U < ﹣ 1 (with respect to the detection gain G U , G U < 0), the absolute values |F U |, |F V |, |F W | of F U , F V , F W become the following equations (31) to (33).

[0220] |F U |=(A U 2 +A U )I 2 / 2...(31)

[0221] |F V |=﹣A U I 2 / 4...(32)

[0222] |F W |=﹣A U I 2 / 4...(33)

[0223] According to the above equations (31) to (33), in A U < ﹣ 1 (G U < 0), |F U | + |F V | + |F W | becomes the following equation (34).

[0224] |F U | + |F V | + |F W | = A U 2 I 2 / 2...(34)

[0225] The anomaly of A U < ﹣ 1 shown in equations (31) to (34) is an anomaly in which the degree of polarity inversion of G U < 0 is large.

[0226] Typically, it needs to be at an abnormality level A. U It deviated from the predetermined range close to 0 (e.g., -0.1 < A). U An anomaly was detected at a time point <0.1), and upon reaching A... U Anomalies can be detected before large anomalies such as <-1 are detected.

[0227] Therefore, the degree of abnormality A shown in equations (31) to (34) is omitted below. * The anomaly detection method is not <-1 (* represents U, V, or W), but rather the anomaly degree A is recorded as shown in equations (23) to (30). * Anomaly detection method with ≥-1.

[0228] In the case of abnormal detection gain caused by aging of the current detector, the detection gain G of the abnormal current detector... * (* represents U, V, or W) gradually increases or decreases from 1, therefore, in the early stages of degradation of the current detector, A U absolute value | A U |Become|A U |<<1.

[0229] Therefore, according to equations (23) to (30) above, in |A U When | << 1, |F U |≈2×|F V |、|F U |≈2×|F W |、|F U |+|F V |+|F W |≈|A U |×I 2 .

[0230] Furthermore, when the current amplitude I can be estimated based on the command value, |A U |≈I 2 / (|F U |+|F V |+|F W |), based on |F U |+|F V |+|F W |, can be presumed|A U |(|A U |=|1﹣G U |).

[0231] Additionally, in |F U |>|F V |and|F U |>|F W When established, it can be determined that there is an abnormality in the U-phase current detector 34.

[0232] Next, a case where the V-phase current detector 35 is abnormal (detection gain G V = 1 + A V ≠ 1) and the U-phase current detector 34 and the W-phase current detector 36 are normal (detection gain G U = 1 + A U = 1, detection gain G W = 1 + A W = 1) is considered.

[0233] At this time, if the same calculation as that of the equations (12) to (21) is performed, F U , F V , and F W become the equations (19B) to (21B) shown below.

[0234] F U = -A V I 2 / 4... (19B)

[0235] F V = (A V 2 + A V ) I 2 / 2... (20B)

[0236] F W = -A V I 2 / 4... (21B)

[0237] When |A V | < < 1, when the same calculation as that of the equations (22) to (30) described above is performed using F U , F V , and F W calculated according to the equations (19B) to (21B), |F V | ≈ 2 x |F U |, |F V | ≈ 2 x |F W |, and |F U | + |F V | + |F W | ≈ |A V | x I 2 , and when |F V | > |F U | and |F V | > |F W | are established, it can be determined that the V-phase current detector 35 is abnormal.

[0238] Next, a case where the W-phase current detector 36 is abnormal (detection gain GW =1+A W ≠1) U-phase current detector 34 and V-phase current detector 35 are normal (detection gain G) U =1+A U =1, Detection gain G V =1+A V =1). In this case, if the same calculations as in equations (12) to (21) are performed, then F U F V F W This becomes Equation (19C) to Equation (21C).

[0239] F U =﹣A W I 2 / 4...(19C)

[0240] F V =﹣A W I 2 / 4...(20C)

[0241] F W =(A W 2 +A W )I 2 / 2...(21C)

[0242] In |A W When | << 1, when using F obtained from equations (19C) to (21C) U F V F W When performing the same calculations as in equations (22) to (30) above, |F W |≈2×|F U |、|F W |≈2×|F V |、|F U |+|F V |+|F W |≈|A W |×I 2 , in |F W |>|F U |and|F W |>|F V When established, it can be determined that the W-phase current detector 36 is abnormal.

[0243] <Flowchart of the exception judgment process performed by the exception judgment unit 724: Part 2>

[0244] Based on the above calculation example, the following will follow... Figure 3 The flowchart shown illustrates the processing of the exception detection unit 724.

[0245] Step S101

[0246] In Figure 3 the case where the determination of the abnormality determination section 724 Figure 2B is "start", the process proceeds to Step S101.

[0247] In Figure 3 Step S101, the abnormality determination section 724 determines whether the detection values of the three current detectors 34, 35, 36 are all zero (no pulsation component).

[0248] The abnormality determination section 724 proceeds to Step S102 in the case where the detection values of the three current detectors 34, 35, 36 are all zero (S101: Yes).

[0249] In Step S101, in the case where the detection values of the three current detectors 34, 35, 36 are not all zero (S101: No), the process proceeds to Step S103.

[0250] Step S102

[0251] As a result of the determination of Step S101, in the case of proceeding to Step S102, in Step S102, it is determined that the inverter power conversion section 31 has an abnormality.

[0252] Then, the display 73 is caused to display information indicating that the power conversion section has an abnormality ("power conversion section abnormality") (Step S102). Then, the subsequent process proceeds to Step S112.

[0253] Further, Step S112 is described later.

[0254] Step S103

[0255] In Step S103, the abnormality determination section 724 determines whether the detection value of any one of the three current detectors 34, 35, 36 is continuously outputting zero (or a value close to zero).

[0256] The abnormality determination section 724 proceeds to Step S104 in the case where the detection value of any one of the three current detectors 34, 35, 36 is continuously outputting zero (S103: Yes).

[0257] In Step S103, the abnormality determination section 724 proceeds to Step S105 in the case where the detection value of none of the three current detectors 34, 35, 36 is continuously outputting zero (S103: No).

[0258] Step S104

[0259] As a result of the determination in step S103, if the process proceeds to step S104, in step S104, considering the abnormality caused by the current detection loop (current detection loop: wiring) used by the AC current detector, such as the wire breakage or looseness, it is determined that there is an abnormality in the current detection loop.

[0260] Then, the display 73 shows a message indicating an abnormality in the current sensing loop ("Current Sensing Loop") (step S104). Then, the subsequent processing proceeds to step S112.

[0261] Furthermore, step S112 will be described later.

[0262] Step S105

[0263] In step S105, the exception judgment unit 724 judges |F U |+|F V |+|F W Is it greater than the predetermined value?

[0264] If |F U |+|F V |+|F W If the value is greater than the predetermined value (S105: Yes), then the exception judgment unit 724 proceeds to step S106.

[0265] In step S105, the anomaly detection unit 724 determines the anomaly in |F U |+|F V |+|F W If the value is not greater than the predetermined value (S105: No), proceed to step S113.

[0266] Furthermore, step S113 will be described later.

[0267] Step S106

[0268] In step S106, the anomaly detection unit 724 determines |F U |>|F V |and|F U |>|F w Is this true?

[0269] In |F U |>|F V |and|F U |>|F w If the condition is met (S106: Yes), the exception judgment unit 724 proceeds to step S107.

[0270] In step S106, at |F U |>|F V |and|FU |F w |is not true (S106: No), the abnormality determination section 724 determines that the current detector 34 of phase U is normal, and proceeds to step S108.

[0271] Step S107

[0272] As a result of the determination of step S106, in the case of proceeding to step S107, in step S107, it is determined that the current detector 34 of phase U is abnormal, and the display 73 is caused to display information indicating that the current detector of phase U is abnormal ("current detector of phase U is abnormal"). Then, the subsequent processing is caused to proceed to step S112.

[0273] Further, step S112 is described later.

[0274] Step S108

[0275] In step S108, the abnormality determination section 724 determines whether |F V |F U |and |F V |F W |is true.

[0276] In the case where |F V |F U |and |F V |F W |is true (S108: Yes), the abnormality determination section 724 proceeds to step S109.

[0277] On the other hand, in the case where the above inequality is not true in step S108 (S108: No), the abnormality determination section 724 determines that the current detector 35 of phase V is normal, and proceeds to step S110.

[0278] Step S109

[0279] As a result of the determination of step S108, in the case of proceeding to step S109, in step S109, it is determined that the current detector 35 of phase V is abnormal.

[0280] Then, the display 73 is caused to display information indicating that the current detector of phase V is abnormal ("current detector of phase V is abnormal"). Then, the subsequent processing is caused to proceed to step S112.

[0281] Further, step S112 is described later.

[0282] Step S110

[0283] In step S110, the abnormality determination section 724 determines whether |F W |FU |and|F W |>|F V Is this true?

[0284] Anomaly detection unit 724 in |F W |>|F U |and|F W |>|F V If the condition is met (S110: Yes), proceed to step S111.

[0285] On the other hand, when the above inequality does not hold in step S110 (S110: No), the anomaly determination unit 724 determines that the current detector 36 of phase W is normal. Then, it proceeds to step S113.

[0286] Step S111

[0287] As a result of the determination in step S110, if the process proceeds to step S111, in step S111, it is determined that the current detector 36 of phase W is abnormal.

[0288] Furthermore, the display 73 shows a message indicating an abnormality in the W-phase current detector ("W-phase current detector abnormality"). Then, the subsequent processing proceeds to step S112.

[0289] Additionally, step S112 is as follows.

[0290] Step S112

[0291] In step S112, following steps S102, S104, S107, S109, and S111, the next process is executed.

[0292] In step S112, the anomaly detection unit 724 causes the display 73 to show the statement "Please check the anomaly location and replace it" and then ends the process.

[0293] Step S113

[0294] In step S113, it is determined that all current detectors, including the U-phase current detector 34, V-phase current detector 35, and W-phase current detector 36, are normal. However, it is not necessary to display on the display 73 that the current detectors are normal.

[0295] Then, the process ends.

[0296] <Supplement to the above steps>

[0297] conduct Figure 3 The inequality (|F) recorded in step S105 U |+|F V |+|FW The "predetermined value" for the determination of |>predetermined value) can be either fixed or variable.

[0298] The detection gain G of a certain current detector (e.g., phase U) U From 1, it deviated from A. U The above is when you want to determine if the current detector is malfunctioning, based on |F U |+|F V |+|F W |≈|A U |×I 2 Using the current amplitude "I" estimated based on the current command value, etc., the predetermined value is made to match I. 2 Just make sure it's in proportion.

[0299] In principle, when the current is zero, the A signal, which indicates the degree of sensor malfunction, cannot be observed. U Therefore, abnormal diagnosis cannot be performed. Thus, to avoid misjudgments when the current is low, the aforementioned "predetermined value" can be made variable.

[0300] Furthermore, if the current flowing in the current detector has a variable frequency due to reasons such as the variable operating frequency of the motor 4, it is preferable to use the current detector in step S105, etc. Figure 2B The time constant (or cutoff frequency) of the filter is set to be variable, so that even when the operating frequency of motor 4 is low, the AC component contained in the filter input can be significantly removed.

[0301] Alternatively, the time constant of the filter can be preset to significantly reduce the AC component in the filter input even at low speeds. Furthermore, when the operating frequency of motor 4 is extremely low, the time constant of the filter becomes extremely large, thus eliminating the need for anomaly detection when the operating frequency of motor 4 is low.

[0302] exist Figure 3 In the flowchart, after step S105, to ensure correctness, steps S106, S108, S110, S107, S109, S111, S112, and S113 are also executed.

[0303] However, there are also methods that stop at steps S101 to S105. That is, in step S105, when |F U |+|F V |+|F W If a "yes" decision is made in the determination of the predetermined value, it is determined that "at least one of the current detectors is abnormal".

[0304] Although the level of rigor has been reduced, the judgment time is shortened to facilitate a quicker response.

[0305] In addition, in Figure 3 the flowchart, in the process of step S106 to step S111, it can be said that the following process: the abnormality determiner 72 Figure 2B ) compares the absolute values of the outputs of the plurality of phases (|F U |, |F V |, |F W |) with each other, and determines that the phase current detector corresponding to the absolute value calculator that outputs the maximum value in the comparison of the plurality of absolute values is abnormal.

[0306] <Waveform Examples Regarding Abnormality Determination Operation of Filter 723>

[0307] Referring to Figures 4-9 , a plurality of waveform examples of the abnormality determination operation of the filter 723 (723U, 723V, 723W) will be described.

[0308] Figures 4-9 are calculation examples of the current detection values I U , I V , I W , the output I I0 of the adder 721, the output D U of the multiplier 722, D V , D W , the output F U of the filter 723 (723U, 723V, 723W), F V , F W in the case where all the current detectors are normal or in the case where one current detector is abnormal.

[0309] Figure 4 indicate examples of the current detection values, various outputs of the adder 721, the multiplier 722 (722U, 722V, 722W), the filter 723 (723U, 723V, 723W), and the like of the inverter-side abnormality determiner 72 in the case where all the current detectors are normal and the 3-phase load (Y connection) of the motor 4 is balanced.

[0310] In the upper part of the graph of Figure 4 , the time variations (time t) of the currents I U , I V , I W , I I0 are shown.

[0311] In the lower part of the graph of Figure 4 , the outputs D U , D V , DW The output F of the filter 723 (723U, 723V, 723W) U F V F W The change over time (time t).

[0312] like Figure 4 As shown, under normal conditions of all current detectors, I I0 Become 0, therefore F U =F V =F W =0. Therefore, Figure 3 In step S105, |F U |+|F V |+|F W If the value becomes 0, it can be accurately determined that the current detector is not abnormal.

[0313] Next, regarding Figure 5 and Figure 6 Please provide an explanation.

[0314] Figure 5 The detection gain G of the current detector in phase U is represented by... U Examples of various outputs of the inverter-side fault detector 72 include the current waveform of the current detection value when the current of the motor 4 is abnormal and the 3-phase load (Y-connected) is balanced, the adder 721, multiplier 722 (722U, 722V, 722W), filter 723 (723U, 723V, 723W), etc., when the current is 125% abnormal and the 3-phase load (Y-connected) of the motor 4 is balanced; and various outputs of the inverter-side fault detector 72, such as the adder 721, multiplier 722 (722U, 722V, 722W).

[0315] In addition, Figure 5 The upper part of the diagram shows the current I. U I V I W I I0 The change over time (time t).

[0316] In addition, Figure 5 The diagram in the lower section shows the output D of the multiplier 722 (722U, 722V, 722W) (current detection values ​​for each phase and the sum of the current detection values ​​for the three phases). U D V D W The output F of the filter 723 (723U, 723V, 723W) U F V F W The change over time (time t).

[0317] exist Figure 5 In the middle, the current I U Specific current I V I Wlarge, in addition, the current I I0 flows with a current value that is not 0.

[0318] In addition, the output F U is output on the positive side, and the outputs F V , F W are output on the negative side with predetermined values.

[0319] In addition, Figure 6 represents the detection gain G U = 75% so that the current waveform of the current detection value at the time when the 3-phase load (Y connection) of the motor 4 is balanced, the various outputs of the adder 721, the multipliers 722 (722U, 722V, 722W), the filters 723 (723U, 723V, 723W), and the like of the inverter-side abnormality determiner 72 are examples.

[0320] In Figure 6 the upper graph, the time variation (time t) of the current I U , I V , I W , I I0 is shown.

[0321] In Figure 6 the lower graph, the time variation (time t) of the outputs D U , D V , D W of the multipliers 722 (722U, 722V, 722W) and the outputs F U , F V , F W of the filters 723 (723U, 723V, 723W) is shown.

[0322] In Figure 6 , the current I U is smaller than the current I V , I W , in addition, the current I I0 flows with a current value that is not 0.

[0323] In addition, the output F U is output on the negative side, and the outputs F V , F W are output on the positive side with predetermined values.

[0324] As Figure 5 and Figure 6As shown, in the case of an abnormal current detector in phase U, |F U |+|F V |+|F W | is greater than 0, therefore it is determined as "yes" in step S105.

[0325] In addition, Figure 5 , Figure 6 In the middle, all are |F U |>|F V |and|F U |>|F W Therefore, in step S106, it can be accurately determined that the U-phase current detector is abnormal.

[0326] Figure 7 Examples of current waveforms representing the current detection values ​​when all current detectors are normal and the 3-phase load (Y-connected) of motor 4 is unbalanced (the U-phase load is 0.8 times the V-phase load and W-phase load), and various outputs of the inverter-side fault detector 72, including adder 721, multiplier 722 (722U, 722V, 722W), filter 723 (723U, 723V, 723W), etc.

[0327] exist Figure 7 The upper part of the diagram shows the current I. U I V I W I I0 The change over time (time t).

[0328] exist Figure 7 The diagram below shows the output D of the multiplier 722 (722U, 722V, 722W) (current detection values ​​for each phase and the sum of the current detection values ​​for the three phases). U D V D W The output F of the filter 723 (723U, 723V, 723W) U F V F W The change over time (time t).

[0329] exist Figure 7 In the case shown, the load of phase U is as small as 0.8 times that of phase V and phase W, so the current of phase U is larger than that of the other phases (approximately 1 / 0.8 times).

[0330] On the other hand, assuming all current detectors are functioning normally, based on Kirchhoff's current law, I I0 =0, therefore F U =F V =F W =0. That is, as shown in the image. Figure 7 As shown, II0 =0,F U =F V =F W =0.

[0331] Therefore, in step S105, |F U |+|F V |+|F W If the value becomes 0, it can be accurately determined that the current detector is not abnormal.

[0332] To illustrate the features and effects of the first embodiment of the present invention, compared with Patent Document 1, based on Figure 7 When using the method of Patent Document 1 under the conditions shown, since the judgment is based on the effective value, it is possible to mistakenly identify it as current detector I. U abnormal.

[0333] In the first embodiment of the present invention, as described above, in Figure 7 Under the conditions shown, it can be accurately determined that the current detector is not abnormal.

[0334] Figure 8 The current detector representing phase V has a detection gain G. V Examples of current waveforms of current detection values ​​when the current is 110% abnormal and the three-phase load (Y-connected) of motor 4 is unbalanced (the U-phase load is 0.8 times the V-phase load and W-phase load), and various outputs of the inverter-side abnormality judgment unit 72, such as adder 721, multiplier 722 (722U, 722V, 722W), and filter 723 (723U, 723V, 723W).

[0335] exist Figure 8 The upper part of the diagram shows the current I. U I V I W I I0 The change over time (time t).

[0336] exist Figure 8 The diagram in the lower section shows the output of the 722 multiplier (722U, 722V, 722W) (multiplier output) D (the sum of the current detection values ​​of each phase and the current detection values ​​of the three phases). U D V D W The output (filter output) F of the 723 (723U, 723V, 723W) filter. U F V F W The change over time (time t).

[0337] exist Figure 8In the illustrated case, since the U-phase load is small, the U-phase current is larger than the other phases (G-phase, V-phase), and the detection value of the V-phase current detector 35 is 1.1 times the true value, so the current detection value I V is larger than I W . Thus, the currents I Figure 8 , I U , I V , I W , I I0 , the multiplier outputs D U , D V , D W , the filter outputs F U , F V , F W become as shown in the drawing.

[0338] In the case of Figure 8 , |F U | + |F V | + |F W | is greater than 0, so in step S105 it is determined to be (Yes).

[0339] In addition, in the case of Figure 8 , |F V | > |F U | and |F V | > |F W | are established, so in step S108 it is determined to be (Yes), and in step S109 it is accurately determined that the V-phase current detector 35 is abnormal.

[0340] In order to express the features and effects of the first embodiment of the present application, in the case of using the method of Patent Literature 1 based on the conditions shown in Figure 8 , in the method of Patent Literature 1, since determination is made based on the effective value, there is a possibility of false determination that the current detector I U is abnormal.

[0341] In the first embodiment of the present application, |F U |, |F V |, |F W | used in the method of the embodiment become large values when the phase difference between I U , I V , I W and I I0 is close to 0 degrees or 180 degrees, and become small values when the phase difference between I U , I V , I W and I I0 is close to 90 degrees or 270 degrees.

[0342] Even in the case where 3-phase imbalance occurs, the phase change amount of the phase U , V , W is small, and thus the method of the present application can accurately determine even in the case where 3-phase imbalance occurs.

[0343] Figure 9 the detection gain G of the current detector of the V-phase V = 110% to be abnormal, the 3-phase load (Y connection) of the motor 4 is imbalanced (the U-phase load is 0.8 times the V-phase load and the W-phase load), and the current waveform of the current detection value in the case where the fundamental current waveform contains current pulsation (the maximum value of the current pulsation is 0.8 times the fundamental current amplitude), the various outputs of the adder 721, the multipliers 722 (722U, 722V, 722W), the filters 723 (723U, 723V, 723W), and the like of the inverter-side abnormality determiner 72.

[0344] In the upper graph of Figure 9 , the time variation (time t) of the current I U , I V , I W , I I0 is shown.

[0345] In the lower graph of Figure 9 , the time variation (time t) of the outputs D U , D V , D W of the multipliers 722 (722U, 722V, 722W) and the outputs F U , F V , F W of the filters 723 (723U, 723V, 723W) is shown.

[0346] In Figure 9 , the current waveform in the case where the 3-phase load is imbalanced, the current waveform in the case where the current waveform contains current pulsation of a size that cannot be ignored or current pulsation of a frequency close to the fundamental current frequency, and the various output waveforms are shown.

[0347] Under the conditions of Figure 9 , |F U | + |F V | + |F W | is greater than 0, and thus it is determined that (Yes) in step S105.

[0348] In addition, in Figure 9 , since |F V | > |F U , it is determined that (Yes) in step S105.|and|F V |>|F W Therefore, it is possible to accurately determine that the V-phase current detector is abnormal in step S108.

[0349] Thus, the filter 723 (723U, 723V, 723W) removes the AC component containing the fundamental frequency of the current waveform. Therefore, even when the current waveform contains a large current ripple component, or when the fundamental frequency of the current waveform is close to the frequency of the current ripple, the filter can still function effectively because the F-value, which has sufficiently removed the ripple component, is optimized. U F V F W It performs anomaly detection, thus enabling it to make correct judgments.

[0350] In order to illustrate the features and effects of the first embodiment of the present invention, compared with Patent Document 2 and Patent Document 3, in terms of... Figure 9 When the waveform shown is applied using the methods of Patent Documents 2 and 3, it is possible to misjudge due to the current pulsation component.

[0351] In Patent Documents 2 and 3, a filter for removing the AC component containing the fundamental frequency of the current waveform in order to sufficiently remove the current ripple component is applied to I. I0 In the case of I I0 The value becomes 0, therefore the anomaly of the current detector cannot be detected.

[0352] Furthermore, in Patent Documents 2 and 3, when the current ripple component is not sufficiently removed by a filter, it is necessary to... I0 The judgment benchmark value is set to a value sufficiently far from 0 to avoid misjudging anomalies and failing to detect the detection gain G. U An anomaly close to 1.

[0353] As described above, in the power conversion device 100 of the first embodiment, even when the three-phase load is unbalanced, or when the current waveform contains current ripples of a magnitude that cannot be ignored or current ripples of a frequency close to the fundamental frequency of the current, the abnormality of the current detector can be accurately determined.

[0354] <Operation and Principle of Converter-Side Anomaly Detector 71>

[0355] like Figure 2A As shown, the converter-side fault detector 71 has the same circuit module structure as the inverter-side fault detector 72.

[0356] That is, in Figure 2A In the converter-side fault detector 71 shown, the following will be used: Figure 2BThe adder 721, three multipliers 722 (722U, 722V, 722W), three filters 723 (723U, 723V, 723W), and the fault detection unit 724 of the inverter-side fault detector 72 shown are respectively replaced by adder 711, three multipliers 712 (712R, 712S, 712T), three filters 713 (713R, 713S, 713T), and fault detection unit 714.

[0357] Additionally, the input to the inverter-side fault detector 72 is the I output from the U-phase current detector 34, V-phase current detector 35, and W-phase current detector 36, respectively. U I V I W In contrast, the input to the converter-side fault detector 71 is the I output from the R-phase current detector 26, the S-phase current detector 27, and the T-phase current detector 28, respectively. R I S I T .

[0358] Additionally, relative to the output current I of the adder 721 of the inverter-side fault detector 72 IO The outputs of three 722 multipliers (722U, 722V, 722W) are D U D V D W The output F of 3 filters 723 (723U, 723V, 723W) U F V F W In the converter-side fault detector 71, it becomes the output current I of the adder 711. CO The output D of three 712 multipliers (712R, 712S, 712T) R D S D T The output F of three 713 filters (713R, 713S, 713T) R F S F T And each corresponds to the other.

[0359] That is, as mentioned above, Figure 2A The converter-side fault detector 71 and shown Figure 2B The inverter-side fault detector 72 shown has a very similar structure. Therefore, the operation and principle of the converter-side fault detector 71 can be referred to in form as the operation and principle of the inverter-side fault detector 72.

[0360] Specifically, in equations (1) to (34), Figure 3In the flowchart, the action and the principle of the inverter-side abnormality determiner 72 are also able to be explained by substituting the subscripts U, V, W with R, S, T.

[0361] Therefore, in fact, the action and the principle of the inverter-side abnormality determiner 72 are substituted for the action and the principle of the converter-side abnormality determiner 71, and the repeated explanation is omitted.

[0362] <Effects and Summary of the Power Conversion Device 100 of the First Embodiment>

[0363] As explained above, in the power conversion device 100 of the first embodiment of the present application, even in a case where a 3-phase load (a motor) connected to the power conversion device 100 is unbalanced, or in a case where a large current pulsation component is included in an alternating current, an abnormality of a current detector in the power conversion device can be appropriately detected.

[0364] In addition, the filter 723 removes an alternating component including a fundamental frequency of a current waveform, and therefore even in a case where a size of a current pulsation is a size that cannot be ignored compared with a fundamental wave of a current waveform, or in a case where a frequency of the current pulsation is close to a fundamental frequency of the current waveform, the current pulsation can be sufficiently removed.

[0365] In addition, by estimating the detection gain including information of a degree of abnormality of the current detector, a period until an output of the current detector exceeds a predetermined threshold value for determining an abnormality, that is, a period until an abnormality occurs can be predicted, and the occurrence of the abnormality can be prevented in advance, and preparation for the occurrence of the abnormality can be made.

[0366] In addition, the display is made to recommend inspection and replacement of the abnormal current detector, and therefore the inspection and the replacement of the current detector can be made according to a deterioration development of the current detector before an unexpected stop such as a trip caused by an abnormality of the current detector occurs in the power conversion device 100.

[0367] <Variant of the First Embodiment: Power Conversion Device>

[0368] Next, a variant of the first embodiment of the present application is explained.

[0369] Figure 10 An example of a flowchart of an abnormality determination process made by the abnormality determination part 724 of the inverter-side abnormality determiner 72 in the variant of the first embodiment of the present application.

[0370] In the variant of the first embodiment of the present application, Figure 10 The difference is that steps S106, S108, S110 in the first embodiment of the present application are replaced with steps S206, S208, S210. Figure 3

[0371] ​ Figure 10 and Figure 3 Steps S101 to S105, S107, S109, and S111 to S113 are the same steps.

[0372] In the Figure 10 Before explaining the exception judgment process of the exception judgment unit 724 shown, the judgment formulas in steps S206, 208, and S210 are... Figure 3 They are different. Therefore, equations (44) to (49) used in steps S206, 208 and S210 will be explained.

[0373] First, consider Figure 1 The U-phase current detector 34 in the middle is abnormal (detection gain G). U =1+A U ≠1), V-phase current detector 35 and W-phase current detector 36 are normal (detection gain G) V =1+A V =1, Detection gain G W =1+A W =1).

[0374] When A U When ≥0 (regarding the detection gain G) U G U When ≥1), |F U |﹣|F V |﹣|F W |、|F V |﹣|F W |﹣|F U |、|F W |﹣|F U |﹣|F V | Become the following equations (35) to (37).

[0375] |F U |﹣|F V |﹣|F W |=A U 2 I 2 / 2...(35)

[0376] |F V |﹣|F W |﹣|F U |=﹣(A U 2 +A U )I 2 / 2...(36)

[0377] |F W |﹣|F U|﹣|F V |=﹣(A U 2 +A U )I 2 / 2...(37)

[0378] -1≤A U When ≤0 (regarding the detection gain G) U , 0≤G U When ≤1), |F U |﹣|F V |﹣|F W |、|F V |﹣|F W |﹣|F U |、|F W |﹣|F U |﹣|F V | Become the following equations (38) to (40).

[0379] |F U |﹣|F V |﹣|F W |=﹣A U 2 I 2 / 2...(38)

[0380] |F V |﹣|F W |﹣|F U |=(A U 2 +A U )I 2 / 2...(39)

[0381] |F W |﹣|F U |﹣|F V |=(A U 2 +A U )I 2 / 2...(40)

[0382] When A U When ≤﹣1 (regarding the detection gain G) U G U When ≤0), |F U |﹣|F V |﹣|F W |、|F V |﹣|F W |﹣|F U |、|F W |﹣|F U |﹣|F V| Become Equation (41) to Equation (43).

[0383] |F U |﹣|F V |﹣|F W |=(A U 2 +2A U )I 2 / 2...(41)

[0384] |F V |﹣|F W |﹣|F U |=﹣(A U 2 +A U )I 2 / 2...(42)

[0385] |F W |﹣|F U |﹣|F V |=﹣(A U 2 +A U )I 2 / 2...(43)

[0386] Therefore, according to Figure 3 The flowchart uses equation (22), and in Figure 10 Equations (35) to (43) described in the flowchart, when equation (44) shown below holds, can determine that the U-phase current detector is A. U ≥0 (Regarding the detection gain G) U G U ≥1) is an abnormality.

[0387] Furthermore, when equation (45) shown below holds, it can be determined that -1 ≤ A for the U-phase current detector. U ≤0 (Regarding the detection gain G) U , 0≤G U ≤1) is an anomaly.

[0388] |F U |﹣|F V |﹣|F W |﹣(F U +F V +F W )=0...(44)

[0389] |F U |﹣|F V |﹣|F W |+(F U +F V+F W ) = 0... (45)

[0390] Next, consider the case where the V-phase current detector 35 is abnormal (the detection gain G V = 1 + A V ≠ 1) and the U-phase current detector 34 and the W-phase current detector 36 are normal (the detection gain G U = 1 + A U = 1, the detection gain G W = 1 + A W = 1).

[0391] At this time, using F U , F V , and F W calculated from the above-described equations (19B) to (21B), the same calculation as equations (22) to (43) is performed, and the following conclusion is obtained.

[0392] When the following equation (46) is satisfied, it is possible to judge that the V-phase current detector 35 is abnormal in that A V ≥ 0 (with respect to the detection gain G V , G V ≥ 1).

[0393] Also, when the following equation (47) is satisfied, it is possible to judge that the V-phase current detector 35 is abnormal in that -1 ≤ A V ≤ 0 (with respect to the detection gain G V , 0 ≤ G V ≤ 1).

[0394] |F V | - |F W | - |F U | - (F U + F V + F W ) = 0... (46)

[0395] |F V | - |F W | - |F U | + (F U + F V + F W ) = 0... (47)

[0396] Next, consider the case where the W-phase current detector 36 is abnormal (the detection gain G W = 1 + A W ≠ 1) and the U-phase current detector 34 and the V-phase current detector 35 are normal (the detection gain G U = 1 + A U = 1, the detection gain G V= 1 + A V = 1).

[0397] At this time, F U , F V , and F W calculated from the above-described equations (19C) to (21C) are used to perform the same calculation as equations (22) to (43), and the following conclusion is obtained.

[0398] When the equation (48) shown below is satisfied, it is possible to judge that A W ≥ 0 (an abnormality with respect to the detection gain G W , G W ≥ 1) with respect to the W-phase current detector 36.

[0399] Also, when the equation (49) shown below is satisfied, it is possible to judge that -1 ≤ A W ≤ 0 (an abnormality with respect to the detection gain G W , 0 ≤ G W ≤ 1) with respect to the W-phase current detector 36.

[0400] |F W | - |F U | - |F V | + (F U + F V + F W ) = 0... (48)

[0401] |F W | - |F U | - |F V | + (F U + F V + F W ) = 0... (49)

[0402] The abnormality judgment by the abnormality judging section 724 of the inverter-side abnormality judging device 72 based on the equations (44) to (49) can also be described as follows. That is,

[0403] The abnormality judging device (the inverter-side abnormality judging device 72) calculates the sum (F U + F V + F W ) of the outputs of the plurality of filters 723 (723U, 723V, 723W) respectively, and the operation value (either of the following) obtained by subtracting the output of the other phase from the output of one phase with respect to the output of the plurality of above-described absolute value calculators respectively.

[0404] |F U | - |F V | - |F W |

[0405] |F V |F W |F U |

[0406] |F W |F U |F V |

[0407] When the operation value obtained by subtracting the output of the other phase from the output of one phase with respect to the output of the absolute value of each of the plurality of above-mentioned absolute value calculators is equal to the sum of the outputs of the plurality of above-mentioned filters (any one of the following),

[0408] |F U |F V |F W |=(F U +F V +F W )

[0409] |F V |F W |F U |=(F U +F V +F W )

[0410] |F W |F U |F V |=(F U +F V +F W )

[0411] Or, when the operation value obtained by subtracting the output of the other phase from the output of one phase with respect to the output of the absolute value of each of the plurality of above-mentioned absolute value calculators is equal to the sum of the outputs of the plurality of above-mentioned filters (any one of the following),

[0412] |F U |F V |F W |+(F U +F V +F W )=0

[0413] |F V |F W |F U |+(F U +F V +F W )=0

[0414] |FW |﹣|F U |﹣|F V |+(F U +F V +F W ) = 0

[0415] It was determined that an anomaly had occurred in the current detector corresponding to the aforementioned one (power conversion device).

[0416] <Flowchart of the anomaly detection process in a variation of the first embodiment>

[0417] Next, based on the above calculation example, for Figure 10 Inverter-side fault detector 72 shown Figure 2B The exception detection unit 724 in ) Figure 2B The processing of ) will be explained.

[0418] Steps S101 to S105

[0419] Figure 10 The processing of steps S101 to S105 is related to... Figure 3 The process is the same as steps S101 to S105. Additionally, steps S107, 109, 111, 112, and 113 are the same as... Figure 3 Same. Repetitive descriptions should be omitted appropriately.

[0420] Step S206

[0421] exist Figure 10 In step S206, the exception judgment unit 724 determines whether equation (44) or equation (45) is true.

[0422] If equation (44) or equation (45) is true (S206: Yes), the anomaly detection unit 724 proceeds to step S107. Furthermore, in step S107, the current detector 34, which is determined to be phase U, ( Figure 1 , Figure 2B )abnormal.

[0423] In step S206, if the abnormality judgment unit 724 determines "no" in step S206 (S206: "no"), it determines that the current detector 34 of phase U is normal and proceeds to step S208.

[0424] Step S208

[0425] In step S208, the exception judgment unit 724 determines whether equation (46) or equation (47) is true.

[0426] The abnormality determination section 724 proceeds to step S109 when the formula (46) or the formula (47) is satisfied (S208: YES). Further, it is determined that the current detector 35 of the V phase is abnormal in step S109.

[0427] In step S208, the abnormality determination section 724 determines that the current detector 35 of the V phase is normal when the determination in step S208 is NO (S208: NO), and proceeds to step S210.

[0428] Step S210

[0429] In step S210, the abnormality determination section 724 determines whether the formula (48) or the formula (49) is satisfied.

[0430] The abnormality determination section 724 proceeds to step S111 when the formula (48) or the formula (49) is satisfied (S110: YES). Further, it is determined that the current detector 36 of the W phase is abnormal in step S111.

[0431] In step S210, the abnormality determination section 724 determines that the current detector 36 of the W phase is normal when the determination in step S210 is NO (S210: NO), and proceeds to step S113.

[0432] In step S113, it is determined that all of the current detectors of the U phase current detector 34, the V phase current detector 35, and the W phase current detector 36 are normal. Then, the processing is ended.

[0433] In Figure 10 In the modification of the first embodiment shown in FIG. 17, even in the case where the three-phase load is unbalanced or the case where the current ripple of a size that cannot be ignored or the current ripple of a frequency close to the fundamental frequency of the current is included in the current waveform, the abnormality of the current detector can be accurately determined.

[0434] In Figure 10 In the flowchart of FIG. 16, after step S105, in order to ensure accuracy, steps S206, S208, S210, steps S107, S109, S111, S112, S113 are further executed.

[0435] However, there is also a method of staying in steps S101 to S105. That is, in step S105, in the determination of YES in the determination of whether |F U |+|F V |+|F W | is greater than a predetermined value, it is determined that "at least one of the current detectors is abnormal".

[0436] Although the degree of strictness is lowered, the determination time is reduced for simple determination, and it is possible to respond quickly.

[0437] The above description is a description of the abnormality determination section 724 of the inverter-side abnormality determiner 72.

[0438] However, as described above, Figure 2A the converter-side abnormality determiner 71 and Figure 2B the inverter-side abnormality determiner 72 are very similar structures, and thus the operation and principle of the converter-side abnormality determiner 71 can be described by referring to the operation and principle of the inverter-side abnormality determiner 72 in form.

[0439] Specifically, in the flowcharts of Formulae (1) to (34), Formulae (35) to (49), Figure 10 the operation and principle of the converter-side abnormality determiner 71 can be described by substituting the subscripts U, V, and W with R, S, and T.

[0440] Therefore, in fact, the operation and principle of the converter-side abnormality determiner 71 are replaced with the operation and principle of the inverter-side abnormality determiner 72, and the repeated description is omitted.

[0441] Effects of the Modified Example of the First Embodiment

[0442] In the modified example of the first embodiment described above, Figure 10 even in a case where a 3-phase load is unbalanced or a case where a current ripple of a size that cannot be ignored or a current ripple of a frequency close to a current fundamental frequency is included in a current waveform, the abnormality of the current detector can be accurately determined.

[0443] Second Embodiment: Power Conversion Device

[0444] Next, the power conversion device of the second embodiment will be described with reference to Figure 11

[0445] The following description is not only a description of the power conversion device but also a description of an abnormality detection method of the power conversion device.

[0446] The second embodiment differs from the first embodiment in the processing of the abnormality determination section 714 and the abnormality determination section 724.

[0447] Flowchart of the Abnormality Determination Processing by the Abnormality Determination Section of the Second Embodiment: One

[0448] Next, the flowchart of the abnormality determination processing by the abnormality determination section 724 of the second embodiment will be described.

[0449] ​However, although there are two abnormality judgment units, the inverter-side abnormality judgment unit 724 and the converter-side abnormality judgment unit 714, they perform the same operation. Therefore, the operation of the abnormality judgment unit 724 of the inverter-side abnormality judgment unit 72 will be explained as a representative example.

[0450] <Regarding the operation of the fault detection unit 724 of the inverter-side fault detector 72>

[0451] Figure 11 An example flowchart illustrating the abnormal judgment process performed by the abnormal judgment unit 724 of the inverter-side abnormal judgment unit 72 according to the second embodiment of the present invention.

[0452] First, regarding Figure 11 The mathematical expressions and calculation examples of equations (51) to (53) appearing in steps S306, S309, and S312 of the flowchart are explained as follows.

[0453] Formula (51) of step S306

[0454] First, regarding the calculation example of equation (51) in step S306, it is assumed that the U-phase current detector 34 is abnormal (detection gain G). U =1+A U ≠1), V-phase current detector 35 and W-phase current detector 36 are normal (detection gain G) V =1+A V =1, detection gain G W =1+A W Let's explain the case where =1).

[0455] When using F from equations (19) to (21) above U F V F W Calculate (F) U +F V +F W ) / (F V +F W When ), it becomes the following formula (50).

[0456] (F U +F V +F W ) / (F V +F W )=﹣A U ...(50)

[0457] Therefore, according to the above equation (50), the detection gain G is expressed by the following equation (51). U .

[0458] G U= 1 + A U = 1 - (F U + F V + F W ) / (F V + F W )...(51)

[0459] Equation (52) of Step S309

[0460] Next, a calculation example of Equation (52) of Step S309 will be described with the case where the V-phase current detector 35 is abnormal (detection gain G V = 1 + A V ≠ 1), and the U-phase current detector 34 and the W-phase current detector 36 are normal (detection gain G U = 1 + A U = 1, detection gain G W = 1 + A W = 1).

[0461] When F U , F V , and F W are calculated as (F U + F V + F W ) / (F W + F U ), -A V is obtained, and thus the detection gain G V is expressed by Equation (52) shown below.

[0462] G V = 1 + A V = 1 - (F U + F V + F W ) / (F W + F U )...(52)

[0463] Equation (53) of Step S312

[0464] Next, a calculation example of Equation (53) of Step S312 will be described with the case where the W-phase current detector 36 is abnormal (detection gain G W = 1 + A W ≠ 1), and the U-phase current detector 34 and the V-phase current detector 35 are normal (detection gain G U = 1 + A U = 1, detection gain G V = 1 + A V = 1).

[0465] When using the above formulas (19C) to (21C) F U F V F W Calculate (F) U +F V +F W ) / (F U +F V When ), it becomes -A W Therefore, the detection gain G is expressed by the following equation (53). W .

[0466] G W =1+A W =1﹣(F U +F V +F W ) / (F U +F V ...(53)

[0467] <Flowchart of the anomaly detection process performed by the anomaly detection unit in the second embodiment: Part Two>

[0468] Next, regarding Figure 11 The processing of the abnormality judgment unit 724 shown will be explained.

[0469] Steps S101 to S104

[0470] Figure 11 The processing in steps S101 to S104 is related to... Figure 3 The same process applies to steps S101 through S104. Repeated explanations are omitted.

[0471] Step S305

[0472] In step S305, the anomaly determination unit 724 determines whether the above formula (44) or formula (45) is true.

[0473] If equation (44) or equation (45) is true (S305: Yes), the anomaly detection unit 724 determines that the current detector 34 of phase U is abnormal. Then, the process proceeds to step S306.

[0474] On the other hand, if the anomaly determination unit 724 determines "no" in step S305 (S305: "No"), it determines that the current detector 34 of phase U is normal. Then, the process proceeds to step S308.

[0475] Step S306

[0476] In step S306, the anomaly detection unit 724 calculates the detection gain G, for example, using equation (51). Uwhether the calculated detection gain G U is within a predetermined range.

[0477] The abnormality determination section 724 determines whether the detection gain G U is not within a predetermined range (S306: No), and proceeds to step S307.

[0478] On the other hand, in the case where step S306 is Yes, the abnormality determination section 724 determines that the current detector 34 of phase U is normal, and proceeds to step S308.

[0479] Step S307

[0480] In step S307, it is determined that the current detector 34 of phase U is abnormal. Furthermore, information indicating that the current detector of phase U is abnormal ("abnormality of current detector of phase U") is displayed on the display 73.

[0481] Then, the process proceeds to step S314. Note that step S314 is described later.

[0482] Step S308

[0483] In step S308, the abnormality determination section 724 determines whether Expression (46) or Expression (47) is established.

[0484] In the case where Expression (46) or Expression (47) is established (S308: Yes), the abnormality determination section 724 determines that the current detector 35 of phase V is abnormal. Then, the process proceeds to step S309.

[0485] On the other hand, in the case where step S308 is No (S308: No), the abnormality determination section 724 determines that the current detector 35 of phase V is normal. Then, the process proceeds to step S311.

[0486] Step S309

[0487] In step S309, the abnormality determination section 724 calculates the detection gain G V , for example, by Expression (52), and determines whether the calculated detection gain G V is within a predetermined range.

[0488] In the case where the detection gain G V is not within a predetermined range (S309: No), the process proceeds to step S310.

[0489] On the other hand, in the case where step S309 is Yes (S309: Yes), the abnormality determination section 724 determines that the current detector 35 of phase V is normal. Then, the process proceeds to step S311.

[0490] Step S310

[0491] In step S310, the abnormality judging section 724 judges that the V-phase current detector 35 has an abnormality, and causes the display 73 to display information indicating that the V-phase current detector has an abnormality ("V-phase current detector abnormality").

[0492] Then, the processing proceeds to step S314. Note that step S314 is described later.

[0493] Step S311

[0494] In step S311, the abnormality judging section 724 judges whether or not the expression (48) or the expression (49) is established.

[0495] The abnormality judging section 724 judges that the W-phase current detector 36 has an abnormality in a case where the expression (48) or the expression (49) is established (S311: Yes). Then, the processing proceeds to step S312.

[0496] On the other hand, the abnormality judging section 724 judges that the W-phase current detector 36 is normal in a case where step S311 is "No" (S311: No). Then, the processing proceeds to step S315.

[0497] Step S312

[0498] In step S312, the abnormality judging section 724 calculates the detection gain G W , for example, by the expression (53) W , and judges whether or not the calculated detection gain G W is within a predetermined range.

[0499] The abnormality judging section 724 judges that the W-phase current detector 36 has an abnormality in a case where the detection gain G W is not within the predetermined range (S312: No). Then, the processing proceeds to step S313.

[0500] On the other hand, the abnormality judging section 724 judges that the W-phase current detector 36 is normal in a case where step S312 is "Yes" (S312: Yes). Then, the processing proceeds to step S315.

[0501] Step S313

[0502] In step S313, the display 73 is caused to display information indicating that the W-phase current detector has an abnormality ("W-phase current detector abnormality"). Then, the processing proceeds to step S314.

[0503] Step S314

[0504] The processing of step S314 is substantially the same processing as that of step S112 Figure 3 ).

[0505] In step S314, following steps S102, S104, 307, S310, and S313, the next process is executed.

[0506] In step S314, the anomaly detection unit 724 causes the display 73 to show the statement "Please check the anomaly location and replace it", and the process ends.

[0507] Step S315

[0508] The processing in step S315 is essentially the same as that in step S113. Figure 3 The same processing.

[0509] In step S315, it is determined that all current detectors, including the U-phase current detector 34, the V-phase current detector 35, and the W-phase current detector 36, are normal.

[0510] Then, the process ends.

[0511] <Supplement to the above steps>

[0512] The predetermined ranges in steps S306, 309, and S312 can be determined arbitrarily.

[0513] For example, it is possible to convert G in step S306 U The predetermined range is determined to be G U >0.9 and G U <1.2(A) U >-0.1 and A U <0.2). Therefore, it is possible to detect any one of the anomalies with a detection gain less than 1 and anomalies with a detection gain greater than 1 in advance.

[0514] For example, step S106 can be used instead of step S305.

[0515] Alternatively, for example, step S108 can be used instead of the processing in step S308.

[0516] Alternatively, for example, step S110 can be used instead of the process in step S311.

[0517] <Regarding the operation of the fault detection unit 714 of the converter-side fault detector 71>

[0518] The above explanation is related to Figure 11 The following is a description of the abnormality determination unit 724 of the inverter-side abnormality determination unit 72 in the second embodiment of the flowchart example.

[0519] However, as mentioned above, Figure 2AThe converter-side abnormality determiner 71 shown in FIG. 1 is a very similar structure to the inverter-side abnormality determiner 72 shown in FIG. 2, and thus the operation and principle of the converter-side abnormality determiner 71 can be explained by referring to the operation and principle of the inverter-side abnormality determiner 72 in form. Figure 2B The inverter-side abnormality determiner 72 shown in FIG. 2 is a very similar structure to the converter-side abnormality determiner 71 shown in FIG. 1, and thus the operation and principle of the inverter-side abnormality determiner 72 can be explained by referring to the operation and principle of the converter-side abnormality determiner 71 in form.

[0520] Specifically, in the steps S306, S309, and S312 of the flowchart of the formulas (1) to (49), Figure 11 the formulas (51) to (53), the operation and principle of the converter-side abnormality determiner 71 can be explained in the same manner by substituting the subscripts U, V, and W with R, S, and T.

[0521] Therefore, in fact, the operation and principle of the converter-side abnormality determiner 71 are replaced with the operation and principle of the inverter-side abnormality determiner 72, and the repeated explanation is omitted.

[0522] <Effects of the 2nd Embodiment>

[0523] In the 2nd Embodiment, even in the case where the 3-phase load is unbalanced or the case where the current ripple of a size that cannot be ignored or the current ripple of a frequency close to the fundamental frequency of the current is included in the current waveform, the abnormality of the current detector can be accurately determined.

[0524] Also, in the 1st Embodiment, in order to estimate the detection gain (for example, G U = 1 + A U ) of the abnormality detector, the estimated value of the current amplitude I (for example, the current command value) needs to be used, and in contrast, in the 2nd Embodiment, even if the current amplitude I is unknown, the detection gain (for example, G U = 1 + A U ) of the abnormality detector can be estimated with high accuracy by the formulas (51) to (53).

[0525] As described above, in the 2nd Embodiment, the estimation accuracy of the detection gain is improved, and thus the initial deterioration of the current detector in which the detection gain G * (* any one of U, V, and W) approaches 1 can be detected with higher accuracy.

[0526] <Variant 1 of the 2nd Embodiment>

[0527] Next, the variant 1 of the 2nd Embodiment of the present application will be described with reference to Figure 12 and Figure 13 .

[0528] In the above 2nd Embodiment, as the circuit structure, in Figure 2A , Figure 2B , Figure 3In the process, the following steps are used: Figure 11 The processing flow shown replaces the processing flow of the first embodiment. Figure 3 In a variation of the second embodiment shown below, the circuit structures of the converter-side fault detector and the inverter-side fault detector are changed.

[0529] Furthermore, in variation 1 of the second embodiment, the processing flow is applicable Figure 11 The flowchart shown.

[0530] Figure 12 This illustrates a circuit structure example of the converter-side fault detector 71B in Modified Example 1 of the second embodiment of the present invention.

[0531] Figure 13 This section illustrates a circuit structure example of the inverter-side fault detector 72B in Modified Example 1 of the second embodiment of the present invention.

[0532] Figure 12 , Figure 13 The converter-side fault detector 71B and inverter-side fault detector 72B shown respectively are... Figure 2A , Figure 2B The difference between the converter-side fault detector 71 and the inverter-side fault detector 72 shown is that, in the variation 1 of the second embodiment, a multiplier (715 [715R, 715S, 715T], 725 [725U, 725V, 725W]), an adder (716, 726), and a filter (717, 727) are added. The output (H) of the filter (717, 727) is... C H I The result is input to the exception detection unit (714B, 724B).

[0533] Furthermore, the multipliers (715 [715R, 715S, 715T], 725 [725U, 725V, 725W]) are appropriately referred to as "multipliers of the second system," the adders (716, 726) are appropriately referred to as "adders of the second system," and the filters (717, 727) are appropriately referred to as "filters of the second system." The reason for adding "second system" is to distinguish them from the adders 711, multipliers 712 [712R, 712S, 712T], 722 [722U, 722V, 722W], and filters 723 [723U, 723V, 723W].

[0534] Furthermore, the anomaly detection processing in the anomaly detection unit (714B, 724B) of the second embodiment's modified example 1 is similar to... Figure 11 They are the same, but the mathematical expressions used in steps S306, S309, and S312 are different.

[0535] Specifically, the difference is that in step S306, the detection gain G is calculated using the following equation (61) instead of equation (51) U In step S309, the detection gain G is calculated using the following equation (62) instead of equation (52) V In step S312, the detection gain G is calculated using the following equation (63) instead of equation (53) W .

[0536] Equations (61) to (63) used in steps S306, S309, and S312 are shown below. The detection gain can be derived by equations (61) to (63).

[0537] Derivation of Equations (61) to (63) and Detection Gain

[0538] Suppose that the U-phase current detector (34) is abnormal (detection gain G U ≠ 1), the V-phase current detector (35) and the W-phase current detector (36) are normal (detection gain G U ≠ 1), and the detection gain G V ≠ 1), and the detection gain G V ≠ 1), and the detection gain G W ≠ 1), and the detection gain G W ≠ 1).

[0539] When I U 2 + I V 2 + I W 2 , this I U 2 + I V 2 + I W 2 When filtering (removing the periodic variation amount of the trigonometric function) of the high-frequency component included in I U 2 + I V 2 + I W 2 , the filter output H I becomes equation (54).

[0540] H I = I 2 (A U 2 + 2A U + 3) / 2... (54)

[0541] According to equations (19) to (21), in AU = 0 U = F V = F W = 0, so the latter is deformed while paying attention not to divide by 0. If the equation (20) is deformed, it becomes equation (55).

[0542] A U I 2 = -4F V ... (55)

[0543] A is multiplied to both sides of equation (19) U , and substituted into equation (55), it becomes equation (56).

[0544] A U F U = -2F V (A U 2 + A U )... (56)

[0545] A is multiplied to both sides of equation (54) U , and substituted into equation (55), it becomes equation (57).

[0546] A U H I = -2F V (A U 2 + 2A U + 3)... (57)

[0547] If equation (57) is subtracted from equation (56), it becomes equation (58).

[0548] A U (F U - H I ) = -2F V (- A U - 3)... (58)

[0549] If equation (58) is arranged, A U becomes equation (59).

[0550] A U = 6F V / (F U - H I - 2F V )... (59)

[0551] According to equation (20), equation (21), F V = F W . Therefore, F V = F WSubstituting into equation (59) to make the F contained in equation (59) V With F W When the degree of influence is equal, equation (59) becomes equation (60).

[0552] A U =3(F V +F W ) / (F U -H I -F V -F W ...(60)

[0553] Therefore, according to equation (60), the detection gain G is expressed by equation (61). U .

[0554] G U =1+A U =1+3(F V +F W ) / (F U -H I -F V -F W ...(61)

[0555] If the same calculation is performed, then in the case of an anomaly in the V-phase current detector 35 (detection gain G) V =1+A V ≠1), U-phase current detector 34 and W-phase current detector 36 are normal (detection gain G) U =1+A U =1, Detection gain G W =1+A W In the case of =1), the detection gain G is expressed by equation (62). V .

[0556] G V =1+A V =1+3(F W +F U ) / (F V -H I -F W -F U ...(62)

[0557] If the same calculation is performed, then in the case of an anomaly in phase W current detector 36 (detection gain G) W =1+A W ≠1), U-phase current detector 34 and V-phase current detector 35 are normal (detection gain G) U =1+A U =1, Detection gain G V =1+A V= 1) is represented by Equation (63) W .

[0558] G W = 1 + A W = 1 + 3(F U + F V ) / (F W - H I - F U - F V )...(63)

[0559] As described above, the detection gains (G U , G V , G W ) of the current detectors obtained by the inverter-side abnormality determiner 72B Figure 13 described by Equations 61, 62, 63 are able to easily detect abnormalities with respect to the detection gain of the current detector obtained by the inverter-side abnormality determiner 72 described by Equation 60. Figure 2B

[0560] The above is a description of the inverter-side abnormality determiner 72B Figure 13 described above, but with respect to the converter-side abnormality determiner 71B Figure 12 described above, the subscripts U, V, W are simply replaced with R, S, T, and the same can be derived. In fact, the repeated description is omitted.

[0561] Effects of Modification Example 1 of the 2nd Embodiment

[0562] The detection gains (G U , G V , G W ) of the current detectors obtained by the inverter-side abnormality determiner 72B Figure 13 described in Modification Example 1 of the 2nd Embodiment have an effect of being able to easily detect abnormalities with respect to the detection gain of the current detector obtained by the abnormality determiner 72 described by Equation 60. Figure 2B

[0563] Modification Example 2 of the 2nd Embodiment: Power Conversion Device

[0564] Next, Modification Example 2 of the 2nd Embodiment of the present application will be described with reference to Figure 14 and Figure 15 .

[0565] Figure 14 represents an example of a circuit structure of the converter-side abnormality determiner 71C in Modification Example 2 of the 2nd Embodiment of the present application.

[0566] Figure 15 ​​A circuit configuration example of the inverter-side abnormality determiner 72C in Modification 2 of the 2nd embodiment of the present application is shown.

[0567] Figure 14 Figure 15 The abnormality determiners (the converter-side abnormality determiner 71C, the inverter-side abnormality determiner 72C) shown in Figure 2A Figure 2B The difference between the abnormality determiners (the converter-side abnormality determiner 71, the inverter-side abnormality determiner 72) shown in Figure 14 Figure 15 In Modification 2 of the 2nd embodiment, multipliers (multiplication units: 715 [715RC, 715SC, 715TC], 725 [725UC, 725VC, 725WC]), adders (addition units: 716C, 726C), and filters (filter units: 717C, 727C) are added in C I The outputs (K U , K V ) of the filters (filter units: 717C, 727C) are input to the abnormality determination sections (714C, 724C).

[0568] The flow of the process is applied to the flowchart of Figure 11 However, as described later, the mathematical expressions used in steps S306, S309, and S312 are different from those of Figure 11

[0569] In addition, the converter-side abnormality determiner 71C and the inverter-side abnormality determiner 72C shown in Figure 14 Figure 15 The difference between the converter-side abnormality determiner 71B and the inverter-side abnormality determiner 72B shown in Figure 12 Figure 13 is the difference in the input signals to the multipliers 715 and 725.

[0570] For example, in Figure 15 , the 1st multiplier 725UC of the multipliers 725 (1st, 2nd, and 3rd: 725UC, 725VC, 725WC) is I U × I V , the 2nd multiplier 725VC is I V × I W , and the 3rd multiplier 725WC is I V × I W In Figure 13 , the 1st multiplier of the multipliers 725 (1st, 2nd, and 3rd) is I U 2 , the 2nd multiplier is I V 2 , and the 3rd multiplier is I W ​​​2 .

[0571] Should Figure 15 and Figure 13 The different wiring of the input signals in the multiplier 725 (first, second, and third), or Figure 15 and Figure 2A , Figure 2B The differences in circuits and Figure 11 The differences in the process lead to the differences in the mathematical formulas for calculation, which will be explained below.

[0572] Mathematical formula for the modified steps in Variation 2 of the second embodiment

[0573] Next, regarding Figure 11 The mathematical expressions in steps S306, S309, and S312 illustrate the use of mathematical expressions in variation 2 of the second embodiment. Figure 15 When determining the circuit structure, what method should be used for the mathematical expressions in the above steps?

[0574] The anomaly detection processing in the anomaly detection unit (714, 724) of the second embodiment of the modified example 2 is the same as... Figure 11 The process is the same, but as mentioned above, the mathematical formulas used in steps S306, S309, and S312 are different.

[0575] Specifically, the difference lies in that, in step S306, the detection gain G is calculated using equation (68) described later, instead of equation (51). U In step S309, the detection gain G is calculated by equation (69) described later, instead of equation (52). V In step S312, the detection gain G is calculated by equation (70) described later, instead of equation (53). W .

[0576] The following indicates that based on Figure 15 The circuit structure is derived, and the equations (68) to (70) used in steps S306, S309, and S312 are derived, and the detection gain can be derived through equations (68) to (70).

[0577] Assuming the U-phase current detector 34 is malfunctioning (detection gain G) U =1+A U ≠1), V-phase current detector 35 and W-phase current detector 36 are normal (detection gain G) V =1+A V =1, detection gain G W =1+A W =1).

[0578] Calculate I according to equations (12) to (14).U I V +I V I W +I W I U (Adder 726C:) Figure 15 ).

[0579] Then, on the calculated I U I V +I V I W +I W I U Apply removal I U I V +I V I W +I W I U Filtering of high-frequency components (Filter 727C): Figure 15 When (removing the periodic variations of trigonometric functions), the filter output K of filter 727C is... I It becomes the following formula (64).

[0580] K I = -1 / 4 × I 2 (3+2A U ...(64)

[0581] According to equations (19) to (21) above, in A U =0 F U =F V =F W =0, so be careful not to divide by 0 while transforming.

[0582] Multiply both sides of equation (64) by A U Substituting this into equation (20), we get equation (65).

[0583] A U K I =3F V +2F V A U ...(65)

[0584] If we rearrange the above equation (65), then A U It becomes the following equation (66).

[0585] A U =3F V / (K I -2F V ...(66)

[0586] According to equations (20) and (21), FV =F W Therefore, in F V =F W Substituting into equation (66), so that F contained in equation (66) V With F W When the degree of influence is equal, equation (66) becomes equation (67).

[0587] A U =3 / 2×(F V +F W ) / (K I -F V -F W ...(67)

[0588] Therefore, according to equation (67), the detection gain G is expressed by the following equation (68). U .

[0589] G U =1+A U =1 + 3 / 2 × (F V +F W ) / (K I -F V -F W ...(68)

[0590] If the same calculation is performed, the V-phase current detector 35 is abnormal (detection gain G). V =1+A V ≠1), U-phase current detector 34 and W-phase current detector 36 are normal (detection gain G) U =1+A U =1, Detection gain G W =1+A W In the case of =1), the detection gain G is expressed by the following equation (69). V .

[0591] G V =1+A V =1 + 3 / 2 × (F W +F U ) / (K I -F W -F U ...(69)

[0592] If the same calculation is performed, then in the case of an anomaly in phase W current detector 36 (detection gain G) W =1+A W ≠1), U-phase current detector 34 and V-phase current detector 35 are normal (detection gain G) U =1+A U =1, Detection gain GV =1+A V In the case of =1), the detection gain G is expressed by the following equation (70). W .

[0593] G W =1+A W =1 + 3 / 2 × (F U +F V ) / (K I -F U -F V ...(70)

[0594] As described above, the inverter-side fault detector 72C shown in equations (68), (69), and (70) Figure 15 The detection gain (G) of the current detector obtained U G V G W Relative to Figure 2B The current detector obtained by the inverter-side fault detector 72 shown has a detection gain that can easily detect faults.

[0595] The above is about Figure 15 The description of the inverter-side fault detector 72C shown, but regarding... Figure 14 The converter-side fault detector 71C shown can be derived in the same way by simply replacing the subscripts U, V, and W with R, S, and T. In fact, redundant explanations are omitted.

[0596] <Effects of Modification 2 of Embodiment 2>

[0597] Inverter-side fault detector 72C in Modification 2 of Embodiment 2 ( Figure 15 The detection gain (G) of the current detector obtained U G V G W Relative to Figure 2B The current detector obtained by the inverter-side fault detector 72 shown has the effect of easily detecting faults.

[0598] Third Embodiment: Power Conversion Device

[0599] Next, refer to Figure 16 and Figure 17 The power conversion device according to the third embodiment of the present invention will be described.

[0600] Figure 16 This section illustrates an example of the circuit structure of the converter-side fault detector 71D and the inverter-side fault detector 72D of the power conversion device according to the third embodiment of the present invention.

[0601] Figure 16 The diagram shown in the upper section is the converter-side fault detector 71D. Figure 16 The diagram shown in the lower section is the inverter-side fault detector 72D.

[0602] Regarding the converter-side fault detector 71D and inverter-side fault detector 72D in the third embodiment, Figure 16 The inverter-side fault detector 72D shown in the lower section will be used as an example for explanation.

[0603] Figure 16 The inverter-side fault detector 72D shown in the lower section is configured to include an adder 721D, three multipliers 722 (722U, 722V, 722W), three filters 723 (723U, 723V, 723W), and a fault detection unit 724D. In addition, three filters (second filters) 728 (728U, 728V, 728W) and three adders / subtractors 729 (729U, 729V, 729W) are newly added.

[0604] Next, the structure added to the inverter-side fault detector 72D will be explained.

[0605] Current detectors 34, 35, and 36 are input to three 723 filters (723U, 723V, and 723W) respectively. Figure 1 The current detection signal (U phase, V phase, W phase of 3-phase AC).

[0606] Input current detection signals (I0) to the first input terminal of each of the three adders / subtractors 729 (729U, 729V, 729W). U I V I W The inverted signals (I) of the filters 723 (723U, 723V, 723W) are input to the second input terminal respectively. UDC I VDC I WDC ).

[0607] Furthermore, the outputs of the three adders / subtractors 729 (729U, 729V, 729W) are respectively input to the three input terminals of the adder 721D.

[0608] Other structures of the inverter-side fault detector 72D Figure 2B The inverter-side fault detector 72 shown is the same.

[0609] The fault detection unit 724D in the inverter-side fault detector 72D performs, for example... Figure 3 or Figure 10 The first embodiment shown (including variations) or Figure 11 Any one of the processes of the second embodiment (including the modified examples) shown.

[0610] In addition, the operation of the filter 728 (728U, 728V, 728W) and the adder / subtracter 729 (729U, 729V, 729W) newly added in the lower stage of the Figure 16

[0611] The filter 728 (728U, 728V, 728W) removes an alternating current component included in an input waveform (for example, a current I U ) and outputs a direct current component included in the input waveform (for example, a current I UDC ).

[0612] The adder / subtracter 729 (729U, 729V, 729W) outputs an alternating current component (for example, a current I UA ) included in a current (for example, a current I U ) by subtracting an offset component (for example, a current I UDC ) from an input current (for example, a current I U ).

[0613] <Current waveform example based on filter and adder / subtracter>

[0614] Figure 17 A current waveform example in each of the output of the filter 728U and the adder / subtracter 729U in the inverter-side abnormality determiner 72D of the power conversion device of the third embodiment of the present application is shown.

[0615] In Figure 17 , a current I U is a current detection signal of the U phase of the current detector 34. In addition, a current signal I UDC is an output signal of the filter 728U. In addition, a current I UA is an output signal of the adder / subtracter 729U.

[0616] In addition, Figure 17 in the current I U , the current I UDC , and the current I UA , the horizontal axis indicates time (passage of time).

[0617] The current signal I UDC as the output signal of the filter 728U is input to the adder / subtracter 729U after being inverted, and thus in Figure 17 , the amount of the current signal I UDC is subtracted from the current I U , and the current I UA becomes the output signal of the adder / subtracter 729U. ​

[0618] In Figure 17 , the current I U of the U-phase is shown. UDC , the output signal I UA of the filter 723U. V , the output signal I VDC of the adder / subtracter 729U. VA , the current I W of the W-phase. WDC , the output signal I WA of the filter 723W. The same is true for the I

[0619] That is, as shown in the relationship of the current I Figure 17 of the U-phase. U , the output signal I UDC of the filter 723U. UA of the adder / subtracter 729U. Figure 16 , the filter 728 (728U, 728V, 728W) and the adder / subtracter 729 (729U, 729V, 729W) in the lower drawing, the offset component included in the current detection value can be removed.

[0620] In the third embodiment, the following feature is provided: by removing the offset component (DC component) included in the current detection value in advance, even in the case where the offset component is included in the current detection value, the abnormality degree A * of the detection gain abnormality of the current detector can be detected with high accuracy.

[0621] Effects of the Third Embodiment

[0622] As described above, in the third embodiment, the following effects are provided: by removing the offset component (DC component) included in the current detection value in advance, even in the case where the offset component (DC component) is included in the current detection value, the abnormality degree A * of the detection gain abnormality of the current detector can be detected with high accuracy.

[0623] Fourth Embodiment: Power Conversion Device

[0624] Next, the fourth embodiment of the power conversion device of the present application will be described with reference to Figure 18 .

[0625] Figure 18 The circuit structure example of the power conversion device 101 of the fourth embodiment of the present application, and the connection structure example with the alternating current power source 1, the motor 4 are shown. In Figure 18 , the same symbols are attached to the same structures as those of the first embodiment of the power conversion device shown in Figure 1 .

[0626] In Figure 18 In Figure 18 In the power conversion device 101 of the 4th embodiment shown in Figure 1 The 3-level converter unit 2 and the inverter unit 3 in the power conversion device 100 of the 1st embodiment shown in

[0627] Converter unit 2B of 2 levels

[0628] In addition, in Figure 18 In addition, in Figure 1 In addition, in

[0629] In addition, since there is no C wiring but only P wiring and N wiring, a direct current voltage detector that detects a direct current voltage is constituted by one direct current voltage detector 29 that detects a potential between electrodes of a smoothing capacitor 22, 23 on the converter side.

[0630] Figure 18 The converter power conversion section 21B in the converter unit 2B shown in

[0631] Two transistors (1st and 2nd transistors) are connected in series before the P wiring 40 and the N wiring 42. Diodes (1st and 2nd diodes) that are inversely connected in parallel are connected to the two transistors (1st and 2nd transistors), respectively.

[0632] The collector of the 1st transistor is connected to the P wiring 40.

[0633] The emitter of the 2nd transistor is connected to the N wiring 42.

[0634] In Figure 18 In the 1st embodiment shown in

[0635] In Figure 18 In the 1st embodiment shown in

[0636] In addition, although not directly illustrated in Figure 18 the R-phase power line is connected to the connection points of the first and second transistors of the converter power conversion unit 21B (first converter power conversion unit 21B), and the R-phase power is input to the converter power conversion unit 21B (first converter power conversion unit 21B).

[0637] In addition, although not directly illustrated in Figure 18 the T-phase power line is connected to the connection points of the first and second transistors of the converter power conversion unit 21B (third converter power conversion unit 21B), and the T-phase power is input to the converter power conversion unit 21B (third converter power conversion unit 21B).

[0638] However, the direct-current power lines, that is, the P wiring 40 and the N wiring 42 of the first to third converter power conversion units 21B are shared in the first to third converter power conversion units 21B.

[0639] The R-phase, S-phase, and T-phase of the three-phase alternating current of the alternating current power source 1 are input to the three converter power conversion units 21 (first to third converter power conversion units 21B), but are shared on the direct-current power side after conversion by the converter power conversion units 21B. That is, the three-phase alternating current power (voltage) of the R-phase, S-phase, and T-phase is converted to one (common) direct-current power (voltage).

[0640] In addition, the first to third converter power conversion units 21 are collectively controlled by the converter control device 5.

[0641] The R-phase current detector 26, S-phase current detector 27, and T-phase current detector 28 are provided in the converter unit 2B and detect the currents flowing in the R-phase, S-phase, and T-phase of the three-phase alternating current, respectively.

[0642] In addition, Figure 18 The smoothing capacitor 22 and the smoothing capacitor 23 in the converter unit 2B illustrated in Figure 1 are described directly after the smoothing capacitor 22 and the smoothing capacitor 23 in the converter unit 2 illustrated in

[0643] However, Figure 18 The converter unit 2B illustrated in Figure 1 does not have the C wiring 41 (neutral point potential) in the converter unit 2 illustrated in Figure 18 As illustrated in , in the case where the smoothing capacitor 22 and the smoothing capacitor 23 are connected in series, the electrostatic capacitance of the integrated capacitor decreases, but the withstand voltage of the both-end voltage of the integrated capacitor increases.

[0644] Inverter unit 3B of 2 levels

[0645] In Figure 18 , the inverter unit 3B replaces the inverter unit 3 of 3 levels in Figure 1 with the inverter unit 3B of 2 levels.

[0646] As for the structure of the inverter unit 3B of 2 levels in Figure 18 , because it is a common change in structure with the converter unit 2B in Figure 18 , the repeated explanation is omitted in fact.

[0647] Power conversion device 101

[0648] Figure 18 The other structures of the power conversion device 101 of the 4th embodiment shown in FIG. 10 except for the converter unit 2B and the inverter unit 3B are substantially the same as those of the power conversion device 100 of the 1st embodiment, so the repeated explanation is omitted appropriately.

[0649] As described above, the power conversion device 101 is provided with the converter unit 2B and the inverter unit 3B of 2 levels.

[0650] Depending on the difference of the conversion mode (pulse waveform) of 3 levels and 2 levels, the current pulsation is different, but in the power conversion device 101, the converter-side abnormality determiner 71 performs the same processing as the 1st embodiment based on the detection values of the current detectors 26, 27, 28, whereby the abnormality of the current detectors 26, 27, 28 can be determined appropriately.

[0651] In addition, the inverter-side abnormality determiner 72 performs the same processing as the 1st embodiment based on the detection values of the current detectors 34, 35, 36, whereby the abnormality of the current detectors 34, 35, 36 can be determined appropriately.

[0652] Effects of the 4th embodiment

[0653] The power conversion device 101 is provided with the converter unit 2B and the inverter unit 3B of 2 levels, whereby the circuit structure becomes simple, having the effects of low cost and miniaturization.

[0654] 5th embodiment: power conversion device

[0655] Next, the power conversion device of the 5th embodiment of the present application is described with reference to Figure 19 and Figure 20 .

[0656] Figure 19 The circuit structure example of the power conversion device 102 of the 5th embodiment of the present application, and the connection structure example with the alternating current power source 1 and the motor 4 are shown. Furthermore, in Figure 19 In the first embodiment of the power conversion device shown in FIG. 1, the same reference numerals are assigned to the same structures. Figure 1

[0657] The power conversion device 102 of the fifth embodiment is provided with a converter-side output estimator 74 and an inverter-side output estimator 75 in addition to the power conversion device 100 of the first embodiment.

[0658] In the first embodiment of the power conversion device shown in FIG. 1, the same reference numerals are assigned to the same structures. Figure 19

[0659] The operation processing of the converter-side output estimator 74 is constituted, for example, by executing a program stored in a memory by a processor not shown.

[0660] The method of estimating the accurate detection value related to the detection object of the abnormal current detector in the fifth embodiment utilizes the relationship that, in the power conversion device 102, if each current detector is in a normal state, the resultant current value obtained by adding the detection values of the converter-side current detectors 26, 27, 28 is zero.

[0661] According to this relationship that the resultant current value is zero, in the case where any one of the current detectors is abnormal, by subtracting the value obtained by adding the detection values of the two healthy current detectors from zero, the accurate detection value of the detection object of the abnormal current detector can be estimated.

[0662] Circuit structure example of the converter-side output estimator 74

[0663] Next, the specific circuit structure and operation of the converter-side output estimator 74 will be described.

[0664] Figure 20 The circuit structure example of the part of the power conversion device of the fifth embodiment of the present application including the converter-side output estimator 74 is shown.

[0665] In the first embodiment of the power conversion device shown in FIG. 1, the same reference numerals are assigned to the same structures. Figure 20

[0666] In the first embodiment of the power conversion device shown in FIG. 1, the same reference numerals are assigned to the same structures. Figure 20 R In the first embodiment of the power conversion device shown in FIG. 1, the same reference numerals are assigned to the same structures.​​​​S The detected value of the T-phase current detector 28 is set as I T In addition, Figure 20 An example when the T-phase current detector 28 is abnormal is shown.

[0667] The converter-side abnormality determiner 71 is input with the detected value (I R ) of the R-phase current detector 26, the detected value (I S ) of the S-phase current detector 27, and the detected value (I T ) of the T-phase current detector 28.

[0668] Then, the converter-side abnormality determiner 71 outputs abnormality determination information of the abnormal current detector to the converter-side output estimator 74 when it is determined that any one of the above R-phase, S-phase, and T-phase current detectors is abnormal.

[0669] In Figure 20 , a case where the converter-side abnormality determiner 71 determines that the T-phase current detector 28 is abnormal is shown.

[0670] Then, the converter-side abnormality determiner 71 outputs information that the T-phase current detector 28 is abnormal (I T abnormality determination information) to the converter-side output estimator 74.

[0671] The converter-side output estimator 74 subtracts the sum of the detected value (I R ) of the R-phase current detector 26 and the detected value (I S ) of the S-phase current detector 27 from zero (0) to calculate an estimated value (I TH ) of the detection of the T-phase current detector 28 estimated to be normal. Then, the estimated value (I TH ) is input to the selection section 74a.

[0672] The selection section 74a of the converter-side output estimator 74 inputs the detected value (I T ) of the T-phase current detector 28 and the estimated value (I TH ) of the T-phase current detector 28, and in a case where information that the T-phase current detector 28 is abnormal (I T abnormality determination information) is input from the converter-side abnormality determiner 71, selects the estimated value (I TH ) of the T-phase current detector 28 and outputs it to a predetermined transmission destination (in this example, the converter control device 5).

[0673] In addition, in a case where information that the T-phase current detector 28 is abnormal (I T abnormality determination information) is not input from the converter-side abnormality determiner 71, the detected value (I T) and output to a predetermined transmission destination (in this case, the inverter control device 6).

[0674] With this structure, in the case where the T-phase current detector 28 is abnormal, an appropriate estimated value can be output instead of the detection value of the current detector 28.

[0675] In the case where the T-phase current detector 28 is abnormal, the structure is shown in Figure 20 . The same structure is also applied to the other R-phase and S-phase current detectors. Also, in the case where it is abnormal, an appropriate estimated value can be output.

[0676] For example, in the case of the R-phase current detector 26, the structure in which the T-phase current detector 28 is replaced by the R-phase current detector 26 is adopted, and in the case of the S-phase current detector 27, the structure in which the T-phase current detector 28 is replaced by the S-phase current detector 27 is adopted.

[0677] <About the Inverter Side Output Estimator 75>

[0678] In addition, in Figure 20 , the inverter side (the inverter side output estimator 75) is described, but the same structure is also applied to the inverter side, and in the case where it is abnormal, an appropriate estimated value can be output, as long as the structure in which the R-phase is replaced by the U-phase, the S-phase is replaced by the V-phase, and the T-phase is replaced by the W-phase is adopted. In addition, the selection section 74a is replaced by the selection section 75a, and the predetermined transmission destination, the inverter control device 5 is replaced by the inverter control device 6.

[0679] In Figure 20 , the structure of the inverter side output estimator 75 is shown. In Figure 20 , an example in the case where the W-phase current detector 36 is abnormal is shown.

[0680] <About the "Temporary Operation">

[0681] As described above, in the power conversion device 102 of the 5th embodiment, in the case where it is determined that the current detector is abnormal, based on the detection value of the sound current detector other than the abnormal current detector, the normal detection value of the detection object of the abnormal current detector is estimated.

[0682] With this structure, the power conversion device 102 can be used without replacing the abnormal current detector. For example, until the next periodic inspection (predetermined period), the power conversion device can be continued to be operated. Such an operation method is called "temporary operation".

[0683] By performing this "expedient operation", it is not necessary to "unexpectedly stop" the power conversion device 102.

[0684] With respect to the "expedient operation" described above, in the 2-level system of the 4th embodiment shown in Figure 18 the same can be performed as well.

[0685] <Effects of the 5th Embodiment>

[0686] In the power conversion device 102 of the 5th embodiment, in a case where it is determined that the current detector has an abnormality, a normal detection value of the detection object of the current detector having the abnormality is estimated based on a detection value of a sound current detector other than the current detector having the abnormality.

[0687] By adopting this structure, the following effects are obtained: it is possible to use the power conversion device 102 without replacing the current detector having the abnormality.

[0688] For example, there is an effect that it is possible to continue the operation of the power conversion device until the next regular inspection (predetermined period).

[0689] <Other Embodiments>

[0690] The present application is not limited to the embodiments described above, and various modifications are included within the scope of the present application without departing from the spirit of the present application. For example, the above-described embodiments are exemplified in order to easily understand the present application, and are not limited to necessarily having all the structures described. In addition, a part of the structure of an embodiment can be replaced with a part of the structure of another embodiment, and it is also possible to add, delete, or replace a part or all of the structure of another embodiment to the structure of an embodiment.

[0691] Hereinafter, other embodiments and modifications will be described.

[0692] <Transistor>

[0693] In the description of the 1st embodiment, Figure 1 In the description of the 1st embodiment,

[0694] <Number of phases of wiring of alternating current circuit>

[0695] Based on Figure 1 In the first to third embodiments, the wiring of the AC circuit is assumed to be three-phase, but the number of phases of the AC circuit wiring in the anomaly judgment calculation is not limited to three-phase.

[0696] By performing the same calculations as Equations (9) to (70) in the first to third embodiments (including variations) (product operation of the current detection value of each phase and the sum of the current detection values, and judgment method based on the filter operation output), it can also be applied to the abnormal judgment of current detectors configured in all phases of a current circuit with an arbitrary number of phases (e.g., 4 phases, 5 phases, 6 phases) larger than 3 phases.

[0697] Level Number of Power Conversion Devices

[0698] exist Figure 1 The first embodiment shown or Figure 18 In the fourth embodiment shown, a 3-level converter or a 2-level converter is used as an example.

[0699] However, the number of levels of a level converter is not limited to 3 levels or 2 levels.

[0700] It can also be applied to the anomaly detection of current detectors configured in all phases between the power converter and the power supply or between the power converter and the load in any multilevel converter (e.g., 5-level, 7-level).

[0701] Prevention and Response to Display-Based Anomalies

[0702] exist Figure 11 In the second embodiment shown, for example, the detection gain (G) containing information about the degree of anomaly of the current detector can be estimated with high accuracy using equations (51) to (53). U or G V or G W Therefore, it is also possible to include Figure 11 The detection gain values ​​calculated in steps S306, S309, and S312 are displayed on the display 73. Figure 1 ).

[0703] In this way, we can detect early signs of abnormalities, prevent them from occurring, and prepare in advance to deal with them.

[0704] Display-based prediction of the period until an anomaly occurs

[0705] exist Figure 11 In the second embodiment shown, for example, the detection gain (G) containing information about the degree of anomaly of the current detector can be estimated with high accuracy using equations (51) to (53).U or G V or G W Therefore, the converter-side fault detector 71 or the inverter-side fault detector 72 can store the history of the abnormal pre-condition value (the abnormal pre-condition value refers to the abnormal value that has not been reached for fault judgment) of the current detector's detection value (e.g., execution date and time, abnormal pre-condition value). Based on the history of the abnormal pre-condition value, it can grasp the changes in the abnormal pre-condition value obtained by the current detector, predict the period until the output of the current detector exceeds the predetermined threshold used for fault judgment, that is, the period until the fault occurs, and make the display 73 ( Figure 1 The prediction result is displayed.

[0706] By adopting this method, we can detect early signs of anomalies, prevent their occurrence in advance, and prepare for their response.

[0707] Structure for removing offset components from current detection values

[0708] In indicating the third embodiment Figure 16 In the inverter-side fault detector 72D of the lower section, filters 728 (728U, 728V, 728W) and adders / subtractors 729 (729U, 729V, 729W) are used to remove the offset component contained in the current detection value.

[0709] However, the structure is not limited to the above as long as the purpose is to remove the offset component contained in the current detection value.

[0710] For example, instead of filter 728 and adder / subtractor 729, a high-pass filter or the like can be used to allow frequencies other than DC to pass through.

[0711] Software and Hardware Processing

[0712] In addition, Figure 19 In the fifth embodiment shown, regarding the processing performed by the converter-side fault detector 71, the converter-side output estimator 74, the inverter-side fault detector 72, and the inverter-side output estimator 75, an example of software processing is shown, in which a program stored in memory is executed by a processor (not shown).

[0713] However, it is not limited to processing through software. Some or all of the above processing can also be performed through hardware circuits.

[0714] The conversion objects of power conversion devices

[0715] exist Figure 1 The first embodiment shown Figure 18In the fourth embodiment shown, the power converter (converter unit 2) that converts alternating current to direct current, or the power converter (inverter unit 3) that converts direct current to alternating current is exemplified, but is not limited thereto.

[0716] For example, an AC converter (e.g., transformer, AC-AC power converter) that converts alternating current to alternating current can also be provided between the power supply and the load.

[0717] Alternatively, an AC converter (e.g., transformer) that converts alternating current voltage to alternating current can also be provided between the power supply and the power converter (converter unit 2).

[0718] Alternatively, an AC converter (e.g., transformer) that converts alternating current voltage to alternating current can also be provided between the power converter (inverter unit 3) and the load (motor 4).

[0719] The abnormality determination of the current detector provided in all phases (e.g., 3 phases) between the power converter and the power supply, or between the power converter and the load in the above structure can also be applied.

[0720] Further, regarding the abnormality determination of the current detector, the structure and method described in Figure 2A , Figure 2B , Figure 3 , Figure 10 , Figure 11 , Figure 13 , Figure 15 , Figure 16 can be applied.

[0721] "Regarding the Position of the Current Detector and the Abnormality Determinator"

[0722] In Figure 1 , Figure 18 , Figure 19 , a current detector (26, 27, 28) is provided between the power supply 1 and the converter unit (2, 2B), and the abnormality determination of the current detector is performed by the converter-side abnormality determinator 71. In addition, a current detector (34, 35, 36) is provided between the inverter unit (3, 3B) and the motor (load) 4, and the abnormality determination of the current detector is performed by the inverter-side abnormality determinator 72.

[0723] However, it is not necessary to provide the current detector, the converter-side abnormality determinator 71, and the inverter-side abnormality determinator 72 on both the converter side and the inverter side. Depending on the situation, there is a method of providing the current detector, the converter-side abnormality determinator 71, and the inverter-side abnormality determinator 72 on one of the converter side and the inverter side.

[0724] In this case, Figure 2A the inverter-side abnormality determiner 72, Figure 2B the circuit structure of the inverter-side abnormality determiner 72, Figure 3 、 Figure 10 、 Figure 11 the flow (flowchart) of the abnormality determination process shown in FIG. 9 is also effective. In addition, Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 the circuit structure of the converter-side abnormality determiner and the inverter-side abnormality determiner shown in FIG. 10 is also effective.

[0725] "Current detector using shunt resistor and its configuration"

[0726] In Figure 1 、 Figure 18 、 Figure 19 , a current detector (34, 35, 36) is provided between the inverter unit (3, 3B) and the motor (load) 4, and abnormality determination of the current detector is performed by the inverter-side abnormality determiner 72.

[0727] However, the current detector is not limited to between the inverter unit (3, 3B) and the motor (load) 4.

[0728] Figure 22 A circuit structure example of a 3-shunt method in which shunt resistors (34B, 35B, 36B) are provided as current detectors on the DC power source side of the inverter unit 3C in the power conversion device 103 is shown.

[0729] In Figure 22 , the inverter unit 3C is configured to include inverter power conversion sections 31U, 31V, 31W. On the N-wire 42 side of each of the inverter power conversion sections 31U, 31V, 31W, a shunt resistor 34B, 35B, 36B for measuring an alternating current is provided.

[0730] When the inverter power conversion sections 31U, 31V, 31W of the inverter unit 3C operate and alternating currents flow through them, respectively, the shunt resistors 34B, 35B, 36B detect and measure the alternating currents of the U-phase, V-phase, and W-phase of the 3-phase alternating current, respectively.

[0731] These measured alternating currents are transmitted to the inverter-side abnormality determiner (72: Figure 1 ). The method of abnormality determination in the inverter-side abnormality determiner (72: Figure 1 ) is as explained in the first embodiment. The repeated explanation is omitted.

[0732] As described above, there is also a configuration example in which a shunt resistor is used as a current detector of the inverter unit 3C.

[0733] In Figure 22 , the inverter power conversion sections 31U, 31V, 31W in the inverter unit 3C convert Figure 1 in the three inverter power conversion sections (first to third inverter power conversion sections 31) are specifically described as three, and the structure of the inverter power conversion section in the inverter unit is Figure 22 and Figure 1 the same structure.

[0734] In addition, in Figure 22 , a method in which a shunt resistor is provided in the inverter unit 3C is described, but there is also a method in which a shunt resistor is provided for Figure 1 in the three converter power conversion sections (first to third converter power conversion sections 21) of the converter unit 2.

[0735] In addition, in Figure 22 , a case in which the shunt resistors 34B, 35B, 36B are provided on the N wiring 42 side is described, but a method in which a shunt resistor is provided on the P wiring 40 side to detect an alternating current is also effective.

[0736] "Abnormality determination of 3-phase alternating current wiring without power converter"

[0737] In Figure 1 , Figure 18 , Figure 19 , abnormality determination related to each phase of the 3-phase alternating current wiring, for example, (R phase, S phase, T phase), (U phase, V phase, W phase) is described in the case where a power conversion device is used.

[0738] However, regarding the abnormality determination method of the 3-phase alternating current wiring in the description of the first to fourth embodiments, it is sometimes possible to apply even in the case where a power conversion device (power converter) having a converter and an inverter is not provided.

[0739] Figure 21 Examples of an abnormality determination method of a 3-phase alternating current wiring without a power conversion device (power converter) are shown.

[0740] In Figure 21 , the 3-phase alternating current power (voltage) of the alternating current power supply 1 is directly supplied to the motor 4 of the 3-phase load.

[0741] The U-phase current detector 34, the V-phase current detector 35, and the W-phase current detector 36 are respectively provided on the 3-phase alternating current wiring on which the motor 4 is input.

[0742] In addition, in the U-phase current detector 34, the V-phase current detector 35, and the W-phase current detector 36, the detected current detection values Iu, Iv, and Iw, respectively, are input to the inverter-side abnormality determiner 72. U V W

[0743] In the inverter-side abnormality determiner 72, the abnormality determination of the current detectors (34, 35, 36) is performed by the method described in the first embodiment, or the second embodiment, or the third embodiment.

[0744] In the first embodiment, the second embodiment, and the third embodiment, the abnormality determination method of the current detectors (34, 35, 36) is appropriately called an "abnormality detection method of a power transmission unit". In addition, the abnormality determination method of the current detectors in the case of having the power conversion device (power converter) or in the case of not passing through the power conversion device is appropriately called an "abnormality detection method of a power transmission unit" in a broad sense. Figure 21 Figure 21 That is, in the case of the first embodiment, the second embodiment, and the third embodiment, the power conversion device is the "power transmission unit", and in the case of the fourth embodiment, the three-phase wiring is the "power transmission unit". In addition, although not illustrated, a transformer is also the "power transmission unit". In addition, in the case of combining a plurality of "power transmission units", the entire combination is appropriately called the "power transmission unit".

[0745] In addition, in the case of the first embodiment, the second embodiment, and the third embodiment, the motor 4 can be a star connection or a delta connection. In addition, in the first embodiment, the second embodiment, and the third embodiment, the motor 4 as the three-phase load is described, but the load (4) is not limited to the motor. Figure 1 Figure 18 In addition, in the first embodiment, the second embodiment, and the third embodiment, the motor 4 as the three-phase load is described, but the load (4) is not limited to the motor. Figure 21 In addition, in the first embodiment, the second embodiment, and the third embodiment, the motor 4 as the three-phase load is described, but the load (4) is not limited to the motor.

[0746] Figure 21 In addition, in the first embodiment, the second embodiment, and the third embodiment, the motor 4 as the three-phase load is described, but the load (4) is not limited to the motor. Figure 21 In addition, in the first embodiment, the second embodiment, and the third embodiment, the motor 4 as the three-phase load is described, but the load (4) is not limited to the motor.

[0747] In the fourth embodiment, the three-phase AC power (voltage) of the AC power source 1 is directly supplied to the motor 4 of the three-phase load, and the current detectors (34, 35, 36) are respectively provided on the three-phase wiring of the three-phase AC power (voltage).

[0748] In the fourth embodiment, the three-phase AC power (voltage) of the AC power source 1 is directly supplied to the motor 4 of the three-phase load, and the current detectors (34, 35, 36) are respectively provided on the three-phase wiring of the three-phase AC power (voltage).

[0749] Figure 21 In the fourth embodiment, the three-phase AC power (voltage) of the AC power source 1 is directly supplied to the motor 4 of the three-phase load, and the current detectors (34, 35, 36) are respectively provided on the three-phase wiring of the three-phase AC power (voltage).

[0750] In the fourth embodiment, the three-phase AC power (voltage) of the AC power source 1 is directly supplied to the motor 4 of the three-phase load, and the current detectors (34, 35, 36) are respectively provided on the three-phase wiring of the three-phase AC power (voltage). Figure 21 ​​​​​​​In this case, the AC power source 1 and the motor 4 can be connected via an AC converter such as a transformer. In this case, the voltage of the 3-phase AC power supplied from the AC power source 1 and the appropriate voltage of the motor 4 as a 3-phase load can be easily adjusted.

[0751] Explanation of Reference Numerals

[0752] 1 AC power source

[0753] 2, 2B converter unit

[0754] 3, 3B, 3C inverter unit

[0755] 4 motor (load)

[0756] 5 converter control device

[0757] 6 inverter control device

[0758] 7 speed detector

[0759] 21 converter power conversion section (1st to 3rd converter power conversion sections)

[0760] 22, 23, 32, 33 smoothing capacitor

[0761] 24, 25, 29 DC voltage detector

[0762] 26 R-phase current detector (converter-side current detector, current detector, current detection unit)

[0763] 27 S-phase current detector (converter-side current detector, current detector, current detection unit)

[0764] 28 T-phase current detector (converter-side current detector, current detector, current detection unit)

[0765] 31 inverter power conversion section (1st to 3rd inverter power conversion sections)

[0766] 31 U, 31 V, 31 W inverter power conversion section

[0767] 34 U-phase current detector (inverter-side current detector, current detector, current detection unit)

[0768] 34B, 35B, 36B shunt resistor (current detector)

[0769] 35 V-phase current detector (inverter-side current detector, current detector, current detection unit)

[0770] 36 W-phase current detector (inverter-side current detector, current detector, current detection unit)

[0771] 40 P wiring

[0772] 41 C wiring

[0773] 42 N wiring

[0774] 51 DC voltage command generator

[0775] 52 DC voltage controller

[0776] 53, 63 current controller

[0777] 54, 64 pulse generator

[0778] 61 speed command generator

[0779] 62 speed controller

[0780] 71, 71B, 71C, 71D converter abnormality determiner (abnormality determiner)

[0781] 72, 72B, 72C, 72D inverter-side abnormality determiner (abnormality determiner)

[0782] 73 display

[0783] 74 converter-side output estimator

[0784] 75 inverter-side output estimator

[0785] 100, 101, 102, 103 power conversion device (power conversion unit, power transmission unit)

[0786] 711, 721 adder (addition unit)

[0787] 716, 726 adder (addition unit, adder of the second system)

[0788] 712, 712R, 712S, 712T, 722, 722U, 722V, 722W multiplier (multiplication unit)

[0789] 715, 715R, 715S, 715T, 715RC, 715SC, 715TC, 725, 725U, 725V, 725W, 725UC, 725VC, 725WC multiplier (multiplier of the second system)

[0790] 713, 713R, 713S, 713T, 723, 723U, 723V, 723W filter (filter unit)

[0791] 717, 727, 717C, 727C filter (filter unit, filter of the second system)

[0792] 718R, 718S, 718T, 728U, 728V, 728W filter, 2nd filter (filter unit)

[0793] 714, 714B, 714C, 714D, 724, 724B, 724C, 724D abnormality judging section (abnormality judging unit)

[0794] 719, 719R, 719S, 719T, 729, 729U, 729V, 729W adder-subtracter.

Claims

1. A power conversion device that has at least any one of a converter that converts alternating current into direct current, an inverter that converts direct current into alternating current, and an AC converter that converts alternating current into alternating current, characterized by comprising: a plurality of current detectors that detect currents of a plurality of phases that flow between a power supply and the power conversion device or between the power conversion device and a load device; and an abnormality determiner that determines an abnormality of the plurality of current detectors, the abnormality determiner comprising: a summer that calculates a sum of current detection values of the plurality of phases detected by the plurality of current detectors; a plurality of multipliers that respectively calculate products of the current detection value of each of the plurality of phases and an output of the summer; a plurality of filters that have a function of reducing or removing harmonic components of the outputs of the plurality of multipliers respectively; and an abnormality determination section that determines an abnormality of the current detectors based on the outputs of the plurality of filters respectively.

2. The power conversion device according to claim 1, characterized in that the abnormality determiner comprises a plurality of absolute value calculators that calculate absolute values of the outputs of the plurality of filters respectively, and in that the abnormality determiner determines that at least one of the plurality of current detectors is abnormal when a sum of the absolute values of the outputs of the plurality of absolute value calculators is greater than a predetermined value.

3. The power conversion device according to claim 2, characterized in that the abnormality determiner compares the outputs of the absolute values of the plurality of absolute value calculators with each other, and determines that a current detector of a phase corresponding to an absolute value calculator that outputs a maximum value among the outputs of the absolute values is abnormal.

4. The power conversion device according to claim 2, characterized in that the abnormality determiner calculates a sum of the outputs of the plurality of filters and an operation value obtained by subtracting outputs of other phases from an output of one phase with respect to the outputs of the absolute values of the plurality of absolute value calculators respectively, and in that the abnormality determiner determines that a current detector corresponding to the one phase is abnormal when the operation value obtained by subtracting the outputs of the other phases from the output of the one phase with respect to the outputs of the absolute values of the plurality of absolute value calculators respectively is equal to the sum of the outputs of the plurality of filters, or when a total of the operation value and the sum of the outputs of the plurality of filters is 0.

5. The power conversion device according to claim 2, characterized in that the abnormality determiner performs a predetermined operation of a detection gain based on the outputs of the filters, the detection gain including information of a degree of abnormality of a current detector of a phase in which an abnormality is assumed to have occurred, and in that the abnormality determiner determines that an abnormality has occurred in the current detector of the phase in which the abnormality is assumed to have occurred when the operation detection gain becomes outside a predetermined range.

6. The power conversion device according to claim 1, characterized in that ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The abnormality determiner changes the setting of the filter according to the frequency of the current flowing through the current detector.

7. The power conversion device according to claim 2, wherein The abnormality determiner changes the predetermined value according to the magnitude of the current flowing through the current detector.

8. The power conversion device according to claim 1, wherein The abnormality determiner further includes: a plurality of second-system multipliers that respectively calculate the product of the current detection values of each of the plurality of phases or the current detection values of the plurality of phases with each other; a second-system adder that calculates the sum of the plurality of outputs of the plurality of second-system multipliers; and a second-system filter that has a function of reducing or removing the harmonic component of the output of the second-system adder, The abnormality determination section determines the abnormality of the current detector based on the output of the second-system filter.

9. The power conversion device according to claim 1, wherein The abnormality determiner includes a second filter that removes or reduces the direct current component included in the input of the adder and the filter.

10. The power conversion device according to claim 1, wherein The power conversion device includes an output estimation section, In a case where the abnormality determiner determines that an abnormality has occurred, the output estimation section estimates the detection value of the detection object of the current detector in which the abnormality has occurred based on the current detector of the other phase other than the phase in which the abnormality has occurred, In a state where the current detector in which the abnormality has occurred is used continuously, the operation of the power conversion device is continued for a predetermined period.

11. The power conversion device according to claim 1, wherein The power conversion device includes a display device, In a case where the abnormality determiner determines that an abnormality has occurred, the display device displays information related to the abnormality.

12. The power conversion device according to claim 11, wherein The abnormality determiner stores the history of the detection gain including the degree of abnormality of the current detector, predicts the period until the abnormality of the current detector occurs based on the history of the detection gain, and causes the display device to display the prediction result.

13. The power conversion device according to any one of claims 1 to 12, wherein The plurality of currents are three-phase currents.

14. The power conversion device according to any one of claims 1 to 3, wherein The abnormality determiner determines that at least one of the plurality of current detectors is abnormal in any one of the following three cases: a case where the outputs of the plurality of current detectors are all zero, a case where there is zero in the outputs of the plurality of current detectors, and a case where the sum of the absolute values of the outputs of the plurality of current detectors is greater than a predetermined value.

15. An abnormality detection method of a power transmission unit that supplies power of an alternating current power source to a load device, the method comprising: The power transmission unit includes: a plurality of current detection units that detect the currents of a plurality of phases flowing between the alternating current power source and the load device; an addition unit that calculates a sum of current detection values of a plurality of phases detected by a plurality of the current detection units; a plurality of multiplication units that respectively calculate products of the current detection value of each of the plurality of phases and an output of the addition unit; a plurality of filter units that have a function of reducing or removing harmonic components of the respective outputs of the plurality of multiplication units; and an abnormality determination unit that determines an abnormality of the current detection unit based on the respective outputs of the plurality of filter units. ​

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