A low-power design method of high-speed trans-impedance amplifier

Abstract

The application discloses a low-power consumption design method of a high-speed trans-impedance amplifier, belongs to the low-power consumption research and development field of the trans-impedance amplifier in an integrated circuit, and aims at solving the problem of large chip power consumption of the current injection technology of the existing high-speed trans-impedance amplifier.The method is characterized in that: tail current of an output driving stage BUFF is injected into the input tube MN1 drain of a preamplifier TIA, so as to reduce or eliminate the large current injected into the input tube MN1 drain through a resistor or a current source, and low power consumption is achieved.

Description

Technical Field

[0001] This invention relates to a tail current re-injection technology, belonging to the field of low-power research and development in transimpedance amplifiers of integrated circuits. Background Technology

[0002] See Figure 1 A high-speed transimpedance amplifier includes a preamplifier (TIA), a phase splitting stage (PS), a pre-drive stage (Pre-Drive), an output drive stage (BUFF), and an offset cancellation circuit (OC). Located at the receiver end of an optical fiber communication integrated circuit, its function is to convert the current signal output by the photodiode (D0) into a voltage signal and amplify it. Low-power design is one of the development directions for high-speed transimpedance amplifiers, requiring trade-offs between performance characteristics such as sensitivity, dynamic range, and transimpedance, and power consumption. Through technological innovation, chip performance can be improved while reducing chip power consumption.

[0003] Current injection (also known as gain enhancement in some literature) is a common high-performance design technique for transimpedance amplifiers. See also Figure 2 , 3 As shown, a common current injection technique is given, which uses resistor R5 ( Figure 2 ) or current source I0 ( Figure 3 A large current (typically 10mA or more) is injected into the drain of the input transistor M1 to increase the transconductance gm of M1 and the resistance of the load resistor R1, thereby increasing the gain A = gm * R1 of the preamplifier TIA, thus achieving a high bandwidth and low noise design for the transimpedance amplifier. However, this injected current is large and will significantly increase the power consumption of the chip.

[0004] Therefore, improving chip performance while reducing chip power consumption using current injection technology is key to the low-power design of high-performance transimpedance amplifiers. Summary of the Invention

[0005] The purpose of this invention is to solve the problem of high chip power consumption in existing high-speed transimpedance amplifiers that use current injection technology, and to provide a low-power design method for high-speed transimpedance amplifiers.

[0006] The present invention discloses a low-power design method for a high-speed transimpedance amplifier, which injects the tail current of the output driver stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA to reduce or eliminate the large current injected into the drain terminal of the input transistor MN1 through a resistor or current source, thereby achieving low power consumption.

[0007] Preferably, the tail current of the output driver stage BUFF is injected entirely into the drain of the input transistor MN1 of the preamplifier TIA, and the following relationship exists:

[0008] I1 = I7

[0009] Where I1 is the injected current at the drain of the input transistor MN1, and I7 is the tail current of the output drive stage BUFF.

[0010] Preferably, the tail current of the output driver stage BUFF is injected into the drain of the input transistor MN1 of the preamplifier TIA, and a supplementary injection current is also injected into the drain of the input transistor MN1 at the same time. The supplementary injection current is injected by a resistor or a current source.

[0011] And the following relationship exists:

[0012] I1 = I7 + I S

[0013] Where I1 is the injected current at the drain of input transistor MN1, I7 is the tail current of the output driver stage BUFF, and I... S To supplement the injected current.

[0014] Preferably, the tail current portion of the output driver stage BUFF is injected into the drain terminal of the input transistor MN1 of the preamplifier TIA;

[0015] The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71 To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded.

[0016] Existence relation:

[0017] I1=I 71

[0018] Where I1 is the injected current at the drain terminal of input transistor MN1.

[0019] Preferably, the tail current portion of the output driver stage BUFF is injected into the drain terminal of the input transistor MN1 of the preamplifier TIA;

[0020] The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71 To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded;

[0021] A supplementary injection current is also injected into the drain terminal of the input transistor MN1, and the supplementary injection current is injected by a resistor or a current source.

[0022] And the following relationship exists:

[0023] I1=I 71 +I S

[0024] Where I1 is the injected current at the drain terminal of input transistor MN1, I S To supplement the injected current.

[0025] Preferably, the NMOS transistor MN7 in the output driver stage BUFF outputs the tail current;

[0026] The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3.

[0027] The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

[0028] Preferably, the NMOS transistor MN7 in the output driver stage BUFF outputs the tail current;

[0029] The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3.

[0030] The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA.

[0031] The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

[0032] Preferably, the NMOS transistor MN7 in the output driver stage BUFF outputs the tail current;

[0033] The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3; the other part of the tail current is grounded through NMOS transistor MN9.

[0034] The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

[0035] Preferably, the NMOS transistor MN7 in the output driver stage BUFF outputs the tail current;

[0036] The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3; the other part of the tail current is grounded through NMOS transistor MN9.

[0037] The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA.

[0038] The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

[0039] Preferably, the output drive stage BUFF includes NMOS transistors MN5, MN6, and MN7, resistors R3 and R4, and a tail current extraction unit. The output drive stage BUFF also includes a voltage regulation auxiliary circuit for stabilizing the voltage at point X of the drain terminal of NMOS transistor MN7.

[0040] The voltage regulation auxiliary circuit includes an operational amplifier AMP, a low-pass filter LPF, PMOS transistors MP1 to MP4, resistors R5 to R8, capacitors C1 and C2, a current source I2, and a current source I3.

[0041] Signal input ports VINP and VINN are simultaneously connected to the input of low-pass filter LPF, one end of capacitor C2, and one end of capacitor C1;

[0042] The output of the low-pass filter LPF is simultaneously connected to the gates of PMOS transistors MP4 and MP3, and the drains of PMOS transistors MP2 and MP1.

[0043] The gates of PMOS transistors MP1 and MP2 are connected to the output of operational amplifier AMP; the inverting input of operational amplifier AMP is connected to the reference voltage Vref; the non-inverting input of operational amplifier AMP is simultaneously connected to the drain of NMOS transistor MN7 and the source of NMOS transistors MN5 and MN6, and the junction is point X.

[0044] The source terminal of PMOS transistor MP3 is simultaneously connected to one end of resistor R8 and the negative terminal of current source I3.

[0045] The source terminal of the PMOS transistor MP4 is simultaneously connected to one end of resistor R7 and the negative terminal of current source I2.

[0046] The other end of resistor R7 is connected to both the other end of capacitor C1 and the gate of NMOS transistor MN6.

[0047] The other end of resistor R8 is connected to both the other end of capacitor C2 and the gate of NMOS transistor MN5.

[0048] The drain of NMOS transistor MN5 is connected to both one end of resistor R3 and the signal output port OUTN.

[0049] The drain of NMOS transistor MN6 is connected to both one end of resistor R4 and the signal output port OUTP.

[0050] The gate of NMOS transistor MN7 is connected to the voltage bias port VB3.

[0051] The tail current output from the source terminal of NMOS transistor MN7 is injected into the drain terminal of the output transistor MN1 of preamplifier TIA through the tail current extraction unit.

[0052] The other end of capacitor C3, the drain of PMOS transistors MP4 and MP3 are connected to ground;

[0053] The other ends of resistors R3, R4, R5 and R6, and the positive terminals of current sources I2 and I3 are connected to the power supply voltage VDD.

[0054] The beneficial effects of this invention are as follows: It proposes a high-performance, low-power design method and specific implementation circuit for transimpedance amplifiers. By injecting the bias current of the output driver into the preamplifier, replacing the resistor or current source in traditional current injection techniques, the bandwidth and noise performance of the transimpedance amplifier are improved. Because all or part of the current in the current injection technique and the bias current of the output buffer are multiplexed, zero or low power consumption of the current injection technique is achieved, thus realizing the goal of high-performance, low-power design. Attached Figure Description

[0055] Figure 1 This is a block diagram of an existing high-speed transimpedance amplifier;

[0056] Figure 2 This is a block diagram illustrating the principle of injecting a large current into the drain terminal of the TIA input transistor using a resistor. Figure 2 (a) in the diagram is the circuit diagram of the preamplifier. Figure 2 (b) in the diagram is the circuit diagram of the output driver stage BUFF;

[0057] Figure 3 This is a block diagram illustrating the principle of injecting a large current into the drain terminal of the TIA input transistor using a current source. Figure 3 (a) in the diagram is the circuit diagram of the preamplifier. Figure 3 (b) in the diagram is the circuit diagram of the output driver stage BUFF;

[0058] Figure 4 This is a schematic diagram of a low-power design method for a high-speed transimpedance amplifier as described in this invention.

[0059] Figure 5 This is the tail current injection scheme of the present invention;

[0060] Figure 6 This is the second tail current injection scheme of the present invention;

[0061] Figure 7 This is the third tail current injection scheme of the present invention;

[0062] Figure 8 This is the fourth tail current injection scheme of the present invention;

[0063] Figure 9 This is a specific embodiment of the circuit of Scheme 1;

[0064] Figure 10 This is the circuit of the first specific embodiment of Scheme 2;

[0065] Figure 11 This is the second specific embodiment of the circuit in Scheme 2;

[0066] Figure 12 This is a specific embodiment of the circuit of scheme three;

[0067] Figure 13 This is the circuit of the first specific embodiment of Scheme 4;

[0068] Figure 14 This is the second specific embodiment of the circuit in Scheme 4. Detailed Implementation

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0071] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0072] Specific Implementation Method 1: The following is combined with... Figures 4-14 This embodiment describes a low-power design method for a high-speed transimpedance amplifier: injecting the tail current of the output driver stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA to reduce or eliminate the large current injected into the drain terminal of the input transistor MN1 through a resistor or current source, thereby achieving low power consumption.

[0073] In the explanation of commonly used preamplifier and output driver circuits, the drain current injected into the input transistor MN1 and the current from the tail current source MN7 each consume 10mA of current (large current), and they cannot be reused between each other, which increases the overall power consumption of the TIA. Figure 4 The output drive tail current re-injection pre-transimpedance amplifier technology proposed in this invention solves the problem that the two current beams cannot be reused, and can reduce the overall power consumption of the circuit by 10mA.

[0074] In this invention, the source terminal of the tail current source MN7 is no longer grounded. Instead, it is re-injected into the drain terminal of the input transistor MN1 in the preamplifier TIA via MN8, replacing the function of the current source I0 or resistor R5 for large current injection. The reason for adding MN8 to extract the tail current is that when the input terminal TINP of the preamplifier receives a small-amplitude photoelectric signal, it is amplified by successive amplifier stages, generating a large-amplitude signal at the output ports OUTP and OUTN of the output driver stage BUFF. This results in voltage ripple at the corresponding X node, meaning the output affects the input. Therefore, adding transistor MN8 creates a three-layer cascode structure with the input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7, increasing the output impedance of the X node and shielding the influence of the X node and even the output ports OUTP and OUTN on the drain terminal of the input transistor MN1. This ensures that the sensitivity of the high-speed TIA remains unaffected under low photocurrent input conditions.

[0075] Adding transistor MN8, which provides electrical shielding, eliminates the output's influence on the input. However, the preamplifier input transistors MN1, MN8, and MN7 together form a three-layer cascode structure. This structure severely amplifies the photocurrent signal at the gate of input transistor MN1, generating excessively large voltage ripple at node X. This affects the output voltage waveforms at OUTP and OUTN, causing intersymbol interference and large jitter. In other words, the input affects the output. Therefore, additional auxiliary circuitry is needed to stabilize the voltage at point X.

[0076] The input signals VINP and VINN are divided into AC and DC signals. The AC signal is coupled to the gates of transistors MN5 and MN6 through capacitors C1 and C2, and this signal is valid AC data information. The DC signal passes through a low-pass filter LPF to filter out high-frequency signals and retain low-frequency signals. After passing through transistors MP3 and MP4 and resistors R7 and R8, the gates of transistors MN5 and MN6 are DC biased.

[0077] When the voltage at node X increases due to the influence of the input signal TINP, the output voltage of the operational amplifier AMP, which forms a negative feedback loop, increases accordingly. This causes the drain voltages of MP1 and MP2 to decrease, and the source voltages of MP3 and MP4 to decrease. Ultimately, this leads to a decrease in the source voltages of transistors MN5 and MN6, i.e., the voltage at node X. The voltage at node X will then be unaffected by the input signal TINP and, through the negative feedback loop, tends to stabilize.

[0078] To address the issue of mutual interference between input and output signals, we added a common source cascode structure and a negative feedback structure, which enabled tail current multiplexing technology to function effectively in practical designs.

[0079] This invention includes four schemes for injecting the tail current of the output drive stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA.

[0080] Option 1, see Figure 5 As shown, the tail current of the output driver stage BUFF is injected entirely into the drain of the input transistor MN1 of the preamplifier TIA, and the following relationship exists:

[0081] I1 = I7

[0082] Where I1 is the injected current at the drain of input transistor MN1 (the current described here is the injected current, not the total current flowing through MN1, i.e., excluding the current generated by resistor R1), and I7 is the tail current of the output drive stage BUFF.

[0083] The NMOS transistor MN7 in the output driver stage BUFF outputs tail current;

[0084] The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3.

[0085] In this scheme, if the tail current is 10mA, and it is injected entirely into the drain terminal of MN1, and it is the total injection current of TIA, then the chip as a whole saves all the energy consumption of the existing technical solutions (resistor injection or current source injection of large current), thus greatly saving chip power consumption.

[0086] As an example, see Figure 9 As shown,

[0087] The output drive stage BUFF includes NMOS transistors MN5, MN6, and MN7, resistors R3 and R4, and a tail current extraction unit. The output drive stage BUFF is characterized by further including a voltage regulation auxiliary circuit for stabilizing the voltage at point X of the drain terminal of NMOS transistor MN7.

[0088] The voltage regulation auxiliary circuit includes an operational amplifier AMP, a low-pass filter LPF, PMOS transistors MP1 to MP4, resistors R5 to R8, capacitors C1 and C2, a current source I2, and a current source I3.

[0089] Signal input ports VINP and VINN are simultaneously connected to the input of low-pass filter LPF, one end of capacitor C2, and one end of capacitor C1;

[0090] The output of the low-pass filter LPF is simultaneously connected to the gates of PMOS transistors MP4 and MP3, and the drains of PMOS transistors MP2 and MP1.

[0091] The gates of PMOS transistors MP1 and MP2 are connected to the output of operational amplifier AMP; the inverting input of operational amplifier AMP is connected to the reference voltage Vref; the non-inverting input of operational amplifier AMP is simultaneously connected to the drain of NMOS transistor MN7 and the source of NMOS transistors MN5 and MN6, and the junction is point X.

[0092] The source terminal of PMOS transistor MP3 is simultaneously connected to one end of resistor R8 and the negative terminal of current source I3.

[0093] The source terminal of the PMOS transistor MP4 is simultaneously connected to one end of resistor R7 and the negative terminal of current source I2.

[0094] The other end of resistor R7 is connected to both the other end of capacitor C1 and the gate of NMOS transistor MN6.

[0095] The other end of resistor R8 is connected to both the other end of capacitor C2 and the gate of NMOS transistor MN5.

[0096] The drain of NMOS transistor MN5 is connected to both one end of resistor R3 and the signal output port OUTN.

[0097] The drain of NMOS transistor MN6 is connected to both one end of resistor R4 and the signal output port OUTP.

[0098] The gate of NMOS transistor MN7 is connected to the voltage bias port VB3.

[0099] The tail current output from the source terminal of NMOS transistor MN7 is injected into the drain terminal of the output transistor MN1 of preamplifier TIA through the tail current extraction unit.

[0100] The other end of capacitor C3, the drain of PMOS transistors MP4 and MP3 are connected to ground;

[0101] The other ends of resistors R3, R4, R5 and R6, and the positive terminals of current sources I2 and I3 are connected to the power supply voltage VDD.

[0102] The tail current extraction unit is an NMOS transistor MN8. The drain of MN8 is connected to one end of capacitor C3 and the source of MN7. The gate of MN8 is connected to the voltage bias port VB4. The source of MN8 is connected to the drain of MN1.

[0103] To stabilize the voltage at node X, a voltage regulator auxiliary circuit was introduced. The voltage regulator auxiliary circuit occupies an area of ​​only 0.1mm*0.1mm, which is a very small part of the total chip area of ​​1mm*1mm. At the same time, the power consumption of the voltage regulator auxiliary circuit is only 0.5mA, which is negligible in terms of the overall power consumption of the chip.

[0104] Option 2, see below Figure 6 As shown, the tail current of the output driver stage BUFF is injected into the drain of the input transistor MN1 of the preamplifier TIA. At the same time, a supplementary injection current is also injected into the drain of the input transistor MN1. The supplementary injection current is injected by a resistor or a current source.

[0105] And the following relationship exists:

[0106] I1 = I7 + I S

[0107] Where I1 is the injected current at the drain of input transistor MN1, I7 is the tail current of the output driver stage BUFF, and I... S To supplement the injected current.

[0108] The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3.

[0109] The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA.

[0110] In this scheme, the entire tail current is injected into the drain of MN1, but this cannot meet the injection current requirements. For example, if the tail current is 10mA, but the drain of MN1 needs to be injected with 15mA, then the remaining 5mA is achieved by the resistor or current source injection method. Although this scheme still uses the existing injection current method, due to the participation of the tail current, the supplementary injection current injected by the resistor or current source method is no longer a large current, which can significantly reduce the overall power consumption of the chip.

[0111] As an example, please refer to Figure 10 and Figure 11 , Figure 10 To supplement the injection current, a resistive injection method is used. Figure 11To supplement the injected current, a current source injection method is adopted. Similarly, the output drive stage BUFF also includes a voltage regulation auxiliary circuit for stabilizing the voltage at point X. The structure of the voltage regulation auxiliary circuit is the same as that of Scheme 1.

[0112] Option 3, see Figure 7 As shown, the tail current portion of the output driver stage BUFF is injected into the drain terminal of the input transistor MN1 of the preamplifier TIA.

[0113] The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71 To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded.

[0114] Existence relation:

[0115] I1=I 71

[0116] Where I1 is the injected current at the drain terminal of input transistor MN1.

[0117] The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3. The other part of the tail current is grounded through NMOS transistor MN9. Specifically, the drain of MN9 is connected to the source (point X) of MN5 and MN6, the source of MN9 is grounded, and the gate of MN9 is connected to the voltage bias port VB5.

[0118] In this scheme, if the tail current is 20mA, it is divided into two parts. 10mA is injected into the drain of the input transistor MN1, which meets the TIA injection current requirement. The remaining 10mA tail current is grounded, so there is no need to inject a large current using a resistor or current source, thus saving chip power consumption.

[0119] As an example, see Figure 12 As shown, similarly, the output driver stage BUFF also includes a voltage regulation auxiliary circuit for stabilizing the voltage at point X, and the structure of the voltage regulation auxiliary circuit is the same as that in Scheme 1.

[0120] Option 4, see below Figure 8 As shown, the tail current portion of the output driver stage BUFF is injected into the drain terminal of the input transistor MN1 of the preamplifier TIA.

[0121] The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded;

[0122] A supplementary injection current is also injected into the drain terminal of the input transistor MN1, and the supplementary injection current is injected by a resistor or a current source.

[0123] And the following relationship exists:

[0124] I1=I 71 +I S

[0125] Where I1 is the injected current at the drain terminal of input transistor MN1, I S To supplement the injected current.

[0126] The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3; the other part of the tail current is grounded through NMOS transistor MN9. Specifically, the drain of MN9 is connected to the source (point X) of MN5 and MN6, the source of MN9 is grounded, and the gate of MN9 is connected to the voltage bias port VB5.

[0127] The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA.

[0128] In this solution, a portion of the tail current is used as part of the TIA injection current. For example, if the tail current is 20mA and the TIA injection current requirement is 10.5mA, then 10mA of the tail current is injected into the TIA. The remaining 0.5mA of the required injection current is injected using a resistor or current source. This partial injection method using a resistor or current source allows for arbitrary adjustment of the injection current. The reason why the entire tail current is not injected is because the tail current is split using MN8 and MN9, and it is not easy to achieve such a small adjustment as splitting out a 0.5mA current. This implementation method uses a method with high adjustment precision, enabling the TIA to achieve optimal performance. This solution also avoids injecting large currents using resistors or current sources, saving chip power consumption.

[0129] As an example, please refer to Figure 13 and Figure 14 , Figure 13 To supplement the injection current, a resistive injection method is used. Figure 14 To supplement the injected current, a current source injection method is adopted. Similarly, the output drive stage BUFF also includes a voltage regulation auxiliary circuit for stabilizing the voltage at point X. The structure of the voltage regulation auxiliary circuit is the same as that of Scheme 1.

[0130] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A low-power design method for a high-speed transimpedance amplifier, characterized in that, The output drive stage BUFF includes NMOS transistors MN5, MN6, and MN7, resistors R3 and R4, and a tail current extraction unit. The output drive stage BUFF also includes a voltage regulation auxiliary circuit to stabilize the voltage at point X of the drain terminal of NMOS transistor MN7. The voltage regulation auxiliary circuit includes an operational amplifier AMP, a low-pass filter LPF, PMOS transistors MP1 to MP4, resistors R5 to R8, capacitors C1 and C2, a current source I2, and a current source I3. Signal input ports VINP and VINN are simultaneously connected to the input of low-pass filter LPF, one end of capacitor C2, and one end of capacitor C1; The output of the low-pass filter LPF is simultaneously connected to the gates of PMOS transistors MP4 and MP3, and the drains of PMOS transistors MP2 and MP1. The gates of PMOS transistors MP1 and MP2 are connected to the output of operational amplifier AMP; the inverting input of operational amplifier AMP is connected to the reference voltage Vref; the non-inverting input of operational amplifier AMP is simultaneously connected to the drain of NMOS transistor MN7 and the source of NMOS transistors MN5 and MN6, and the junction is point X. The source terminal of PMOS transistor MP3 is simultaneously connected to one end of resistor R8 and the negative terminal of current source I3. The source terminal of the PMOS transistor MP4 is simultaneously connected to one end of resistor R7 and the negative terminal of current source I2. The other end of resistor R7 is connected to both the other end of capacitor C1 and the gate of NMOS transistor MN6. The other end of resistor R8 is connected to both the other end of capacitor C2 and the gate of NMOS transistor MN5. The drain of NMOS transistor MN5 is connected to both one end of resistor R3 and the signal output port OUTN. The drain of NMOS transistor MN6 is connected to both one end of resistor R4 and the signal output port OUTP. The gate of NMOS transistor MN7 is connected to the voltage bias port VB3. The tail current output from the source terminal of NMOS transistor MN7 is injected into the drain terminal of the output transistor MN1 of preamplifier TIA through the tail current extraction unit. The other end of capacitor C3, the drain of PMOS transistors MP4 and MP3 are connected to ground; The other ends of resistors R3, R4, R5 and R6, and the positive terminals of current sources I2 and I3 are connected to the power supply voltage VDD; The method involves injecting the tail current of the output driver stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA to reduce or eliminate the large current injected into the drain terminal of the input transistor MN1 through a resistor or current source, thereby achieving low power consumption.

2. The low-power design method for a high-speed transimpedance amplifier according to claim 1, characterized in that, The entire tail current of the output driver stage BUFF is injected into the drain of the input transistor MN1 of the preamplifier TIA, and the following relationship exists: I1 = I7 Where I1 is the injected current at the drain of the input transistor MN1, and I7 is the tail current of the output drive stage BUFF.

3. The low-power design method for a high-speed transimpedance amplifier according to claim 1, characterized in that, All the tail current of the output driver stage BUFF is injected into the drain of the input transistor MN1 of the preamplifier TIA. At the same time, a supplementary injection current is also injected into the drain of the input transistor MN1. The supplementary injection current is injected by a resistor or a current source. And the following relationship exists: I1=I7+I S Where I1 is the injected current at the drain of input transistor MN1, I7 is the tail current of the output driver stage BUFF, and I... S To supplement the injected current.

4. The low-power design method for a high-speed transimpedance amplifier according to claim 1, characterized in that, Inject the tail current portion of the output driver stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA; The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71 To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded. Existence relation: I1=I 71 Where I1 is the injected current at the drain terminal of input transistor MN1.

5. The low-power design method for a high-speed transimpedance amplifier according to claim 1, characterized in that, Inject the tail current portion of the output driver stage BUFF into the drain terminal of the input transistor MN1 of the preamplifier TIA; The tail current I7 of the output driver stage buff is divided into two parts: I7 = I 71 +I 72 I 71 To inject the tail current into the drain terminal of input transistor MN1, I 72 The tail current is grounded; A supplementary injection current is also injected into the drain terminal of the input transistor MN1, and the supplementary injection current is injected by a resistor or a current source. And the following relationship exists: I1=I 71 +I S Where I1 is the injected current at the drain terminal of input transistor MN1, I S To supplement the injected current.

6. The low-power design method for a high-speed transimpedance amplifier according to claim 2, characterized in that, The NMOS transistor MN7 in the output driver stage BUFF outputs tail current; The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3. The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

7. The low-power design method for a high-speed transimpedance amplifier according to claim 3, characterized in that, The NMOS transistor MN7 in the output driver stage BUFF outputs tail current; The low-power design method leads the tail current out through NMOS transistor MN8 and injects it into the drain of input transistor MN1 in preamplifier TIA; at the same time, the drain of NMOS transistor MN8 is grounded through capacitor C3. The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA. The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

8. The low-power design method for a high-speed transimpedance amplifier according to claim 4, characterized in that, The NMOS transistor MN7 in the output driver stage BUFF outputs tail current; The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3; the other part of the tail current is grounded through NMOS transistor MN9. The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

9. The low-power design method for a high-speed transimpedance amplifier according to claim 5, characterized in that, The NMOS transistor MN7 in the output driver stage BUFF outputs tail current; The low-power design method divides the tail current into two parts. One part of the tail current is led out through NMOS transistor MN8 and injected into the drain of input transistor MN1 in preamplifier TIA, and the drain of NMOS transistor MN8 is grounded through capacitor C3; the other part of the tail current is grounded through NMOS transistor MN9. The low-power design method also synchronously injects the supplementary injection current formed by the resistor or current source into the drain of the input transistor MN1 in the preamplifier TIA. The input transistor MN1, NMOS transistor MN8, and NMOS transistor MN7 form a three-layer common-source common-gate structure.

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