A novel single event hardening flip-flop circuit

Abstract

The application discloses a novel single event hardening flip-flop circuit, comprising: a main stage latch and a slave stage latch which are connected in series, at least one delay element is arranged in a feedback loop of the main stage latch and / or the slave stage latch; the delay element is used for keeping the level of a second node of the feedback loop unchanged when a first node of the feedback loop is affected by single particle incidence during a data holding stage of the latch, and restoring the level of the first node affected by the single particle incidence after ionizing radiation ends. The application provides the flip-flop circuit with low production cost, small occupied area and good single particle upset resistance through simple structure improvement.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a novel single-event hardened trigger circuit. Background Technology

[0002] In a radiation environment, charged particles incident on a digital circuit chip will induce ionizing radiation, generating a certain number of electron-hole pairs around the particle's trajectory. When enough electron-hole pairs are deposited along the incident direction of the particles, the current caused by the electron-hole pairs collected by the depletion layer will cause the drain level to flip, forming a single-event upset.

[0003] Traditional hardening methods include Dual Inter-locked Storage Cell (DICE) and Guard-gates DICE (GDICE), which are implemented by adding transmission channels and storage nodes and using an interlocking structure. A DICE is essentially a four-node storage unit, with data written from two nodes and the voltage levels at the other two nodes generated by feedback, ultimately forming a four-point interlocking structure.

[0004] However, traditional hardening methods increase the number of transistors in the circuit due to the addition of storage nodes and interlocking structures, resulting in increased area overhead. Simultaneously, the added interlocking structures slow down data transmission speed. Furthermore, when the radiation energy is high or the transistors used in the triggers are small, traditional hardening structures cannot recover the node levels caused by ionizing radiation through the interlocking structures, thus leading to single-event upsets. Summary of the Invention

[0005] This application provides a novel single-event hardened trigger circuit that, based on simple structural improvements, offers a trigger circuit with low production cost, small footprint, and good single-event upset resistance.

[0006] In a first aspect, the present invention provides the following technical solution through an embodiment of the present invention:

[0007] A novel single-event hardened trigger circuit is characterized by comprising: a master latch and a slave latch connected in series, wherein at least one delay element is provided in the feedback loop of the master latch and / or the slave latch; the delay element is used to maintain the level of the second node of the feedback loop unchanged when the first node of the latch's feedback loop is affected by single-event radiation during the data holding phase of the latch, and to restore the level of the first node affected by single-event radiation after the ionizing radiation ends.

[0008] Preferably, the delay element includes a resistor and a gate switch, the resistor and the gate switch are connected in parallel, the first terminal of the resistor and the gate switch serve as the input terminal of the delay element, and the second terminal of the resistor and the gate switch serve as the output terminal of the delay element; the gate switch is used to disconnect during the data holding phase of the latch, and when the first node of the latch feedback loop is affected by single-particle incident radiation, it keeps the level of the second node of the feedback loop unchanged, and restores the level of the first node after the ionizing radiation ends.

[0009] Preferably, the delay element includes a capacitor and a gate switch. One end of the capacitor is connected in series with one end of the gate switch, and the other end of the gate switch serves as the input and output of the delay element. The other end of the capacitor is connected to a fixed voltage level. The gate switch is used to close during the data holding phase of the latch. When the first node of the latch feedback loop is affected by a single-particle incident event, the load characteristics of the delay element are used to maintain the voltage level of the second node of the feedback loop unchanged. The voltage level of the first node is restored after the ionizing radiation ends.

[0010] Preferably, the feedback loop of the master-level latch includes at least one delay element. The master-level latch includes a first inverter and a first clock gating element. The first inverter and the first clock gating element are connected in parallel. The input terminal of the first inverter and the output terminal of the first clock gating circuit serve as the input terminal of the master-level latch, and the output terminal of the first inverter and the input terminal of the first clock gating circuit serve as the output terminal of the master-level latch. The delay element is provided in the branch where the first inverter is located and / or the branch where the first clock gating element is located.

[0011] Preferably, the branch containing the first inverter and the first clock gating element is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the first node and the input terminal of the first inverter, and the second delay element is disposed between the second node and the input terminal of the first clock gating element.

[0012] Preferably, the branch containing the first inverter and the first clock gating element is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the second node and the output terminal of the first inverter, and the second delay element is disposed between the first node and the output terminal of the first clock gating element.

[0013] Preferably, the branch containing the first inverter is provided with the delay element, which is disposed between the first node and the input terminal of the first inverter.

[0014] Preferably, the branch where the first clock gating element is located is provided with the delay element, and the delay element is disposed between the second node and the input terminal of the first clock gating element.

[0015] Preferably, the feedback loop of the slave latch includes at least one delay element. The slave latch includes a second inverter and a second clock gating element. The second inverter and the second clock gating element are connected in parallel. The input terminal of the second inverter and the output terminal of the second clock gating element serve as the input terminal of the slave latch, and the output terminal of the second inverter and the input terminal of the second clock gating element serve as the output terminal of the slave latch. The delay element is provided in the branch where the second inverter is located and / or the branch where the second clock gating element is located.

[0016] Preferably, the branch containing the second inverter and the second clock gating element is provided with the delay element, the delay element including: a first delay element and a second delay element, the first delay element being between the first node and the input terminal of the second inverter, and the second delay element being between the second node and the input terminal of the second clock gating element.

[0017] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0018] This invention provides a novel single-event hardened trigger circuit, comprising: a master latch and a slave latch connected in series. At least one delay element is provided in the feedback loop of the master latch and / or the slave latch. The delay element is used during the data holding phase of the latch to maintain the level of the second node of the feedback loop when the first node of the feedback loop experiences a level flip due to single-event radiation. The level of the first node affected by single-event radiation is restored after the ionizing radiation ends. Based on the original structure, this application adds a delay element within the latch, enabling the trigger circuit to maintain the level of the node at the other end of the feedback loop until the ionizing radiation ends, even when subjected to high-energy radiation or when the transistor technology used in the trigger is small. This is achieved by leveraging the load delay characteristics of the delay element when a node experiences a level flip due to single-event radiation, thus restoring the level of the first node after the ionizing radiation ends. Therefore, this application provides a trigger circuit with low production cost, small footprint, and good single-event upset resistance through simple structural improvements. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a structural diagram of a single-event hardened trigger circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of a first type of delay element provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of a second delay element provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of a conventional trigger circuit provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of a first type of master stage latch including a delay element provided by an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of a second type of master stage latch including a delay element provided in an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of a third type of master stage latch including a delay element provided in an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of a fourth type of master stage latch including a delay element provided in an embodiment of the present invention;

[0028] Figure 9 A schematic diagram of the logic input circuit provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of a clock gating element provided in an embodiment of the present invention. Detailed Implementation

[0030] The flip-flop consists of a master-level latch structure and a slave-level latch structure. The master-level and slave-level latches have the same structure (a feedback loop composed of an inverter and a gate circuit). The clock is latched at high and low levels by time-division control of the gate circuit. As a structure with storage and memory functions in the flip-flop circuit, the latch becomes the core of the single-event hardening design of the flip-flop.

[0031] The applicant's research revealed that traditional hardening methods, DICE and GDICE, achieve their effects by adding transmission channels and storage nodes, and employing interlocking structures. DICE is essentially a four-node storage unit; data is written to two nodes, and the voltage levels of the other two nodes are generated by feedback, ultimately forming a four-node interlocking structure. The GDICE structure, building upon the interlocking of the DICE structure, adds a pair of protection gates to each storage node. When the inputs at the two nodes differ, the output has high impedance; therefore, if one of the adjacent nodes of a node flips, its output remains unchanged. Their hardening principle is that when a node flips due to a single-particle incident event, the adjacent two nodes, through interlocking, restore the node's voltage level after the ionizing radiation ends. However, traditional hardening methods, due to the addition of storage nodes and interlocking structures, increase the number of transistors in the circuit, increasing area overhead, and the trigger circuits show poor hardening performance under high-energy radiation.

[0032] Therefore, the embodiments of this application provide a novel single-event hardened trigger circuit, which can provide a trigger circuit with low production cost, small footprint and good anti-single-event upset characteristics based on simple structural improvements.

[0033] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:

[0034] A novel single-event hardened trigger circuit includes: a master latch and a slave latch connected in series. At least one delay element is provided in the feedback loop of the master latch and / or the slave latch. The delay element is used to maintain the level of the second node of the feedback loop unchanged during the data holding phase of the latch when the first node of the latch's feedback loop is affected by a single-event incident radiation. The level of the first node affected by the single-event incident radiation is restored after the ionizing radiation ends.

[0035] It should be noted that the single-event hardened trigger circuit provided in this application is applicable to rising-edge / falling-edge D flip-flop circuits, and can also be applied to other types of flip-flops, such as registers. Furthermore, this application can be applied to single-event hardening of other sequential circuits such as high / low level latch circuits.

[0036] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0037] Firstly, the embodiments of the present invention provide a novel single-event hardened trigger circuit, specifically, as follows: Figure 1 As shown, it includes a master latch 10 and a slave latch 20 connected in series, and at least one delay element 30 is provided in the feedback loop of the master latch 10 and / or the slave latch 20.

[0038] In a specific embodiment, the trigger circuit further includes: a logic input circuit 40, a third clock gate element 501, a fourth clock gate element 502, a third inverter 503, and a fourth inverter 504. The logic input circuit is sequentially connected to the third clock gate element 501, the master latch 10, the fourth clock gate element 502, the slave latch 20, and the third inverter 503. The output terminal of the third inverter 503 serves as the Qn terminal of the trigger circuit. The input terminal of the fourth inverter 504 is connected to the input terminal of the slave latch, and the output terminal of the fourth inverter 504 serves as the Q terminal of the trigger circuit.

[0039] Among them, the gate switch of the third clock gate element 501 is reversed with that of the first clock gate element 102, the gate switch of the fourth clock gate element 502 is reversed with that of the second clock gate element 202, and the gate switch of the third clock gate element 501 is reversed with that of the fourth clock gate element 502.

[0040] The delay element is used during the data holding phase of the latch to maintain the level of the second node of the feedback loop when the first node of the latch's feedback loop experiences a level flip due to a single-event incident event, and restores the level of the first node after the ionizing radiation ends. Alternatively, when the second node of the latch's feedback loop experiences a level flip due to a single-event incident event, the level of the first node of the feedback loop remains unchanged, and the level of the first node is restored after the ionizing radiation ends.

[0041] It should be noted that the delay capability of the delay element here will be designed based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor process used in the trigger. Furthermore, since the master-level latch and the slave-level latch are time-division controlled, the control terminals (c and cn) of the delay element where the master-level latch is located are reversed compared to the control terminals (c and cn) of the delay element where the slave-level latch is located.

[0042] Specifically, as an optional embodiment, such as Figure 2 As shown, the delay element 30 may include a resistor 301 and a gate switch 302. The resistor 301 and the gate switch 302 are connected in parallel. The first end of the resistor 301 and the gate switch 302 serves as the input end of the delay element 30, and the second end of the resistor 301 and the gate switch 302 serves as the output end of the delay element 30.

[0043] In this case, the gate switch 302 is used to close the gate switch of the delay element 30 during the data transmission phase of the latch, thereby short-circuiting the two ends of the resistor 301, causing the load to fail, and the data will be transmitted directly through the gate switch 302.

[0044] Specifically, the gate switch 302 is used to disconnect the latch during the data holding phase, with the resistor active. When the first node of the latch feedback loop experiences a level flip due to a single-particle incident radiation, the level of the second node of the feedback loop remains unchanged. The level of the first node is restored after the ionizing radiation ends. It should be noted that the resistance value of resistor 301 can be determined based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor used in the trigger.

[0045] For example, taking the delay switch set in the master latch as an example, during the data holding phase of the master latch, the gate switch 302 is open, and data transmission needs to pass through resistor 301. The delay element will be equivalent to a passive load. When the first node of the feedback loop of the master latch ( Figure 2 When the level of point A is flipped due to the influence of a single particle incident, resistor 301 delays the time for data transmission to reach point B. This means that the level of the second node of the feedback loop can remain unchanged for a certain period of time. After the ionizing radiation ends, the level of the first node (point A) is restored, thereby achieving the purpose of latch hardening, which is also the purpose of trigger circuit hardening.

[0046] As another alternative embodiment, such as Figure 3 As shown, the delay element 30 may include a capacitor 303 and a gate switch 304. One end of the capacitor 303 is connected in series with one end of the gate switch 304. The other end of the gate switch 304 serves as the input and output of the delay element 30. The other end of the capacitor 303 is connected to a fixed level (power supply or ground).

[0047] Among them, the gate switch 304 is used to disconnect the gate switch of the delay element 30 during the data transmission phase of the latch, thereby disconnecting the capacitor 303 and causing the capacitor load to fail.

[0048] Specifically, the gate switch 304 is used to close during the data holding phase of the latch, with the capacitor active. When the first node of the latch's feedback loop experiences a level flip due to a single-particle incident event, the load characteristics of the delay element are used to maintain the level of the second node of the feedback loop unchanged. The level of the first node is restored after the ionizing radiation ends. It should be noted that the capacitance value of capacitor 303 can be determined based on factors such as the magnitude of ionizing radiation received by the trigger circuit and the size of the transistor technology used in the trigger.

[0049] For example, taking a delay switch set in a slave latch as an example, during the data holding phase of the slave latch, the gate switch 304 is closed, and voltage will pass through capacitor 303. The delay element will be equivalent to a passive load. When the first node of the feedback loop of the slave latch ( Figure 3When the voltage level of points A / B is reversed due to the influence of a single particle incident, the capacitor charges / discharges the voltage, causing a time delay in the data transmission to the second node. This means that the voltage level of the second node of the feedback loop can be kept constant for a certain period of time. After the ionizing radiation ends, the voltage level of the first node (point A) is restored, thereby achieving the purpose of latch hardening, which is also the purpose of trigger circuit hardening.

[0050] Of course, in addition to the two types of delay elements mentioned above, other devices can also be used to construct delay elements, such as a delay element that includes a diode. This application does not limit the specific delay element used in the embodiments.

[0051] It should be noted that the aforementioned gate switch 302 or 304 can be a clock gate composed of PMOS and NMOS, or a PMOS clock gate or an NMOS clock gate. Of course, other gate switches suitable for this application can also be used, and this application does not impose any restrictions.

[0052] like Figure 4 As shown, the master latch 10 includes a first inverter 101 and a first clock gating element 102. As an optional embodiment, at least one delay element 30 is provided in the feedback loop of the master latch 10.

[0053] The first inverter 101 is connected in parallel with the first clock gate element 102. The input terminal of the first inverter 101 and the output terminal of the first clock gate circuit 102 serve as the input terminals of the master stage latch 10, and the output terminal of the first inverter 101 and the input terminal of the first clock gate circuit 102 serve as the output terminals of the master stage latch 10. The branch where the first inverter 101 is located and / or the branch where the first clock gate element 102 is located are provided with a delay element 30.

[0054] In a preferred embodiment, both the branch containing the first inverter 101 and the first clock gating element 102 are provided with delay elements 30, wherein the delay elements 30 include: a first delay element 305 and a second delay element 306, such as... Figure 5 As shown, the first delay element 305 is disposed between the first node of the master stage latch feedback loop and the input terminal of the first inverter 101, and the second delay element 306 is disposed between the second node of the master stage latch feedback loop and the input terminal of the first clock gating element 102.

[0055] Of course, as another optional embodiment, if both the branch containing the first inverter 101 and the first clock gating element 102 are provided with delay elements 30, the delay elements 30 include: a first delay element 305 and a second delay element 306, such as... Figure 6As shown, the first delay element 305 is disposed between the second node of the master stage latch feedback loop and the output terminal of the first inverter 101, and the second delay element 306 is disposed between the first node of the master stage latch feedback loop and the output terminal of the first clock gating element 102.

[0056] Optionally, if only the branch containing the first inverter 101 is equipped with a delay element 30, such as Figure 7 As shown, the delay element 30 is disposed between the first node and the input terminal of the first inverter 101. The delay element 30 is only disposed in the branch containing the first clock gate element 102, as shown below. Figure 8 As shown, the delay element 30 is disposed between the second node and the input terminal of the first clock gate element 102.

[0057] Optionally, if only the branch containing the first inverter 101 is provided with a delay element 30, the delay element 30 is disposed between the second node and the output terminal of the first inverter 101. If only the branch containing the first clock gate element 102 is provided with a delay element 30, the delay element 30 is disposed between the first node and the output terminal of the first clock gate element 102.

[0058] like Figure 4 As shown, the slave latch 20 includes a second inverter 201 and a second clock gating element 202. As another optional embodiment, at least one delay element 30 is provided in the feedback loop of the slave latch 20.

[0059] The second inverter 201 is connected in parallel with the second clock gate element 202. The input terminal of the second inverter 201 and the output terminal of the second clock gate element 202 serve as the input terminals of the slave latch 20, and the output terminal of the second inverter 201 and the input terminal of the second clock gate element 202 serve as the output terminals of the slave latch 20. The branch where the second inverter 201 is located and / or the branch where the second clock gate element 202 is located are provided with a delay element 30.

[0060] Similarly, in a preferred embodiment, the branches containing the second inverter 201 and the second clock gating element 202 are each provided with a delay element 30. The delay element 30 includes a first delay element 305 and a second delay element 306. The first delay element 305 is disposed between the first node of the slave latch feedback loop and the input terminal of the second inverter 201, and the second delay element 306 is disposed between the second node of the slave latch feedback loop and the input terminal of the second clock gating element 202.

[0061] Of course, as another optional embodiment, if both the branch containing the second inverter 201 and the second clock gating element 202 are provided with delay elements 30, the delay elements 30 include: a first delay element 305 and a second delay element 306. The first delay element 305 is disposed between the second node of the slave latch feedback loop and the output terminal of the second inverter 201, and the second delay element 306 is disposed between the first node of the slave latch feedback loop and the output terminal of the second clock gating element 202.

[0062] Optionally, if only the branch where the second inverter 201 is located is provided with a delay element 30, the delay element 30 is provided between the first node and the input terminal of the second inverter 201.

[0063] Only the branch containing the second clock gate element 202 is equipped with a delay element 30, which is located between the second node and the input of the second clock gate element 202.

[0064] Optionally, if only the branch containing the second inverter 201 is provided with a delay element 30, the delay element 30 is disposed between the second node and the output terminal of the second inverter 201. If only the branch containing the second clock gate element 202 is provided with a delay element 30, the delay element 30 is disposed between the first node and the output terminal of the second clock gate element 202.

[0065] Preferably, the trigger circuit provided in this application may also be: both the feedback loop of the master latch 10 and the feedback loop of the slave latch 20 are provided with delay elements 30, the master latch 10 includes a first inverter 101 and a first clock gate element 102, and the slave latch 20 includes a second inverter 201 and a second clock gate element 202.

[0066] The branch containing the first inverter 101 and / or the branch containing the first clock gating element 102 is provided with a delay element, and the branch containing the second inverter 201 and / or the branch containing the second clock gating element 202 is provided with a delay element.

[0067] Preferably, both the branch containing the first inverter 101 and the branch containing the first clock gate element 102 are provided with delay elements, and both the branch containing the second inverter 201 and the branch containing the second clock gate element 202 are provided with delay elements.

[0068] Optionally, only the branch containing the first inverter 101 and the branch containing the second inverter 201 are provided with delay elements; only the branch containing the first clock gate element 102 and the branch containing the second clock gate element 202 are provided with delay elements; only the branch containing the first inverter 101 and the branch containing the second clock gate element 202 are provided with delay elements; only the branch containing the first clock gate element 102 and the branch containing the second inverter 201 are provided with delay elements.

[0069] It should be noted that when the delay element is located in the branch where the clock gating element is located, the delay switch may not have a switching function, and the branch can be controlled by the switching of the clock gating element. Simply put, since the clock gating element already controls the on / off state of the branch, there is no need to adjust the on / off state of the delay element, thus simplifying the circuit control process.

[0070] Specifically, during the data transmission phase, the delay elements of the inverter branch are disabled by switching, and the delay elements of the clock gating branch are disabled by clock gating, thus not affecting the data transmission speed; during the data latching phase, the delay elements of the inverter branch are enabled by switching, and the delay elements of the clock gating branch are enabled by clock gating.

[0071] For example, such as Figure 5 , Figure 6 or Figure 8 As shown, the branch delay element 306 or 30 where the first clock gating element 102 is located is enabled or disabled by the switching of the first clock gating element.

[0072] Therefore, regardless of whether it is a master-level latch or a slave-level latch, the method of adding a delay element in the latch feedback loop in this application can include: (a) adding two delay elements in the feedback loop, with the delay elements located before the inverter and the clock gating circuit, respectively; (b) adding two delay elements in the feedback loop, with the delay elements located after the inverter and the clock gating circuit, respectively; (c) adding one delay element in the feedback loop, with the delay element located before or after the clock gating circuit; (d) adding one delay element in the feedback loop, with the delay element located before or after the inverter.

[0073] Among them, targeting Figure 2 For the delay element including resistor and gate switch shown, during the data transmission phase, the gate switch of the delay element is closed, which disables the passive load (i.e., short-circuit the two ends of the resistor) and does not affect the data transmission speed; during the data holding phase, the gate switch is open, and the delay element is equivalent to a passive load (resistor).

[0074] against Figure 3For the delay element including the capacitor and the gate switch shown, during the data transmission phase, the gate switch of the delay element is opened, which disables the passive load (i.e., the capacitor is open-circuited) and does not affect the data transmission speed; during the data holding phase, the gate switch is closed, and the delay element is equivalent to a passive load (capacitor).

[0075] Optionally, such as Figure 9 As shown in Figure a, the logic input circuit 40 can be a D flip-flop.

[0076] As another alternative embodiment, such as Figure 9 As shown in figures b, c, and d, the logic input circuit 40 can be a synchronous reset D flip-flop, a D scan flip-flop, or a synchronous reset D scan flip-flop, etc. Of course, other flip-flops with different structures suitable for this application can also be used, and this application does not impose any restrictions.

[0077] As an alternative embodiment, such as Figure 10 As shown in Figure a, the clock gating element mentioned in this application can be a single clock gating element.

[0078] As another alternative embodiment, such as Figure 10 As shown in Figures b and c, the clock gating element can be a clock gating element composed of PMOS and NMOS transistors. Of course, other clock gating elements with different structures suitable for this application can also be used, and this application does not impose any restrictions.

[0079] The following is combined Figure 4 The working principle of the single-event upset-hardened rising-edge D flip-flop circuit provided in this application is explained by the master-level latch and slave-level latch, which are equipped with delay elements:

[0080] Phase 1: When the clock is low, the third clock gate 501 is open and the first clock gate 102 is closed. The master stage is in data transmission mode (the delay element in the master stage latch is disabled, i.e., the resistor is short-circuited or the capacitor is open-circuited). Data will be transmitted from the input to the feedback loop of the master stage latch, and then transmitted to the master stage output through the first inverter 101. At this time, the fourth clock gate 502 is closed and the second clock gate 202 is open. The slave stage is in data latching mode (the delay element in the slave stage latch is active, i.e., the resistor or capacitor is active). The slave stage output maintains the data from the previous phase.

[0081] Phase Two: When the clock transitions from low to high (i.e., the rising edge of the clock), the fourth clock gate 502 opens and the second clock gate 202 closes. The slave stage is in data transmission mode (the delay elements in the slave latch will be disabled, i.e., the resistor is short-circuited or the capacitor is open-circuited). Data is transmitted from the master stage output to the feedback loop of the slave latch, and then transmitted to the slave stage output through the second inverter 201. At this time, the third clock gate 501 closes and the first clock gate 102 opens. The master stage is in data latching mode (the delay elements in the master stage latch will be effective, i.e., the resistor or capacitor is effective). The master stage output maintains the data from the previous phase.

[0082] The above two stages complete the data transmission process from the input to the output of a circuit.

[0083] This application provides a novel single-event hardened trigger circuit. By adding a delay element to the latch feedback loop, it can adapt to different radiation energies and different process dimensions by adjusting the delay element (e.g., ...). Figure 2 The resistance value shown or Figure 3 The capacitance value shown can achieve single-event immunity for the trigger. Since the load on the switch-controlled delay element is small during data transmission, the data transmission speed of the trigger is unaffected. Therefore, this application only requires a small increase in area overhead to achieve a good ruggedization effect on the trigger circuit. This solves the problem that traditional ruggedization methods have large area overhead and suffer from single-event upsets due to ruggedization defects when exposed to high-energy radiation or when the transistors used in the trigger have small dimensions.

[0084] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0085] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0086] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A single-event hardened trigger circuit, characterized in that, include: A master-level latch and a slave-level latch connected in series, wherein at least one delay element is provided in the feedback loop of the master-level latch and / or the slave-level latch; The delay element is used to maintain the level of the second node of the feedback loop unchanged when the first node of the latch feedback loop is affected by a single particle incident during the data holding phase of the latch, and to restore the level of the first node affected by the single particle incident after the ionizing radiation ends. The delay element includes a resistor and a gate switch. The resistor and the gate switch are connected in parallel. The first terminal of the resistor and the gate switch serves as the input terminal of the delay element, and the second terminal of the resistor and the gate switch serves as the output terminal of the delay element. The gate switch is used to disconnect during the data holding phase of the latch. Alternatively, the delay element includes a capacitor and a gate switch, with one end of the capacitor connected in series with one end of the gate switch, the other end of the gate switch serving as both the input and output of the delay element, and the other end of the capacitor connected to a fixed voltage level. The gate switch is used to close during the data holding phase of the latch.

2. The trigger circuit as described in claim 1, characterized in that, The feedback loop of the master latch is provided with at least one delay element, and the master latch includes a first inverter and a first clock gating element. The first inverter is connected in parallel with the first clock gating element. The input terminal of the first inverter and the output terminal of the first clock gating element serve as the input terminal of the master stage latch, and the output terminal of the first inverter and the input terminal of the first clock gating element serve as the output terminal of the master stage latch. The branch containing the first inverter and / or the branch containing the first clock gating element are provided with the delay element.

3. The trigger circuit as described in claim 2, characterized in that, The branch containing the first inverter and the first clock gating element is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the first node and the input terminal of the first inverter, and the second delay element is disposed between the second node and the input terminal of the first clock gating element.

4. The trigger circuit as described in claim 2, characterized in that, The branch containing the first inverter and the first clock gating element is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is disposed between the second node and the output terminal of the first inverter, and the second delay element is disposed between the first node and the output terminal of the first clock gating element.

5. The trigger circuit as described in claim 2, characterized in that, The branch containing the first inverter is provided with the delay element, which is located between the first node and the input terminal of the first inverter.

6. The trigger circuit as described in claim 2, characterized in that, The branch containing the first clock gating element is provided with the delay element, which is located between the second node and the input terminal of the first clock gating element.

7. The trigger circuit as described in claim 1, characterized in that, The feedback loop of the slave latch is provided with at least one delay element, and the slave latch includes a second inverter and a second clock gating element; The second inverter is connected in parallel with the second clock gate element. The input terminal of the second inverter and the output terminal of the second clock gate element serve as the input terminal of the slave latch, and the output terminal of the second inverter and the input terminal of the second clock gate element serve as the output terminal of the slave latch. The branch containing the second inverter and / or the branch containing the second clock gating element are provided with the delay element.

8. The trigger circuit as described in claim 7, characterized in that, The branch containing the second inverter and the second clock gating element is provided with the delay element. The delay element includes a first delay element and a second delay element. The first delay element is located between the first node and the input terminal of the second inverter, and the second delay element is located between the second node and the input terminal of the second clock gating element.

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