Image pickup element and image pickup device

Abstract

The imaging element includes: a first substrate provided with a photoelectric conversion unit that generates charges through photoelectric conversion, a signal line that outputs a signal based on the charges generated by the photoelectric conversion unit, and a supply unit that supplies voltage to the signal line in such a manner that the voltage of the signal line does not become lower than a specified voltage; and a second substrate laminated on the first substrate, which is provided with a processing unit that processes the signal output to the signal line.

Description

Technical Field

[0001] The present invention relates to an imaging element and an imaging device. Background Art

[0002] There is known an imaging element (Patent Document 1) in which a transistor for clamping a signal output from a pixel to a predetermined voltage level is provided for each column. Heretofore, improvement in image quality has been pursued.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-222273 Summary of the Invention

[0006] According to a first aspect, an imaging element includes: a first substrate provided with a photoelectric conversion unit that generates charges by photoelectric conversion, a signal line that outputs a signal based on the charges generated by the photoelectric conversion unit, and a supply unit that supplies a voltage to the signal line so as not to let the voltage of the signal line become lower than a predetermined voltage; and a second substrate laminated on the first substrate and provided with a processing unit that processes a signal output to the signal line.

[0007] According to a second aspect, an imaging device includes: the imaging element according to the first aspect; and a generation unit that generates image data based on a signal processed by the processing unit. Brief Description of the Drawings

[0008] Figure 1 It is a diagram showing a configuration example of the imaging device according to the first embodiment.

[0009] Figure 2 It is a block diagram showing a configuration example of the imaging element according to the first embodiment.

[0010] Figure 3 It is a diagram showing an example of a cross-sectional structure of a part of the imaging element according to the first embodiment.

[0011] Figure 4 It is a diagram showing an example of a configuration of a part of the imaging element according to the first embodiment.

[0012] Figure 5 It is a timing chart showing an operation example of the imaging element according to the first embodiment.

[0013] Figure 6 It is a timing chart showing an operation example of the imaging element according to the first embodiment.

[0014] Figure 7 It is a diagram showing an example of a layout of a part of the imaging element according to the first embodiment.

[0015] Figure 8 This is a diagram showing an example of the layout of a part of an imaging element of a modified example.

[0016] Figure 9 This is a diagram showing another example of the layout of a part of an imaging element of a modified example. Detailed Description of the Invention

[0017] (First Embodiment)

[0018] Figure 1 This is a diagram showing a configuration example of a camera 1 as an example of an imaging device according to the first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2, an imaging element 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The photographing optical system 2 includes a plurality of lenses including a focus adjustment lens (focusing lens) and an aperture stop, and forms a subject image on the imaging element 3. In addition, the photographing optical system 2 may be configured to be detachable from the camera 1.

[0019] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives a light beam that has passed through the photographing optical system 2 and captures the subject image formed by the photographing optical system 2. A plurality of pixels having a photoelectric conversion unit are arranged two-dimensionally (in the row direction and the column direction) on the imaging element 3. The photoelectric conversion unit is composed of a photodiode (PD). The imaging element 3 performs photoelectric conversion on the received light to generate a signal, and outputs the generated signal to the control unit 4.

[0020] The memory 5 is a recording medium such as a memory card. Image data, control programs, etc. are recorded in the memory 5. Writing data to the memory 5 and reading data from the memory 5 are controlled by the control unit 4. The display unit 6 displays an image based on the image data, information related to shooting such as the shutter speed and aperture value, and a menu screen, etc. The operation unit 7 includes various setting switches such as a release button, a power switch, and a switch for switching between various modes, and outputs signals based on respective operations to the control unit 4.

[0021] The control unit 4 is composed of a processor such as a CPU, FPGA, or ASIC, and a memory such as a ROM or RAM, and controls each part of the camera 1 based on a control program. The control unit 4 supplies a signal for controlling the imaging element 3 to the imaging element 3 and controls the operation of the imaging element 3. When performing still image shooting, when performing moving image shooting, when the display unit 6 displays a live view image (live view image) of the subject, etc., the control unit 4 causes the imaging element 3 to capture a subject image and output a signal.

[0022] The control unit 4 performs various image processes on the signal output from the imaging element 3 to generate image data. The control unit 4 is also a generation unit 4 that generates image data, and generates still image data and moving image data based on the signal output from the imaging element 3. The image process includes image processes such as grayscale conversion process and color interpolation process.

[0023] Figure 2 FIG. is a block diagram showing a configuration example of the imaging element according to the first embodiment. The imaging element 3 is configured by laminating a first substrate 111 having a plurality of pixels 10 and a second substrate 112 having a readout unit 60. The first substrate 111 and the second substrate 112 are each configured using a semiconductor substrate. The circuit provided on the first substrate 111 and the circuit provided on the second substrate 112 are electrically connected by connection parts such as electrodes and bumps.

[0024] The first substrate 111 includes a plurality of regions 20 in which a plurality of pixels 10 are respectively arranged. In Figure 2 the example shown, four regions 20 are illustrated. These four regions 20 each show one region when the region for arranging the pixels 10 of the first substrate 111 is divided into regions including a specified number of pixels. In addition, the regions 20 may partially overlap or may not overlap. The number of pixels in each region 20 may be 4 pixels of 2 pixels × 2 pixels, may be 16 pixels of 4 pixels × 4 pixels, and may be any number. Hereinafter, the region 20 is referred to as a pixel block 20.

[0025] For each pixel block 20, a signal line 22 and a supply unit 30 described later are provided on the first substrate 111. In addition, for each pixel block 20, a pixel control unit and a supply control unit are provided on the first substrate 111, which will be described in detail later. The signal line 22 is a signal line that connects the pixel block 20 and the readout unit 60, and outputs a signal from the pixel 10. The signal line 22 is a signal line using connection parts such as electrodes and bumps.

[0026] The readout unit 60 includes a processing unit 50 including an analog / digital conversion unit (AD conversion unit) 40. The processing unit 50 is provided for each pixel block 20. In the imaging element 3 of the present embodiment, using the signal lines 22 respectively provided in the pixel blocks 20, the signals of the pixels from the plurality of pixel blocks 20 are read in parallel. The readout unit 60 can output the signals of the pixels of each pixel block 20 to the processing unit 50 provided for each pixel block 20 simultaneously (in parallel), and perform signal processing on the signals of the pixels in each processing unit 50 at the same time. Since each processing unit 50 performs signal processing on the signals output from each pixel block 20 at the same time, the readout unit 60 can perform high-speed signal processing.

[0027] The AD conversion unit 40 of the processing unit 50 converts the signal of each pixel 10 of the pixel block 20, which is an analog signal input via the signal line 22, into a digital signal. In addition, the processing unit 50 may also have an amplification unit that amplifies the signal of the pixel input via the signal line 22 at a specified gain (amplification rate). In this case, the AD conversion unit 40 converts the signal of the pixel amplified by the amplification unit into a digital signal.

[0028] The signal of the pixel converted into a digital signal is output to the control unit 4 of the camera 1 after being subjected to signal processing such as correlated double sampling (CDS; Correlated Double Sampling) or correction of the signal amount in the processing unit 50. In addition, signal processing such as correlated double sampling of the signal of the pixel may be performed in a signal processing unit (not shown). In this case, the processing unit 50 outputs the signal of the pixel converted into a digital signal by the AD conversion unit 40 to the signal processing unit. The signal processing unit outputs the processed signal of the pixel to the control unit 4 after performing signal processing such as correlated double sampling on the input signal of the pixel.

[0029] Around the area where each pixel 10 is arranged in the first substrate 111, a plurality of electrodes (pads) 200 for supplying (applying) the power supply voltage VDD are provided. The electrodes 200 are connected to the plurality of pixels 10 and the supply unit 30 arranged on the first substrate 111 via wirings (power supply lines) 121. The power supply voltage VDD is supplied to the pixels 10 and the supply unit 30 via the power supply lines 121. The electrodes 200 are electrodes shared by the plurality of pixels 10 and the supply unit 30, and are arranged on one surface of the first substrate 111 as Figure 2 shown.

[0030] Hereinafter, the configuration of the imaging element 3 of the present embodiment will be further described with reference to the drawings.

[0031] Figure 3 FIG. is an example of a cross-sectional structure of a part of the imaging element according to the first embodiment. Figure 4 FIG. is an example of a configuration of a part of the imaging element according to the first embodiment. Figure 3 The imaging element 3 shown is a back-illuminated type imaging element. The imaging element 3 includes a first substrate 111, a wiring layer 101 laminated on the first substrate 111, a second substrate 112, and a wiring layer 102 laminated on the second substrate 112. The wiring layer 101 and the wiring layer 102 are each a wiring layer including a conductor film (metal film) and an insulating film, and are provided with a plurality of wirings or connection parts, interlayer insulating films, etc.

[0032] Light from the subject is incident in the positive Z-axis direction of Figure 3 In addition, as Figure 3As shown by the coordinate axes, the right direction of the paper surface orthogonal to the Z-axis is set as the positive X-axis direction, and the front direction of the paper surface orthogonal to the Z-axis and the X-axis is set as the positive Y-axis direction. In the subsequent figures, there are also cases where the coordinate axes are shown in a way to understand the orientation of each figure based on the Figure 3 coordinate axes. In the first substrate 111 and the wiring layer 101, a plurality of pixel blocks 20 including a plurality of pixels 10 and the supply unit 30 are arranged in the X-axis direction and the Y-axis direction. In the second substrate 112 and the wiring layer 102, a plurality of processing units 50 are arranged in the X-axis direction and the Y-axis direction.

[0033] In Figure 4 , a part of the pixels 10 among the plurality of pixels 10 provided in the imaging element 3, a part of the current sources 25 and the supply unit 30, a part of the pixel control units 35 and the supply control unit 36, and the readout control unit 70 are shown. The current sources 25 and the supply unit 30 are provided with respect to the signal line 22. The pixel control units 35 and the supply control unit 36 are arranged for each pixel block 20, respectively. In addition, in Figure 4 , in order to simplify the drawings, only one pixel 10 is illustrated for one pixel block 20.

[0034] The pixel 10 has a photoelectric conversion unit 11, a transfer unit 12, a floating diffusion unit (FD) 13, a reset unit 14, an amplification unit 15, and a selection unit 16. The photoelectric conversion unit 11 is a photodiode PD, which converts the incident light into charges and accumulates the charges after photoelectric conversion.

[0035] The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and transfers the charges photoelectrically converted by the photoelectric conversion unit 11 to the FD 13. The transistor M1 is a transfer transistor. The FD 13 accumulates (holds) the charges transferred to the FD 13 and converts the voltage obtained by dividing by the capacitance value. The FD 13 is an accumulation unit 13 that accumulates the charges generated by the photoelectric conversion unit 11.

[0036] The amplification unit 15 is composed of a transistor M3 whose gate (terminal) is connected to the FD 13, amplifies the signal based on the charges accumulated in the FD 13, and outputs it. The drain (terminal) of the transistor M3 is connected to the electrode 200 via the power supply line 121 (refer to Figure 2 ), and is supplied with the power supply voltage VDD. The source (terminal) of the transistor M3 is connected to the signal line 22 via the selection unit 16. The amplification unit 15 uses the current source 25 as a load current source and functions as a part of a source follower circuit. The transistor M3 is an amplification transistor. The amplification unit 15 and the selection unit 16 constitute an output unit that generates and outputs a signal based on the charges generated by the photoelectric conversion unit 11.

[0037] The reset unit 14 is composed of a transistor M2 controlled by a signal RST, and electrically connects or disconnects the FD13 and the power supply line 121. The reset unit 14 resets the charge accumulated in the FD13. The reset unit 14 discharges the charge accumulated in the FD13 and resets the voltage of the FD13. The transistor M2 is a reset transistor. The selection unit 16 is composed of a transistor M4 controlled by a signal SEL, and electrically connects or disconnects the amplification unit 15 and the signal line 22. When the transistor M4 of the selection unit 16 is in the on state, the signal from the amplification unit 15 is output to the signal line 22. The transistor M4 is a selection transistor.

[0038] The current source 25 includes a transistor M5 that inputs a signal VB to the gate. The current source 25 is connected to each pixel 10 of the pixel block 20 and the supply unit 30 via the signal line 22. The current source 25 generates a current based on the signal level of the signal VB and supplies the generated current to the signal line 22, the pixel 10, and the supply unit 30. In addition, the current source 25 may be composed of two transistors connected in cascade. The signal VB is generated by a signal generation unit (not shown). The signal generation unit is commonly connected to the current source 25 provided for each signal line 22 and supplies the signal VB to each current source 25. The gates of the transistors M5 of the current sources 25 are electrically connected to each other, and the signal VB is input from the signal generation unit.

[0039] A signal (dark signal) when resetting the voltage of the FD13 and a signal (photoelectric conversion signal) based on the charge transferred from the photoelectric conversion unit 11 to the FD13 by the transfer unit 12 are sequentially output to the signal line 22. The dark signal is used to remove the noise included in the photoelectric conversion signal. The dark signal is also referred to as an analog signal representing the reference level with respect to the photoelectric conversion signal and is used for correcting the photoelectric conversion signal. The photoelectric conversion signal is an analog signal generated based on the charge photoelectrically converted by the photoelectric conversion unit 11. The dark signal and the photoelectric conversion signal are input to the processing unit 50 of the reading unit 60 via the signal line 22 (see Figure 2 ). In the present embodiment, the processing unit 50 has an arithmetic unit that performs a subtraction operation between the photoelectric conversion signal and the dark signal, performs a CDS based on the subtraction operation between the photoelectric conversion signal and the dark signal, and removes the noise component from the photoelectric conversion signal.

[0040] The supply unit 30 has a signal output unit 31 and a switch unit 32 as shown in Figure 4 and has a function of supplying a voltage to the signal line 22. The signal output unit 31 is composed of a transistor M11 that inputs a signal CLIP to the gate, and generates and outputs a signal based on the voltage level of the signal CLIP. The drain of the transistor M11 is connected to the electrode 200 via the power supply line 121 (see Figure 2 ) and is supplied with the power supply voltage VDD. The source of the transistor M11 is connected to the signal line 22 via the switch unit 32.

[0041] The switch unit 32 is composed of a transistor M12 controlled by a signal CLIP_SW, and electrically connects or disconnects the signal output unit 31 and the signal line 22. When the transistor M12 of the switch unit 32 is in the on state, the signal from the signal output unit 31 can be output to the signal line 22. In the present embodiment, when the switch unit 32 is in the on state, the voltage (potential) of the signal line 22 is limited by the signal output unit 31 to a value within a range with the voltage based on the signal CLIP as the lower limit value. The supply unit 30 supplies voltage to the signal line 22 in such a manner that the voltage of the signal line 22 does not become lower than a specified voltage. The supply unit 30 may also be a limiting unit 30 that limits the voltage of the signal line 22. It can also be said that the supply unit 30 supplies voltage to the signal line 22 in such a manner that the voltage of the signal line 22 becomes a value from the power supply voltage VDD to the voltage based on the signal CLIP, and controls (adjusts) the voltage of the signal line 22.

[0042] The pixel control unit 35 is composed of a switch and a buffer, and is controlled by the read control unit 70. The pixel control unit 35 supplies signals such as the above-mentioned signal TX, signal RST, and signal SEL to the pixels 10 of the pixel block 20, and controls the operations of the respective pixels 10. The pixel control unit 35 supplies signals to the gates of the respective transistors of the pixel 10, and sets the transistors to the on state (connected state, conducting state, short-circuit state) or the off state (disconnected state, non-conducting state, open state, cutoff state).

[0043] The read control unit 70 and the pixel control unit 35 control the period during which charge is accumulated in the pixel block 20 and the timing of reading the signals of the pixels by controlling the signals TX and signal SEL input to the pixels 10. The pixel control unit 35 provided for each pixel block 20 can control the pixel 10 in such a manner that the charge accumulation time is different for each pixel block 20, and can also control the pixel 10 in such a manner that the charge accumulation time is the same for all pixel blocks 20. In addition, each pixel control unit 35 can control the pixel 10 in such a manner that the timing of reading the signals of the pixels is different for each pixel block 20, and can also control the pixel 10 in such a manner that the timing of reading the signals of the pixels is the same for all pixel blocks 20. By controlling the pixel 10 in such a manner that the charge accumulation time is different for each pixel block 20, the pixel control unit 35 enables shooting in accordance with the brightness of each subject even when there are multiple subjects. In addition, by controlling the pixel 10 in such a manner that the timing of reading the signals of the pixels is different for each pixel block 20, the pixel control unit 35 enables shooting in accordance with the moving speed of each subject even when there are multiple subjects.

[0044] The supply control unit 36 includes a switch and a buffer, and is controlled by the readout control unit 70. As described above, the pixel control unit 35 can control the pixels 10 in such a way that the charge storage time varies for each pixel block 20, and can also control the pixels 10 in such a way that the timing of reading the signals of the pixels varies for each pixel block 20. In this case, since the timing of outputting signals to the signal line 22 is different for each block 20, the supply control unit 36 must control the operation of each switch unit 32 for each pixel block 20. The supply control unit 36 supplies the above-mentioned signal CLIP_SW to the switch unit 32 of the pixel block 20 to control the operation of each switch unit 32. The supply control unit 36 performs on / off control of the switch unit 32 to start and stop supplying voltage from the signal output unit 31 to the signal line 22. In the present embodiment, the supply control unit 36 provided for each pixel block 20 adjusts the timing of supplying voltage from the signal output unit 31 to the signal line 22 in the pixel block 20 based on the timing of reading the dark signal and the photoelectric conversion signal in the pixel block 20. For example, the supply control unit 36 of each pixel block 20 controls the switch unit 32 so that voltage can be supplied to the signal line 22 provided for a certain pixel block 20 and the signal line 22 provided for other pixel blocks 20 at different timings. In addition, each supply control unit 36 can control each switch unit 32 so that voltage can be supplied at the same timing in all pixel blocks 20.

[0045] The readout control unit 70 is provided in common for a plurality of pixel blocks 20. The readout control unit 70 is composed of a plurality of circuits including a timing generator and is arranged on the second substrate 112. The readout control unit 70 is controlled by the control unit 4 of the camera 1. The readout control unit 70 controls signals such as the signal TX, the signal RST, and the signal SEL input to the pixels 10 via the pixel control unit 35, thereby controlling the operation of the pixels 10. In addition, the readout control unit 70 controls the signal CLIP_SW input to the supply unit 30 via the supply control unit 36, thereby controlling the operation of the supply unit 30.

[0046] In addition, the above-mentioned pixel control unit 35 and supply control unit 36 may be arranged on either the first substrate 111 or the second substrate 112, or may be separately arranged on the first substrate 111 and the second substrate 112. The pixel control unit 35 and the supply control unit 36 may be arranged on a substrate different from the first substrate 111 and the second substrate 112. The readout control unit 70 may be separately arranged on the first substrate 111 and the second substrate 112, or may be arranged on the first substrate 111. The readout control unit 70 may be arranged on a substrate different from the first substrate 111 and the second substrate 112.

[0047] The selection unit 16 of pixel 10 and the switching unit 32 of the supply unit 30 are respectively turned on, whereby the source of the amplification unit 15 and the source of the signal output unit 31 are electrically connected to the signal line 22. In this case, based on the magnitude relationship between the voltage of the gate of the amplification unit 15 (i.e., the voltage of FD13) and the voltage of the gate of the supply unit 30 (i.e., the voltage of signal CLIP), the path through which the current of the current source 25 connected to the signal line 22 flows changes.

[0048] When the voltage of FD13 is higher than the voltage of signal CLIP, the current of the current source 25 mainly flows through the signal line 22 and the selection unit 16 to the amplification unit 15. The amplification unit 15 outputs a signal based on the voltage of FD13 to the signal line 22. As a result, the voltage of the signal line 22 becomes a voltage corresponding to the voltage of FD13. When the voltage of FD13 is lower than the voltage of signal CLIP, the current of the current source 25 mainly flows through the signal line 22 and the switching unit 32 to the signal output unit 31. At this time, the signal output unit 31 outputs a signal based on the voltage of signal CLIP to the signal line 22, thereby limiting the voltage of the signal line 22 to the voltage based on the voltage of signal CLIP. The voltage of the signal line 22 becomes a voltage corresponding to the voltage of signal CLIP.

[0049] In this way, when the switching unit 32 of the supply unit (limiting unit) 30 is turned on, the supply unit 30 limits the voltage of the signal line 22 according to the voltage of FD13 and the voltage of signal CLIP. The transistor M11 of the supply unit 30 is a transistor that limits (clamps) the voltage of the signal line 22, and is sometimes referred to as a clamping transistor or a clamping transistor. When the voltage of FD13 is relatively low, the voltage of the signal line 22 is limited to the voltage based on the voltage of signal CLIP. As a result, it is possible to prevent the current source 25 from malfunctioning due to a decrease in the voltage of the signal line 22. As a result, it is possible to prevent the current of the current source 25 from not being supplied. In addition, it is possible to prevent the voltage of the signal line 22 from becoming a voltage outside the assumed range and being input to the reading unit 60.

[0050] In addition, in the imaging element 3 of the present embodiment, signals CLIP of different signal levels are input to the supply unit 30 when reading dark signals and when reading photoelectric conversion signals. As a result, the supply unit 30 can supply different voltages to the signal line 22 when reading dark signals and when reading photoelectric conversion signals.

[0051] When reading out the dark signal, a first voltage V1 is supplied to the gate of the transistor M11 of the signal output unit 31. In this case, the voltage of the signal line 22 is limited such that the voltage based on the first voltage V1 becomes the lower limit. Thereby, the voltage of the signal output to the readout unit 60 as the dark signal is limited. When reading out the photoelectric conversion signal, a second voltage V2 lower than the first voltage V1 is supplied to the gate of the transistor M11. In this case, the voltage of the signal line 22 is limited such that the voltage based on the second voltage V2 becomes the lower limit. Thereby, the voltage of the signal output to the readout unit 60 as the photoelectric conversion signal is limited.

[0052] Due to the lack of pixels, charges are accumulated in FD13, and there is a case where the voltage of the dark signal drops. When photographing a high-brightness subject, charges are also accumulated in FD13, resulting in a drop in the voltage of the dark signal. In this case, the difference between the dark signal and the photoelectric conversion signal becomes smaller, and the image quality of the image generated using the signal after CDS processing deteriorates. In the present embodiment, as described above, the voltage of the dark signal can be limited, and the difference in signal level between the dark signal and the photoelectric conversion signal can be ensured. Therefore, it is possible to suppress the deterioration of the image quality due to the decrease in the difference between the dark signal and the photoelectric conversion signal.

[0053] The second voltage V2 described above is defined in such a way that the voltage of the signal line 22 does not drop to the voltage required for the operation of the transistor M5 of the current source 25, and in such a way that the voltage of the signal line 22 takes as low a voltage as possible. Thereby, it is possible to suppress the change in the voltage of the signal line 22 that occurs when the charge generated by the photoelectric conversion unit 11 is transferred to FD13. In addition, it is possible to suppress the variation in the current of the current source 25, and it is possible to suppress the mixing of noise into the photoelectric conversion signal output to the signal line 22.

[0054] Figure 5 And Figure 6 are timing charts showing the operation examples of the imaging element 3 of the first embodiment. In Figure 5 And Figure 6 In the shown timing charts, the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. FD represents the signal (voltage signal) of FD13, and VOUT represents the signal output to the signal line 22. In Figure 5 And Figure 6 In the shown example, the signal CLIP_SW is set to a high level, and the switch unit 32 of the supply unit 30 is in an on state. In Figure 5 And Figure 6 , the transistors to which control signals (signal SEL, signal RST, signal TX) with a high level (for example, power supply voltage VDD) are input are in an on state, and the transistors to which control signals with a low level (for example, ground voltage) are input are in an off state.

[0055] At Figure 5 the shown time t1, the signal RST becomes high level. As a result, the transistor M2 of the reset section 14 of the pixel 10 becomes on state, and the FD13 and the power supply line 121 are electrically connected. Thereby, the charge of the FD13 is reset, and the voltage of the FD13 becomes the reset voltage. In addition, at the time t1, the signal SEL becomes high level. As a result, the transistor M4 of the selection section 16 becomes on state. Thereby, the amplification section 15 and the selection section 16 can output the signal based on the reset voltage of the pixel 10, that is, the signal after the charge of the FD13 of the pixel 10 is reset, to the signal line 22. At the time t2, the signal RST becomes low level. As a result, the transistor M2 of the reset section 14 becomes off state.

[0056] The signal output section 31 of the supply section 30 is input with the signal CLIP of the first voltage V1, and is in a state where the voltage based on the first voltage V1 (the limiting voltage Vc1 shown by the dotted line in Figure 5 ) can be supplied to the signal line 22. In Figure 5 the shown example, during the period from the time t2 to the time t3, the voltage of the FD13 ( Figure 5 the voltage of the FD shown) is higher than the first voltage V1 which is the voltage of the signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 becomes the voltage based on the voltage of the FD13, that is, becomes the voltage based on the reset voltage after the charge accumulated in the FD13 is reset.

[0057] At the time t3, the processing section 50 of the readout section 60 samples the signal VOUT which becomes the voltage based on the reset voltage as the dark signal. It can also be said that the voltage of the dark signal is determined at the time t3. The AD conversion section 40 of the processing section 50 converts the dark signal into a digital signal. At the time t4, the signal output section 31 is input with the signal CLIP of the second voltage V2 which is lower than the first voltage V1. The voltage of the signal CLIP changes from the first voltage V1 to the second voltage V2, and the signal output section 31 becomes in a state where the voltage based on the second voltage V2 (the limiting voltage Vc2 shown by the dotted line in Figure 5 ) can be supplied to the signal line 22.

[0058] At the time t5, the signal TX becomes high level. As a result, the transistor M1 of the transmission section 12 becomes on state, and the charge photoelectrically converted by the photoelectric conversion section 11 is transmitted to the FD13. Thereby, the voltage of the FD13 becomes the voltage based on the charge transmitted from the photoelectric conversion section 11. In addition, since the signal SEL is high level, the amplification section 15 and the selection section 16 are in a state where the signal based on the charge generated by the photoelectric conversion section 11 can be output to the signal line 22. At the time t6, the signal TX becomes low level. As a result, the transistor M1 of the transmission section 12 becomes off state.

[0059] In Figure 5 In the example shown, during the period from time t6 to time t7, the voltage of FD13 is higher than the second voltage V2 which is the voltage of signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 becomes the voltage based on the voltage of FD13, that is, the voltage based on the charge photoelectrically converted by the photoelectric conversion unit 11.

[0060] At time t7, the processing unit 50 samples the signal VOUT whose voltage is based on the charge photoelectrically converted by the photoelectric conversion unit 11 as the photoelectric conversion signal. It can also be said that the voltage of the photoelectric conversion signal is determined at time t7. The AD conversion unit 40 of the processing unit 50 converts the photoelectric conversion signal into a digital signal. The processing unit 50 performs CDS on the converted digital dark signal and photoelectric conversion signal, and the CDS processing performs differential processing between the dark signal and the photoelectric conversion signal. After performing signal processing such as CDS processing, the processing unit 50 outputs the processed signal to the control unit 4.

[0061] Next, refer to Figure 6 Another example of the operation of the imaging element 3 will be described. At Figure 6 At the time t11 shown, the signal RST becomes high level, whereby the transistor M2 of the reset unit 14 of the pixel 10 becomes in an on state. Thereby, the charge of FD13 is reset, and the voltage of FD13 becomes the reset voltage. In addition, at time t11, the signal SEL becomes high level, whereby the transistor M4 of the selection unit 16 becomes in an on state. Thereby, the amplification unit 15 and the selection unit 16 can output a signal based on the reset voltage of the pixel 10 to the signal line 22. At time t12, the signal RST becomes low level, whereby the transistor M2 of the reset unit 14 becomes in an off state.

[0062] The signal output unit 31 of the supply unit 30 is in a state where the signal CLIP inputting the first voltage V1 can supply the voltage based on the first voltage V1 (limiting voltage Vc1) to the signal line 22. At Figure 6 In the example shown, during the period from time t12 to time t13, the voltage of FD13 is higher than the first voltage V1 which is the voltage of signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 becomes the voltage based on the reset voltage of FD13.

[0063] At time t13, the processing unit 50 of the readout unit 60 samples the signal VOUT whose voltage is based on the reset voltage as the dark signal. The processing unit 50 converts the dark signal into a digital signal. At time t14, the signal output unit 31 is in a state where the signal CLIP inputting the second voltage V2 lower than the first voltage V1 can supply the voltage based on the second voltage V2 (limiting voltage Vc2) to the signal line 22.

[0064] At time t15, the signal TX becomes high, whereby the transistor M1 of the transmission unit 12 becomes conductive, and the charge obtained by the photoelectric conversion of the electro-conversion unit 11 is transferred to the FD13. Thus, the voltage of the FD13 becomes a voltage based on the charge transferred from the electro-conversion unit 11. In addition, since the signal SEL is high, the amplification unit 15 and the selection unit 16 are in a state capable of outputting a signal based on the charge generated by the electro-conversion unit 11 to the signal line 22. At time t16, the signal TX becomes low, whereby the transistor M1 of the transmission unit 12 becomes non-conductive.

[0065] In Figure 6 In the example shown, during the period from time t16 to time t17, the voltage of the FD13 is lower than the second voltage V2 which is the voltage of the signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 is limited to the voltage based on the second voltage V2, that is, the limiting voltage Vc2.

[0066] At time t17, the processing unit 50 samples the signal VOUT which has become the limiting voltage Vc2 as the photoelectric conversion signal. The processing unit 50 converts the photoelectric conversion signal into a digital signal. After the processing unit 50 performs signal processing such as CDS processing using the converted digital dark signal and photoelectric conversion signal, the processed signal is output to the control unit 4. In this way, in the present embodiment, the supply unit 30 is input with signals CLIP having different signal levels when reading the dark signal and when reading the photoelectric conversion signal. The supply unit 30 supplies a voltage to the signal line 22 according to the voltage of the signal CLIP and the voltage of the FD13, whereby the voltage of the signal line 22 can be limited.

[0067] As Figure 4 shown, the gates of the transistors M5 of the respective current sources 25 provided for each signal line 22 are commonly connected to the signal line to which the signal VB is input. In addition, a parasitic capacitance (load capacitance) may be added between the signal line 22 that outputs the signal of the pixel and the gate of the transistor M5 connected to the signal line 22. Due to the influence of this parasitic capacitance, the voltage of the signal VB changes according to the change in the voltage of the signal line 22, and the magnitude of the current flowing through each current source 25 changes. Assuming that the imaging element 3 does not have the supply unit 30, the voltage of the signal line 22 drops significantly, and the voltage of the signal VB also drops significantly, considering that the current supplied from the current source 25 decreases or no current is supplied from the current source 25. When the voltage of the signal line 22 provided for a certain pixel block 20 changes, the voltage of the signal line 22 provided for other pixel blocks 20 also changes due to the change in the voltage of the signal VB commonly supplied to each current source 25.

[0068] On the other hand, in the imaging element 3 of the present embodiment, a supply unit 30 is provided for each pixel block 20. When the switch unit 32 is in the on state, the supply unit 30 can supply a voltage based on the signal CLIP to the signal line 22, and can limit the voltage of the signal line 22. Therefore, the imaging element 3 can suppress the change in the voltage of the signal VB by limiting the voltage of the signal line 22. Thus, it is possible to suppress the mixing of noise caused by the change in the voltage of the signal VB into the signal (photoelectric conversion signal, dark signal) output to the signal line 22.

[0069] In this embodiment, when the voltage of FD13 is relatively low, the voltage of the signal line 22 is limited (limiting operation), and when the voltage of FD13 is relatively high, the limiting operation is not performed. When the limiting operation is performed and when the limiting operation is not performed, the flow path of the current of the current source 25 changes as described above. When the limiting operation is performed, the current of the current source 25 flows between the power supply line 121 and the power supply line 122. Figure 4 The current of the current source 25 flows between the power supply line 121 and the ground line (ground wiring) 131 via the signal output unit 31 of the supply unit 30. When the limiting operation is not performed, the current of the current source 25 flows between the power supply line 121 and the ground line (ground wiring) 131 via the amplifier unit 15 of the pixel 10. Figure 4 As schematically shown, wiring resistance is added to the power line 121 and the ground line 131 , and therefore a voltage drop (IR drop) due to the wiring resistance occurs.

[0070] Due to the influence of the change in the above-mentioned current path, the voltage drop in the power supply line 121 and the ground line 131 will change in the case of performing the limiting operation and in the case of not performing the limiting operation, and the value of the power supply voltage VDD applied to each pixel 10 via the power supply line 121 will vary. When reading signals simultaneously from multiple pixel blocks 20, during the period of reading the signals, in the pixel blocks 20 where the limiting operation is performed in other pixel blocks 20 and in the pixel blocks 20 where the limiting operation is not performed in other pixel blocks 20, differences in the signals of the pixels will occur due to fluctuations in the power supply voltage VDD. Additionally, if a fluctuation in the power supply voltage VDD occurs during the reading of the photoelectric conversion signal, the signal level of the reset voltage of FD13, that is, the signal level serving as the reference for the voltage change generated according to the charge transmitted from the photoelectric conversion unit 11, will change. If a difference in the signal level of the reset voltage occurs during the reading period of the dark signal and the reading period of the photoelectric conversion signal, CDS processing will be performed using the dark signal with a signal level different from the signal level that should serve as the reference for the photoelectric conversion signal, and the image generated using the signal after CDS processing will exhibit, for example, blackening or streaks. In particular, when supplying the power supply voltage to the pixel 10 and the supply unit 30 via different power supply lines from different electrodes, it is considered that the difference in the value of the power supply voltage supplied to the pixel 10 in the case of performing the limiting operation and in the case of not performing the limiting operation becomes larger.

[0071] In the present embodiment, the pixel 10 and the supply unit 30 are arranged on the same first substrate 111. Additionally, the power supply voltage VDD is supplied to the pixel 10 and the supply unit 30 from a common electrode 200 via a common power supply line 121. Thereby, the difference in the power supply voltage VDD applied to the pixel 10 when performing the limiting operation and when not performing the limiting operation can be reduced. Therefore, it is possible to suppress differences in the signals of the respective pixels caused by fluctuations in the power supply voltage. As a result, it is possible to prevent blackening or streaks from occurring in the image generated using the signals of the pixels.

[0072] Figure 7 FIG. is an example showing a layout of a part of the imaging element according to the first embodiment. In each of the multiple pixel blocks 20 of the imaging element 3, a plurality of pixels 10 including the photoelectric conversion unit 11 are arranged along the row direction (X direction) as the first direction and the column direction (Y direction) as the second direction intersecting the first direction. In Figure 7 In the example shown, the pixel block 20 is provided with four pixels 10, four switch units 32, and one signal output unit 31. In the first substrate 111 of the imaging element 3, a plurality of pixel blocks 20 including four pixels 10 are arranged along the row direction (horizontal direction) and the column direction (vertical direction). The four switch units 32 and one signal output unit 31 constitute the supply unit 30. In addition, inFigure 7 Part of the wiring provided in pixel block 20 is schematically shown.

[0073] In Figure 7 In the example shown, signal output unit 31 is connected to each of the four switch units 32, and supplies voltage to each of the four switch units 32. A limiter operation is performed using one signal output unit 31 provided for each pixel block 20. Therefore, compared with the case where a plurality of signal output units 31 are provided within pixel block 20, the light-receiving area of the photoelectric conversion unit 11 can be increased. A decrease in the aperture ratio of the pixels can be prevented. In addition, the limiter operation can be performed without increasing the chip area, and deterioration of the image quality of the image generated using the signals of the pixels can be suppressed.

[0074] According to the above-described embodiment, the following operational effects can be obtained.

[0075] (1) The imaging element 3 includes: a first substrate 111 provided with a photoelectric conversion unit 11 that generates charges through photoelectric conversion, a signal line 22 that outputs a signal based on the charges generated by the photoelectric conversion unit 11, and a supply unit 30 that supplies voltage to the signal line 22; and a second substrate 112 laminated with the first substrate 111, provided with a processing unit 50 that processes the signal output to the signal line 22. In the present embodiment, the pixel 10 having the photoelectric conversion unit 11 and the supply unit 30 are arranged on the same first substrate 111. Therefore, fluctuations in the power supply voltage accompanying the operation of the supply unit 30 can be reduced, and deterioration of the quality of the pixel signals can be prevented. Thereby, deterioration of the image quality of the image generated using the pixel signals can be suppressed.

[0076] (2) In the present embodiment, the readout unit 60 having a plurality of processing units 50 is arranged on the second substrate 112. Therefore, a plurality of circuits for processing pixel signals can be arranged without increasing the chip area. In addition, a decrease in the aperture ratio of the pixels can be suppressed.

[0077] The following modifications also fall within the scope of the present invention, and one or more of the modification examples can also be combined with the above-described embodiment.

[0078] (Modification Example 1)

[0079] Figure 8 is a diagram showing an example of the layout of a part of the imaging element of Modification Example 1. As Figure 8 shown, pixel block 20 may be configured not to have switch unit 32. Signal output unit 31 is electrically connected to signal line 22 without passing through switch unit 32, and voltage can be supplied to signal line 22 both in the case of reading out dark signals and in the case of reading out photoelectric conversion signals. In this modification example, switch unit 32 can be reduced, and the chip area can be decreased. In addition, the light-receiving area of the photoelectric conversion unit 11 can also be increased.

[0080] (Modification Example 2)

[0081] Figure 9 This is a diagram showing an example of the layout of a part of the imaging element of Modification Example 2. As Figure 9 shown, the signal output section 31 can also be provided for each pixel 10. In Figure 9 the example shown, four signal output sections 31 and four switch sections 32 are arranged for each pixel block 20.

[0082] It is also possible to configure to supply the signal CLIP to each signal output section 31 or to every plurality of signal output sections 31 using different wirings. In this case, the number of signal output sections 31 connected to one wiring can be reduced, and the switching of the signal level of the signal CLIP can be performed at high speed.

[0083] (Modification Example 3)

[0084] In the above-described embodiment, an example in which the signal line 22 and the supply section 30 are provided for each pixel block 20 has been described. However, the signal line 22 may be arranged for each pixel 10, and the supply section 30 may be arranged for each signal line 22. In this case, the pixel control section 35 may be arranged for each pixel 10, and the supply control section 36 may be arranged for each supply section 30. Each supply control section 36 can also control the supply section 30 provided for each signal line 22 so that a voltage can be supplied at different timings for each signal line 22.

[0085] (Modification Example 4)

[0086] The pixel 10 and the supply section 30 are constituted by an analog circuit using MOS transistors. The analog circuit is provided on the first substrate 111, and a digital circuit such as the AD conversion section 40 is provided on the second substrate 112. A process most suitable for the analog circuit can be applied to the first substrate 111, and a process most suitable for the digital circuit can be applied to the second substrate 112. Moreover, if the pixel 10 and the supply section 30 are constituted by using NMOS transistors (or PMOS transistors), well isolation can be dispensed with. In addition, by using the same NMOS transistors to constitute the pixel 10 and the supply section 30, the manufacturing process of the imaging element can be shortened.

[0087] The pixel 10 and the supply unit 30 can be formed using NMOS transistors, or can be formed using PMOS transistors. The pixel 10 and the supply unit 30 can also be formed using both NMOS transistors and PMOS transistors. When the amplification unit 15 and the signal output unit 31 are formed of NMOS transistors, when reading the photoelectric conversion signal, as described above, a signal CLIP with a voltage lower than that when reading the dark signal can also be supplied to the signal output unit 31. When the amplification unit 15 and the signal output unit 31 are formed of PMOS transistors, when reading the photoelectric conversion signal, a signal CLIP with a voltage higher than that when reading the dark signal can be supplied to the signal output unit 31. The supply unit 30 supplies a voltage to the signal line 22 such that the voltage of the signal line 22 becomes a value from the power supply voltage (or the ground voltage) to the voltage based on the signal CLIP. The voltage of the signal line 22 is limited by the supply unit 30 to a value within a range with the voltage based on the signal CLIP as the upper limit value or the lower limit value.

[0088] (Modification Example 5)

[0089] In the above-described embodiment, an example in which the imaging element 3 is formed by laminating the first substrate 111 and the second substrate 112 has been described. However, the first substrate 111 and the second substrate 112 may not be laminated.

[0090] (Modification Example 6)

[0091] In the above-described embodiment, an example in which the imaging element 3 has a back-illuminated structure has been described. However, the imaging element 3 may have a front-illuminated structure in which a wiring layer 101 is provided on the light-incident surface side.

[0092] (Modification Example 7)

[0093] In the above-described embodiment and modification examples, an example in which a photodiode is used as the photoelectric conversion unit has been described. However, a photoelectric conversion film (organic photoelectric film) may also be used as the photoelectric conversion unit.

[0094] (Modification Example 8)

[0095] The imaging element and the imaging device described in the above-described embodiment and modification examples can be applied to cameras built into cameras, smartphones, tablet computers, cameras of PCs, in-vehicle cameras, cameras mounted on unmanned aircraft (drones, radio-controlled aircraft, etc.), and the like.

[0096] As described above, various embodiments and modification examples have been described, but the present invention is not limited to these. Other aspects that can be considered within the technical idea of the present invention are also included in the scope of the present invention.

[0097] The disclosure of the following priority-based application is hereby incorporated by reference as a cited document.

[0098] Japanese Patent Application No. 2019-180780 (filed on September 30, 2019)

[0099] Explanation of Reference Numerals

[0100] 1... imaging device, 3... imaging element, 4... control unit, 10... pixel, 11... photoelectric conversion unit, 20... pixel block, 30... supply unit, 35... pixel control unit, 36... supply control unit, 40... AD conversion unit, 50... processing unit, 60... readout unit, 70... readout control unit, 111... first substrate, 112... second substrate.

Claims

1. An imaging element includes a first substrate and a second substrate laminated with the first substrate. The first substrate has: A first pixel block including a first photoelectric conversion unit that converts light into charge, and a first signal based on the charge converted by the first photoelectric conversion unit is output to a first signal line; A second pixel block including a second photoelectric conversion unit arranged side by side with the first photoelectric conversion unit in the column direction. The second photoelectric conversion unit is a photoelectric conversion unit that converts light into charge, and a second signal based on the charge converted by the second photoelectric conversion unit is output to a second signal line; A first supply unit that supplies a first voltage to the first signal line; and A second supply unit that supplies a second voltage to the second signal line. The second substrate has: A first processing unit that performs signal processing on the first signal output to the first signal line; and A second processing unit that performs signal processing on the second signal output to the second signal line. A first pixel control unit for reading the first signal from the first pixel block to the first signal line; A second pixel control unit for reading the second signal from the second pixel block to the second signal line; A first control unit that controls to supply the first voltage from the first supply unit to the first signal line when the first pixel control unit reads the first signal from the first pixel block to the first signal line; and A second control unit that controls to supply the second voltage from the second supply unit to the second signal line when the second pixel control unit reads the second signal from the second pixel block to the second signal line. The second pixel control unit controls such that the timing of reading the second signal from the second pixel block to the second signal line is different from the timing of reading the first signal from the first pixel block to the first signal line.

2. The imaging element according to claim 1, wherein The first supply unit controls so as not to make the voltage of the first signal line fall below a specified voltage. The second supply unit controls so as not to make the voltage of the second signal line fall below a specified voltage.

3. The imaging element according to claim 1, wherein The first pixel control unit reads a first dark signal from the first pixel block to the first signal line. The first dark signal is used to remove noise included in the first signal. The second pixel control unit reads a second dark signal from the second pixel block to the second signal line. The second dark signal is used to remove noise included in the second signal. The first control unit controls to supply a third voltage higher than the first voltage from the first supply unit to the first signal line when the first pixel control unit reads the first dark signal from the first pixel block to the first signal line. When the second pixel control unit reads the second dark signal from the second pixel block to the second signal line, the second control unit controls to supply a fourth voltage different from the second voltage from the second supply unit to the second signal line.

4. The imaging element according to claim 3, wherein the third voltage is higher than the first voltage, the fourth voltage is higher than the second voltage.

5. The imaging element according to claim 1, wherein the first pixel block includes a third photoelectric conversion unit that converts light into charge and is disposed adjacent to the first photoelectric conversion unit in the column direction, the second pixel block includes a fourth photoelectric conversion unit that converts light into charge and is disposed adjacent to the second photoelectric conversion unit in the column direction, a third signal based on the charge converted by the third photoelectric conversion unit is output to the first signal line, a fourth signal based on the charge converted by the fourth photoelectric conversion unit is output to the second signal line, the first processing unit performs signal processing on the third signal output to the first signal line, the second processing unit performs signal processing on the fourth signal output to the second signal line, the first pixel control unit reads the third signal from the first pixel block to the first signal line, the second pixel control unit reads the fourth signal from the second pixel block to the second signal line.

6. The imaging element according to claim 5, wherein when the first pixel control unit reads the third signal from the first pixel block to the first signal line, the first control unit controls to supply the first voltage from the first supply unit to the first signal line, when the second pixel control unit reads the fourth signal from the second pixel block to the second signal line, the second control unit controls to supply the second voltage from the second supply unit to the second signal line.

7. The imaging element according to claim 6, wherein the first pixel block includes a fifth photoelectric conversion unit that converts light into charge and is disposed adjacent to the first photoelectric conversion unit in the row direction, the second pixel block includes a sixth photoelectric conversion unit that converts light into charge and is disposed adjacent to the second photoelectric conversion unit in the row direction, a fifth signal based on the charge converted by the fifth photoelectric conversion unit is output to the first signal line, a sixth signal based on the charge converted by the sixth photoelectric conversion unit is output to the second signal line, the first processing unit performs signal processing on the fifth signal output to the first signal line, the second processing unit performs signal processing on the sixth signal output to the second signal line, the first pixel control unit reads the fifth signal from the first pixel block to the first signal line, The second pixel control unit reads out the sixth signal from the second pixel block to the second signal line.

8. The imaging element according to claim 7, comprising: When the first control unit reads out the fifth signal from the first pixel block to the first signal line by the first pixel control unit, the first control unit controls to supply the first voltage from the first supply unit to the first signal line. When the second control unit reads out the sixth signal from the second pixel block to the second signal line by the second pixel control unit, the second control unit controls to supply the second voltage from the second supply unit to the second signal line.

9. The imaging element according to claim 1, wherein The first pixel block includes a third photoelectric conversion unit disposed beside the first photoelectric conversion unit in the row direction, and the third photoelectric conversion unit is a photoelectric conversion unit that converts light into charges. The second pixel block includes a fourth photoelectric conversion unit disposed beside the second photoelectric conversion unit in the row direction, and the fourth photoelectric conversion unit is a photoelectric conversion unit that converts light into charges. The first signal line outputs a third signal based on the charges converted by the third photoelectric conversion unit. The second signal line outputs a fourth signal based on the charges converted by the fourth photoelectric conversion unit. The first processing unit performs signal processing on the third signal output to the first signal line. The second processing unit performs signal processing on the fourth signal output to the second signal line. The first pixel control unit reads out the third signal from the first pixel block to the first signal line. The second pixel control unit reads out the fourth signal from the second pixel block to the second signal line.

10. The imaging element according to claim 9, wherein When the first control unit reads out the third signal from the first pixel block to the first signal line by the first pixel control unit, the first control unit controls to supply the first voltage from the first supply unit to the first signal line. When the second control unit reads out the fourth signal from the second pixel block to the second signal line by the second pixel control unit, the second control unit controls to supply the second voltage from the second supply unit to the second signal line.

11. The imaging element according to claim 1, wherein The first pixel control unit controls the storage time for storing the charges converted by the first photoelectric conversion unit. The second pixel control unit controls the storage time for storing the charges converted by the second photoelectric conversion unit.

12. The imaging element according to claim 11, wherein The second pixel control unit controls such that the storage time of the charges converted by the second photoelectric conversion unit is different from the storage time of the charges converted by the first photoelectric conversion unit.

13. The imaging element according to claim 1, wherein The second photoelectric conversion unit is disposed beside the first photoelectric conversion unit in the column direction.

14. The imaging element according to claim 1, wherein An electrode provided on the first substrate and supplied with a power supply voltage, The first supply unit and the second supply unit are electrically connected to the electrode.

15. The imaging element according to claim 1, wherein, It further includes a third processing unit, The first processing unit has a first conversion unit that converts the first signal output to the first signal line into a digital signal, The second processing unit has a second conversion unit that converts the second signal output to the second signal line into a digital signal, The third processing unit has a third conversion unit that converts the third signal output to the third signal line into a digital signal.

16. The imaging element according to claim 15, wherein, The first signal line, the second signal line, and the third signal line are arranged in a wiring layer sandwiched between the first substrate and the second substrate in the stacking direction in which the first substrate and the second substrate are stacked.

17. An imaging device comprising the imaging element according to any one of claims 1 to 16.

Images