Method, device and medium for implementing data arrangement

Abstract

The embodiments of the present disclosure relate to a method, device and medium for realizing data arrangement, the method comprising: based on the number of threads of a thread group and data arrangement requirements, obtaining first auxiliary data and second auxiliary data; shifting data in a first register, the first auxiliary data, the data in a second register and the second auxiliary data to a transfer register; based on the address of the transfer register, extracting the data in the transfer register, thereby obtaining first data, second data, third data and fourth data; based on the number of threads of the thread group and data arrangement requirements, determining mapping parameters; and based on the mapping parameters, mapping the third data to the first register and mapping the fourth data to the second register, thereby realizing data arrangement in registers. Thus, data arrangement between multiple registers can be realized more quickly without calculating a shared memory address.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of processors, and more particularly to a method, a computing device, and a computer-readable storage medium for implementing data arrangement. Background Art

[0002] Generally speaking, in general-purpose computing on graphics processing units (GPGPU), it usually involves fast Fourier transform (FFT) operations with real input and complex output (R2C). The operation requires the real number sequence of the original input to be arranged (for example, odd-even rearrangement) to be reassembled into a new complex number sequence. This involves arranging data between thread groups (warps) between different registers. The arrangement operation requires data interaction between thread groups.

[0003] The main way of data interaction between existing thread groups is through shared memory. The system first calculates the corresponding shared memory address of different thread data according to the index, and then writes the data on the register to the shared memory through the store instruction. Finally, it is written back to the register through the load instruction. Due to the uncertainty of scheduling between threads, it is necessary to wait for all threads to complete the write operation before performing the read operation, which requires additional synchronization operations. At the same time, if there is a write to the same location, it can only be processed serially. This method increases the reading delay of instructions and wastes the data bandwidth of the instruction memory. In addition, the index calculation of the shared memory is relatively complex and requires additional calculation to be converted into the corresponding address.

[0004] In summary, the shortcomings of the traditional solution for realizing data arrangement are: adding complex calculation operations of shared memory index address conversion, and the read and write operations of the shared memory have a long delay, which affects the program performance. Summary of the invention

[0005] In view of the above problems, the present disclosure provides a method, a computing device and a computer-readable storage medium for implementing data arrangement, which can more quickly implement data arrangement among multiple registers without calculating shared memory addresses.

[0006] According to a first aspect of the present disclosure, a method for implementing data arrangement in a register is provided, comprising: acquiring first auxiliary data and second auxiliary data based on the number of threads of a thread group and data arrangement requirements; shifting the data in the first register, the first auxiliary data, the data in the second register, and the second auxiliary data to a transfer register; extracting the data in the transfer register based on the address of the transfer register, thereby acquiring first data, second data, third data, and fourth data; determining mapping parameters based on the number of threads of the thread group and data arrangement requirements; and mapping the third data to the first register and mapping the fourth data to the second register based on the mapping parameters, thereby implementing data arrangement in the register.

[0007] According to a second aspect of the present disclosure, a computing device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method of the first aspect of the present disclosure.

[0008] In a third aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the method of the first aspect of the present disclosure.

[0009] In one embodiment, the method further includes: writing the first data, the second data, the third data and the fourth data into the first register, the second register, the third register and the fourth register respectively.

[0010] In one embodiment, mapping the third data to the first register and mapping the fourth data to the second register includes: applying a mask to the third register and the fourth register; and mapping the data in the third register with the mask applied to the first register every mapping parameter bit and mapping the data in the fourth register with the mask applied to the second register every mapping parameter bit, wherein the mapping parameter bit is determined based on the mapping parameter.

[0011] In one embodiment, mapping the third data to the first register and mapping the fourth data to the second register includes: mapping the data of the current mapping parameter bits of the third register and the fourth register to the current mapping parameter bits of the fifth register and the sixth register, respectively; mapping the data of the third register and the fourth register to the next mapping parameter bits of the fifth register and the sixth register, respectively, wherein the data of the last mapping parameter bits of the third register and the fourth register are not mapped; applying a mask to the fifth register and the sixth register; and mapping the data in the fifth register with the mask applied to the first register and mapping the data in the sixth register with the mask applied to the second register.

[0012] In one embodiment, determining the mapping parameter based on the number of threads of the thread group and the data arrangement requirement includes: determining the mapping parameter as one eighth of the number of threads of the thread group.

[0013] In one embodiment, performing extraction on the data in the transfer register includes: constructing a sequence based on the number of threads in the thread group, wherein each element in the constructed sequence corresponds to the data in the transfer register; combining the data in the transfer register into a set of multiple data columns; and performing extraction on the combined set consisting of multiple data columns.

[0014] In one embodiment, performing extraction on the combined set consisting of multiple data columns includes: determining coordinate values ​​of elements in the multiple number columns, wherein the coordinate values ​​include horizontal coordinates and vertical coordinates corresponding to the elements; and based on the determined coordinate values, performing extraction on the combined set of multiple number columns in the order of the horizontal coordinate being an even number and the vertical coordinate being an even number, the horizontal coordinate being an even number and the vertical coordinate being an odd number, the horizontal coordinate being an odd number and the vertical coordinate being an even number, and the horizontal coordinate being an odd number and the vertical coordinate being an odd number.

[0015] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0017] Figure 1 A schematic diagram of a system 100 for implementing a method for data arrangement according to an embodiment of the present invention is shown.

[0018] Figure 2 A flow chart of a method 200 for implementing data arrangement in a register according to an embodiment of the present disclosure is shown.

[0019] Figure 3 A schematic diagram of a transfer register after shifting according to an embodiment of the present disclosure is shown.

[0020] Figure 4 A schematic diagram of data of a transfer register composed of a set of multiple number series according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A schematic diagram showing the extracted first data, second data, third data and fourth data according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A schematic diagram showing a mapping result according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic diagram of mapping the third register, the fourth register, the fifth register and the sixth register according to an embodiment of the present disclosure is shown.

[0024] Figure 8 A schematic diagram is shown of mapping data in the fifth register and the sixth register to the first register and the second register according to an embodiment of the present disclosure.

[0025] Fig. 9 A schematic block diagram of an example electronic device 900 is shown that may be used to implement embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0027] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0028] As described above, the existing method of data interaction between thread groups is mainly through shared memory. The system first calculates the corresponding shared memory address of different thread data according to the index, and then writes the data on the register to the shared memory through the store instruction (store). Finally, it is written back to the register through the load instruction (load). Due to the uncertainty of scheduling between threads, it is necessary to wait for all threads to complete the write operation before performing the read operation, which requires additional synchronization operations. At the same time, if there is a write to the same location, it can only be processed serially. This method increases the delay of instruction reading and wastes the data bandwidth of the instruction memory. In addition, the index calculation of the shared memory is relatively complex and needs to be converted into additional calculations of the corresponding address. Therefore, the additional calculation of the shared memory index and address calculation consumes a lot of energy and has serious delays. At the same time, the delay in the read and write operations of the shared memory is long, which affects the performance of the program.

[0029] In order to at least partially solve one or more of the above problems and other potential problems, an example embodiment of the present disclosure proposes a scheme for generating a data report. In the scheme of the present disclosure, by utilizing two additional registers and a transfer register in a thread group, it is possible to arrange the data stored in the two registers, for example, continuous 1-64. Arrangement may refer to reordering a plurality of continuous data, for example, continuous data 1-64 stored in two registers of 32 threads in a thread group (warp), into odd columns 1, 3, 5..., 63 and even columns 2, 4, 6..., 64. Finally, the two registers will store corresponding odd columns and even columns.

[0030] Figure 1 FIG. 1 is a schematic diagram of a system 100 for implementing a method for data arrangement according to an embodiment of the present invention. Figure 1 As shown in FIG. 1 , the system 100 includes a computing device 110, a data storage device 130, and a network 140. The computing device 110 and the data storage device 130 can exchange data through the network 140 (eg, the Internet).

[0031] The data storage device 130 may store, for example, multiple types of different data storage, for example, storing consecutive numbers to be sorted, etc. The data storage device 130 may also send the stored data storage to the computing device 110. The data storage device may be a one-stop storage computing structure running on one or more computer nodes for implementing high-concurrency, high-throughput query services, which may include dedicated processing units such as GPUs, FPGAs, and ASICs, as well as general-purpose processing units such as CPUs.

[0032] Regarding the computing device 110, it is used, for example, to obtain data storage from the data storage device 130; thereby performing arrangement on the received data. The rearranged odd and even columns can be stored in two registers in the same warp. The computing device 110 can have one or more processing units, including dedicated processing units such as GPU, FPGA and ASIC, and general processing units such as CPU. In addition, one or more virtual machines can also be running on each computing device 110. In some embodiments, the computing device 110 and the data storage device 130 can be integrated together or separately arranged from each other. In some embodiments, the computing device 110 includes, for example, an acquisition module 112, a shift module 114, an extraction module 116, a determination module 118 and a mapping module 120.

[0033] The acquisition module 112 is configured to acquire the first auxiliary data and the second auxiliary data based on the number of threads of the thread group and the data arrangement requirement.

[0034] The shift module 114 is configured to shift the data in the first register, the first auxiliary data, the data in the second register, and the second auxiliary data to the transfer register.

[0035] The extraction module 116 is configured to extract the data in the transfer register based on the address of the transfer register, thereby obtaining the first data, the second data, the third data and the fourth data.

[0036] The determination module 118 is configured to determine mapping parameters based on the number of threads and data arrangement requirements of the thread group.

[0037] The mapping module 120 is configured to map the third data to the first register and map the fourth data to the second register based on the mapping parameters, thereby achieving data arrangement in the registers.

[0038] Figure 2 1 is a flow chart of a method 200 for implementing data arrangement in a register according to an embodiment of the present disclosure. The method 200 may be performed as follows: Figure 1 The computing device 110 shown may also be executed in Figure 8 The method 200 is executed at the electronic device 800 shown. It should be understood that the method 200 may further include additional blocks not shown and / or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0039] In the context of this application, a register may refer to a warp, for example, a register set including a first register and a second register. The register sets may be located in the same warp or in different warps.

[0040] In one embodiment, for example, a warp may include 8, 16, 32, or 64 threads. For the sake of brevity, the present disclosure will be introduced with 32 threads. It is noted that warps with other numbers of threads are also applicable to the technical solutions introduced in the present disclosure.

[0041] In step 202 , the computing device 110 may obtain first auxiliary data and second auxiliary data based on the number of threads of the thread group and data arrangement requirements.

[0042] In one embodiment, the number of bits of the first auxiliary data and the second auxiliary data may be the same as the number of threads of the thread group. For example, if the number of threads of the thread group is 32, the first auxiliary data and the second auxiliary data may be 32-bit data. For the sake of simplicity, the context of this application uses 32 threads as an illustration. As described above, the first and second registers corresponding to the 32 threads respectively store data columns 1, 2, 3 ..., 32 and 33, 34, 35, ..., 64. In the context of this application, the data arrangement requirement may refer to exchanging, inserting, rearranging, etc. the data corresponding to the threads. For the sake of simplicity, the context of this application will be described by reordering the data corresponding to the two groups of 32 threads by 1 bit. For example, the data in the first thread group and the second thread group are exchanged and sorted, so that after sorting, the first register corresponding to the first thread group stores odd columns (1, 3, 5, 7, ..., 63) and the second register corresponding to the second thread group stores even columns (2, 4, 6, 8, ..., 64).

[0043] In one embodiment, the first auxiliary data and the second auxiliary data may be any data used to fill the register. For example, the first auxiliary data and the second auxiliary data may be selected from 32 consecutive number sequences, such as 1, 2, 3 ... 32, or the same data sequence, such as 32 zeros. For the sake of introduction, the context of this application uses 32 consecutive zeros as the first auxiliary data and the second auxiliary data.

[0044] At step 204 , the computing device 110 may shift the data in the first register, the first auxiliary data, the data in the second register, and the second auxiliary data to the transfer register.

[0045] In one embodiment, the computing device 110 may shift the data 1, 2, 3, ..., 32 in the first register R4, the first auxiliary data 32 zeros, the data 33, 34, 35, ..., 64 in the second register R5, and the second auxiliary data 32 zeros to the transfer register X0. Figure 3 A schematic diagram of a shifted transfer register according to an embodiment of the present disclosure is shown. The shifted transfer register X0 will be extracted in subsequent steps to achieve data arrangement. Since the transfer register X0 is a special register, its size is 4 times that of the first register, and it can store data of 4 first registers.

[0046] In step 206 , the computing device 110 may extract the data in the transfer register X0 based on the address of the transfer register, thereby obtaining the first data, the second data, the third data, and the fourth data.

[0047] In one embodiment, performing extraction on the data in the transfer register X0 may include: constructing a sequence based on the number of threads (eg, 32) of the thread group, wherein each element in the constructed sequence corresponds to the mapped data.

[0048] Specifically, the computing device 110 may construct a sequence based on the 32-bit data of the first register and the second register. The sequence is constructed as a 4×8 sequence, so that a 32-bit register is divided into 4 groups of 8 bits. For example, the data shifted to the first row in the transfer register X0 may be divided into 1, 2, 3…8 and 9, 10, 11…18 and 19, 20, 21…24 and 25, 26, 27…32. The data shifted to the second row in the transfer register may be divided into eight bits 0 and eight bits 0 and eight bits 0 and eight bits 0. The data shifted to the third row in the transfer register may be divided into 33, 34, 35…40 and 41, 42, 43…48 and 49, 50, 51…56 and 57, 58, 59…64. The data shifted to the second row in the transfer register may be divided into eight bits 0 and eight bits 0 and eight bits 0 and eight bits 0.

[0049] Subsequently, in one embodiment, the computing device 110 may combine the data of the transfer register into a set of multiple data columns, such as a set of four 4×8 data columns. Figure 4 FIG. 1 is a schematic diagram showing data of a transfer register composed of a set of multiple number series according to an embodiment of the present disclosure. Figure 4As shown, the data of the transfer register X0 can be represented by a set consisting of four 4×8 number sequences. For example, for the data of the first row in the transfer register X0, it can be constructed as 1, 2, 3, ..., 8 and 9, 10, 11, ..., 16 and 17, 18, 19, ..., 24 and 25, 26, 27, ..., 32, that is, 4×8 data sequences. For the data of the second row in the transfer register X0, it can be constructed as 4 8-bit data sequences of 0, and so on. Based on the constructed data sequences, the address of the transfer register can be combined into, for example, a set of 4 4×8 data sequences, wherein the 4×8 data sequence composed of the data of the first row can be located at the upper left of the set, the 4×8 data sequence composed of the data of the second row can be located at the upper right of the set, the 4×8 data sequence composed of the data of the third row can be located at the lower left of the set, and the 4×8 data sequence composed of the data of the fourth row can be located at the lower right of the set.

[0050] The data in the upper left corner of the set composed of multiple data columns is composed of a 4×8 number sequence originally belonging to the first register (1, 2, 3...8 and 9, 10, 11...18 and 19, 20, 21...24 and 25, 26, 27...32), the data in the upper right corner is composed of a 4×8 number sequence originally belonging to the first auxiliary data (eight bits 0 and eight bits 0 and eight bits 0 and eight bits 0), the data in the lower left corner is composed of a 4×8 number sequence originally belonging to the second register (33, 34, 35...40 and 41, 42, 43...48 and 49, 50, 51...56 and 57, 58, 59...64), and the data in the lower right corner is composed of a 4×8 number sequence originally belonging to the second auxiliary data (eight bits 0 and eight bits 0 and eight bits 0 and eight bits 0).

[0051] The set can be represented by a coordinate system, where the coordinate values ​​of the coordinate system include the horizontal coordinate and the vertical coordinate corresponding to the data. Taking the upper left point, the y-axis is to the right and the x-axis is to the bottom. Starting from the origin, in the first 2×2 matrix, the coordinate value corresponding to the first data 1 is (0, 0), the coordinate value corresponding to data 2 is (0, 1), the coordinate value corresponding to data 9 is (1, 0), the coordinate value corresponding to data 10 is (1, 1), and so on for the remaining data.

[0052] Based on the determined coordinate values, the computing device 110 may perform extraction on the combined set consisting of the plurality of data columns. Specifically, the set consisting of the plurality of data columns may be extracted in the order of an even abscissa and an even ordinate, an even abscissa and an odd ordinate, an odd abscissa and an even ordinate, and an odd abscissa and an odd ordinate. The extracted data may be four types of data, namely, first data having an even abscissa and an even ordinate, second data having an even abscissa and an odd ordinate, third data having an odd abscissa and an even ordinate, and fourth data having an odd abscissa and an odd ordinate.

[0053] In one embodiment, the computing device 110 may also write the extracted first data, second data, third data and fourth data into the first register R4, the second register R5, the third register R6 and the fourth register R7 respectively. The third register R6 and the fourth register R7 will be used for mapping data in subsequent steps.

[0054] Figure 5 FIG. 1 is a schematic diagram showing the first data, the second data, the third data and the fourth data extracted according to an embodiment of the present disclosure. Figure 5 As shown, the extracted first data, second data, third data and fourth data are written into the first register R4, the second register R5, the third register R6 and the fourth register R7 respectively.

[0055] At step 208 , the computing device 110 may determine mapping parameters based on the number of threads and data arrangement requirements of the thread group.

[0056] In one embodiment, the mapping parameter k is determined as one eighth of the number of threads in the thread group. When the number of threads in the thread group is 32, the mapping parameter k may be 4.

[0057] In step 210 , the computing device 110 may map the third data to the first register and map the fourth data to the second register based on the mapping parameters, thereby achieving data arrangement in the registers.

[0058] In one embodiment, the computing device 110 may apply a mask to the third register R6 and the fourth register R7. For example, the mask may be 0xf0f0f0f0, that is, 11110000111100001111000011110000. When such a mask is applied, data will be mapped once every four threads, that is, threads at positions where the number of bits of the applied mask is 1 may be mapped and threads at positions where the number of bits of the applied mask is 0 may not be mapped.

[0059] In one embodiment, the computing device 110 maps the data in the third register R6 to which the mask is applied to the first register R4 every mapping parameter bit (i.e., 4 bits) and maps the data in the fourth register R7 to which the mask is applied to the second register R5 every mapping parameter bit (i.e., 4 bits), wherein the mapping parameter bit is determined based on the mapping parameter. For example, if the mapping parameter is 4, the mapping parameter bit is 4 bits.

[0060] For example, based on the applied mask (0xf0f0f0f0), the computing device 110 may map the data (9, 11, 13, 15) corresponding to threads T0-T3 in the third register R6 to threads T4-T7 in the first register R4 and overwrite 0, 0, 0, 0 in threads T4-T7. By analogy, the computing device 110 may map the data (25, 27, 29, 31) corresponding to threads T8-T11 in the third register R6 to threads T12-T15 of the first register R4 and overwrite 0, 0, 0, 0 of threads T12-T15, map the data (41, 43, 45, 47) corresponding to threads T16-T19 in the third register R6 to threads T20-T23 of the first register R4 and overwrite 0, 0, 0, 0 of threads T20-T23, and map the data (57, 59, 61, 63) corresponding to threads T24-T27 in the third register R6 to threads T28-T31 of the first register R4 and overwrite 0, 0, 0, 0 of threads T28-T31.

[0061] Similarly, the computing device 110 may map the data (10, 12, 14, 16) corresponding to the threads T0-T3 in the fourth register R7 to the threads T4-T7 of the second register R5 and overwrite 0, 0, 0, 0 of the threads T4-T7, map the data (26, 28, 30, 32) corresponding to the threads T8-T11 in the fourth register R7 to the threads T12-T15 of the second register R5 and overwrite 0, 0, 0, 0 of the threads T12-T15, map the data (42, 44, 46, 48) corresponding to the threads T16-T19 in the fourth register R7 to the threads T20-T23 of the second register R5 and overwrite 0, 0, 0, 0 of the threads T20-T23, and map the data (58, 60, 62, 64) corresponding to the threads T24-T27 in the fourth register R7 to the threads T28-T31 of the second register R5. bits and overwrite 0, 0, 0, 0 of threads T28-T31.

[0062] Figure 6 FIG. 4 is a schematic diagram showing a mapping result according to an embodiment of the present disclosure. Figure 6As shown, the first register R4 stores data 1, 3, 5, 7, 9, ... and the second register R5 stores data 2, 4, 6, 8, 10, ..., thereby achieving rearrangement of data between the two registers, ie, parity rearrangement.

[0063] By adopting the above means, the computing device 110 can quickly use the additional registers to implement data arrangement. Also, this does not require the calculation of the address of the shared memory, and the data calculated in the previous method can be used, thereby reducing the power consumption of the arrangement.

[0064] In another embodiment, the computing device 110 may also directly map the data of the pre-mapped parameter bits of the third register R6 and the fourth register R7 to the pre-mapped parameter bits of the fifth register and the sixth register. For example, the computing device 110 may also directly map the pre-mapped parameter bits of the third register R6 and the fourth register R7, i.e., the first 4 bits of data, to the pre-mapped parameter bits of the fifth register R8 and the sixth register R9, i.e., the first 4 bits. For example, data 9, 11, 13, and 15 of the third register R6 corresponding to threads T0-T3 are directly mapped to the fifth register R8. Data 10, 12, 14, and 16 of the fourth register R7 corresponding to threads T0-T3 are directly mapped to the sixth register R9.

[0065] Subsequently, the computing device 110 may map the data of the third register R6 and the fourth register R7 to the next mapping parameter bit of the fifth register R8 and the sixth register R9, that is, the bit with 4 bits added. Since the first 4 bits of the fifth register R8 and the sixth register R9 have been mapped to the first 4 bits of the data of the third register R6 and the fourth register R7, the data of the last mapping parameter bit of the third register R6 and the fourth register R7 are not mapped, that is, the data of the fifth register and the sixth register corresponding to the last 4 threads (that is, the data corresponding to threads T28-T31) are not mapped. Figure 7 FIG. 4 shows a schematic diagram of mapping the third register R6, the fourth register R7, the fifth register R8, and the sixth register R9 according to an embodiment of the present disclosure. Figure 7 As shown, for example, the computing device 110 maps the data of the third register R6 corresponding to the threads T0-T27 to the fifth register R8. At the same time, the computing device 110 maps the data of the fourth register R7 corresponding to the threads T0-T27 to the sixth register R9.

[0066] Subsequently, the computing device 110 may apply a mask to the fifth register R8 and the sixth register R9. As described above, the mask may be 0xf0f0f0f0. When such a mask is applied, data will be mapped once every four threads, i.e., threads at positions where the number of bits of the applied mask is 1 may be mapped and threads at positions where the number of bits of the applied mask is 0 may not be mapped.

[0067] The computing device 110 maps the data in the masked fifth register R8 to the first register R4 every other mapping parameter bit (ie, 4 bits) and maps the data in the masked sixth register R9 to the second register R5 every other mapping parameter bit (ie, 4 bits).

[0068] Figure 8 FIG. 2 shows a schematic diagram of mapping the data in the fifth register R8 and the sixth register R9 to the first register R4 and the second register R5 according to an embodiment of the present disclosure. Figure 8 As shown, the data of the fifth register R8 and the sixth register R9 corresponding to the threads T4-T7, T12-T15, T20-T23, and T28-T31 are mapped to the respective first register R4 and the second register R5. Figure 6 Graph 1 shows the mapping result according to an embodiment of the present disclosure. Figure 6 As shown, the first register R4 stores data 1, 3, 5, 7, 9 ... and the second register R5 stores data 2, 4, 6, 8, 10 ..., thereby achieving data rearrangement between the two registers, for example, odd-even rearrangement. In this way, when two more registers are used, data rearrangement is also achieved.

[0069] By using the above technical means, data can be quickly arranged between two registers using only two additional registers and one transfer register, and there is no need to calculate the address of the shared memory, thereby reducing the power consumption of the arrangement.

[0070] By adopting the above means, the computing device 110 can quickly use the additional registers to implement data arrangement. Also, this does not require the calculation of the address of the shared memory, and the data calculated in the previous method can be used, thereby reducing the power consumption of the arrangement.

[0071] Fig. 9 900 is a schematic block diagram of an example electronic device 900 that can be used to implement an embodiment of the present disclosure. Figure 1The computing device 110 shown can be implemented by an electronic device 900. As shown, the electronic device 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 902 or computer program instructions loaded from a storage unit 908 into a random access memory (RAM) 903. In the random access memory 903, various programs and data required for the operation of the electronic device 900 can also be stored. The central processing unit 901, the read-only memory 902, and the random access memory 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0072] Multiple components in the electronic device 900 are connected to the input / output interface 905, including: an input unit 906, such as a keyboard, a mouse, a microphone, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0073] The various processes and processing described above, such as method 200, may be performed by the central processing unit 901. For example, in some embodiments, method 200 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via the read-only memory 902 and / or the communication unit 909. When the computer program is loaded into the random access memory 903 and executed by the central processing unit 901, one or more actions of the method 200 described above may be performed.

[0074] The present disclosure relates to methods, apparatuses, systems, electronic devices, computer-readable storage media and / or computer program products. The computer program products may include computer-readable program instructions for executing various aspects of the present disclosure.

[0075] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0076] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge computing devices. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0077] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of a computer-readable program instruction, and the electronic circuit may execute a computer-readable program instruction, thereby realizing various aspects of the present disclosure.

[0078] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0079] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0080] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0081] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0082] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for implementing data arrangement in a register, comprising: Based on the number of threads and data arrangement requirements of the thread group, obtain first auxiliary data and second auxiliary data; Shifting the data in the first register, the first auxiliary data, the data in the second register, and the second auxiliary data to the transfer register; Based on the address of the transfer register, extracting the data in the transfer register to obtain the first data, the second data, the third data and the fourth data, which includes constructing a data column based on the number of threads of the thread group, combining the data of the transfer register into a set of multiple data columns, and extracting the combined set consisting of the multiple data columns; Determine mapping parameters based on the number of threads and data arrangement requirements of the thread group; as well as Based on the mapping parameters, the third data is mapped to the first register and the fourth data is mapped to the second register, thereby realizing data arrangement in the registers, which includes applying a mask to the third register and the fourth register, mapping the data in the third register with the mask applied to the first register every mapping parameter bit and mapping the data in the fourth register with the mask applied to the second register every mapping parameter bit.

2. The method according to claim 1, further comprising: The first data, the second data, the third data and the fourth data are written into the first register, the second register, the third register and the fourth register respectively.

3. The method of claim 2, mapping the third data to the first register and mapping the fourth data to the second register comprising: Mapping the data of the current mapping parameter bits of the third register and the fourth register to the current mapping parameter bits of the fifth register and the sixth register respectively; Mapping the data of the third register and the fourth register to the next mapping parameter bits of the fifth register and the sixth register respectively, wherein the data of the last mapping parameter bits of the third register and the fourth register are not mapped; Applying a mask to the fifth register and the sixth register; as well as Data in the masked fifth register is mapped to the first register and data in the masked sixth register is mapped to the second register.

4. The method according to claim 1, wherein determining the mapping parameters based on the number of threads and data arrangement requirements of the thread group comprises: The mapping parameter is determined as one eighth of the number of threads of the thread group.

5. The method according to claim 1, wherein performing extraction on the combined set consisting of the plurality of data columns comprises: Determine coordinate values ​​of elements in the plurality of data columns, wherein the coordinate values ​​include abscissas and ordinates corresponding to the elements; as well as Based on the determined coordinate values, extraction is performed on the combined set of multiple data columns in the order of even abscissa and even ordinate, even abscissa and odd ordinate, odd abscissa and even ordinate, odd abscissa and odd ordinate.

6. A computing device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

7. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method of any one of claims 1 to 5.

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