Dynamic binary translation method using rule-based translation for stack-based floating-point architecture

Abstract

This invention provides a dynamic binary translation method for stack-based floating-point architectures using rule-based translation, expanding the applicability of translation rules and improving the support of existing dynamic binary translation systems for stack-based floating-point instruction sets. The specific operation of this invention is as follows: During the translation rule matching process, the correctness of the translation rules is ensured by virtualizing stack registers, thereby generating the correct target architecture instruction sequence in the instantiation of translation rules; when generating target code, the characteristics of the floating-point register stack are considered, and register allocation constraints are used to allocate registers on the floating-point stack. By identifying the target register and performing pop operations, the source architecture registers and target architecture registers are synchronized, ultimately generating an efficient target architecture floating-point instruction sequence. Compared to software-simulated floating-point instruction translation methods, the method of this invention achieves efficient dynamic binary translation while ensuring correct translation.

Description

Technical Field

[0001] This invention belongs to the field of system simulation technology, specifically relating to a dynamic binary translation method for rule-based translation in stack-based floating-point architecture. Background Technology

[0002] Dynamic binary translation is a widely used technology in system-level applications. A dynamic binary translation system translates the binary code of a source instruction set architecture into binary code of a target architecture in real time, and then runs the generated binary code directly on the target architecture host. Currently, dynamic binary translation has wide applications in system simulation, system virtualization, system analysis and debugging, and system security.

[0003] With the development of computer graphics, AI, and other fields, floating-point arithmetic has become increasingly important in industry and research. Hardware developers such as AMD and Intel have proposed coprocessors to accelerate floating-point operations. There are two main architectures for coprocessors used for floating-point operations: stack-based and non-stack-based. Stack-based floating-point architecture uses instructions with stack operation characteristics and stack registers for floating-point operations. Non-stack-based floating-point architecture uses the same instruction addressing mode as ordinary instructions and treats floating-point registers as ordinary registers. Stack-based floating-point architecture, as the earliest floating-point instruction set architecture, was first proposed and used by Intel. The x87 FPU, as the stack-based floating-point arithmetic unit of the x86 architecture, still exists in various processors today. However, with the continuous improvement of computational precision and the increasing computational load, non-stack-based floating-point architecture has gradually become the mainstream for floating-point operations due to its larger number of registers, higher computational precision, and faster processing speed. For example, Intel later proposed the SSE and AVX instruction sets to accelerate floating-point operations, while ARM proposed the VFP floating-point instruction set. These floating-point instruction sets all belong to non-stack floating-point architectures.

[0004] The x87 FPU is a general-purpose floating-point architecture in Intel processors. It can operate in both 32-bit and 64-bit compatibility modes and still plays an important role in various versions of Intel processors today. Compared to instruction sets like SSE and AVX, x87 was proposed earlier and is more prevalent on host machines, with a large amount of x87 code present in some early floating-point applications. With the development of the RISC (Reduced Instruction Set Computing) system, RISC uniformly adopted a non-stack floating-point architecture. Due to the significant differences in instruction sets between different processors and the different host machines they run on, managing the floating-point application code ecosystem has become very difficult. Therefore, this invention proposes a more widely applicable dynamic binary translation method for x87 stack-based floating-point architecture, improving binary translation support for stack-based floating-point architectures.

[0005] The x87 FPU is a dedicated arithmetic unit for scalar floating-point operations, capable of performing single-precision, double-precision, and extended double-precision floating-point calculations. For example... Figure 1The diagram shows the structure of the X87 FPU floating-point register stack. As shown, the X87 FPU has eight floating-point registers with a width of extended double precision. Unlike ordinary registers, these eight registers can only be accessed via the stack. The floating-point register stack grows from top to bottom. All addressing of these registers is related to the top register. The register number of the top register is stored in the TOP field of the X87 FPU status byte. For example, in the diagram, the current TOP field stores the binary number '011', indicating that the current top register is the register pointed to by the number 3. In X87 instructions, most instruction design and implementation are closely related to stack operations. The entire stack contains registers 'ST(0)-ST(7)', where 'ST(0)' is the top register. Accessing each register in the stack is obtained by adding the TOP value and the offset. In actual operation, we do not need to care about the current offset, as the offset is calculated directly by the hardware. We only need to directly access 'ST(i)' to get the value of the corresponding register. In terms of instruction design, all instructions in the x87 instruction set can only operate on the stack top register. That is, if an instruction has one operand, the target operand of the instruction must be the stack top register 'ST(0)'; if an instruction contains two operands, one of the operands of the instruction must be the stack top register 'ST(0)'. For stack management, x87 uses 'FLD' for push operations and 'FST' for pop operations. It also supports the option to directly pop the result of arithmetic operations from the stack to speed up computation. For example, for a stack-based addition operation, the x87 instruction 'FADDP ST(1)' indicates that the value in 'ST(0)' is added to the value in 'ST(1)' and stored in 'ST(0)', and then the value of 'ST(0)' is popped from the stack. For non-stack-based instruction sets, such as the VFP instruction set, an addition operation requires three operands 'VADD S0,S0,S1' to complete the addition operation. The biggest difference between the two is that x87 instructions use the stack precisely for computation, which can omit some operands in the instruction implementation, making the instructions short and dense, but the use of registers is limited, and in most cases only the registers at the top of the stack can be operated on; for non-stack instruction sets, register operations are more convenient and easier to maintain and manage.

[0006] Currently, there are three main methods in the field of dynamic binary translation: one using an intermediate expression language, one using translation rules, and one using software simulation. The intermediate expression language method involves adding a new intermediate language to both the source and target instruction architectures. This is done by translating the source instruction sequence into the intermediate language and then translating the intermediate language back into the target instruction sequence, thereby reducing front-end and back-end coupling. The translation rule method establishes a one-to-one correspondence between the source and target instruction architectures for translation. The software simulation method uses some instructions from the target instruction set for translation, aiming to ensure the semantic correctness of the source instruction translation, such as the translation of atomic instructions and system-level instructions. Regarding the intermediate floating-point instruction set method, Chinese patent CN201010300269.3 uses an intermediate floating-point instruction set to translate SSE2 floating-point instructions. Its key feature is the reduction of front-end and back-end architecture coupling. This patent's implemented intermediate floating-point instruction set supports the translation of non-stack floating-point instructions, but it cannot be used for stack floating-point instructions. Regarding the method of translating floating-point instructions using software simulation, Chinese patent number CN200410074532.6 uses a simulated floating-point stack to map the simulated floating-point stack to the fixed floating-point registers of the RISC architecture for floating-point operations. Chinese patent number CN200810112231.6 also uses a simulated floating-point stack method, using integer data variables and floating-point array variables to simulate the TOP register and simulate the data register, dynamically realizing the register allocation of the target architecture, thereby reducing the overhead of data exchange and data transfer instruction translation caused by fixed mapped registers.

[0007] Regarding the use of translation rules, Chinese patent CN202010625228.5 proposes a novel dynamic binary translation method. This method automatically learns and generates translation rules, applying these rules between the source and target architectures to achieve dynamic binary translation. While this method is applicable to non-stack-based floating-point instructions, it cannot automatically learn and generate translation rules for stack-based floating-point instructions, thus making it unsuitable for stack-based floating-point architectures. Furthermore, directly translating the instruction set using translation rules also makes this method unsuitable for stack-based floating-point architectures.

[0008] For floating-point instructions, traditional dynamic binary translation methods can also employ other software emulation methods for floating-point operations, that is, using integer instructions to simulate floating-point operations. For example, QEMU uses software emulation to support floating-point instructions. However, this software emulation incurs significant performance overhead, making the execution time of applications unacceptable. Summary of the Invention

[0009] This invention addresses the aforementioned problems and aims to provide a dynamic binary translation method applicable to stack-based floating-point architectures that achieves ideal translation quality and efficiency. The invention employs the following technical solution:

[0010] This invention provides a dynamic binary translation method for rule-based translation in stack-based floating-point architectures, characterized by the following steps:

[0011] Step S1: Virtualize the pop register for each stack-based floating-point instruction in the translation rules;

[0012] Step S2: Parameterize the opcodes and operands of all the translation rules to obtain the parameterized translation rules.

[0013] Step S3: Apply the parameterized translation rules to perform rule matching and translation on the source instruction sequence of the source instruction set architecture, and instantiate the successfully matched source instruction sequence to obtain the target instruction sequence;

[0014] Step S4: Perform actual register allocation on the target instruction sequence and generate the corresponding target binary code from the target instruction sequence.

[0015] The dynamic binary translation method for stack-based floating-point architecture using rule translation provided by the present invention may also have the following technical features, wherein step S2 includes the following sub-steps: step S2-1, parameterizing the opcode of the source instruction sequence and the opcode of the target instruction sequence according to the constructed mapping relationship;

[0016] Step S2-2: Parameterize the operands of the source instruction sequence and the target instruction sequence in the translation rule according to the mapping relationship and the type of the operands, respectively, to obtain the parameterized translation rule.

[0017] The dynamic binary translation method for stack-based floating-point architecture using rule translation provided by the present invention may also have the following technical features, wherein step S3 includes the following sub-steps: step S3-1, determining whether the source instruction sequence in the source base block can be matched using the translation rule;

[0018] If step S3-2 or step S3-1 determines that the binary translation is not performed, then the software simulation method is selected for binary translation.

[0019] Step S3-3: Generate executable code for the target instruction set architecture using the software simulation method;

[0020] If step S3-4 or step S3-1 is correct, further determine whether the opcode of the current source instruction can establish the mapping relationship with the parameterized opcode in the parameterized translation rule;

[0021] If the determination in steps S3-5 and S3-4 is yes, further determine whether the operand of the source instruction can establish the mapping relationship with the parameterized operand in the translation rule;

[0022] Steps S3-6: Based on the mapping relationship, the virtualized translation rule is instantiated into a complete translation rule;

[0023] Step S3-7: Extract the target instruction sequence from the complete translation rules to generate the executable code of the target instruction set architecture, i.e., the target instruction sequence.

[0024] The dynamic binary translation method for rule-based translation for stack-based floating-point architecture provided by the present invention may also have the following technical features, wherein step S4 includes the following sub-steps: step S4-1, for each target instruction in the target instruction sequence, identify the opcode of the target instruction and determine whether the target instruction contains floating-point operations;

[0025] When the determination in steps S4-2 and S4-1 is yes, the stack register is allocated to the target instruction. According to the stack register constraints, the top register of the floating-point stack is allocated as the target register to the target operand of the target instruction. The target operand is the stack register virtualized in step S1.

[0026] Step S4-3: After the target instruction finishes execution, the execution result is saved to the location of the operand of the target instruction in the memory simulation to complete the result synchronization of the target register, and at the same time, the resources of the stack top register are released.

[0027] If step S4-4 or step S4-1 determines that the result is no, the linear pool scan algorithm is used to allocate ordinary registers for the target instruction.

[0028] Step S4-5: Generate the corresponding target binary code based on the opcode and operands of the target instruction.

[0029] Invention Function and Effect

[0030] The dynamic binary translation method for stack-based floating-point architectures according to the present invention first virtualizes the stack registers. For stack-based floating-point instructions, the registers implicitly located at the top of the stack in the translation rules are virtualized, making the translation rules complete and consistent with other translation rules. Then, parameterized translation rules are applied, unifying the operands and opcodes of stack-based floating-point instructions with those of integer instructions. During the translation rule matching process, the correct target instruction sequence is generated through instantiation. For stack-based floating-point instructions, when generating the target code, the characteristics of the floating-point register stack are considered, and register allocation constraints are used to allocate the registers required by the target instructions. Finally, the corresponding target architecture floating-point instruction sequence is generated. The method of the present invention is an efficient method for binary translation using parameterized translation rules. This invention expands the scope of application of translation rules, generates high-quality target code while ensuring that the translation rules remain unchanged, and significantly improves the efficiency of floating-point operations in dynamic binary translation. Attached Figure Description

[0031] Figure 1 This is a simplified flowchart of the dynamic binary translation method in an embodiment of the present invention;

[0032] Figure 2 This is a flowchart of the dynamic binary translation method in an embodiment of the present invention;

[0033] Figure 3 This is a simplified flowchart of the parameterized translation rules in an embodiment of the present invention;

[0034] Figure 4 This is a simplified flowchart of the translation rule matching and instantiation process in an embodiment of the present invention;

[0035] Figure 5 This is a simplified flowchart of stack register allocation and code generation in an embodiment of the present invention;

[0036] Figure 6 This is an example diagram of the virtualized stack register and parameterized translation rules in an embodiment of the present invention;

[0037] Figure 7 This is an example diagram of translation rule matching and instantiation in an embodiment of the present invention;

[0038] Figure 8 This is an example diagram of stack register allocation and target code generation in an embodiment of the present invention;

[0039] Figure 9 This is a schematic diagram of the structure of the X87 FPU floating-point stack in the prior art. Detailed Implementation

[0040] To make the technical means, creative features, objectives and effects of this invention easier to understand, the following describes in detail the dynamic binary translation method for rule-based translation of stack-based floating-point architecture according to this invention, in conjunction with embodiments and accompanying drawings.

[0041] <Example>

[0042] This embodiment provides a dynamic binary translation method using rule-based translation for stack-based floating-point architectures. This method translates binary code from a source instruction set architecture into binary code for a target instruction set architecture in real time based on translation rules. The source instruction set architecture is the ARM VFP-d16 floating-point instruction set, and the target instruction set architecture is the x87 FPU floating-point instruction set of the x86 architecture. Both contain multiple stack-based floating-point instructions. The structure of the x87 FPU floating-point stack is as follows... Figure 9 As shown, the translation method in this embodiment is based on the improved dynamic binary translation system QEMU.

[0043] Figure 1 This is a simplified flowchart of the dynamic binary translation method in this embodiment.

[0044] Figure 2 This is a flowchart of the dynamic binary translation method in this embodiment.

[0045] like Figure 1 and Figure 2 As shown, the dynamic binary translation method using rule-based translation for stack-based floating-point architecture in this embodiment mainly includes five steps: virtualizing stack registers, parameterizing translation rules, matching and instantiating translation rules, allocating stack registers, and generating floating-point target code, specifically including the following steps:

[0046] Step S1: In the translation rules, a pop register is virtualized for each stack-based floating-point instruction to obtain the complete translation rules.

[0047] For stack-based floating-point instructions, due to their special instruction format, most stack-based floating-point instructions contain only one operand, and some even have no operands at all. These operands are hidden because of stack operations. Therefore, it is necessary to first virtualize the missing operands in the stack-based floating-point instructions. For the x87 floating-point instruction set used in this embodiment, the hidden operand of all stack-based floating-point instructions is the target operand of the instruction, which is the top register of the floating-point stack. Therefore, in the translation rules, the stack register in the instruction is virtualized first.

[0048] Figure 6 This is a schematic diagram of the virtualized stack registers and parameterized translation rules in this embodiment.

[0049] like Figure 6As shown, in this embodiment, the stack register is first virtualized for the learned translation rules containing stack-based floating-point instructions. The operands of the translation rules containing floating-point instructions are virtualized, and a stack top register 'ST(0)' is virtualized for each stack-based floating-point instruction. Figure 2 In this context, 'faddp' is an x87 stack-based floating-point addition instruction, such as... Figure 2 As shown, this instruction has only one operand, so the target operand 'ST(0)' is virtualized for this instruction. For this translation rule, the source instruction sequence does not need to be modified.

[0050] Step S2 involves parameterizing the opcodes and operands of all translation rules to obtain general translation rules.

[0051] After virtualizing the stack registers, the instruction format of stack-based floating-point instructions is consistent with that of integer instructions, thus allowing for parameterization together to form a unified representation and increase the applicability of the translation rules. An instruction consists of an opcode and operands. The opcode represents the actual operation meaning of the instruction, while the operands are the content the instruction operates on, such as specific registers or memory addresses. After parameterization, the universality of the translation rules is greatly improved, increasing code coverage. Parameterization first requires classifying the opcodes. Based on the instruction's function and characteristics, all instructions are divided into the following four categories: 1) Arithmetic and logical operation instructions, such as integer addition, floating-point multiplication, and division; 2) Memory access instructions, such as load and store instructions; 3) Comparison instructions, generally used for comparing two values, such as cmp and test instructions; 4) Other instructions, including special instructions that cannot be parameterized, such as jump instructions. Secondly, the opcodes need to be categorized. Operands in instructions are mainly divided into three categories: registers, immediate values, and memory operands. Parameterization is performed on each type of operand: all registers are parameterized to a unified representation 'reg', all immediate values ​​are converted to a unified representation 'imm', and all memory operations are converted to 'imm(reg)'. Based on the classification, a mapping relationship is established between instructions and parameterized representations, and then parameterization is performed.

[0052] Figure 3 This is a simplified flowchart of the parameterized translation rules in this embodiment.

[0053] like Figure 3 As shown, based on the pre-built mapping relationship, the parameterization process of one of the translation rules in step S2 specifically includes the following sub-steps:

[0054] Step S2-1, Opcode parameterization of translation rules. The opcodes of the source instruction sequence and the target instruction sequence in the translation rules are parameterized according to the constructed mapping relationship to obtain the opcode-parameterized translation rules.

[0055] Step S2-2, Parameterization of translation rule operands. All operands in the source instruction sequence and target instruction sequence of the translation rule are parameterized according to their operand types to obtain the complete parameterized translation rule.

[0056] Repeat steps S2-1 and S2-2 until all translation rules have been parameterized. The translation rules, after opcode and operand parameterization, are used to match the instruction sequence in the source instruction block and are subsequently used to generate the final target code.

[0057] like Figure 6 As shown, in this embodiment, arithmetic and logical operation instructions of the source instruction set are mapped to parameterized opcode 'op1', memory access instructions are mapped to parameterized opcode 'op2', comparison instructions are mapped to parameterized opcode 'op3', all registers are mapped to 'reg', and 'imm(reg)' is mapped to a unified representation of memory. These parameterized translation rules are then applied to the dynamic binary translation of floating-point applications.

[0058] Step S3: Apply the parameterized translation rules to match and translate the source instruction sequence of the source instruction set architecture, and instantiate the successfully matched source instruction sequence to obtain the target instruction sequence.

[0059] Translation rule matching involves matching the source instruction sequence with the source instruction sequence in the translation rules. Specifically, it matches the opcode and operands within each instruction. In parameterized translation rules, a successful match requires the opcode in the source instruction to have a consistent mapping with the parameterized opcode, and the operand mapping types to match. For a given source base block, one or more translation rules may be matched to translate the entire base block. The matched translation rules, after instantiation, further generate a floating-point instruction sequence, then allocate stack registers, and finally generate the corresponding target code.

[0060] After the translation rules are matched, the target code portion of the translation rules can be used to generate executable target code. Based on the correspondence between the source instruction opcode, operands, and target instruction opcode and operands generated in the parameterized translation rule stage, a specific instruction, including the specific opcode and registers, is instantiated.

[0061] Figure 4 This is a simplified flowchart of the translation rule matching and instantiation process in this embodiment.

[0062] like Figure 4 As shown, step S3 specifically includes the following sub-steps:

[0063] Step S3-1: Determine whether the source instruction sequence in the source base block can be matched using translation rules. If the determination is yes (i.e., it can be matched), proceed to step S3-4. If the determination is no, proceed to step S3-2.

[0064] Step S3-2: Since the source instruction sequence cannot be matched using translation rules, a software simulation method is selected for binary translation. The software simulation method uses some integer instructions to translate floating-point instructions.

[0065] Step S3-3: After software simulation, generate executable code for the target instruction set architecture;

[0066] Step S3-4: The source instruction sequence can be matched using translation rules. It is determined whether the opcode of the current source instruction can establish a mapping relationship with the parameterized opcode in the translation rules. If the determination is yes (i.e., a mapping relationship can be established), the match is successful, and the process proceeds to step S3-5 for operand matching. If the determination is no, the process proceeds to step S3-2.

[0067] Step S3-5: Determine whether the operands of the current source instruction can be mapped to the parameterized operands in the translation rules. If the determination is yes, the match is successful and proceed to step S3-6. If the determination is no, proceed to step S3-2.

[0068] For each source instruction in the source instruction sequence, execute steps S3-4 and S3-5 as described above until all source instruction sequences in the source base block that are matched by the translation rules have gone through steps S3-4 and S3-5.

[0069] Steps S3-6: Based on the mapping relationship established by the parameterized translation rules (i.e., step S2), the virtualized translation rules are instantiated into complete translation rules, and the source instruction sequence part and the target instruction sequence part in the translation rules are improved respectively.

[0070] Step S3-7: Extract the target instruction sequence from the instantiated translation rules to generate the final executable target code.

[0071] Figure 7 This is an example diagram of translation rule matching and instantiation in this embodiment.

[0072] like Figure 7As shown, in this embodiment, the source base block contains a single-precision floating-point addition instruction. In the translation module, the source instruction sequence in the source base block can be matched by the parameterized translation rule 'op1'. During the instantiation process, firstly, the opcode of the source instruction sequence is instantiated as the corresponding opcode, such as 'vadd' in the figure. Secondly, the opcode of the target instruction sequence and the target operand are instantiated as 'fadd' and 'ST(0)' respectively according to the instruction set of the target architecture. 'fadd' is the addition operation of the X87 FPU floating-point instruction set, and the 'ST(0)' register is the top register of the X87 floating-point stack.

[0073] Step S4: Perform actual register allocation on the generated target instruction sequence and generate the corresponding target binary code from the target instruction sequence.

[0074] After completing the translation rule matching and obtaining the complete target instruction sequence, the actual register allocation for these target instructions is performed first. Once register allocation is complete, the instructions are finally handed over to the target code generation module to generate the corresponding target binary code. For other non-floating-point instructions, a linear pool scan algorithm is used for register allocation. For floating-point instructions, the registers in the floating-point stack need to be allocated to the instructions according to the stack operation method: first, the register at the top of the stack is allocated to the target operand of the instruction; then, among the remaining available registers, the nearest available register to the top of the stack is allocated to other operands according to the proximity principle. Because all floating-point instructions need to interact with the top of the stack, after a floating-point instruction finishes execution, the top of the stack needs to be popped for register synchronization, and the top of the stack is then made available for the next instruction. When all registers in the stack are in use, i.e., there are no available registers to be allocated to other operands, all registers in the stack are synchronized, and the values ​​of all registers are synchronized to memory. During register allocation, the assembly instructions with specific operands and opcodes are translated into target code, written to the code buffer, and transferred to the control flow for instruction execution.

[0075] Once an instruction completes register allocation, it means that the instruction has its opcode and actual operands, and can generate the actual binary code. The target code generation module is responsible for translating the actual assembly instructions into their corresponding binary code and storing the binary code in the code buffer. After the entire source base block has generated the corresponding target binary code, it is handed back to the control flow for execution of the target binary code.

[0076] Figure 5 This is a simplified flowchart of stack register allocation and code generation in this embodiment.

[0077] like Figure 5 As shown, step S4 specifically includes the following sub-steps:

[0078] Step S4-1: For each target instruction in the target instruction sequence, identify the opcode of the target instruction and determine whether the target instruction contains floating-point operations. If the determination is yes, proceed to step S4-2. If the determination is no, repeat step S4-1 for the next target instruction until all instructions in the target instruction sequence have executed step S4-1.

[0079] Step S4-2: The target instruction contains floating-point operations. Stack register allocation is performed on the target instruction. Specifically, since the constraint of floating-point stack register operation is that the target operand of the instruction needs to be the stack top register, the register allocation of the target operand of the target instruction needs to be performed first. The target operand is the virtualized stack register generated above. Therefore, according to the stack register constraint, the floating-point stack top register is allocated to the operand and marked as the target register.

[0080] Step S4-3: After a target instruction finishes execution, since the stack top register needs to be used by other instructions, the result of the operand marked as the target register needs to be saved to the location of the operand in the memory simulation to complete the target register result synchronization. At the same time, the stack top register resources are released for use by other instructions. After the source register is synchronized, the target code generation module is executed.

[0081] Step S4-4: For target instructions that do not contain floating-point operations, perform general register allocation using the linear pool scan algorithm.

[0082] Steps S4-5: Generate the corresponding target binary code based on the target instruction opcode and operands, and finally hand it over to the control flow to execute the target binary code.

[0083] Figure 8 This is an example diagram of stack register allocation and target code generation in this embodiment.

[0084] like Figure 8 As shown, in this embodiment, the target binary code is generated sequentially according to the opcode and operands of the target instruction sequence. For floating-point instructions, the target operand is first identified. The target operand marked as 'ST(0)' is identified, and the stack top register is allocated to the instruction. Then, according to the existing mapping relationship, the remaining available 'ST(1)-ST(7)' registers are selected and allocated to other operands. As shown in the figure, the 'ST(3)' register is finally allocated to this instruction, and a target instruction sequence of 'FADD ST(0),ST(3)' is finally generated.

[0085] Finally, this assembly code is placed into the target code generation module to generate the corresponding binary code 'D8 C3', which is then placed in the code cache and handed over to the control flow for execution. After generating the binary code, the dynamic binary translation of a source base block is complete.

[0086] In the aforementioned dynamic binary translation process, the Tiny Code Generator (TCG) in QEMU is used to support instructions in the source base block that require software simulation. This embodiment uses the standard SPEC CPU 2006 test suite for testing on an Intel E52680 physical machine. The test results are compared with those of the software simulation method. The experimental results demonstrate that the method in this embodiment significantly improves performance during code execution, with an average performance improvement of 3.35 times compared to the software simulation method.

[0087] The parts not described in detail in this embodiment are well-known technologies in the art.

[0088] Functions and effects of the embodiments

[0089] According to the dynamic binary translation method using rule-based translation for stack-based floating-point architecture provided in this embodiment, the stack registers are first virtualized. For stack-based floating-point instructions, the registers implicitly located at the top of the stack in the translation rules are virtualized, making the translation rules complete and consistent with other translation rules. Then, parameterized translation rules are performed to unify the operands and opcodes of stack-based floating-point instructions with those of integer instructions. During the translation rule matching process, the correct target instruction sequence is generated through instantiation. For stack-based floating-point instructions, when generating the target code, the characteristics of the floating-point register stack are considered, and register allocation constraints are used to allocate the registers required by the target instructions. Finally, the corresponding target architecture floating-point instruction sequence is generated. The method of this embodiment is an efficient method for binary translation using parameterized translation rules. This embodiment expands the scope of application of translation rules, generates high-quality target code while ensuring that the translation rules remain unchanged, and significantly improves the floating-point operation efficiency in dynamic binary translation.

[0090] The above embodiments are only used to illustrate specific implementations of the present invention, and the present invention is not limited to the scope of the description of the above embodiments.

Claims

1. A dynamic binary translation method for stack-oriented floating point architecture usage rule translation, for translating binary code of a source instruction set architecture into target binary code of a target instruction set architecture in real time based on translation rules, characterized in that, The method comprises the following steps: Step S1, virtualizing a stack register for each stack floating-point instruction in a translation rule; Step S2, performing opcode parameterization and operand parameterization on all the translation rules, so as to obtain the parameterized translation rules; Step S3, applying the parameterized translation rules to perform rule matching and translation on a source instruction sequence of a source instruction set architecture, and instantiating the source instruction sequence matched successfully, so as to obtain a target instruction sequence; Step S4, performing actual register allocation on the target instruction sequence, and generating corresponding target binary code from the target instruction sequence, Wherein, step S3 comprises the following sub-steps: Step S3-1, judging whether the source instruction sequence in a source basic block can be matched using the translation rule; Step S3-2, when the judgment of step S3-1 is no, selecting to use a software simulation method to perform binary translation; Step S3-3, generating executable code of a target instruction set architecture through the software simulation method; Step S3-4, when the judgment of step S3-1 is yes, further judging whether the opcode of the current source instruction can establish a mapping relationship with the parameterized opcode in the parameterized translation rule; Step S3-5, when the judgment of step S3-4 is yes, further judging whether the operand of the source instruction can establish the mapping relationship with the parameterized operand in the translation rule; Step S3-6, instantiating the virtualized translation rule into a complete translation rule according to the mapping relationship; Step S3-7, extracting the target instruction sequence in the complete translation rule, which is used to generate executable code of the target instruction set architecture, i.e., a target instruction sequence, Step S4 comprises the following sub-steps: Step S4-1, for each target instruction in the target instruction sequence, identifying the opcode of the target instruction, And judging whether the target instruction contains a floating-point operation; Step S4-2, when the judgment of step S4-1 is yes, performing stack register allocation on the target instruction, and allocating a top register of a floating-point stack as a target register to a target operand of the target instruction according to stack register constraints, the target operand being the stack register virtualized in step S1; Step S4-3, after the execution of the target instruction ends, saving the execution result to a position of the operand of the target instruction in memory simulation, so as to complete result synchronization of the target register, and release the resource of the top register; Step S4-4, when the judgment of step S4-1 is no, using a linear pool scanning algorithm to perform normal register allocation on the target instruction; Step S4-5, generating corresponding target binary code according to the opcode and the operand of the target instruction.

2. The dynamic binary translation method for stack-oriented floating point architecture usage rule translation of claim 1, Its characteristics are: Wherein, step S2 comprises the following sub-steps: Step S2-1, parameterizing the opcode of the source instruction sequence and the opcode of the target instruction sequence according to the mapping relationship constructed; Step S2-2, parameterizing the operands of the source instruction sequence and the operands of the target instruction sequence in the translation rule according to the mapping relationship and the types of the operands respectively, to obtain the parameterized translation rule.

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