Verilog rtl code hardening method and related device

Abstract

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.

Description

Technical Field

[0001] This invention relates to the field of programming technology, and in particular to a method and related equipment for hardening Verilog RTL code. Background Technology

[0002] When digital integrated circuits are used in harsh environments such as aviation, aerospace, medical, and industrial settings, they are often affected by cosmic rays, charged particles, and various interferences, leading to incorrect data flipping within the circuit.

[0003] If an erroneous flip occurs in the memory circuit, it will cause the stored value to flip incorrectly from 0 to 1 or from 1 to 0, which is a very serious error. If an erroneous flip occurs in SRAM or DRAM, it will cause data corruption; if an erroneous flip occurs in flip-flops or latches, it will cause data corruption or even more serious circuit malfunctions. Summary of the Invention

[0004] In view of the above problems, the present invention provides a Verilog RTL code hardening method and related equipment, the main purpose of which is to solve the problem that there is currently no suitable hardening method to enable the circuit to resist 0 and 1 error toggling.

[0005] To address at least one of the aforementioned technical problems, in a first aspect, the present invention provides a Verilog RTL code hardening method, the method comprising:

[0006] Obtain the timing logic code segment containing timing logic from the original Verilog RTL code file;

[0007] The above-mentioned timing logic code segments are formatted and a timing logic identifier version code file is generated.

[0008] Identify the trigger code within the code segment that has the above format identifier;

[0009] Redundant combinational logic voting circuit code is added to the above trigger code to strengthen the original Verilog RTL code.

[0010] Optionally, the timing logic code segment containing timing logic obtained from the original Verilog RTL code file as described above includes:

[0011] The starting position of the sequential logic code segment is determined based on the always code and the target content code of the sequential logic code segment;

[0012] The end position of the above-mentioned timing logic code segment is determined based on the next target start code after the starting position. The next target start code includes any one of the always code, assign code, and component instantiation code.

[0013] Optionally, determining the trigger code within the code segment having the above format identifier includes:

[0014] The trigger code is determined by querying the assignment symbol in the code segment with the above format identifier. The trigger code is the variable code before the assignment symbol.

[0015] The above methods also include:

[0016] Generate the trigger list from the original Verilog RTL code file described above based on the determined trigger code.

[0017] Optionally, redundant combinational logic voting circuit code is added to the above-mentioned trigger code to strengthen the original Verilog RTL code, including:

[0018] Add at least three modularly redundant combinational logic voting circuit codes to the above trigger code to strengthen the original Verilog RTL code.

[0019] Optionally, the above methods also include:

[0020] Each trigger after the addition of redundancy settings is marked to generate trigger tags.

[0021] Optionally, the above methods also include:

[0022] Based on the above trigger markings, the clock signal, reset signal, and register signal are marked to match each trigger after the addition of redundancy settings.

[0023] Optionally, the above methods also include:

[0024] Replace the code segment comments in the original Verilog RTL code file with comment labels;

[0025] The corresponding code segment comments and comment numbers are stored, and a comment list is generated.

[0026] The hardened Verilog RTL code file can be recovered based on the above list of comments.

[0027] Secondly, embodiments of the present invention also provide a Verilog RTL code hardening device, comprising:

[0028] The acquisition unit is used to acquire the timing logic code segment containing timing logic from the original Verilog RTL code file;

[0029] The identification unit is used to identify the format of the above-mentioned timing logic code segment and generate a timing logic identification version code file.

[0030] The determining unit is used to determine the trigger code in the code segment with the above format identifier;

[0031] The hardening unit is used to add redundant combinational logic voting circuit code to the above-mentioned flip-flop code in order to harden the original Verilog RTL code.

[0032] To achieve the above objectives, according to a third aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium comprising a stored program, wherein the Verilog RTL code hardening method described above is implemented when the program is executed by a processor.

[0033] To achieve the above objectives, according to a fourth aspect of the present invention, an electronic device is provided, including at least one processor and at least one memory connected to the processor; wherein the processor is configured to call program instructions in the memory to execute the Verilog RTL code hardening method described above.

[0034] By employing the above technical solution, the Verilog RTL code hardening method and related equipment provided by this invention address the current lack of a suitable hardening method to enable circuits to resist 0 / 1 error toggling. This invention hardens the original Verilog RTL code by: obtaining the timing logic code segment containing the timing logic from the original Verilog RTL code file; formatting the timing logic code segment to generate a timing logic identifier version code file; identifying the trigger code in the code segment with the aforementioned format identifier; and adding redundant combinational logic voting circuit code to the trigger code. In this solution, by having multiple modules simultaneously perform the same operation and using the majority of identical outputs as the correct output of the voting system, redundant TMR hardening is applied to the original Verilog RTL code. Since multiple modules are independent, the simultaneous occurrence of errors in multiple modules is an extremely low probability event, masking the errors of faulty modules and ensuring the correct output of the system. Therefore, it reduces the probability of errors in the highly readable RTL-level Verilog code, improving fault tolerance.

[0035] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0037] Figure 1 The diagram illustrates a flowchart of a Verilog RTL code hardening method provided by an embodiment of the present invention.

[0038] Figure 2 This diagram illustrates a schematic block diagram of a Verilog RTL code hardening device provided in an embodiment of the present invention.

[0039] Figure 3 This diagram illustrates a schematic block diagram of a Verilog RTL code hardened electronic device provided by an embodiment of the present invention. Detailed Implementation

[0040] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0041] To address the current lack of a suitable hardening method to enable circuits to withstand 0 / 1 error toggling, this invention provides a Verilog RTL code hardening method, such as... Figure 1 As shown, the method includes:

[0042] S101. Obtain the timing logic code segment containing timing logic from the original Verilog RTL code file.

[0043] For example, Verilog (Verilog HDL) is a hardware description language that uses text to describe the structure and behavior of digital system hardware. It can represent logic diagrams, logical expressions, and the logical functions performed by a digital logic system. In digital circuit design, RTL (register-transfer level) is an abstract model of synchronous digital circuits. This model is determined based on the flow of digital signals between hardware registers, memories, combinational logic devices, and buses, as well as their Boolean algebraic operation. This solution first identifies the sequential logic code segments containing sequential logic in the original Verilog RTL code file.

[0044] S102. Format the above-mentioned timing logic code segment and generate a timing logic identifier version code file.

[0045] For example, the sequential logic code segment containing sequential logic obtained above is specially formatted and a specific pattern is added to its beginning and end as a marker to generate a sequential logic identifier version code file.

[0046] S103. Determine the trigger code in the code segment with the above format identifier.

[0047] For example, the timing logic identifier version code file is scanned and retrieved to extract all flip-flops in all timing logic, thereby determining the flip-flop code. The flip-flop is an electronic component that can store circuit states. A commonly used one is the D flip-flop, which has two stable states, "0" and "1". Under the action of a certain external signal, it can flip from one stable state to another.

[0048] S104. Add redundant combinational logic voting circuit code to the above-mentioned flip-flop code to strengthen the original Verilog RTL code.

[0049] For example, adding redundant combinational logic voting circuit code to the above trigger code ensures that even if multiple combinational logic voting circuit codes perform the same operation simultaneously, the majority of identical outputs are taken as the correct output for voting.

[0050] By employing the above technical solution, the Verilog RTL code hardening method provided by this invention addresses the current lack of a suitable hardening method to enable circuits to resist 0 / 1 error toggling. This invention hardens the original Verilog RTL code by obtaining the sequential logic code segment containing the sequential logic from the original Verilog RTL code file; formatting the sequential logic code segment to generate a sequential logic identifier version code file; identifying the flip-flop code within the formatted code segment; and adding redundant combinational logic voting circuit code to the flip-flop code. In this solution, by having multiple modules simultaneously perform the same operation and using the majority of identical outputs as the correct output of the voting system, redundant TMR hardening is applied to the original Verilog RTL code. Since multiple modules are independent, the simultaneous occurrence of errors in multiple modules is an extremely low probability event, masking the errors of faulty modules and ensuring correct system output. Therefore, it reduces the probability of errors in the highly readable RTL-level Verilog code, improving fault tolerance.

[0051] In one embodiment, the above-mentioned acquisition of the timing logic code segment containing timing logic from the original Verilog RTL code file includes:

[0052] The starting position of the sequential logic code segment is determined based on the always code and the target content code of the sequential logic code segment;

[0053] The end position of the above-mentioned timing logic code segment is determined based on the next target start code after the starting position. The next target start code includes any one of the always code, assign code, and component instantiation code.

[0054] For example, the sequential logic code segment containing sequential logic is the target content code of the aforementioned sequential logic code segment. It refers to the code segment containing the description of the D flip-flop. When the above code segment is detected to start with always@(...) and the content within the parentheses contains the words "posedge" or "negedge", this is the starting position of the above sequential logic code segment. The code after always@(...) may be a begin...end sub-segment, an if...else... sub-segment, an if...else if... sub-segment, a case...default...endcase sub-segment, or other types of sub-segments. Each of the above sub-segments may contain one assignment statement (e.g., qout<=#1din;) or multiple assignment statements. When multiple assignment statements are contained, they should be enclosed in begin...end to determine the ending position of the above sequential logic code segment. It should be noted that the above sub-segments can be nested arbitrarily. Another method to locate the end of the aforementioned sequential logic code segment is to scan the code. When the next always block, the next assign code, or the next instantiation (instance) is found, the current sequential always block is considered to have ended. By matching and searching the code with regular expressions according to the above characteristics, the sequential always block in the code can be located, thereby determining the target content code of the aforementioned sequential logic code segment.

[0055] In one embodiment, determining the trigger code in a code segment having the above-described format identifier includes:

[0056] The trigger code is determined by querying the assignment symbol in the code segment with the above format identifier. The trigger code is the variable code before the assignment symbol.

[0057] The above methods also include:

[0058] Generate the trigger list from the original Verilog RTL code file described above based on the determined trigger code.

[0059] For example, the sequential logic code segment containing the aforementioned sequential logic is scanned and searched. The sequential logic code segment containing the aforementioned sequential logic has marked the sequential always blocks with a specific pattern. By matching and searching the aforementioned pattern markers, all sequential always blocks can be obtained. In the aforementioned sequential always blocks, all assignment symbols can be searched, which can be <= and =. The variable to the left of the aforementioned assignment symbol is matched and searched. This variable is the trigger. All triggers in all sequential logic are extracted and stored in the trigger code.

[0060] In one embodiment, the addition of redundant combinational logic voting circuit code to the aforementioned trigger code to harden the original Verilog RTL code includes:

[0061] Add at least three modularly redundant combinational logic voting circuit codes to the above trigger code to strengthen the original Verilog RTL code.

[0062] For example, adding redundant combinational logic voting circuit code to the above-mentioned trigger code can be done even if multiple combinational logic voting circuit codes perform the same operation at the same time, with the majority of the same outputs being the correct output for voting. This could be a 2 out of 3, 3 out of 5, 5 out of 7, etc., but at least three modularly redundant combinational logic voting circuit codes should be added to the above-mentioned trigger code, that is, at least three sets of logic voting circuit codes should be executed, and the majority of the same outputs among them should be the correct output for voting.

[0063] In one embodiment, the above method further includes:

[0064] Each trigger after the addition of redundancy settings is marked to generate trigger tags.

[0065] For example, the trigger code is copied multiple times; that is, the sequential logic is first divided into multiple copies, and then combinational logic voting circuits are added. After adding three sets of combinational logic voting circuit code to the above trigger code, each trigger of the added combinational logic voting circuit code needs to be marked. The sequential always block marked with a specific pattern is copied three times, and the comments accompanying the three always blocks are marked with the order _tmr0, _tmr1, and _tmr2 to generate trigger tags.

[0066] In one embodiment, the above method further includes:

[0067] Based on the above trigger markings, the clock signal, reset signal, and register signal are marked to match each trigger after the addition of redundancy settings.

[0068] For example, based on the aforementioned trigger markers, a matching search is performed according to the _tmr0, _tmr1, and _tmr2 markers in the comments to find the timing always block copied into three copies. The code in the timing always block includes clock, reset, and register signals. The clock signals in the three copies are sequentially appended with the suffixes _tmr0, _tmr1, and _tmr2; the reset signals in the three copies are sequentially appended with the suffixes _tmr0, _tmr1, and _tmr2; and the register signals in the three copies are sequentially appended with the suffixes _tmr0, _tmr1, and _tmr2. These are then saved as a redundancy marker file.

[0069] In one embodiment, the above method further includes:

[0070] Replace the code segment comments in the original Verilog RTL code file with comment labels;

[0071] The corresponding code segment comments and comment numbers are stored, and a comment list is generated.

[0072] The hardened Verilog RTL code file can be recovered based on the above list of comments.

[0073] For example, comments in Verilog code are content that starts with the character / / and extends to the end of the line, or content contained between / * and * / . Regular expressions can be used to match and search for each comment. Each line of extracted comments is numbered, starting from 1 and incrementing line by line. The content of the comments after the added number is saved, generating a comment list. This comment list contains the original content of each pre-extracted comment. The redundant marker file is also read, containing comments that have been replaced with sequential numbers. Comments numbered 0, 1, 2, 3… in the redundant marker file are matched and replaced with comments coded 0, 1, 2, 3… in the comment list. The replaced file is then saved as the hardened Verilog RTL code file.

[0074] The specific implementation code for this solution is as follows:

[0075]

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

[0082]

[0083]

[0084]

[0085]

[0086] Furthermore, as a response to the above Figure 1 In addition to the implementation of the method shown, this embodiment of the invention also provides a Verilog RTL code hardening device for the above-mentioned... Figure 1 The method shown is implemented accordingly. This device embodiment corresponds to the foregoing method embodiment. For ease of reading, this device embodiment will not repeat the details of the foregoing method embodiment, but it should be clear that the device in this embodiment can implement all the contents of the foregoing method embodiment. Figure 2 As shown, the device includes: an acquisition unit 21, an identification unit 22, a determination unit 23, and a reinforcement unit 24, wherein...

[0087] Acquisition unit 21 is used to acquire the timing logic code segment containing timing logic from the original Verilog RTL code file;

[0088] Identification unit 22 is used to identify the format of the above-mentioned timing logic code segment and generate a timing logic identification version code file;

[0089] Determining unit 23 is used to determine the trigger code in the code segment with the above format identifier;

[0090] The hardening unit 24 is used to add redundant combinational logic voting circuit code to the above-mentioned flip-flop code in order to harden the above-mentioned original Verilog RTL code.

[0091] For example, the above-mentioned acquisition of the timing logic code segment containing timing logic from the original Verilog RTL code file includes:

[0092] The starting position of the sequential logic code segment is determined based on the always code and the target content code of the sequential logic code segment;

[0093] The end position of the above-mentioned timing logic code segment is determined based on the next target start code after the starting position. The next target start code includes any one of the always code, assign code, and component instantiation code.

[0094] For example, determining the trigger code in a code segment having the above-described format identifier includes:

[0095] The trigger code is determined by querying the assignment symbol in the code segment with the above format identifier. The trigger code is the variable code before the assignment symbol.

[0096] The above methods also include:

[0097] Generate the trigger list from the original Verilog RTL code file described above based on the determined trigger code.

[0098] For example, the addition of redundant combinational logic voting circuit code to the aforementioned trigger code to harden the original Verilog RTL code includes:

[0099] Add at least three modularly redundant combinational logic voting circuit codes to the above trigger code to strengthen the original Verilog RTL code.

[0100] For example, the above method also includes:

[0101] Each trigger after the addition of redundancy settings is marked to generate trigger tags.

[0102] For example, the above method also includes:

[0103] Based on the above trigger markings, the clock signal, reset signal, and register signal are marked to match each trigger after the addition of redundancy settings.

[0104] For example, the above method also includes:

[0105] Replace the code segment comments in the original Verilog RTL code file with comment labels;

[0106] The corresponding code segment comments and comment numbers are stored, and a comment list is generated.

[0107] The hardened Verilog RTL code file can be recovered based on the above list of comments.

[0108] By employing the above technical solution, the Verilog RTL code hardening device provided by this invention addresses the current lack of a suitable hardening method to enable circuits to resist 0 / 1 error toggling. This invention hardens the original Verilog RTL code by: acquiring the timing logic code segment containing the timing logic from the original Verilog RTL code file; formatting the timing logic code segment to generate a timing logic identifier version code file; identifying trigger codes within the formatted code segment; and adding redundant combinational logic voting circuit code to the trigger codes. In this solution, by having multiple modules execute the same operation simultaneously and using the majority of identical outputs as the correct output of the voting system, redundant TMR hardening is applied to the original Verilog RTL code. Since multiple modules are independent, the simultaneous occurrence of errors in multiple modules is an extremely low probability event, masking the errors of faulty modules and ensuring correct system output. Therefore, it reduces the probability of errors in the highly readable RTL-level Verilog code, improving fault tolerance.

[0109] The processor contains a kernel, which retrieves the corresponding program unit from memory. One or more kernels can be configured, and by adjusting kernel parameters, a Verilog RTL code hardening method can be implemented, addressing the current lack of a suitable hardening method to enable circuits to resist 0 / 1 error toggling.

[0110] This invention provides a computer-readable storage medium including a stored program that, when executed by a processor, implements the Verilog RTL code hardening method described above.

[0111] This invention provides a processor for running a program, wherein the program executes the Verilog RTL code hardening method during runtime.

[0112] This invention provides an electronic device, which includes at least one processor and at least one memory connected to the processor; wherein the processor is used to call program instructions in the memory to execute the Verilog RTL code hardening method described above.

[0113] This invention provides an electronic device 30, such as... Figure 3 As shown, the electronic device includes at least one processor 301, at least one memory 302 connected to the processor, and a bus 303; wherein, the processor 301 and the memory 302 communicate with each other through the bus 303; the processor 301 is used to call program instructions in the memory to execute the Verilog RTL code hardening method described above.

[0114] The smart electronic devices mentioned in this article can be PCs, tablets, mobile phones, etc.

[0115] This application also provides a computer program product, which, when executed on a process management electronic device, is suitable for executing an initialization program having the following method steps: obtaining a timing logic code segment containing timing logic from an original Verilog RTL code file; formatting the aforementioned timing logic code segment to generate a timing logic identifier version code file; determining trigger codes in the code segment with the aforementioned format identifier; and adding redundant combinational logic voting circuit code to the aforementioned trigger codes to strengthen the aforementioned original Verilog RTL code.

[0116] Furthermore, the aforementioned acquisition of the timing logic code segment containing timing logic from the original Verilog RTL code file includes:

[0117] The starting position of the sequential logic code segment is determined based on the always code and the target content code of the sequential logic code segment;

[0118] The end position of the above-mentioned timing logic code segment is determined based on the next target start code after the starting position. The next target start code includes any one of the always code, assign code, and component instantiation code.

[0119] Furthermore, determining the trigger code within the code segment with the aforementioned format identifier includes:

[0120] The trigger code is determined by querying the assignment symbol in the code segment with the above format identifier. The trigger code is the variable code before the assignment symbol.

[0121] The above methods also include:

[0122] Generate the trigger list from the original Verilog RTL code file described above based on the determined trigger code.

[0123] Furthermore, redundant combinational logic voting circuit code is added to the aforementioned trigger code to strengthen the original Verilog RTL code, including:

[0124] Add at least three modularly redundant combinational logic voting circuit codes to the above trigger code to strengthen the original Verilog RTL code.

[0125] Furthermore, the above methods also include:

[0126] Each trigger after the addition of redundancy settings is marked to generate trigger tags.

[0127] Furthermore, the above methods also include:

[0128] Based on the above trigger markings, the clock signal, reset signal, and register signal are marked to match each trigger after the addition of redundancy settings.

[0129] Furthermore, the above methods also include:

[0130] Replace the code segment comments in the original Verilog RTL code file with comment labels;

[0131] The corresponding code segment comments and comment numbers are stored, and a comment list is generated.

[0132] The hardened Verilog RTL code file can be recovered based on the above list of comments.

[0133] This application is described with reference to flowchart illustrations and / or block diagrams of methods, electronic devices (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable process management electronic device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable process management electronic device, generate instructions for implementing the process... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0134] In a typical configuration, an electronic device includes one or more processors (CPUs), memory, and a bus. The electronic device may also include input / output interfaces, network interfaces, etc.

[0135] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM, and memory includes at least one memory chip. Memory is an example of computer-readable media.

[0136] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media for computers include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage electronic devices, or any other non-transferable medium that can be used to store information accessible to a computing electronic device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0137] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or electronic device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or electronic device. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or electronic device that includes that element.

[0138] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable, computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A Verilog RTL code hardening method, characterized in that, include: Obtain the timing logic code segment containing timing logic from the original Verilog RTL code file; The timing logic code segment is formatted and a timing logic identifier version code file is generated; Determine the trigger code within the code segment that has the specified format identifier; Redundant combinational logic voting circuit code is added to the trigger code to strengthen the original Verilog RTL code; Determining the trigger code within the code segment having the format identifier includes: The trigger code is determined by querying the assignment symbol in the code segment with the format identifier, and the trigger code is the variable code before the assignment symbol; The method further includes: Generate a list of triggers from the original Verilog RTL code file based on the determined trigger codes.

2. The method according to claim 1, characterized in that, The step of obtaining the timing logic code segment containing timing logic from the original Verilog RTL code file includes: The starting position of the sequential logic code segment is determined based on the always code and the target content code of the sequential logic code segment; The end position of the timing logic code segment is determined based on the next target start code after the starting position. The next target start code includes any one of always code, assign code, and component instantiation code.

3. The method according to claim 1, characterized in that, The addition of redundant combinational logic voting circuit code to the trigger code to harden the original Verilog RTL code includes: Add at least three modularly redundant combinational logic voting circuit codes to the trigger code to harden the original Verilog RTL code.

4. The method according to any one of claims 1 to 3, characterized in that, Also includes: Each trigger after the addition of redundancy settings is marked to generate trigger tags.

5. The method according to claim 4, characterized in that, Also includes: The clock signal, reset signal, and register signal are marked based on the trigger markings to match each trigger after the addition of redundancy settings.

6. The method according to claim 1, characterized in that, The method further includes: Replace the code segment comments in the original Verilog RTL code file with comment labels; The corresponding code segment comments and comment numbers are stored to generate a comment list; The hardened Verilog RTL code file was recovered based on the aforementioned list of comments.

7. A Verilog RTL code hardening device, characterized in that, include: The acquisition unit is used to acquire the timing logic code segment containing timing logic from the original Verilog RTL code file; An identification unit is used to identify the format of the timing logic code segment and generate a timing logic identification version code file. A determining unit is configured to determine trigger code within a code segment having the format identifier; Determining the trigger code within the code segment having the format identifier includes: The trigger code is determined by querying the assignment symbol in the code segment with the format identifier, and the trigger code is the variable code before the assignment symbol; The apparatus is also used to: generate a list of triggers for the original Verilog RTL code file based on the determined trigger codes; The device further includes a hardening unit for adding redundant combinational logic voting circuit code to the trigger code to harden the original Verilog RTL code.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the VerilogRTL code hardening method as described in any one of claims 1 to 6 is implemented when the program is executed by a processor.

9. An electronic device, characterized in that, The electronic device includes at least one processor and at least one memory connected to the processor; wherein the processor is configured to call program instructions in the memory to execute the Verilog RTL code hardening method as described in any one of claims 1 to 6.

Images