Multi-node flipping resistant latch based on DICE

Abstract

The invention relates to a DICE-based anti-multi-node upset latch, which belongs to the field of anti-radiation reinforcement of integrated circuits and comprises an input circuit, a node holding and restoring circuit, a DICE circuit, a delay circuit and an output circuit. The input circuit consists of two input C unit circuits and is used for controlling signal input; the node holding and restoring circuit, the DICE circuit and the output circuit are used for transmitting and latching data; when the latch is radiated, the latch can tolerate multi-node flipping and restore; the delay circuit is used for recovering multi-node flipping of the DICE and the output circuit by using a delay signal; the multi-node upset resistant latch provided by the invention can realize a single-particle single-node and double-node instantaneous upset self-recovery function, and has the capability of resisting three-node single-particle upset, and meanwhile, the circuit structure is easy to realize.

Description

A DICE-based anti-multi-node flip-flop latch Technical Field

[0001] This invention relates to a DICE-based anti-multi-node flip-flop latch, belonging to the field of radiation hardening of integrated circuits. Background Technology

[0002] Single-event transients (SETs) are brief voltage / current disturbances caused in combinational logic or timing paths when high-energy particles are injected into the sensitive region of a CMOS device. When an incident particle ionizes in a semiconductor material, generating electron-hole pairs, the resulting transient current couples to transistor channels or interconnects, causing picosecond-level voltage spikes. If these transient pulses are captured by subsequent timing units (such as flip-flops or latches), they will be converted into logic error signals. In space radiation environments, the impact of SETs on high-speed digital circuits is particularly significant.

[0003] As CMOS process dimensions shrink to the nanometer scale, the critical charge of circuits decreases significantly, leading to a marked increase in sensitivity to single-event effects. Charge generated by high-energy particle impacts can be shared by multiple neighboring nodes, causing transient multi-node failures and rendering traditional single-node hardening solutions ineffective. Particularly in critical timing units such as latches, erroneous flips, if captured by the clock, can result in core data errors. Therefore, redundant hardening designs are needed to prevent multi-node flips, thereby improving the reliability of aerospace applications and ensuring stable circuit operation under extreme radiation environments. Summary of the Invention

[0004] The technical problem solved by this invention is: to address the vulnerability of latch circuits to charge sharing effects, and to resist multi-node flip-flops, a redundant latch based on DICE is provided, which can realize instantaneous flip-flop self-recovery function for single-event single-node and dual-node flip-flops, and has the ability to resist three-node single-event flip-flops, while the circuit structure is easy to implement.

[0005] The technical solution of this invention is as follows: A DICE-based anti-multi-node-flip latch, comprising: an input circuit, receiving an externally transmitted data signal; under clock control, when the clock signal represents the transparent state of the latch circuit, shaping and flipping the data signal before outputting it; and when the clock signal represents the latch circuit's latching state, not transmitting the data signal; a node hold and restore circuit, receiving the data signal input from the input circuit, the delayed signal input from the delay circuit, and the signal input from the output circuit, judging the received signal, generating a first output terminal and a second output terminal signal, outputting them to the DICE circuit, and resisting single-event flips, maintaining the level of the two output signals in the latching state, and restoring them when a node flip occurs; and a DICE circuit, judging the two input signals of the node hold and restore circuit, generating a first output terminal and a second output terminal signal, and outputting them to the DICE circuit. The output circuit is designed to resist single-event upsets, maintain the level of both output signals in the latched state, and restore the signal when a node flips. A delay circuit receives the signal from the first output terminal of the output circuit, delays it, and outputs it to the node holding and recovery circuit. When multiple node flips occur in the DICE circuit and output circuit, it prevents pulses smaller than the rated width from propagating in the circuit and restores the node signals. The output circuit performs decision processing based on the signals from the first and second input terminals of the DICE circuit, generating signals for the first and second output terminals. The signal from the first output terminal is sent to the delay circuit and the node holding and recovery circuit, while the signal from the second output terminal is output externally and maintains the output level in the latched state. A clock inverter circuit provides input clock signals to the input circuit, the node holding and recovery circuit, and the output circuit, and controls the opening and closing of the three circuits.

[0006] In the aforementioned DICE-based anti-multi-node flip-flop latch, the input circuit has three outputs, which are respectively connected to the first input terminal D1, the second input terminal D2, and the third input terminal D3 of the node hold and restore circuit. The fourth and fifth input terminals of the node hold and restore circuit are respectively connected to the output terminals of the two delay circuits. The sixth input terminal of the node hold and restore circuit is connected to the first output terminal of the output circuit. The first and second output terminals of the node hold and restore circuit are connected to the first input terminal QA and the second input terminal QB of the DICE circuit. The output terminals QAN and QBN of the DICE circuit are respectively connected to the input terminals of the output circuit. The first output terminal QC of the output circuit is connected to the input terminal of the delay circuit. The second output terminal of the output circuit is the output of the entire circuit.

[0007] In the aforementioned DICE-based anti-multi-node flip-flop latch, the input circuit includes three clock control C-unit circuits. The input terminals of the clock control C-unit circuits are connected together as the input terminal D of the input circuit, and the output terminals of the clock control C-unit circuits serve as the first output terminal, second output terminal, and third output terminal of the input circuit, respectively. The three clock control C-unit circuits are connected to the clock signal output by the clock inverter circuit. Under clock control, when the clock signal represents the transparent state of the latch circuit, the signal is shaped and flipped before being output. When the clock signal represents the latch state of the latch circuit, no signal is transmitted.

[0008] In the aforementioned DICE-based anti-multi-node flip-flop latch, the node hold and restore circuit includes a clock control C-cell circuit, a clock control two-input C-cell circuit, an inverter circuit, and a two-input C-cell circuit. The output terminal of the clock control C-cell circuit is connected to the first input terminal of the two-input C-cell circuit as the first input terminal of the node hold and restore circuit. The second input terminal of the two-input C-cell circuit, the first input terminal of the two-input C-cell circuit, and the output terminal of the clock control two-input C-cell circuit are connected as the second input terminal of the node hold and restore circuit. The input terminal of the inverter circuit is connected as the third input terminal of the node hold and restore circuit. The output terminal of the inverter circuit is connected to the first input terminal of the clock control two-input C-cell circuit. The input terminal of the clock control C-cell circuit is connected as the fourth input terminal of the node hold and restore circuit. The input terminal of the clock control C-cell circuit is the fifth input terminal of the node hold and restore circuit. The second input terminal of the clock control two-input C-cell circuit is the sixth input terminal of the node hold and restore circuit. The output terminal of the two-input C-cell circuit is the first output terminal of the node hold and restore circuit. The output terminal of the two-input C-cell circuit is the second output terminal of the node hold and restore circuit.

[0009] In the aforementioned DICE-based anti-multi-node flip-flop latch, the clock-controlled two-input C-cell circuit includes PMOS317, PMOS318, PMOS319, and NMOS320, NMOS321, and NMOS322. The gates of PMOS317 and NMOS322 are connected together as the first input terminal of the clock-controlled two-input C-cell circuit. The gates of PMOS318 and NMOS321 are connected together as the second input terminal of the clock-controlled two-input C-cell circuit. The gate of PMOS319 serves as the second input terminal of the clock-controlled two-input C-cell circuit. The first clock input is the gate of NMOS320, which serves as the second clock input for the clock control C-cell circuit. The source of PMOS317 is connected to the power supply VDD, the drain of PMOS317 is connected to the source of PMOS318, the drain of PMOS318 is connected to the source of PMOS319, the drain of PMOS319 is connected to the drain of NMOS320 and serves as the output of the clock control two-input C-cell circuit, the source of NMOS320 is connected to the drain of NMOS321, the source of NMOS321 is connected to the drain of NMOS322, and the source of NMOS322 is connected to the power supply ground GND.

[0010] In the above-mentioned DICE-based anti-multi-node flip-flop latch, the inverter circuit 205 includes a PMOS323 and an NMOS324. The source of the PMOS323 is connected to the power supply VDD, the gate of the PMOS323 is connected to the gate of the NMOS324 as the input terminal of the inverter circuit 206, the drain of the PMOS323 is connected to the drain of the NMOS324 as the output terminal of the inverter circuit 206, and the source of the NMOS324 is connected to the power supply ground GND.

[0011] In the aforementioned DICE-based anti-multi-node flip-flop latch, the DICE circuit 103 includes PMOS 301, 302, 303, 304 and NMOS 305, 306, 307, 308. The sources of PMOS 301, 302, 303, and 304 are connected to the power supply VDD, and the sources of NMOS 305, 306, 307, and 308 are connected to the power ground GND. The gate of PMOS 301, the drain of PMOS 304, the gate of NMOS 307, and the drain of NMOS 308 are connected together as... The second output terminal QBN, the drain of PMOS301, the gate of PMOS302, the drain of NMOS305 and the gate of NMOS308 are connected together to form the first input terminal QA, the gate of PMOS303, the drain of PMOS302, the gate of NMOS305 and the drain of NMOS306 are connected together to form the first output terminal QAN, and the gate of PMOS304, the drain of PMOS303, the gate of NMOS306 and the drain of NMOS307 are connected together to form the second input terminal QB.

[0012] In the aforementioned DICE-based anti-multi-node flip-flop latch, the delay circuits 104 and 105 include PMOS309, PMOS310, NMOS311, and NMOS312. The gate of PMOS309 is connected to the gate of NMOS311 as the input terminal of delay circuits 104 and 105. The source of PMOS309 is connected to the power supply VDD. The drain of PMOS309, the drain of NMOS311, the gate of PMOS310, and the gate of NMOS312 are connected together. The source of NMOS311 is connected to the power supply ground. The source of PMOS310 is connected to the power supply VDD. The drain of PMOS310 and the drain of NMOS312 are connected as the output terminal of delay circuits 104 and 105. The source of NMOS312 is connected to the power supply ground GND.

[0013] In the above-mentioned DICE-based anti-multi-node flip-flop latch, the output circuit 106 includes a two-input C-cell circuit 210 and a clock control C-cell circuit 211; the first input terminal of the two-input C-cell circuit 210 serves as the first input terminal of the output circuit 106, the second input terminal serves as the second input terminal of the output circuit 106, the output terminal is connected to the input terminal of the clock control C-cell circuit 211 as the first output terminal of the output circuit 106, and the output terminal of the clock control C-cell circuit 211 serves as the second output terminal of the output circuit 106.

[0014] In the aforementioned DICE-based anti-multi-node flip-flop latch, the clock control C-unit circuit 201 / 202 / 203 / 206 / 209 / 211 includes PMOS313, PMOS314, NMOS315, and NMOS316. The gates of PMOS313 and NMOS316 are connected together as the input terminal of the clock control C-unit circuit. The gate of PMOS314 serves as the first clock terminal of the clock control C-unit circuit, and the gate of NMOS315 serves as the second clock terminal of the clock control C-unit circuit. The source of PMOS313 is connected to the power supply VDD, and the drain of PMOS313 is connected to the source of PMOS314. The drain of PMOS314 is connected to the drain of NMOS315 and serves as the output terminal of the clock control C-unit circuit. The source of NMOS315 is connected to the drain of NMOS316, and the source of NMOS316 is connected to the power supply ground GND.

[0015] In the aforementioned DICE-based anti-multi-node flip-flop latch, the two-input C-cell circuit 207 / 208 / 210 includes PMOS325, PMOS326, NMOS327, and NMOS328. The gates of the PMOS325 and NMOS328 are connected together as the first input terminal of the two-input C-cell circuit, and the gates of the PMOS326 and NMOS327 are connected together as the second input terminal of the two-input C-cell circuit. The source of the PMOS325 is connected to the power supply VDD, the drain of the PMOS325 is connected to the source of the PMOS326, the drain of the PMOS326 is connected to the drain of the NMOS327 and serves as the output terminal of the two-input C-cell circuit, the source of the NMOS327 is connected to the drain of the NMOS328, and the source of the NMOS328 is connected to the power supply ground GND.

[0016] In the aforementioned DICE-based anti-multi-node flip-flop latch, the clock inverter circuit 107 includes a PMOS329 and an NMOS330; the gates of the PMOS329 and NMOS330 are connected together as the input terminal CLK of the clock inverter circuit, the source of the PMOS329 is connected to the power supply VDD, the drain of the PMOS329 is connected to the drain of the NMOS3330 and serves as the output terminal CLKN of the clock inverter circuit, and the source of the NMOS330 is connected to the power supply ground GND.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: (1) The present invention provides a DICE-based anti-multi-node flip latch, including an input circuit, a node holding and recovery circuit, a DICE circuit, a delay circuit, and an output circuit; the input circuit is composed of two input C unit circuits and is used for control signal input; the node holding and recovery circuit, the DICE circuit, and the output circuit are used for transmitting and latching data, and can tolerate multi-node flips and recover when the latch is irradiated; the delay circuit is used to recover the multi-node flips of the DICE and the output circuit with a delay signal; the structure proposed in the present invention can realize the instantaneous flip self-recovery function of single-event single-node and dual-node flips, and has the ability to resist three-node single-event flips, while the circuit structure is easy to implement.

[0018] (2) The latch circuit designed in the embodiment of the present invention can realize self-recovery of single-node and double-node flipping, as well as resist three-node flipping.

[0019] (3) In this embodiment of the invention, a delay circuit is used to harden the DICE against radiation. When the DICE circuit undergoes multi-node switching, the delay circuit can prevent the propagation of erroneous signals. The signal of the DICE circuit is restored by the node holding and recovery circuit, thus eliminating the effect of SET.

[0020] (4) In the latch circuit designed in the embodiment of the present invention, the delay circuit is not in the critical path of data transmission, and the timing overhead is small. Attached Figure Description

[0021] Figure 1 is a structural diagram of the latch circuit in an embodiment of the present invention; Figure 2 is a structural diagram of the input circuit in an embodiment of the present invention; Figure 3 is a structural diagram of the node hold and restore circuit in an embodiment of the present invention; Figure 4 is a structural diagram of the DICE circuit in an embodiment of the present invention; Figure 5 is a structural diagram of the delay circuit in an embodiment of the present invention; Figure 6 is a structural diagram of the output circuit in an embodiment of the present invention; Figure 7 is a structural diagram of the clock control C unit circuit in an embodiment of the present invention; Figure 8 is a structural diagram of the clock control two-input C unit circuit in an embodiment of the present invention; Figure 9 is a structural diagram of the inverter circuit in an embodiment of the present invention; Figure 10 is a structural diagram of the two-input C unit circuit in an embodiment of the present invention; Figure 11 is a structural diagram of the clock inverter circuit in an embodiment of the present invention. Detailed Implementation

[0022] The present application will be further described in detail below with reference to the accompanying drawings and embodiments: As shown in Figure 1, the present invention provides a DICE-based anti-multi-node flip-flop latch, including an input circuit, a node holding and recovery circuit, a DICE circuit, a delay circuit, an output circuit, and a clock inverter circuit; the input circuit has three outputs, which are respectively connected to the first input terminal D1, the second input terminal D2, and the third input terminal D3 of the node holding and recovery circuit; the fourth and fifth input terminals of the node holding and recovery circuit are respectively connected to the output terminals of the delay circuit; the sixth input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the third input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the fourth and fifth input terminals of the node holding and recovery circuit are respectively connected to the output terminals of the delay circuit; the sixth input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the sixth input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the third input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the fourth input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the fifth input terminal of the node holding and recovery circuit is connected to the first output terminal of the output circuit; the sixth ... The first and second output terminals are connected to the first input terminal QA and the second input terminal QB of the DICE circuit. The output terminals QAN and QBN of the DICE circuit are connected to the input terminals of the output circuit, respectively. The first output terminal QC of the output circuit is connected to the input terminal of the delay circuit. The second output terminal of the output circuit is the output of the entire circuit. The input circuit receives data signals from the outside. Under clock control, when the clock signal represents the transparent state of the latch circuit, the data signal is shaped and flipped before being output. When the clock signal represents the latch state of the latch circuit, no signal is transmitted. The node holding and recovery circuit receives the data signal input from the input circuit and the delay processing input from the delay circuit. The signal from the output circuit and the signal from the input circuit are used to judge the six input signals, generate the first and second output signals, and output them to the DICE circuit. The DICE circuit resists single-event upsets, maintains the level of the two output signals in the latched state, and recovers when the node flips. The DICE circuit judges the two input signals of the node hold and recover circuit, generates the first and second output signals, outputs them to the output circuit, resists single-event upsets, maintains the level of the two output signals in the latched state, and recovers when the node flips. The delay circuit delays the first output signal of the output circuit before outputting it to the node hold and recover circuit. In this circuit, when multiple nodes flip in the DICE and output circuits, the delay circuit can prevent pulses smaller than the rated width from propagating in the circuit and restore the node signals within that time period. The output circuit performs decision processing based on the signals from the first and second input terminals of the DICE circuit, generating signals for the first and second output terminals. The signal from the first output terminal is transmitted to the delay circuit and the node holding and recovery circuit, while the second output terminal is the output of the entire circuit and maintains the output level in the latched state. The clock inverter circuit is used to provide input clock signals to the input circuit, the node holding and recovery circuit, and the output circuit, controlling the opening and closing of the above circuits.

[0023] In one optional embodiment, as shown in Figure 2, the input circuit includes three clock control C unit circuits 201, 202, and 203. The input terminals of the clock control C unit circuits 201, 202, and 203 are connected together as the input terminal D of the input circuit 101. The output terminals of the clock control C unit circuits 201, 202, and 203 are respectively used as the first input terminal, the second input terminal, and the third input terminal of the input circuit 101. The clock control C unit circuits 201, 202, and 203 are connected to the clock signal output by the clock inverter circuit. Under clock control, when CLK is high and CLKN is low, the clock control C unit circuits 201, 202, and 203 are turned on, the latch circuit is in a transparent state, and the clock control C unit circuits 201, 202, and 203 shape and flip the signal before outputting it. When CLK is low and CLKN is high, the clock control C unit circuits 201, 202, and 203 are turned off, the latch circuit is in a latched state, and no signal is received.

[0024] In an optional embodiment, as shown in FIG3, the node hold and restore circuit 102 includes clock control C unit circuits 206 and 209, clock control two-input C unit circuit 204, inverter circuit 205, and two-input C unit circuits 207 and 208; the output terminal of the clock control C unit circuit 206 is connected to the first input terminal of the two-input C unit circuit 207 as the first input terminal of the node hold and restore circuit 102, the second input terminal of the two-input C unit circuit 207, the first input terminal of the two-input C unit circuit 208, and the output terminal of the clock control two-input C unit circuit 204 are connected as the second input terminal of the node hold and restore circuit 102, and the output terminal of the clock control C unit circuit 209, the second input terminal of the two-input C unit circuit 208, and the second input terminal of the two-input C unit circuit 204 are connected as the second input terminal of the node hold and restore circuit 102. The input terminal of inverter circuit 205 is connected as the third input terminal of node hold and restore circuit 102. The output terminal of inverter circuit 205 is connected to the first input terminal of clock control two-input C unit circuit 204. The input terminal of clock control C unit circuit 206 is connected as the fourth input terminal of node hold and restore circuit 102. The input terminal of clock control C unit circuit 209 is the fifth input terminal of node hold and restore circuit 102. The second input terminal of clock control two-input C unit circuit 204 is the sixth input terminal of node hold and restore circuit 102. The output terminal of two-input C unit circuit 207 is the first output terminal of node hold and restore circuit 102. The output terminal of two-input C unit circuit 208 is the second output terminal of node hold and restore circuit 102.

[0025] When CLK is high and CLKN is low, the latch circuit is in a transparent state. Clock control C unit circuits 206 and 209 and clock control two-input C unit circuit 204 are closed, and two-input C unit circuits 207 and 208 make decisions on the three input signals and output them. When CLK is low and CLKN is high, the latch circuit is in a latching state. Clock control C unit circuits 206 and 209 and clock control two-input C unit circuit 204 are open. Clock control C unit circuit 206 holds the signal at node D1, inverter circuit 205 and clock control two-input C unit circuit 204 hold the signal at node D2, and clock control C unit circuit 209 holds the signal at node D3.

[0026] In one optional embodiment, as shown in FIG4, the DICE circuit 103 includes PMOS (301, 302, 303, 304) and NMOS (305, 306, 307, 308). The sources of PMOS (301, 302, 303, 304) are connected to the power supply VDD, and the sources of NMOS (305, 306, 307, 308) are connected to the power ground GND. The gate of PMOS 301, the drain of PMOS 304, the gate of NMOS 307, and the drain of NMOS 308 are connected together as the first... The two output terminals are QBN, the drain of PMOS301, the gate of PMOS302, the drain of NMOS305, and the gate of NMOS308 are connected together to form the first input terminal QA, the gate of PMOS303, the drain of PMOS302, the gate of NMOS305, and the drain of NMOS306 are connected together to form the first output terminal QAN, and the gate of PMOS304, the drain of PMOS303, the gate of NMOS306, and the drain of NMOS307 are connected together to form the second input terminal QB.

[0027] In one optional embodiment, as shown in FIG5, the delay circuits 104 and 105 include PMOS309, PMOS310, NMOS311 and NMOS312; the gate of PMOS309 and the gate of NMOS311 are connected as the input terminal of the delay circuit, the source of PMOS309 is connected to the power supply VDD, the drain of PMOS309, the drain of NMOS311, the gate of PMOS310 and the gate of NMOS312 are connected together, the source of NMOS311 is connected to the power supply ground, the source of PMOS310 is connected to the power supply VDD, the drain of PMOS310 and the drain of NMOS312 are connected as the output terminal of the delay circuit, and the source of NMOS312 is connected to the power supply ground GND.

[0028] In one optional embodiment, as shown in FIG6, the output circuit 106 includes a two-input C unit circuit 210 and a clock control C unit circuit 211; the first input terminal of the two-input C unit circuit 210 serves as the first input terminal of the output circuit 106, the second input terminal serves as the two input terminals of the output circuit 106, the output terminal is connected to the input terminal of the clock control C unit circuit 211 as the first output terminal of the output circuit 106, and the output terminal of the clock control C unit circuit 211 serves as the second output terminal of the output circuit 106.

[0029] When CLK is high and CLKN is low, the latch circuit is in a transparent state, the clock control C unit circuit (211) is turned off, and the latch circuit maintains its current state; when CLK is low and CLKN is high, the latch circuit is in a latching state, the clock control C unit circuit (211) is turned on, and the latch circuit outputs.

[0030] In one optional embodiment, as shown in FIG7, the clock control C unit circuit (201 / 202 / 203 / 206 / 209 / 211) includes PMOS313, PMOS314, NMOS315 and NMOS316; the gate of PMOS313 and the gate of NMOS316 are connected together as the input terminal of the clock control C unit circuit, the gate of PMOS314 serves as the first clock terminal of the clock control C unit circuit, the gate of NMOS315 serves as the second clock terminal of the clock control C unit circuit, the source of PMOS313 is connected to the power supply VDD, the drain of PMOS313 is connected to the source of PMOS314, the drain of PMOS314 is connected to the drain of NMOS315 and serves as the output terminal of the clock control C unit circuit, the source of NMOS315 is connected to the drain of NMOS316, and the source of NMOS316 is connected to the power supply ground GND.

[0031] In one optional embodiment, as shown in FIG8, the clock-controlled two-input C-cell circuit 204 includes PMOS 317, PMOS 318, PMOS 319 and NMOS 320, NMOS 321, and NMOS 322; the gates of PMOS 317 and NMOS 322 are connected together as the first input terminal of the clock-controlled two-input C-cell circuit, the gates of PMOS 318 and NMOS 321 are connected together as the second input terminal of the clock-controlled two-input C-cell circuit, and the gate of PMOS 319 serves as the second input terminal of the clock-controlled two-input C-cell circuit. The first clock input is the gate of NMOS320, which serves as the second clock input for the clock control C-cell circuit. The source of PMOS317 is connected to the power supply VDD, the drain of PMOS317 is connected to the source of PMOS318, the drain of PMOS318 is connected to the source of PMOS319, the drain of PMOS319 is connected to the drain of NMOS320 and serves as the output of the clock control two-input C-cell circuit, the source of NMOS320 is connected to the drain of NMOS321, the source of NMOS321 is connected to the drain of NMOS322, and the source of NMOS322 is connected to the power supply ground GND.

[0032] In one optional embodiment, as shown in FIG9, the inverter circuit 205 includes a PMOS323 and an NMOS324. The source of the PMOS323 is connected to the power supply VDD, the gate of the PMOS323 is connected to the gate of the NMOS324 as the input terminal of the inverter circuit 206, the drain of the PMOS323 is connected to the drain of the NMOS324 as the output terminal of the inverter circuit 206, and the source of the NMOS324 is connected to the power ground GND.

[0033] In one optional embodiment, as shown in FIG10, the two-input C-cell circuit 207 / 208 / 210 includes PMOS325, PMOS326, NMOS327 and NMOS328; the gate of PMOS325 and the gate of NMOS328 are connected together as the first input terminal of the two-input C-cell circuit, the gate of PMOS326 and the gate of NMOS327 are connected together as the second input terminal of the two-input C-cell circuit, the source of PMOS325 is connected to power supply VDD, the drain of PMOS325 is connected to the source of PMOS326, the drain of PMOS326 is connected to the drain of NMOS327 and serves as the output terminal of the two-input C-cell circuit, the source of NMOS327 is connected to the drain of NMOS328, and the source of NMOS328 is connected to power ground GND.

[0034] In one optional embodiment, as shown in FIG11, the clock inverter circuit 107 includes a PMOS329 and an NMOS330; the gates of the PMOS329 and the NMOS330 are connected together as the input terminal CLK of the clock inverter circuit, the source of the PMOS329 is connected to the power supply VDD, the drain of the PMOS329 is connected to the drain of the NMOS3330 and serves as the output terminal CLKN of the clock inverter circuit, and the source of the NMOS330 is connected to the power supply ground GND.

[0035] As shown in Figure 1, this embodiment of the present invention provides a schematic diagram of a DICE-based anti-multi-node flip-flop latch, which includes an input circuit, a node hold and restore circuit, a DICE circuit, a delay circuit, an output circuit, and a clock inverter circuit.

[0036] The input circuit has three outputs, which are connected to the first input terminal D1, the second input terminal D2, and the third input terminal D3 of the node hold and restore circuit, respectively. The fourth and fifth input terminals of the node hold and restore circuit are connected to the output terminals of the delay circuit, respectively. The sixth input terminal of the node hold and restore circuit is connected to the first output terminal of the output circuit. The first and second output terminals of the node hold and restore circuit are connected to the first input terminal QA and the second input terminal QB of the DICE circuit. The output terminals QAN and QBN of the DICE circuit are connected to the input terminals of the output circuit, respectively. The first output terminal QC of the output circuit is connected to the input terminal of the delay circuit. The second output terminal of the output circuit is the output of the entire circuit.

[0037] As shown in Figure 2, the input circuit includes clock control C unit circuits 201, 202, and 203. CLK is connected to the first clock terminal, and CLKN is connected to the second clock terminal. Under clock control, when CLK is high and CLKN is low, clock control C unit circuits 201, 202, and 203 are enabled, and the latch circuit is in a transparent state. Clock control C unit circuits 201, 202, and 203 receive external data signals, shape and flip the signals, and then output them. When CLK is low and CLKN is high, clock control C unit circuits 201, 202, and 203 are disabled, the latch circuit is in a latched state, and no signals are received.

[0038] As shown in Figure 3, the node holding and recovery circuit 102 includes clock control C unit circuits 206 and 209, clock control two-input C unit circuit 204, inverter circuit 205, and two-input C unit circuits 207 and 208. The first clock input of clock control C unit circuits 206 and 209 and clock control two-input C unit circuit 204 is connected to CLKN, and the second clock input is connected to CLK. When CLK is high and CLKN is low, the latch circuit is in a transparent state. When the primary circuit 204 is off, the two-input C-unit circuits 207 and 208 make decisions and output the three input signals. When CLK is low and CLKN is high, the latch circuit is in latching state, the clock control C-unit circuits 206 and 209 and the clock control two-input C-unit circuit 204 are on. The clock control C-unit circuit 206 holds the signal at node D1, the inverter circuit 205 and the clock control two-input C-unit circuit 204 hold the signal at node D2, and the clock control C-unit circuit 209 holds the signal at node D3.

[0039] As shown in Figure 6, the output circuit 106 includes a two-input C-unit circuit 210 and a clock control C-unit circuit 211. The first clock terminal of the clock control C-unit circuit 211 is connected to CLKN, and the second clock terminal is connected to CLK. When CLK is high and CLKN is low, the latch circuit is in a transparent state, the clock control C-unit circuit 211 is turned off, and the latch circuit maintains its current state. When CLK is low and CLKN is high, the latch circuit is in a latching state, the clock control C-unit circuit 211 is turned on, and the latch circuit outputs.

[0040] When CLK is high and CLKN is low, input circuit 101 is turned on, and clock control C unit circuits 206, 209, and 211 and clock control two-input C unit circuit 204 are turned off. At this time, the latch is in a unidirectional transparent state.

[0041] Normal state: The node signals of D1, D2, and D3 are judged by the node holding and recovery circuit 102, and the output result is transmitted to the QA and QB ports of the DICE circuit 103. The output node Q of the latch saves the previous signal result.

[0042] Flip state: The clock control C unit circuit 211 of the output circuit 106 will block the transmission of error data to node Q, and the continuously input signal will refresh the error state.

[0043] When CLK is low and CLKN is high, input circuit 101 is closed, and clock control C unit circuits 206, 209, and 211 and clock control two-input C unit circuit 204 are opened. At this time, the latch is in latching state.

[0044] Normal state: The node signals of D1, D2, and D3 are transmitted to the QA and QB ports of the DICE circuit 103 after being decided by the two-input C unit circuits 207 and 208. The node signal of D1 is held by the clock-controlled C unit circuit 206, the node signal of D2 is held by the clock-controlled two-input C unit circuit 204, and the node signal of D3 is held by the clock-controlled C unit circuit 209. The node signals of QA and QB are held by the DICE circuit 103, and the node signals QAN and QBN are output. QAN and QBN are inverted from the node signals of QA and QB, respectively. After being decided by the two-input C unit circuit 210, the node signals of QAN and QBN are output in one direction and transmitted to the delay circuit to hold the node signals of D1 and D3. The other direction is output by the clock-controlled two-input C unit circuit 211.

[0045] Single-node flip: Due to the presence of C-unit circuits and DICE circuits, when any of the nodes D1, D2, and D3 flips, the corresponding C-unit circuit will be in a closed state, blocking the transmission of erroneous data, and the corresponding signal holding circuit can recover the single-node flip; when any of the nodes QA, QB, QAN, and QBN flips, the DICE circuit can recover; when point QC flips, the two-input C-unit circuit 210 can recover. Dual-node flip: When nodes D2 and D1 / D3 flip, QA / QB controlled by these two points will flip. Since the DICE circuit recovers the single-node flip, erroneous data will not be transmitted, and the flips of nodes D2 and D1 / D3 will be recovered by clock-controlled two-input C-unit circuit 204 and clock-controlled C-unit circuits 206 and 209; when node D1... When D3 flips, due to the presence of the two-input C-unit circuits 207 and 208, the erroneous data will not be transmitted and will be restored by the clock-controlled C-unit circuits 206 and 209. When nodes QC and D2 flip, since there is no delay circuit at the sixth input of the node holding and recovery circuit 102, the clock-controlled two-input C-unit circuit 204 is turned off. However, there is a path with a delay circuit, so the erroneous data is transmitted to nodes D1 and D3 more slowly. During the delay time, QAN and QBN restore QC through the two-input C-unit circuit 210. After that, the clock-controlled two-input C-unit 204 is turned on and D2 is restored. At this time, the erroneous data is transmitted to nodes D1 and D3. Since the node signal of D2 is restored to correct, the two-input C-unit circuits 207 and 208 are turned off, preventing the erroneous data from being transmitted to the next node and restoring the correct data after the radiation pulse ends.

[0046] Multi-node flipping: When any two nodes in QA / QB / QAN / QBN flip, due to the characteristics of the DICE circuit, all four nodes will flip. The QC node will generate erroneous data, but due to the existence of the delay circuit, this data will not be immediately transmitted to nodes D1 and D2. At this time, the data of nodes D1, D2, and D3 are all in the correct state, and the DICE circuit is restored to the normal state through the two-input C unit circuits 207 and 208. The erroneous data is transmitted to nodes D1 and D3. Since the node signal of D2 is correct, the two-input C unit circuits are restored to the correct state. The C unit circuits 207 and 208 are turned off to prevent erroneous data from propagating backward and to restore correct data after the radiation pulse ends. When any of the nodes D1, D3, QA / QB / QAN / QBN flips, the signal at node D2 remains unchanged, preventing the erroneous signal from propagating backward. The signal flips at nodes D1 and D3 can be restored by the clock control of the C unit circuits 206 and 209. The flips of any of the nodes QA / QB / QAN / QBN can be restored by the DICE circuit, and the final output remains unchanged, thus achieving resistance to the flips of the three nodes.

[0047] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0048] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A DICE-based anti-multi-node flip-flop latch, characterized in that, include: The input circuit receives external data signals. Under clock control, when the clock signal indicates the transparent state of the latch circuit, it shapes and flips the data signal before outputting it. When the clock signal indicates the latch circuit's latched state, it does not transmit the data signal. The node holding and recovery circuit receives the data signal from the input circuit, the delayed signal from the delay circuit, and the signal from the output circuit. It judges the received signals, generates a first output terminal and a second output terminal signal, outputs them to the DICE circuit, resists single-event upsets, maintains the level of the two output signals in the latched state, and recovers when a node flips. The DICE circuit judges the two input signals of the node holding and recovery circuit, generates a first output terminal and a second output terminal signal, outputs them to the output circuit, resists single-event upsets, maintains the level of the two output signals in the latched state, and recovers when a node flips. The delay circuit receives the signal from the first output terminal of the output circuit, performs delay processing, and outputs it to the node holding and recovery circuit. When multiple node flips occur in the DICE circuit and the output circuit, it prevents pulses smaller than the rated width from propagating in the circuit and recovers the node signals. The output circuit performs decision processing based on the signals from the first and second input terminals of the DICE circuit to generate signals from the first and second output terminals. The signal from the first output terminal is sent to the delay circuit and the node holding and recovery circuit, while the signal from the second output terminal is output outward and maintains the output level in the latched state. The clock inverter circuit provides input clock signals to the input circuit, node hold and restore circuit, and output circuit, and controls the opening and closing of the three circuits.

2. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The input circuit has three outputs, which are respectively connected to the first input terminal D1, the second input terminal D2, and the third input terminal D3 of the node hold and restore circuit. The fourth and fifth input terminals of the node hold and restore circuit are respectively connected to the output terminals of the two delay circuits. The sixth input terminal of the node hold and restore circuit is connected to the first output terminal of the output circuit. The first and second output terminals of the node hold and restore circuit are connected to the first input terminal QA and the second input terminal QB of the DICE circuit. The output terminals QAN and QBN of the DICE circuit are respectively connected to the input terminals of the output circuit. The first output terminal QC of the output circuit is connected to the input terminal of the delay circuit. The second output terminal of the output circuit is the output of the entire circuit.

3. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The input circuit (101) includes three clock control C unit circuits (201, 202, 203). The input terminals of the clock control C unit circuits (201, 202, 203) are connected together as the input terminal D of the input circuit (101). The output terminals of the clock control C unit circuits (201, 202, 203) are respectively used as the first output terminal, the second output terminal, and the third output terminal of the input circuit (101). The three clock control C unit circuits (201, 202, 203) are connected to the clock signal output by the clock inverter circuit. Under clock control, when the clock signal represents the transparent state of the latch circuit, the signal is shaped and flipped before being output. When the clock signal represents the latch state of the latch circuit, no signal is transmitted.

4. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The node holding and recovery circuit (102) includes a clock control C unit circuit (206, 209), a clock control two-input C unit circuit (204), an inverter circuit (205), and two-input C unit circuits (207, 208). The output terminal of the clock control C unit circuit (206) is connected to the first input terminal of the two-input C unit circuit (207) as the first input terminal of the node holding and recovery circuit (102). The second input terminal of the two-input C unit circuit (207), the first input terminal of the two-input C unit circuit (208), and the output terminal of the clock control two-input C unit circuit (204) are connected as the second input terminal of the node holding and recovery circuit (102). The output terminal of the clock control C unit circuit (209), the second input terminal of the two-input C unit circuit (208), and the inverter circuit (205) are connected as the second input terminal of the node holding and recovery circuit (102). The input terminal of the inverter circuit (205) is connected as the third input terminal of the node hold and restore circuit (102). The output terminal of the inverter circuit (205) is connected to the first input terminal of the clock control two-input C unit circuit (204). The input terminal of the clock control C unit circuit (206) is connected as the fourth input terminal of the node hold and restore circuit (102). The input terminal of the clock control C unit circuit (209) is the fifth input terminal of the node hold and restore circuit (102). The second input terminal of the clock control two-input C unit circuit (204) is the sixth input terminal of the node hold and restore circuit (102). The output terminal of the two-input C unit circuit (207) is the first output terminal of the node hold and restore circuit (102). The output terminal of the two-input C unit circuit (208) is the second output terminal of the node hold and restore circuit (102).

5. The DICE-based anti-multi-node flip-flop latch according to claim 4, characterized in that, The clock-controlled two-input C-cell circuit (204) includes PMOS (317), PMOS (318), PMOS (319), and NMOS (320), NMOS (321), and NMOS (322). The gates of PMOS (317) and NMOS (322) are connected together as the first input terminal of the clock-controlled two-input C-cell circuit. The gates of PMOS (318) and NMOS (321) are connected together as the second input terminal of the clock-controlled two-input C-cell circuit. The gate of PMOS (319) serves as the first clock terminal of the clock-controlled two-input C-cell circuit. The gate of (320) serves as the second clock terminal of the clock control C unit circuit. The source of the PMOS (317) is connected to the power supply VDD. The drain of the PMOS (317) is connected to the source of the PMOS (318). The drain of the PMOS (318) is connected to the source of the PMOS (319). The drain of the PMOS (319) is connected to the drain of the NMOS (320) and serves as the output terminal of the clock control two-input C unit circuit. The source of the NMOS (320) is connected to the drain of the NMOS (321). The source of the NMOS (321) is connected to the drain of the NMOS (322). The source of the NMOS (322) is connected to the power supply ground GND.

6. The DICE-based anti-multi-node flip-flop latch according to claim 4, characterized in that, The inverter circuit (205) includes a PMOS (323) and an NMOS (324). The source of the PMOS (323) is connected to the power supply VDD. The gate of the PMOS (323) is connected to the gate of the NMOS (324) as the input terminal of the inverter circuit (206). The drain of the PMOS (323) is connected to the drain of the NMOS (324) as the output terminal of the inverter circuit (206). The source of the NMOS (324) is connected to the power ground GND.

7. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The DICE circuit (103) includes PMOS (301, 302, 303, 304) and NMOS (305, 306, 307, 308). The source of PMOS (301, 302, 303, 304) is connected to the power supply VDD, and the source of NMOS (305, 306, 307, 308) is connected to the power ground GND. The gate of PMOS (301), the drain of PMOS (304), the gate of NMOS (307), and the drain of NMOS (308) are connected together as the second output terminal QBN. The drain of PMOS (301), the gate of PMOS (302), the drain of NMOS (305), and the gate of NMOS (308) are connected together as the first input terminal QA. The gate of PMOS (303), the drain of PMOS (302), the gate of NMOS (305), and the drain of NMOS (306) are connected together as the first output terminal QAN. The gate of PMOS (304), the drain of PMOS (303), the gate of NMOS (306), and the drain of NMOS (307) are connected together as the second input terminal QB.

8. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The delay circuit (104, 105) includes PMOS (309), PMOS (310), NMOS (311) and NMOS (312); the gate of PMOS (309) is connected to the gate of NMOS (311) as the input terminal of the delay circuit (104, 105), the source of PMOS (309) is connected to the power supply VDD, the drain of PMOS (309), the drain of NMOS (311), the gate of PMOS (310) and the gate of NMOS (312) are connected together, the source of NMOS (311) is connected to the power supply ground, the source of PMOS (310) is connected to the power supply VDD, the drain of PMOS (310) and the drain of NMOS (312) are connected as the output terminal of the delay circuit (104, 105), and the source of NMOS (312) is connected to the power supply ground GND.

9. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The output circuit (106) includes a two-input C-unit circuit (210) and a clock control C-unit circuit (211); the first input terminal of the two-input C-unit circuit (210) serves as the first input terminal of the output circuit (106), the second input terminal serves as the second input terminal of the output circuit (106), the output terminal is connected to the input terminal of the clock control C-unit circuit (211) as the first output terminal of the output circuit (106), and the output terminal of the clock control C-unit circuit (211) serves as the second output terminal of the output circuit (106).

10. The DICE-based anti-multi-node flip-flop latch according to claim 3, 4, or 7, characterized in that, The clock control C unit circuit (201 / 202 / 203 / 206 / 209 / 211) includes PMOS (313), PMOS (314), NMOS (315) and NMOS (316); the gate of PMOS (313) and the gate of NMOS (316) are connected together as the input terminal of the clock control C unit circuit, the gate of PMOS (314) is used as the first clock terminal of the clock control C unit circuit, the gate of NMOS (315) is used as the second clock terminal of the clock control C unit circuit, the source of PMOS (313) is connected to the power supply VDD, the drain of PMOS (313) is connected to the source of PMOS (314), the drain of PMOS (314) is connected to the drain of NMOS (315) and used as the output terminal of the clock control C unit circuit, the source of NMOS (315) is connected to the drain of NMOS (316), and the source of NMOS (316) is connected to the power supply ground GND.

11. The DICE-based anti-multi-node flip-flop latch according to claim 4 or 9, characterized in that, The two-input C-cell circuit (207 / 208 / 210) includes PMOS (325), PMOS (326), NMOS (327) and NMOS (328); the gate of PMOS (325) and the gate of NMOS (328) are connected together as the first input terminal of the two-input C-cell circuit, the gate of PMOS (326) and the gate of NMOS (327) are connected together as the second input terminal of the two-input C-cell circuit, the source of PMOS (325) is connected to the power supply VDD, the drain of PMOS (325) is connected to the source of PMOS (326), the drain of PMOS (326) is connected to the drain of NMOS (327) and serves as the output terminal of the two-input C-cell circuit, the source of NMOS (327) is connected to the drain of NMOS (328), and the source of NMOS (328) is connected to the power supply ground GND.

12. The DICE-based anti-multi-node flip-flop latch according to claim 1, characterized in that, The clock inverter circuit (107) includes a PMOS (329) and an NMOS (330); the gates of the PMOS (329) and the NMOS (330) are connected together as the input terminal CLK of the clock inverter circuit, the source of the PMOS (329) is connected to the power supply VDD, the drain of the PMOS (329) is connected to the drain of the NMOS (330) and serves as the output terminal CLKN of the clock inverter circuit, and the source of the NMOS (330) is connected to the power supply ground GND.

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