Memory training method, device, computing device and storage medium

Abstract

An embodiment of the present invention provides a memory training method, apparatus, electronic device, and storage medium. The method includes: for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets a first condition, a first training program is executed. The first training program ignores empty slots. The first condition is used to indicate that there is at least one memory slot without a plugged-in memory in the memory channel and the adapted memory frequency is less than a preset frequency; or, for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets a second condition, a second training program is executed. The second training program performs signal compensation on the memory slots without a plugged-in memory. The second condition is used to indicate that there is at least one memory slot without a plugged-in memory in the memory channel and the adapted memory frequency is greater than or equal to the preset frequency. The embodiments of the present invention can improve the effect of memory training and thus improve system performance.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a memory training method, a memory training device, a computing device, and a storage medium. Background Art

[0002] For an electronic device, the memory plays a crucial role in whether the operating system of the electronic device can run properly. To ensure that the memory of the electronic device can be accessed normally, memory control parameters need to be configured.

[0003] The memory control parameters are obtained through memory training. During the memory training process, the memory control parameters are continuously adjusted to obtain the optimal values to ensure that the memory device can work in the most stable state.

[0004] To improve the performance of an electronic device, the electronic device may be configured with multiple central processing units (CPUs), and each CPU can be externally connected to multiple memory modules. However, when the memory slots are not fully occupied, the empty slots (i.e., the memory slots without memory modules plugged in) may cause certain interference to the memory training, affecting the effect of the memory training and thus the performance of the electronic device. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a memory training method, device, computing device, and storage medium that can overcome or at least partially solve the above problems, and can improve the effect of memory training and thus the performance of the electronic device when there are empty slots in the memory slots.

[0006] Correspondingly, embodiments of the present invention also provide a memory training device, a computing device for the memory training device, and a storage medium to ensure the implementation and application of the above method.

[0007] To solve the above problems, embodiments of the present invention disclose a memory training method applied to an electronic device. The electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and satisfies a preset rule of inserting the outer memory slots first. The method includes:

[0008] For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel satisfies a first condition, a first training program is executed. The first training program is used to perform memory training on the plugged-in memories and ignore the memory slots without plugged-in memories. The first condition is used to indicate that there is at least one memory slot without a plugged-in memory in the memory channel and the memory frequency adapted to the memory channel is less than a preset frequency;

[0009] For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the second condition, a second training program is executed. The second training program is used to perform memory training on each inserted memory and perform signal compensation for the memory slots of uninserted memories. The second condition is used to indicate that there is at least one memory slot with an uninserted memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to a preset frequency.

[0010] An embodiment of the present invention also discloses a memory training device, which is applied to an electronic device. The electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and meets a preset rule of inserting the outer memory slots first. The device includes:

[0011] A first training module, which is used for any memory channel supported by any processor in the electronic device. If it is recognized that the memory channel meets the first condition, a first training program is executed. The first training program is used to perform memory training on each inserted memory and ignore the memory slots of uninserted memories. The first condition is used to indicate that there is at least one memory slot with an uninserted memory in the memory channel and the memory frequency adapted to the memory channel is less than a preset frequency;

[0012] A second training module, which is used for any memory channel supported by any processor in the electronic device. If it is recognized that the memory channel meets the second condition, a second training program is executed. The second training program is used to perform memory training on each inserted memory and perform signal compensation for the memory slots of uninserted memories. The second condition is used to indicate that there is at least one memory slot with an uninserted memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to a preset frequency.

[0013] An embodiment of the present invention also discloses a computing device, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of one or more of the memory training methods in the embodiments of the present invention.

[0014] An embodiment of the present invention also discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, it can implement one or more of the memory training methods in the embodiments of the present invention.

[0015] The memory training method, device, equipment, and storage medium provided by the embodiments of the present invention have the following advantages:

[0016] Based on a preset rule, when the memory slots in the memory channel are not fully populated, different memory training processes are set according to the memory frequency adapted to the memory channel, which can avoid the influence of the unpopulated memory slots on memory training, improve the effect of memory training, and further improve the system performance. In addition, based on the preset rule, the stubs of the memory traces only include the stubs generated by the pins of the inner memory slots themselves, and there will be no stubs between the inner memory slots and the outer memory slots, which can reduce the stubs of the memory traces and contribute to the smooth progress of memory training and the stability of the system. Moreover, the memory training method of the embodiments of the present invention does not require additional hardware costs to identify the positions of the unpopulated memory slots, and can save hardware costs while ensuring the effect of memory training. Description of the Drawings

[0017] Figure 1 is a flowchart of the steps of an embodiment of a memory training method of the present invention;

[0018] Figure 2 is a schematic diagram of setting the I2C address through pull-up and pull-down resistors of the present invention;

[0019] Figure 3 is a schematic diagram of the process of identifying that the memory in the memory channel meets the first condition of the present invention;

[0020] Figure 4 is a schematic diagram of the structure of a dual-slot memory channel externally connected with a single memory module of the present invention;

[0021] Figure 5 is a schematic diagram of the structure of a dual-slot memory channel externally connected with two memory modules of the present invention;

[0022] Figure 6 is a schematic diagram of the structure of a single-slot memory channel externally connected with a single memory module of the present invention;

[0023] Figure 7 is a schematic diagram of the process of identifying that the memory in the memory channel meets the second condition of the present invention;

[0024] Figure 8 is another schematic diagram of the structure of a dual-slot memory channel externally connected with a single memory module of the present invention;

[0025] Figure 9 is a block diagram of the structure of an embodiment of a memory training device of the present invention;

[0026] Figure 10 is a schematic diagram of the structure of a computing device of the present invention. Detailed Embodiments

[0027] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category and do not limit the number of objects. For example, the first object can be one or multiple. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0029] Method Embodiment

[0030] Refer to Figure 1 , which shows a step flowchart of an embodiment of a memory training method of the present invention. The method can be applied to an electronic device. The electronic device includes at least one processor, each processor can support at least one memory channel, each memory channel can correspond to at least two memory slots, and satisfies a preset rule of inserting the outer memory slots first. The method can specifically include the following steps:

[0031] Step 101: For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel satisfies the first condition, execute the first training program. The first training program is used to perform memory training on the plugged-in memories and ignore the memory slots of the un-plugged memories. The first condition is used to indicate that there is at least one memory slot of the un-plugged memory in the memory channel and the memory frequency adapted to the memory channel is less than the preset frequency.

[0032] Step 102: For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel satisfies the second condition, execute the second training program. The second training program is used to perform memory training on the plugged-in memories and perform signal compensation for the memory slots of the un-plugged memories. The second condition is used to indicate that there is at least one memory slot of the un-plugged memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to the preset frequency.

[0033] The memory training method provided by the present invention can be applied to an electronic device, and the electronic device includes but is not limited to: a server, a laptop computer, an in-vehicle computer, a desktop computer, a set-top box, a smart TV, etc.

[0034] The electronic device includes at least one CPU. Each CPU can support at least one memory channel, and each memory channel can correspond to at least two memory slots. During the power-on startup process of the electronic device, the Basic Input / Output System (BIOS) program initializes each part of the hardware of the electronic device one by one, including the initialization of the memory. This process requires memory training, that is, the memory controller needs to adjust the delay parameters of all memories one by one to meet the memory read / write timing specifications. This process requires scanning all the memories configured in the electronic device one by one to find the optimal value from the set of training values of the memory controller parameters.

[0035] In the embodiment of the present invention, for a memory channel with more than 1 memory slot, a preset rule is followed: insert the outer memory slot first. For example, if a memory channel leads out two memory slots (that is, this memory channel corresponds to two memory slots), when only one of these two memory slots is plugged with a memory, it must be the outer memory slot among these two memory slots that is plugged with the memory. Here, the outer side refers to the outer side of the Printed Circuit Board (PCB).

[0036] Stub is the length of the remaining redundant copper on the transmission line in the via of the PCB board. When the frequency of the circuit signal increases to a certain level, the stub will cause impedance drop, resulting in impedance discontinuity. The signal reflection generated will interfere with other surrounding signals, and in severe cases, it will affect the normal operation of the line system. Therefore, in order to reduce the stub of the memory trace and ensure the smooth progress of memory training and the stability of the server, the present invention sets the preset rule of inserting the outer memory slot first.

[0037] It should be noted that in specific implementation, a memory channel can correspond to at least two memory slots. In the embodiment of the present invention, the scenario where a memory channel corresponds to two memory slots is mainly used as an example for illustration, and the scenario where a memory channel corresponds to more than three memory slots can be referred to each other.

[0038] Based on the preset rules of the present invention, for a certain memory channel, when there are more than two memory slots corresponding to this memory channel and only one memory slot has a memory plugged in, it must be plugged into the outer memory slot. In this way, the stub on the entire path only includes the stub generated by the pins of the inner memory slot itself, and there will be no stub between the inner memory slot and the outer memory slot, which can reduce the stub of the memory trace and contribute to the smooth progress of memory training and the stability of the system.

[0039] For any memory channel supported by any processor in the electronic device, when there are two memory slots corresponding to this memory channel, there are the following two situations: a single memory module is externally connected to this memory channel or two memory modules are externally connected to this memory channel. When two memory modules are externally connected, since both memory slots corresponding to this memory channel have memories plugged in, there is no memory slot without a plugged-in memory in this memory channel at this time, and thus there will be no influence of an empty slot. Therefore, the present invention mainly describes the situation where a single memory module is externally connected to a dual-slot memory channel. In addition, for the convenience of description, the embodiments of the present invention mainly take a certain memory channel supported by a certain processor in the electronic device as an example for description. The processing processes of other memory channels are the same and can be mutually referred to.

[0040] In the embodiments of the present invention, the memory frequency adapted by the memory channel actually refers to the memory frequency adapted by the PCB, that is, the maximum memory frequency supported by the PCB. In specific implementation, different PCBs can be set to adapt different memory frequencies when leaving the factory.

[0041] Based on the preset rules of the present invention, when there is at least one memory slot without a plugged-in memory (that is, the memory slot is not fully plugged) in a certain memory channel, if the memory frequency adapted by the PCB is less than the preset frequency (such as set as F), the signal interference generated by the stub caused by the pins of the memory slot without a plugged-in memory (referred to as an empty slot in the embodiments of the present invention) is very small and can be ignored; however, if the memory frequency adapted by the PCB is greater than or equal to F, the stub caused by the pins of the empty slot will generate relatively serious signal interference, and this interference cannot be ignored.

[0042] For the above two situations, the embodiments of the present invention set different memory training processes.

[0043] Specifically, for a certain memory channel, if it is recognized that the memory channel meets the first condition, the first training program is executed. The first training program is used to perform memory training on each plugged-in memory corresponding to the memory channel and ignore the memory slots of the unplugged memories (that is, ignore the influence caused by the empty slots). The first condition is used to indicate that there is at least one memory slot with an unplugged memory in the memory channel and the memory frequency adapted to the memory channel is less than the preset frequency. If it is recognized that the memory channel meets the second condition, the second training program is executed. The second training program includes optimized training code for the empty slots and is used to perform memory training on each plugged-in memory corresponding to the memory channel and perform signal compensation for the memory slots of the unplugged memories (empty slots) to eliminate the signal interference caused by the empty slots and improve the signal quality. The second condition is used to indicate that there is at least one memory slot with an unplugged memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to the preset frequency.

[0044] The embodiments of the present invention do not limit the method of signal compensation. Optionally, signal compensation can be performed by adjusting memory parameters to reduce the influence of empty slots on the signal and improve the signal quality. Exemplarily, the adjustment of memory parameters includes, but is not limited to, adjusting parameters such as ODT (on-die termination) and / or Vref (reference voltage signal).

[0045] It can be understood that for the memory channel, there should also be at least one memory slot with a plugged-in memory to ensure that the system can be started normally.

[0046] In the embodiments of the present invention, when there is at least one memory slot with an unplugged memory in a certain memory channel (that is, the memory slots are not fully plugged) and the memory frequency adapted to the PCB is less than the preset frequency, a memory training program that ignores empty slots (such as the first training program) is executed. When there is at least one memory slot with an unplugged memory in a certain memory channel (that is, the memory slots are not fully plugged) and the memory frequency adapted to the PCB is greater than or equal to the preset frequency, a memory training program that optimizes empty slots (such as the second training program) is executed. Through the embodiments of the present invention, when the memory slots corresponding to a certain memory channel are not fully plugged, different memory training processes are set according to the memory frequency adapted to the PCB, which can avoid the influence of empty slots on memory training, improve the effect of memory training, and thus improve the system performance.

[0047] In an optional embodiment of the present invention, the I2C (Inter-Integrated Circuit) address of the memory slot can be preset according to the adapted memory frequency and the position of the memory slot, so as to identify the position of the empty slot without increasing additional hardware costs.

[0048] The I2C bus, also known as the IIC (Inter Integrated Circuit) bus, is short for the IIC Bus. It is a serial communication bus that adopts a multi-master and multi-slave architecture. The I2C uses the serial clock line SCL and the serial data line SDA to implement signal transmission between the master and slave devices according to the I2C protocol. Refer to Figure 2 , which shows a schematic diagram of setting the I2C address through pull-up and pull-down resistors in an embodiment of the present invention. Figure 2 Taking an example where a certain memory channel supported by the processor 10 corresponds to two memory slots, these two memory slots are respectively plugged with memories 20, and the connection structure of each memory 20 to the processor 10 is the same. Among them, SA0, SA1, and SA2 represent three-bit I2C addresses, corresponding to An, An + 1, and An + 2.

[0049] Furthermore, the memory slot includes an inner memory slot and an outer memory slot. The step of presetting the I2C address of the memory slot according to the adapted memory frequency and the position of the memory slot may include:

[0050] When the adapted memory frequency is less than the preset frequency, set the I2C address of the outer memory slot as the first address, and set the I2C address of the inner memory slot as the second address; or, when the adapted memory frequency is greater than or equal to the preset frequency, set the I2C address of the inner memory slot as the first address, and set the I2C address of the outer memory slot as the second address.

[0051] The embodiments of the present invention do not limit the specific values of the first address and the second address. Exemplarily, the embodiments of the present invention set the first address as An and the second address as An + 1. In terms of hardware, the I2C address of the memory slot can be set through the Figure 2 shown pull-up and pull-down resistor circuit. The combination of the pull-up resistors and the pull-down resistors connected to all the address pins of each memory is different, so that the pull-up resistors and the pull-down resistors respectively cooperate with the address pins they are connected to to configure different physical addresses (i.e., I2C addresses) for each memory; the I2C address can be measured by a multimeter.

[0052] Furthermore, when the memory frequency adapted by the PCB is less than F, the present invention sets the I2C address of the outer memory slot corresponding to a memory channel as An. When the memory frequency adapted by the PCB is greater than or equal to F, the present invention sets the I2C address of the outer memory slot corresponding to a memory channel as An + 1.

[0053] Based on the preset rule of inserting into the outer memory slot first, the embodiment of the present invention further pre-sets the I2C address of the memory slot according to the memory frequency adapted by the PCB and the position of the memory slot. In this way, by measuring the I2C address, the insertion situation of each memory slot in the memory channel can be quickly identified. Furthermore, according to the insertion situation of each memory slot in the identified memory channel and the memory frequency adapted by the PCB, it can be quickly determined whether the memory channel meets the first condition or the second condition, which can further improve the efficiency of memory training.

[0054] In addition, the embodiment of the present invention pre-sets the I2C address of the memory slot according to the memory frequency adapted by the PCB and the position of the memory slot, which can accurately identify the position of the empty slot without increasing additional hardware costs. On the basis of ensuring the memory training effect, the hardware costs can be saved.

[0055] In an alternative embodiment of the present invention, the recognition that the memory channel meets the first condition includes:

[0056] Step S11: Detect whether the memory slot with the I2C address of the second address has a memory inserted;

[0057] Step S12: If it is detected that the memory slot with the I2C address of the second address does not have a memory inserted, it is determined that the memory channel meets the first condition.

[0058] Refer to Figure 3 , which shows a schematic flowchart of an embodiment of the present invention for recognizing that a memory channel meets the first condition. It should be noted that Figure 3 The shown flowchart is applicable to the scenario where the memory frequency adapted by the PCB is less than the preset frequency F. In this scenario, the embodiment of the present invention sets the I2C address of the outer memory slot to the first address (An) through a pull-up and pull-down resistor circuit, and sets the I2C address of the inner memory slot to the second address (An + 1). Refer to Figure 4 , which shows a schematic structural diagram of a dual-slot memory channel with a single memory stick externally connected. As Figure 4 shown, the I2C address of the outer memory slot is the first address (An), indicating that the memory frequency adapted by the PCB is less than the preset frequency F.

[0059] As Figure 3As shown, after the electronic device is started, it detects whether the memory slots with I2C address being the second address (An+1) have memory modules plugged in. Based on the preset rules of the present invention, the outer memory slots must have memory modules plugged in (otherwise the system cannot start normally). If it is detected that the memory slots with I2C address being the second address (An+1) do not have memory modules plugged in, it can be determined that the current memory channel meets the first condition (that is, the memory slots corresponding to the current memory channel are not fully plugged and the memory frequency adapted to the memory channel is less than the preset frequency). At this time, the first training program is executed to perform memory training on each plugged-in memory corresponding to the memory channel and ignore the influence of the empty slots.

[0060] In an alternative embodiment of the present invention, the method further includes:

[0061] If it is detected that the memory slots with I2C address being the second address have memory modules plugged in, the third training program is executed. The third training program is used to perform memory training on each plugged-in memory when the memory frequency adapted to it is less than the preset frequency and there are no memory slots with no plugged-in memory in the memory channel.

[0062] Further, as Figure 3 shown, if it is detected that the memory slots with I2C address being the second address (An+1) have memory modules plugged in, it indicates that the memory slots corresponding to the current memory channel are fully plugged (for example, the current memory channel corresponds to two memory slots and both have memory modules plugged in). At this time, there will be no influence of empty slots. Therefore, the third training program can be executed to perform memory training on each plugged-in memory corresponding to the memory channel. Refer to Figure 5 , which shows a schematic structural diagram of a dual-slot memory channel externally connected with two memory modules of the present invention. As Figure 5 shown, the I2C address of the outer memory slot is the first address (An), indicating that the memory frequency adapted by the PCB is less than the preset frequency F.

[0063] Refer to Figure 6 , which shows a schematic structural diagram of a single-slot memory channel externally connected with a single memory module of the present invention. As Figure 6 shown, in the case where the present invention embodiment makes a single-slot memory channel externally connected with a single memory module, the I2C address of the single slot is the first address (An). At this time, Figure 4 and Figure 6 shown have the same hardware structure in essence. Therefore, Figure 4 and Figure 6 shown can share a set of PCB software processes for PCB implementation without developing a separate PCB software version, which can reduce the software development cost. Further, as Figure 5 shown, in the case where a dual-slot memory channel is externally connected with two memory modules when the memory frequency adapted by the PCB is less than the preset frequency F, there is no influence of empty slots at this time, and the empty slots can be ignored. Therefore, Figure 4, Figure 5 , Figure 6 The implementation of the PCB with the structure shown can share a set of software processes (such as sharing the software process shown in Figure 3 ), which can save the costs of software development and maintenance.

[0064] In an alternative embodiment of the present invention, the identifying that the memory channel meets the second condition includes:

[0065] Step S21: Detect whether a memory is plugged into the memory slot with the I2C address being the second address;

[0066] Step S22: If it is detected that a memory is plugged into the memory slot with the I2C address being the second address, then detect whether a memory is plugged into the memory slot with the I2C address being the first address;

[0067] Step S23: If it is detected that no memory is plugged into the memory slot with the I2C address being the first address, then determine that the memory channel meets the second condition.

[0068] Referring to Figure 7 , a schematic flowchart of identifying that the memory channel meets the second condition in the present invention is shown. It should be noted that Figure 7 The flowchart shown is applicable to the scenario where the memory frequency adapted by the PCB is greater than or equal to the preset frequency F. In this scenario, in the embodiment of the present invention, the I2C address of the inner memory slot is set to the first address (An) through the pull-up and pull-down resistor circuit, and the I2C address of the outer memory slot is set to the second address (An + 1). Referring to Figure 8 , a schematic structural diagram of another dual-slot memory channel externally connected with a single memory module in the present invention is shown. As Figure 8 shown, the I2C address of the outer memory slot is the second address (An + 1), indicating that the memory frequency adapted by the PCB is greater than or equal to the preset frequency F.

[0069] As Figure 7 shown, after the electronic device is started, it is detected whether a memory is plugged into the memory slot with the I2C address being the second address (An + 1). Based on the preset rule of the present invention, the outer memory slot must have a memory plugged in. If it is detected that no memory is plugged into the memory slot with the I2C address being the second address (An + 1), then it can be determined that the memory slot with the I2C address being the first address (An) must have a memory plugged in, and it is determined that this is the case of a single-slot memory channel externally connected with a single memory module (that is, Figure 6Case). If it is detected that the memory slot with the I2C address of the second address (An+1) has a memory module plugged in, then it is further detected whether the memory slot with the I2C address of the first address (An) has a memory module plugged in. If it is detected that the memory slot with the I2C address of the first address (An) does not have a memory module plugged in, it is determined that the outer memory slot of the current memory channel has a memory module plugged in, while the inner memory slot does not have a memory module plugged in. And since the I2C address of the outer memory slot is the second address (An+1), it indicates that the memory frequency adapted by the PCB is greater than or equal to the preset frequency F. At this time, it can be determined that the second condition is satisfied, and then the second training program is executed. The second training program includes optimized training code for the empty slot.

[0070] In the embodiment of the present invention, when it is determined that the memory channel satisfies the second condition, the second training program is executed. Since when the memory channel satisfies the second condition, the stub generated by the empty slot will interfere with the memory signal, therefore, the second training program of the embodiment of the present invention compensates the memory signal to reduce the influence generated by the empty slot.

[0071] In an alternative embodiment of the present invention, the method further includes:

[0072] If it is detected that the memory slot with the I2C address of the second address does not have a memory module plugged in, then the fourth training program is executed. The fourth training program is used to perform memory training on the single plugged-in memory when the adapted memory frequency is greater than or equal to the preset frequency and the memory channel corresponds to a single memory slot; or,

[0073] If it is detected that both the memory slot with the I2C address of the second address and the memory slot with the I2C address of the first address have memory modules plugged in, then the fifth training program is executed. The fifth training program is used to perform memory training on each plugged-in memory when the adapted memory frequency is greater than or equal to the preset frequency and there is no memory slot in the memory channel that does not have a memory module plugged in.

[0074] Further, as Figure 7 shown, if it is detected that the memory slot with the I2C address of the second address (An+1) does not have a memory module plugged in, it can be determined that this is the case of a single-slot memory channel externally connected to a single memory module (that is, Figure 6 Case), then the fourth training program is executed to perform memory training on the single memory plugged in the single memory slot when the memory frequency adapted by the PCB is greater than or equal to the preset frequency and the memory channel corresponds to a single memory slot.

[0075] Further, if it is detected that the memory slot with the I2C address of the second address (An+1) has a memory module plugged in, and it is also detected that the memory slot with the I2C address of the first address (An) has a memory module plugged in, it can be determined that this is a situation where two memory modules are externally connected to a dual-slot memory channel. Then, the fifth training program is executed to perform memory training on each plugged-in memory corresponding to this memory channel when the memory frequency adapted by the PCB is greater than or equal to the preset frequency and there is no memory slot without a plugged-in memory in this memory channel.

[0076] It should be noted that in the embodiments of the present invention, the first training program, the third training program, the fourth training program, and the fifth training program do not need to consider the influence of empty slots (either there is no influence of empty slots or the influence of empty slots can be ignored). The embodiments of the present invention do not limit the specific training methods of the first training program, the third training program, the fourth training program, and the fifth training program. The first training program, the third training program, the fourth training program, and the fifth training program can be the same training program or different training programs. For example, a general memory training program can be adopted. By repeatedly trying to adjust the relevant timing parameter values in the memory controller, the delay parameters that can ensure that each signal has sufficient setup time before signal sampling and sufficient hold time after sampling, so that the signal can be correctly sampled, are tested. The optimal value is selected from these delay parameters that can be correctly sampled and configured into the memory controller to ensure that the memory device operates in the most stable state. Among them, the relevant timing parameter values include the delay value of the Addr (Address) signal or the Cmd (Command) signal with respect to the CLK (Clock), and the delay value of the DQ (Bi-directional Data) signal with respect to the DQS (Bi-directional Data Strobe).

[0077] In the embodiments of the present invention, the second training program needs to consider the influence of empty slots. The second training program includes optimized training code for empty slots, which is used to perform memory training on the basis of adjusting memory parameters to eliminate signal interference caused by empty slots and improve signal quality.

[0078] Further, when a memory channel corresponds to multiple memory slots and multiple memory modules are plugged in, the memory training can be performed on each memory module in sequence according to the above memory training method.

[0079] In summary, based on the preset rules, when the memory slots in the memory channel are not fully populated, the embodiments of the present invention set different memory training processes according to the memory frequency adapted to the memory channel, which can avoid the influence of the unpopulated memory slots on memory training, improve the effect of memory training, and further improve the system performance. In addition, based on the preset rules, the embodiments of the present invention ensure that the stubs of the memory traces only include the stubs generated by the pins of the inner memory slots themselves, and there will be no stubs between the inner memory slots and the outer memory slots, which can reduce the stubs of the memory traces and contribute to the smooth progress of memory training and the stability of the system. Moreover, the memory training method of the embodiments of the present invention does not require additional hardware costs to identify the positions of the unpopulated memory slots, and can save hardware costs while ensuring the effect of memory training.

[0080] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequences, because according to the embodiments of the present invention, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0081] Device embodiments

[0082] Referring to Figure 9 , a structural block diagram of an embodiment of a memory training device 900 of the present invention is shown, which is applied to an electronic device. The electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and satisfies the preset rule of inserting the outer memory slots first. The memory training device 900 may specifically include the following modules:

[0083] The first training module 901 is configured to, for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the first condition, execute a first training program, where the first training program is used to perform memory training on each populated memory and ignore the memory slots of the unpopulated memories, and the first condition is used to indicate that there is at least one unpopulated memory slot in the memory channel and the memory frequency adapted to the memory channel is less than a preset frequency;

[0084] A second training module 902, which is configured to, for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets a second condition, execute a second training program. The second training program is used to perform memory training on each inserted memory and perform signal compensation on the memory slots for uninserted memories. The second condition is used to indicate that there is at least one memory slot for an uninserted memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to a preset frequency.

[0085] Optionally, the I2C address of the two-wire serial bus of the memory slot is preset according to the adapted memory frequency and the position of the memory slot.

[0086] Optionally, the memory channel includes an inner memory slot and an outer memory slot, and the device further includes:

[0087] A first setting module, which is configured to, when the adapted memory frequency is less than the preset frequency, set the I2C address of the outer memory slot to a first address and set the I2C address of the inner memory slot to a second address;

[0088] A first setting module, which is configured to, when the adapted memory frequency is greater than or equal to the preset frequency, set the I2C address of the inner memory slot to a first address and set the I2C address of the outer memory slot to a second address.

[0089] Optionally, the first training module includes:

[0090] A first detection sub-module, which is configured to detect whether a memory is inserted into the memory slot with the I2C address of the second address;

[0091] A first determination sub-module, which is configured to, if it is detected that no memory is inserted into the memory slot with the I2C address of the second address, determine that the memory channel meets the first condition.

[0092] Optionally, the device further includes:

[0093] A third training module, which is configured to, if it is detected that a memory is inserted into the memory slot with the I2C address of the second address, execute a third training program. The third training program is used to perform memory training on each inserted memory when the adapted memory frequency is less than the preset frequency and there is no memory slot for an uninserted memory in the memory channel.

[0094] Optionally, the second training module includes:

[0095] A second detection sub-module, which is configured to detect whether a memory is inserted into the memory slot with the I2C address of the second address;

[0096] The third detection sub-module is used to detect whether the memory slot with the I2C address of the first address has a memory plugged in if it detects that the memory slot with the I2C address of the second address has a memory plugged in;

[0097] The second determination sub-module is used to determine that the memory channel meets the second condition if it detects that the memory slot with the I2C address of the first address does not have a memory plugged in.

[0098] Optionally, the device further includes:

[0099] The fourth training module is used to execute the fourth training program if it detects that the memory slot with the I2C address of the second address does not have a memory plugged in. The fourth training program is used to perform memory training on the single plugged-in memory when the adapted memory frequency is greater than or equal to the preset frequency and the memory channel corresponds to a single memory slot;

[0100] The fifth training module is used to execute the fifth training program if it detects that both the memory slot with the I2C address of the second address and the memory slot with the I2C address of the first address have memories plugged in. The fifth training program is used to perform memory training on each plugged-in memory when the adapted memory frequency is greater than or equal to the preset frequency and there is no memory slot without a plugged-in memory in the memory channel.

[0101] Optionally, the I2C address of the memory slot is set through a pull-up and pull-down resistor circuit.

[0102] Based on the preset rules, when the memory slots in the memory channel are not fully plugged in, different memory training processes are set according to the memory frequency adapted by the memory channel in the embodiments of the present invention. This can avoid the influence of the memory slots without plugged-in memories on memory training, improve the effect of memory training, and thus improve the system performance. In addition, based on the preset rules, the stub of the memory trace in the embodiments of the present invention only includes the stub generated by the pins of the inner memory slot itself, and there will be no stub between the inner memory slot and the outer memory slot, which can reduce the stub of the memory trace and contribute to the smooth progress of memory training and the stability of the system. Moreover, the memory training method in the embodiments of the present invention does not require additional hardware costs to identify the positions of the memory slots without plugged-in memories, and can save hardware costs while ensuring the memory training effect.

[0103] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0104] Refer to Figure 10 , which is a schematic structural diagram of a computing device provided by an embodiment of the present invention. As Figure 10As shown, the computing device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the memory access control method in the foregoing embodiments.

[0105] An embodiment of the present invention provides a non-transitory computer-readable storage medium, which is applied to an electronic device. The electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and satisfies a preset rule of inserting the outer memory slots first. When the instructions in the storage medium are executed by a program or a processor of a terminal, the electronic device can execute the steps of one or more of the memory training methods in the embodiments of the present invention.

[0106] The embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0107] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of an all-hardware embodiment, an all-software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the specified function in Figure 1 one or more of the flows Figure 1 or multiple flows and / or blocks

[0109] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the function in the flowFigure 1 one process or multiple processes and / or blocks Figure 1 the functions specified in one block or multiple blocks.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, so that a series of operation steps are executed on the computer or other programmable terminal devices to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal devices provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 in one block or multiple blocks.

[0111] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0112] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0113] The above has introduced in detail a memory training method and device, a device for memory training, and a storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A memory training method, characterized in that, Applied to an electronic device, the electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and meets the preset rule of inserting into the outer memory slot first. The method includes: For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the first condition, then execute the first training program. The first training program is used to perform memory training on the inserted memories and ignore the memory slots of the uninserted memories. The first condition is used to indicate that there is at least one memory slot of the uninserted memory in the memory channel and the memory frequency adapted to the memory channel is less than the preset frequency; For any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the second condition, then execute the second training program. The second training program is used to perform memory training on the inserted memories and perform signal compensation for the memory slots of the uninserted memories. The second condition is used to indicate that there is at least one memory slot of the uninserted memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to the preset frequency.

2. The method according to claim 1, characterized in that, The two-wire serial bus I2C address of the memory slot is pre-set according to the adapted memory frequency and the position of the memory slot.

3. The method according to claim 2, characterized in that, The memory slot includes an inner memory slot and an outer memory slot. Pre-setting the I2C address of the memory slot according to the adapted memory frequency and the position of the memory slot includes: When the adapted memory frequency is less than the preset frequency, set the I2C address of the outer memory slot as the first address, and set the I2C address of the inner memory slot as the second address; When the adapted memory frequency is greater than or equal to the preset frequency, set the I2C address of the inner memory slot as the first address, and set the I2C address of the outer memory slot as the second address.

4. The method according to claim 3, characterized in that, The recognizing that the memory channel meets the first condition includes: Detect whether the memory slot with the I2C address of the second address has a memory inserted; If it is detected that the memory slot with the I2C address of the second address has no memory inserted, then determine that the memory channel meets the first condition.

5. The method according to claim 4, characterized in that, The method further includes: If it is detected that the memory slot with the I2C address of the second address has a memory inserted, then execute the third training program. The third training program is used to perform memory training on the inserted memories when the adapted memory frequency is less than the preset frequency and there is no memory slot of the uninserted memory in the memory channel.

6. The method according to claim 3, characterized in that, The recognizing that the memory channel meets the second condition includes: Detect whether the memory slot with the I2C address of the second address has a memory inserted; If it is detected that the memory slot with the I2C address of the second address has a memory inserted, then detect whether the memory slot with the I2C address of the first address has a memory inserted; If it is detected that the memory slot with the I2C address of the first address has no memory inserted, then determine that the memory channel meets the second condition.

7. The method according to claim 6, characterized in that, The method further includes: If it is detected that no memory is inserted into the memory slot with the I2C address being the second address, the fourth training program is executed. The fourth training program is used to perform memory training on the single inserted memory when the adapted memory frequency is greater than or equal to the preset frequency and the memory channel corresponds to a single memory slot. If it is detected that memories are inserted into both the memory slot with the I2C address being the second address and the memory slot with the I2C address being the first address, the fifth training program is executed. The fifth training program is used to perform memory training on each inserted memory when the adapted memory frequency is greater than or equal to the preset frequency and there is no memory slot without inserted memory in the memory channel.

8. The method according to any one of claims 1 to 7, characterized in that, The I2C address of the memory slot is set through a pull-up and pull-down resistor circuit.

9. A memory training device, characterized in that, Applied to an electronic device, the electronic device includes at least one processor, each processor supports at least one memory channel, each memory channel corresponds to at least two memory slots, and satisfies the preset rule of inserting the outer memory slot first. The device includes: A first training module, for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the first condition, the first training program is executed. The first training program is used to perform memory training on each inserted memory and ignore the memory slots without inserted memory. The first condition is used to indicate that there is at least one memory slot without inserted memory in the memory channel and the memory frequency adapted to the memory channel is less than the preset frequency. A second training module, for any memory channel supported by any processor in the electronic device, if it is recognized that the memory channel meets the second condition, the second training program is executed. The second training program is used to perform memory training on each inserted memory and perform signal compensation for the memory slots without inserted memory. The second condition is used to indicate that there is at least one memory slot without inserted memory in the memory channel and the memory frequency adapted to the memory channel is greater than or equal to the preset frequency.

10. The device according to claim 9, characterized in that, The two-wire serial bus I2C address of the memory slot is preset according to the adapted memory frequency and the position of the memory slot.

11. The device according to claim 10, characterized in that, The memory channel includes an inner memory slot and an outer memory slot. The device further includes: A first setting module, for the case where the adapted memory frequency is less than the preset frequency, setting the I2C address of the outer memory slot as the first address and setting the I2C address of the inner memory slot as the second address. A first setting module, for the case where the adapted memory frequency is greater than or equal to the preset frequency, setting the I2C address of the inner memory slot as the first address and setting the I2C address of the outer memory slot as the second address.

12. The device according to claim 11, characterized in that, The first training module includes: A first detection sub-module, for detecting whether a memory is inserted into the memory slot with the I2C address being the second address. A first determination sub-module, for if it is detected that no memory is inserted into the memory slot with the I2C address being the second address, determining that the memory channel meets the first condition.

13. The device according to claim 12, characterized in that, The device further includes: A third training module, configured to execute a third training program if it is detected that a memory module has been inserted into a memory slot with an I2C address of a second address, where the third training program is used to perform memory training on each inserted memory module when the adapted memory frequency is less than a preset frequency and there is no memory slot without an inserted memory module in the memory channel.

14. The device according to claim 10, characterized in that, The second training module includes: A second detection sub-module, configured to detect whether a memory module has been inserted into a memory slot with an I2C address of a second address; A third detection sub-module, configured to detect whether a memory module has been inserted into a memory slot with an I2C address of a first address if it is detected that a memory module has been inserted into a memory slot with an I2C address of a second address; A second determination sub-module, configured to determine that the memory channel meets a second condition if it is detected that no memory module has been inserted into a memory slot with an I2C address of a first address.

15. The device according to claim 14, characterized in that, The device further includes: A fourth training module, configured to execute a fourth training program if it is detected that no memory module has been inserted into a memory slot with an I2C address of a second address, where the fourth training program is used to perform memory training on the single inserted memory module when the adapted memory frequency is greater than or equal to a preset frequency and the memory channel corresponds to a single memory slot; A fifth training module, configured to execute a fifth training program if it is detected that memory modules have been inserted into both the memory slot with an I2C address of a second address and the memory slot with an I2C address of a first address, where the fifth training program is used to perform memory training on each inserted memory module when the adapted memory frequency is greater than or equal to a preset frequency and there is no memory slot without an inserted memory module in the memory channel.

16. The device according to any one of claims 9 - 15, characterized in that, The I2C address of the memory slot is set through a pull-up and pull-down resistor circuit.

17. A computing device, characterized in that, It includes: A processor, a memory, a communication interface, and a communication bus, where the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the memory training method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the memory training method according to any one of claims 1 to 8 are implemented.

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