Method for managing computing units in heterogeneous computing and corresponding processor

Abstract

The disclosure provides a management method of a computing unit in heterogeneous computing and a corresponding processor, wherein a command management register and a command state register corresponding to each computing unit are provided for each computing unit, each bit of the command management register indicates whether each entry in the command cache of the computing unit corresponding to the bit is in an idle state, and each bit of the command state register indicates the execution state of each command in the computing unit corresponding to the bit. The scheme realizes the management of multiple computing units based on the command management register and the command state register, improves the execution efficiency of the computing command of the heterogeneous computing processor, and has good scalability.

Description

Technical Field

[0001] The present application relates to high-performance computing and heterogeneous computing, and in particular to a management method for computing units in heterogeneous computing and corresponding processors. Background Art

[0002] The statements in this section are merely intended to provide background information related to the technical solution of the present application to aid understanding, and they do not necessarily constitute prior art with respect to the technical solution of the present application.

[0003] Deep neural networks have become extremely popular in recent years. Their computational tasks are characterized by large amounts of data, computational complexity, and a wide variety of computational types. These computational tasks are typically organized in a directed acyclic data flow graph (DAG). These computational tasks can be executed serially or in parallel. Based on the graph's topology, these tasks are often assigned to multiple command lists. Computational tasks that require serial execution are typically assigned to the same command list to facilitate sequential hardware execution; whereas computational tasks that can be executed in parallel are typically assigned to multiple command lists to facilitate parallel execution and improve computational efficiency. Existing central processing units (CPUs), which execute instructions serially, are inefficient in executing parallel algorithms. This has led to the emergence of a heterogeneous computing architecture known as "CPU + hardware accelerator," in which hardware accelerators (also known as coprocessors) handle the bulk of the computational tasks, while the CPU (also known as the main processor) handles other non-computational tasks.

[0004] Among various hardware accelerators for deep neural networks, heterogeneous computing processors offer higher computing efficiency and lower power consumption than traditional graphics processing units (GPUs). These processors contain a variety of specialized hardware computing units specifically designed to accelerate computational tasks. However, the diverse nature of the computing units within heterogeneous processors, combined with their differing command execution characteristics, creates numerous challenges in managing these units.

[0005] It should be noted that the above content is only used to help understand the technical solution of this application and is not used as a basis for evaluating the prior art of this application. Summary of the Invention

[0006] The purpose of this application is to provide a method for managing computing units in heterogeneous computing and a heterogeneous computing processor, which realizes the management of multiple computing units in a simple and efficient manner and improves the execution efficiency of computing commands.

[0007] The above objectives are achieved through the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, a method for managing computing units in heterogeneous computing is provided, wherein each computing unit is provided with a corresponding command management register and a command status register, each bit of the command management register indicates whether each entry in the command cache of the corresponding computing unit is in an idle state, and each bit of the command status register indicates the execution status of each command in the corresponding computing unit; the method includes:

[0009] According to the type of command to be executed, determine the command management register corresponding to the computing unit suitable for executing the command of this type; select a command management register having a bit indicating an idle state from the determined command management registers, use the serial number of one of the bits indicating the idle state in the command management register as the serial number of the command to be executed and set the bit to indicate a non-idle state; send the command to be executed and its serial number to the computing unit corresponding to the selected command management register, and set the bit corresponding to the serial number in the command status register corresponding to the computing unit to indicate an unfinished state; and in response to receiving a command completion signal from the computing unit, set the bit corresponding to the serial number of the completed command in the command status register corresponding to the computing unit to indicate a completed state, and set the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit to indicate an idle state.

[0010] In some embodiments, selecting a command management register having bits indicating an idle state may include: identifying the number of bits indicating an idle state in the command management register by reading the value of the command management register; and selecting a command management register having the largest number of bits indicating an idle state.

[0011] In some embodiments, selecting the command management register having a bit indicating an idle state may include selecting the command management register having a bit indicating an idle state in a polling manner.

[0012] In some embodiments, the method may further include: setting the status of the computing unit to unavailable by setting the value of a corresponding command management register of the computing unit.

[0013] In some embodiments, the widths of the command management register and the command status register depend on the lengths of the command buffers of their corresponding computing units.

[0014] In some embodiments, the method may further include: in response to receiving a command completion signal from a computing unit, after a preset time period, setting the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit to indicate an idle state.

[0015] In some embodiments, the method may further include: recording a correspondence between the serial number of the command to be executed and the hardware command queue to which the command to be executed belongs.

[0016] In some embodiments, the method may further include: in response to receiving a command completion signal from the computing unit, searching the hardware command queue corresponding to the command according to the sequence number of the completed command, and feeding back a signal indicating completion of the command.

[0017] In some embodiments, the method may further include: continuously distributing multiple commands to be executed from the same hardware queue to each computing unit for processing.

[0018] In some embodiments, the method may further include: in response to receiving a command completion signal from a computing unit, determining whether the completed command still needs to wait for other commands; only when it is determined that the command does not need to wait for other commands, setting the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit to indicate an idle state.

[0019] In some embodiments, the method may further include: distributing, for commands to be executed from a plurality of hardware command queues, each command to be executed to a computing unit according to a preset priority.

[0020] According to a second aspect of an embodiment of the present application, a heterogeneous computing processor is provided, which includes a controller, multiple computing units of different types, a command management register and a command status register corresponding to each computing unit, wherein each bit of the command management register indicates whether each entry in the command cache of the corresponding computing unit is in an idle state; each bit of the command status register indicates the execution status of each command in the corresponding computing unit, and the controller is configured to execute the method described in the first aspect above.

[0021] The technical solutions of the embodiments of the present application may have the following beneficial effects:

[0022] A computational unit management method based on command management registers and command status registers is proposed. This method eliminates the need for complex software programming and avoids inefficient waiting due to accessing external storage. Furthermore, it implements a simple, non-blocking command queue execution method, improving the efficiency of computing command execution in heterogeneous computing processors. Furthermore, this register-based computational unit management mechanism improves the robustness of heterogeneous computing processors and offers good scalability.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0025] Figure 1 A schematic diagram of the structural modules of a heterogeneous computing processor provided in an embodiment of the present application.

[0026] Figure 2 A schematic diagram of the structural modules of a front-end control engine in a heterogeneous computing processor provided in an embodiment of the present application.

[0027] Figure 3 A flowchart of a computing unit management method in heterogeneous computing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of this application more clearly understood, the present application is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the embodiments described are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0030] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0032] In a heterogeneous computing architecture, the main processor can assign computing tasks to be executed into multiple command lists and instruct corresponding coprocessors to execute these computing tasks. These command lists can be stored in memory for the coprocessors to read, parse, and execute. In an embodiment of the present application, a heterogeneous computing processor is used as a coprocessor to execute the command list prepared by the main processor.

[0033] Figure 1 A schematic diagram of the structural modules of a heterogeneous computing processor provided in an embodiment of the present application.

[0034] This heterogeneous computing processor includes at least two different types of computing units, such as a general-purpose image processing unit, a computing unit dedicated to processing matrix addition and multiplication, a computing unit dedicated to vector operations and derivative operations, and so on. Each computing unit has a command cache that can receive multiple commands, thereby avoiding the waste of computing resources due to gaps in command transmission. The command cache includes multiple entries, and each received command is stored in a corresponding entry. Due to the different command receiving capabilities of different computing units, the number of entries in the command cache of each computing unit (which can be understood as the depth, length or size of the command cache) is also different.

[0035] The heterogeneous computing processor also includes a host interface, a front-end control engine, a command network, and a memory interface. The host interface is primarily used for command or data communication between the heterogeneous processor and the main processor. The memory interface is used for communication between the heterogeneous computing processor and the memory. The front-end control engine connects to each computing unit via the command network and distributes the list of commands to be executed to each computing unit for execution. The command network can be implemented in the form of an on-chip data exchange network, which is not limited in this document.

[0036] In heterogeneous computing processors, the management of different types of computing units faces many challenges. For example, different types of computing units may have different capabilities for receiving commands and different orders for executing commands, and need to be scheduled according to the characteristics of each computing unit's execution of commands; parallel execution command queues may call the same computing unit at the same time, and the competition relationship between command queues needs to be handled; when there is a need for multiple computing units to collaboratively process computing tasks, the waiting relationship between the computing units needs to be handled. In the embodiments of the present application to be elaborated in detail below, a computing unit management method for heterogeneous computing processors is provided, which can improve the execution efficiency of computing commands of heterogeneous processors, reduce the management complexity of computing units, and has good scalability.

[0037] Figure 2 This is a schematic diagram of the structural modules of a front-end control engine in a heterogeneous computing processor provided in an embodiment of the present application. The front-end control engine can be used to read and parse command lists and distribute commands based on the parsing results.

[0038] like Figure 2 As shown, the front-end control engine includes a hardware queue scheduling module, a computing management module, and multiple hardware command queues that can be executed in parallel. The hardware queue scheduling module can distribute the command lists to be executed to each hardware command queue. Since the number of command lists created and stored in the memory by the main processor according to the corresponding computing tasks may be greater than the number of hardware command queues in the heterogeneous computing processor, the hardware queue scheduling module needs to schedule the hardware command queues, for example, sending the command lists to the idle hardware command queues through a certain scheduling strategy. After each hardware command queue parses the received commands, it distributes the commands to the computing units via the computing management module. Each hardware command queue can also independently read the command list prepared by the software from the memory, and then parse the commands and distribute the commands to the computing management module. The computing management module can send the commands to different computing units for processing based on the type of command and the execution status of the commands of each computing unit.

[0039] In an embodiment of the present application, the computing management module monitors or detects the command execution status of each computing unit by setting two registers for each computing unit. One register is used to record the command cache status of the computing unit and can therefore be called a command management register. The other register is used to record the command execution status of the computing unit and can therefore be called a command status register.

[0040] In this embodiment, each bit in the command management register corresponding to each computing unit indicates whether an entry in the command cache of the computing unit is idle. For example, if the value is 1, it indicates that the entry is not allocated and a computing command can be received; if the value is 0, it indicates that the entry is occupied and a computing command cannot be received, and vice versa.

[0041] Hereinafter, each bit in the command management register is described by taking the example that a value of 1 indicates idle and a value of 0 indicates occupied.

[0042] The number of bits in the command management register (i.e., the width of the register) depends on the depth of the command cache of the computing unit. Since different computing units have different capabilities of receiving commands, the depths of the command caches of the computing units are different, and accordingly the widths of the command management registers corresponding to the computing units can also be different. If the values of all the bits in the command management register corresponding to a computing unit are 1, it indicates that all the entries in the command cache of the computing unit are idle and the computing unit currently has the maximum capability of receiving commands; if the values of all the bits in the command management register are 0, it indicates that the computing unit cannot receive new commands. In this way, when the computing management module sends a computing command to the computing units, it can first determine the computing units capable of processing the type of the computing command based on the type of the computing command; then it queries the command management registers corresponding to the computing units of the corresponding type and selects a computing unit currently capable of receiving commands to send the computing command to the computing unit. If all the computing units of the type cannot receive new commands, the computing management module can block the computing command, but subsequent computing commands not belonging to the type can still be sent, so that the computing units still having computing resources can receive new computing commands and continue to run, and the command network is not blocked, which can improve the execution efficiency of the heterogeneous computing processor.

[0043] Continuing to refer to Figure 2 The command state register corresponding to each computing unit can have the same width as the command management register described above. Each bit in the command state register corresponds to the execution state of a computing command of the computing unit and is used to record the completion of the command. For example, when the value is 1, it indicates that the computing command has been completed, and when the value is 0, it indicates that the computing command is being executed or has not been started, and vice versa.

[0044] Hereinafter, each bit in the command state register is described by taking the example that a value of 1 indicates that the command has been completed and a value of 0 indicates that the command has not been completed or has not been started. In one embodiment, the initial values of all the bits in the command state register are 0, and when a computing command is completed, the corresponding bit is set to 1.

[0045] By the cooperation of the command state registers and the command management registers, the non-blocking execution or out-of-order execution of the same hardware command queue can be achieved. That is, the hardware command queue does not need to be blocked after transmitting a command in the queue order, and then transmit the next command after the completion of the command. In the embodiment of the present application, each hardware command queue can continuously distribute several commands to the computing unit according to the state of the command management register of the computing unit without blocking immediately, thereby reducing the command waiting time and improving the execution efficiency of the command. The execution of each command is recorded in the corresponding command state register of the computing unit. When a hardware command queue needs to wait for the completion of a command, it only needs to query the corresponding bit in the corresponding command state register to obtain the relevant information, without additional storage or tracking. In addition, the order of command completion in the computing unit or between computing units can also be different. Since the command state register can track each transmitted command, the out-of-order completion of the transmitted command is also allowed, further improving the execution efficiency of the computing command of the heterogeneous computing processor.

[0046] In this embodiment, the computing management module sets the command management register and the command state register corresponding to each computing unit. These command management registers and command state registers are visible to all hardware command queues, that is, all computing units of the heterogeneous processor share all hardware command queues, and the computing management module can directly allocate according to the command management register of each computing unit. For example, when two hardware command queues compete for the same computing unit, the computing management module can ensure that each computing command of the computing unit can be executed normally and each command in the command cache of the computing unit cannot be changed or replaced by the command of the other queue by setting the command management register and the command state register of the computing unit for each command distributed to the computing unit. It can be seen that the command state register and the command management register here are somewhat similar to the "synchronization lock" in hardware form, which simply and conveniently solves the problem of different hardware command queues competing for the same computing unit. If the problem of different hardware command queues competing for the same computing unit is solved by software programming, each hardware command queue often needs to repeatedly query the memory to obtain the command execution status of the computing unit. Moreover, it is difficult to predict the real-time execution of each command through software programming, so unnecessary synchronization waiting often occurs, wasting hardware computing resources. In addition, the software programming method is often not conducive to the efficiency of the hardware, because the synchronization instruction used to synchronize between each command queue itself has overhead, and most synchronization instruction implementations are achieved by reading and writing the flag signal in the external memory, which also needs to repeatedly read the memory, thereby introducing a lot of memory access delay or waiting, affecting the execution efficiency of the computing command.

[0047] In some embodiments, the state of a computing unit can also be set by setting the value of the corresponding command management register of the computing unit in response to commands or configuration information from upper-level software or a host processor. This design not only reduces the complexity of computing unit management but also improves the robustness of the heterogeneous computing processor. For example, if some computing units are unavailable due to chip yield issues, the initial value of the command management register of these computing units will be set to all 0s, indicating that no commands can be assigned to these computing units. This simple design ensures that the heterogeneous computing processor chip can continue to operate even when some computing units are unavailable. In addition, this register setting method also provides good scalability for the heterogeneous computing processor. When it is necessary to add new types of computing units or change the number of computing units, it is only necessary to set or adjust the command management register and command status register corresponding to the computing management unit. This application does not limit the chip yield detection method; external hardware detection methods or external software detection methods can be used. The chip yield detection method should not be construed as a limitation of this application.

[0048] The following combination Figure 3 The flowchart shown describes the management process of the computing management module for multiple computing units in more detail.

[0049] In step S1, the computing management module receives a command to be executed from the hardware command queue. Since heterogeneous computing processors usually contain multiple computing units of different types. Therefore, the computing management module first detects the command management register corresponding to the computing unit suitable for executing this type of command according to the type of command to be executed received, so as to determine the idle state of the command cache of these computing units. As mentioned above, each bit of the command management register indicates whether each entry in the command cache of the corresponding computing unit is in an idle state. Taking the example of a value of 1 indicating idle and a value of 0 indicating occupied, by reading the value of the command management register, it is possible to easily know which bits are 1 and which bits are 0, and based on this, the number of idle entries in the command cache of the computing unit can be counted, that is, how many commands the computing unit can still receive.

[0050] Heterogeneous computing processors usually include multiple hardware command queues. In some embodiments, the computing management module can also be configured to arbitrate requests for allocation of computing units from multiple hardware command queues according to a certain algorithm, preferentially select one of the hardware command queues to serve it according to the arbitration algorithm, and distribute the commands in the hardware command queue to the computing units. In one embodiment, such an arbitration algorithm can be a polling algorithm to ensure fairness in the execution of commands for each hardware command queue. In another embodiment, such an arbitration algorithm can be a greedy algorithm to ensure that the commands of a certain hardware command queue are executed first. In another embodiment, the computing management module can schedule according to the pre-set weights of each hardware command queue, which not only ensures that the scheduling has a certain priority, but also enables all queue commands to be sent to the computing unit, thereby preventing a queue from starving due to permanent blocking.

[0051] As mentioned above, the computing management module can determine the idle state of the command cache of the corresponding computing unit by reading the value of the command management register of the computing unit. In step S2, the computing management module can select one of the command management registers with a bit indicating the idle state and use the computing unit corresponding to the command management register as the target computing unit for the executed command. The serial number of the command management register is the serial number of the target computing unit.

[0052] In one embodiment, the computing management module may select a command management register based on the number of free entries in the command cache of the computing unit (i.e., the number of bits indicating the idle state in the command management register). For example, the computing unit with the most free entries may be preferentially selected to ensure load balancing among the computing units.

[0053] In another embodiment, the calculation management module may also adopt a simple polling allocation method to avoid the logic and cycle generated by comparing the number of bits indicating the idle state in each command management register.

[0054] For the selected command management register, the computing management module assigns a bit indicating an idle state to the command to be executed. For example, the sequence number of the bit in the command management register is used as the sequence number of the command to be executed (also known as the command identification number, or command ID), and the bit is set to indicate a non-idle state. As mentioned above, in the command management register corresponding to the computing unit, each bit indicates the state of an entry in the command cache of the computing unit, that is, each bit corresponds to a command cache entry of the computing unit. Therefore, in this embodiment, the sequence number of the bit in the command management register is used as the sequence number for identifying the command to be executed, which helps to simplify the subsequent setting of the cache and execution status of the command. Since the sequence number of this bit is the sequence number of the entry that the command to be executed will occupy in the command cache of the target computing unit, it can be directly saved in the corresponding entry of the command cache according to the sequence number of the command to be executed received. In addition, setting the bit to indicate a non-idle state here can ensure that the entry will not be occupied by other commands before the command cache is released. If the current command has been executed and the bit corresponding to the command has been set to indicate the idle state, the serial number of the bit in the command management register can be assigned to a new command to be executed. That is, by querying or accessing the value of each bit in the command management register, it can be known whether the serial number (or identifier) ​​of the corresponding bit in the command management register is currently allowed to be assigned to the next command to be executed. This method is simple and efficient, and can save additional access query process.

[0055] In some embodiments, the computing management module may further record the correspondence between the serial number assigned to the command to be executed and the hardware command queue to which the command to be executed belongs, so as to subsequently feed back the execution status of the command to the corresponding hardware queue.

[0056] Continue to refer Figure 3 In step S3, the computing management module sends the command to be executed and its serial number to the computing unit corresponding to the selected command management register through the command network. The computing unit will save the received command and serial number in the corresponding entry of its command cache. While sending the command, the computing management module can directly set the bit corresponding to the serial number in the command status register corresponding to the computing unit to indicate an unfinished state based on the serial number of the command to be executed, so as to prevent the subsequent computing management module from misjudging the command execution status due to the previous operation not clearing the status in time. The computing unit reads a computing command from its command cache and executes it. When the command execution is completed, the computing unit will return the command completion signal and the serial number of the completed command to the computing management module through the command network.

[0057] In step S4, in response to receiving the command completion signal from the computing unit, the computing management module sets the bit corresponding to the serial number of the completed command in the command status register corresponding to the computing unit to indicate the completed state to indicate that the computing command has been completed.

[0058] In one embodiment, the computing management module can also feed back command completion information to the corresponding hardware command queue. In such an embodiment, when assigning a sequence number to a command to be executed, the computing management module can record which hardware command queue the command sequence number belongs to. In this way, upon receiving a command completion signal, the relevant information can be returned to the corresponding hardware command queue.

[0059] In another embodiment, the computing management module may not feed back the command completion information to the corresponding hardware command queue. When the execution status of a command needs to be queried, for example, when the hardware command queue is blocked or synchronization between commands is required, the computing management module may proactively query the corresponding command status register, thereby saving hardware register resources.

[0060] After receiving the command completion signal from the computing unit, the computing management module can also set the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit to indicate an idle state, thereby releasing the corresponding entry in the command cache of the computing unit.

[0061] As an implementation method, the computing management module can immediately modify the corresponding bit of the command management register to indicate an idle state after receiving the command completion signal, thereby quickly releasing the command cache entry space of the computing unit to allow subsequent new commands to continue to be executed.

[0062] Taking into account the possible synchronization operations between commands, the computing management module can also modify and update the bits of the command management register in the following manner after receiving the command completion signal:

[0063] As another embodiment, the computing management module may not modify the corresponding bit of the command management register immediately after receiving the command completion signal, but may choose to delay for a period of time before modifying it to indicate an idle state (that is, in response to receiving the command completion signal from the computing unit, after a preset time period, the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit is set to indicate an idle state). This is to take into account the possible synchronization operations between commands. When a command is completed, it is necessary to wait for other commands. At this time, the serial number of the completed command needs to be retained in the command management register for a period of time so that other commands can judge the completion status of the command by querying the corresponding command status register. If synchronization is not taken into account and the serial number of the completed command is directly modified in the corresponding bit of the command management register to indicate an idle state, then the serial number will most likely be assigned to a subsequent new command, and the corresponding bit in the command status register will also be reset, resulting in the inability to query the execution status of the command.

[0064] As another embodiment, after receiving a command completion signal, the computation management module can determine whether the completed command needs to wait for other commands. Only when it is determined that the command does not need to wait for other commands, the computation management module sets the bit corresponding to the sequence number of the completed command in the command management register corresponding to the computation unit to indicate an idle state. Compared to the method of modifying the bit state after waiting for a fixed period of time, this embodiment can adapt to a wider range of synchronous operation scenarios and has greater flexibility.

[0065] In the above embodiments, although the hardware queue scheduling module and the computing management module are introduced in the form of independent modules, it should be understood that the above modules or the circuits implementing the above modules can be implemented as part of the control circuit, control logic or controller of the heterogeneous computing processor, or the control circuit, control logic or controller of the heterogeneous computing processor can be configured to perform the functions, steps or methods described above in conjunction with the hardware queue scheduling module and the computing management module. Based on the same inventive concept, the embodiment of the present application also provides a heterogeneous computing processor. The heterogeneous computing processor includes a controller, a plurality of different types of computing units, and a command management register and a command status register corresponding to each computing unit as described above. The controller is configured to implement the functions described above in conjunction with the hardware queue scheduling module and the computing management module, or to perform the management process of multiple computing units in the heterogeneous computing described in conjunction with the above embodiments. For other details about the heterogeneous computing processor, please refer to the relevant description above, which will not be repeated here.

[0066] Reference throughout this specification to "various embodiments", "some embodiments", "one embodiment", or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrases "in various embodiments", "in some embodiments", "in one embodiment", or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It has to be emphasized that, according to a general principle of the patent law, neither the description nor the examples are to be understood as restricting the scope of the application. In particular, a feature described "in an embodiment" can be combined with features described in other embodiments, unless otherwise implicitly or explicitly excluded.

[0067] As used in this specification and claims, the terms "for example", "for instance", "such as", or "like", and the verbs "comprising", "having", "including", and their conjugates, do not exclude other possible features. Also, the use of these terms does not limit the features listed thereafter to the list set forth directly above. The term "comprising" can mean "including", "containing", "involving", "having" or "characterized by", "characterized by", "characterized by", "including", "containing", "involving", "having" or "characterized by". Any term or expression that can be used in this specification and / or claims (including, for example, non-singular forms of expressions) can be used interchangeably with any other term or expression, including singular forms of expressions. The use herein of "one" or "the" to refer to an element or an element by an indication of a related sole or single element does not exclude the existence of more than one of such one or said element or the existence of additional or other elements.

[0068] Although the present application has been described with reference to the above embodiments, the application is not limited to the embodiments described above, but various changes and modifications can be made without departing from the scope of the application.

Claims

1. A method for managing computing units in heterogeneous computing, wherein each computing unit is provided with a corresponding command management register and a command status register, each bit of the command management register indicating whether each entry in the command cache of the corresponding computing unit is in an idle state, and each bit of the command status register indicating the execution status of each command in the corresponding computing unit; the method comprising: Determining, according to the type of command to be executed, command management registers corresponding to one or more computing units suitable for executing the command of the type; Selecting one of the determined command management registers having a bit indicating an idle state, and setting the computing unit corresponding to the command management register as the target computing unit of the command to be executed; using the sequence number of the bit indicating the idle state in the selected command management register as the sequence number of the command to be executed, the sequence number also indicating the sequence number of the entry that the command to be executed will occupy in the command cache of the target computing unit; and setting the bit to indicate a non-idle state; Sending the command to be executed and its sequence number to the computing unit corresponding to the selected command management register, and setting the bit corresponding to the sequence number in the command status register corresponding to the computing unit to indicate an unfinished state; In response to receiving a command completion signal from a computing unit, the bit corresponding to the serial number of the completed command in the command status register corresponding to the computing unit is set to indicate a completed state, and the bit corresponding to the serial number of the completed command in the command management register corresponding to the computing unit is set to indicate an idle state.

2. The method according to claim 1, wherein selecting a command management register having a bit indicating an idle state comprises: Identifying the number of bits in the command management register indicating an idle state by reading a value of the command management register; The command management register having the largest number of bits indicating the idle state is selected.

3. The method according to claim 1 , wherein selecting a command management register having a bit indicating an idle state comprises: The command management register having a bit indicating an idle state is selected in a polling manner. 4 . The method according to claim 1 , further comprising setting the status of the computing unit to unavailable by setting the value of a corresponding command management register of the computing unit. 5 . The method according to claim 1 , wherein the widths of the command management register and the command status register depend on the lengths of the command buffers of the corresponding computing units.

6. The method according to claim 1, further comprising: The corresponding relationship between the serial number of the command to be executed and the hardware command queue to which the command to be executed belongs is recorded.

7. The method according to claim 6, further comprising: In response to receiving a command completion signal from the computing unit, the hardware command queue corresponding to the completed command is searched according to the sequence number of the completed command, and a signal indicating completion of the command is fed back to the hardware command queue.

8. The method according to claim 6, further comprising: Multiple commands to be executed from the same hardware command queue are continuously distributed to each computing unit for processing.

9. The method according to any one of claims 1 to 8, further comprising: In response to receiving a command completion signal from the computing unit, determining whether the completed command still needs to wait for other commands; Only when it is determined that the command does not need to wait for other commands, the bit corresponding to the sequence number of the completed command in the command management register corresponding to the computing unit is set to indicate an idle state.

10. The method according to any one of claims 1 to 8, further comprising: In response to receiving a command completion signal from a computing unit, after a preset time period, a bit corresponding to the sequence number of the completed command in a command management register corresponding to the computing unit is set to indicate an idle state. 11 . The method according to claim 1 , further comprising distributing, for commands to be executed from a plurality of hardware command queues, each command to be executed to a computing unit according to a preset priority.

12. A heterogeneous computing processor, comprising a controller, multiple computing units of different types, a command management register and a command status register corresponding to each computing unit, wherein each bit of the command management register indicates whether each entry in the command cache of the corresponding computing unit is in an idle state; each bit of the command status register indicates the execution status of each command in the corresponding computing unit, and the controller is configured to execute the method described in any one of claims 1 to 11.

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