Sensing circuit and its source driver

Abstract

This disclosure discloses a sensing circuit and a source driver including the sensing circuit, which can reduce the impact of panel load on the performance of the integrator and reduce the chip area by eliminating the feedback capacitor of the integrator. The sensing circuit can convert the input current received from the display panel into an output current with linearity and a current quantity less than the input current.

Description

Technical Field

[0001] Various implementations generally relate to display devices, and more specifically, to sensing circuits for sensing pixel signals of a display panel and source drivers including the sensing circuits. Background Technology

[0002] Typically, a display device includes a display panel, a display driver, and a timing controller.

[0003] Display driving devices may include source drivers integrated as a chip. Considering the size and resolution of the display panel, display driving devices may include multiple source drivers. These source drivers convert digital image data provided by a timing controller into source signals and provide these source signals to the display panel.

[0004] The source driver senses the pixel signals of the display panel and converts the pixel signals into digital data.

[0005] According to conventional technology, a source driver may include sensing circuitry that senses pixel signals, and each sensing circuit may include an integrator that converts input current into voltage.

[0006] However, the integrator of the source driver according to conventional technology has different performance depending on the panel load and requires feedback capacitors for each of the multiple channels.

[0007] Therefore, it is necessary to reduce the impact of panel load on the performance of the integrator and reduce the chip area of ​​the sensing circuit and source driver by eliminating the feedback capacitor of the integrator.

[0008] Furthermore, the sensing circuit and source driver require sampling capacitors for sampling pixel signals. Therefore, in order to reduce the chip area of ​​the sensing circuit and source driver, sampling capacitors with smaller dimensions need to be implemented. Summary of the Invention

[0009] Various implementations involve sensing circuits and source drivers including such sensing circuits, which can reduce the impact of panel load on the performance of the integrator and reduce chip area by eliminating the feedback capacitor of the integrator.

[0010] Furthermore, various implementations involve sensing circuits and source drivers including such sensing circuits, which can reduce chip area by using small-sized sampling capacitors to reduce the amount of current used for sampling.

[0011] In one embodiment, the sensing circuit may include an amplifier circuit configured to receive an input current from the display panel, wherein the amplifier circuit converts the input current into an output current with linearity, and the amount of the output current is less than the amount of the input current.

[0012] In one embodiment, the source driver may include: a sensing circuit configured to output a sampled voltage by sensing an input current received from a display panel; a global amplifier configured to output an amplified signal by amplifying the sampled voltage; and an analog-to-digital converter configured to convert the amplified signal into digital data. The sensing circuit includes an amplifier circuit and a sampling circuit. The amplifier circuit is configured to convert the input current into an output current with linearity, and the magnitude of the output current is less than the magnitude of the input current. The sampling circuit is configured to output a sampled voltage by sampling the output current.

[0013] As described above, by including an amplifier circuit that converts the input current into the output current, the impact of panel load on the performance of the integrator can be reduced, and the chip area can be reduced by eliminating the feedback capacitor of the integrator.

[0014] Furthermore, compared to conventional technologies, the reference voltage of the amplifier circuit can be set to a lower level.

[0015] Furthermore, since the amplifier circuit is configured to output a current less than the input current, the sampling capacitor used to sample the output current can be designed to have a small capacitance. That is, a small-area sampling capacitor can be used to implement the sensing circuit and source driver, thus reducing the chip area.

[0016] Furthermore, it can accurately sense the signal of pixels, regardless of whether the number of multiple channels increases. Attached Figure Description

[0017] Figure 1 This is a block diagram of a sensing circuit and a source driver including the sensing circuit according to an embodiment.

[0018] Figure 2 This is a circuit diagram of the sensing circuit according to the implementation method.

[0019] Figure 3 yes Figure 1 and Figure 2 The circuit diagram of the amplifier circuit shown is shown.

[0020] Figure 4 This is a timing diagram of the sensing circuit according to the implementation method. Detailed Implementation

[0021] This disclosure discloses a sensing circuit and an embodiment of a source driver including the sensing circuit, which can reduce the impact on the performance of the integrator according to the load of the display panel and reduce the chip area by eliminating the feedback capacitor of the integrator.

[0022] In this implementation, multiple channels can be connected to the sensing lines of the display panel, and the input current received through the channels can be defined as a pixel signal for detecting pixel characteristics. For example, pixel characteristics may include the threshold voltage of the driving transistor and the organic light-emitting diode, mobility, etc.

[0023] In an implementation, each of the plurality of channels may include sensing circuitry, and for ease of explanation, the sensing circuitry of one channel will be described.

[0024] In implementation, terms such as first and second can be used to identify various components. These components are not limited by terms such as first and second.

[0025] Figure 1 This is a block diagram of a sensing circuit 10 and a source driver 100 including the sensing circuit 10 according to an embodiment.

[0026] refer to Figure 1 The display device may include a display panel 200 and a source driver 100.

[0027] The display panel 200 may include pixels arranged in a matrix.

[0028] Each pixel may include an organic light-emitting diode (OLED), a storage capacitor (Csc), a driving transistor (Qd), a gate transistor (Qg), and a sensing transistor (Qs).

[0029] Vdata represents the driving voltage used to control light emission and is supplied to the drain of the gate transistor Qg, while Vgate represents the gate signal used to operate the gate transistor Qg. Therefore, the gate transistor Qg can switch the transmission of the driving voltage Vdata to the gate of the driving transistor Qd via the gate signal Vgate.

[0030] PVDD represents a constant voltage and is supplied to the drain of the driving transistor Qd. Therefore, the driving transistor Qd can control the amount of current supplied to the organic light-emitting diode (OLED) through the constant voltage PVDD based on the level of the driving voltage Vdata applied to the gate of the driving transistor Qd through the gate transistor Qg.

[0031] Vsen represents the sensing control signal used to control the operation of the sensing transistor Qs. Therefore, the sensing transistor Qs can provide an input current to the sensing circuit 10 through the panel load, corresponding to the voltage charged into the node between the driving transistor Qd and the organic light-emitting diode OLED, according to the sensing control signal Vsen.

[0032] Each pixel of the display panel 200 is connected to the sensing circuit 10 of the source driver 100 via a panel load. It can be understood that the panel load applied to each pixel represents an equivalent capacitor assembly Cp and a resistor assembly Rp formed on the sensing line configured between the sensing transistor Qs and the sensing circuit 10.

[0033] The source driver 100 may include a sensing circuit 10, a global amplifier GA, and an analog-to-digital converter ADC.

[0034] The sensing circuit 10 can be configured to correspond to each of a plurality of channels. A channel means that each panel load (i.e., sensing line) of the display panel 200 is connected to the sensing circuit 10. The source driver 100 may include a plurality of channels, and the sensing circuit 10 can be configured for each of the plurality of channels.

[0035] The sensing circuit 10 can receive an input current Iin from a pixel of a corresponding channel of the display panel 200. The sensing circuit 10 is configured to convert the input current Iin into an output current Iout with linearity. The resulting output current Iout has a smaller current amount than the input current Iin.

[0036] The sensing circuit 10 can sample the output current Iout of the channel and output a sampled voltage Vsam to the global amplifier GA. The sensing circuit 10 corresponding to multiple channels can be configured to output the sampled voltage Vsam sequentially, and for this purpose, a multiplexer (not shown) can be configured between the sensing circuit 10 and the global amplifier GA.

[0037] The global amplifier GA can amplify the sampling voltage Vsam sequentially output from the sensing circuit 10, and can output the amplified signal to the analog-to-digital converter ADC.

[0038] An analog-to-digital converter (ADC) can convert an amplified signal into digital data and provide the digital data to a timing controller (not shown). The timing controller can use the digital data to generate compensation data corresponding to the pixel characteristics, and can use the compensation data to correct the image data.

[0039] Figure 2 This is a circuit diagram of the sensing circuit 10 according to the embodiment. Figure 3 yes Figure 1 and Figure 2 The circuit diagram of the amplifier circuit shown is shown.

[0040] refer to Figure 2The sensing circuit 10 may include an amplifier circuit 20 and a sampling circuit 30. The amplifier circuit 20 is configured to convert the input current Iin into an output current Iout with linearity, and to output an output current Iout with a current magnitude less than the input current Iin. The sampling circuit 30 is configured to sample the output current Iout to output a sampled voltage Vsam.

[0041] First, refer to Figure 3 Amplifier circuit 20 is described in detail.

[0042] The amplifier circuit 20 may include an input and load stage circuit 22, an output stage circuit 24, and a current mirror circuit 26.

[0043] The input and load stage circuit 22 may include a first input terminal Vin(-) for receiving input current Iin and a second input terminal Vin(+) for receiving a first reference voltage Vpre.

[0044] The input and load stage circuit 22 can output a pull-up signal UP and a pull-down signal DN in response to the input current Iin and the first reference voltage Vpre. Specifically, the input and load stage circuit 22 is configured to generate the pull-up signal UP and the pull-down signal DN corresponding to the potential difference between the first input terminal Vin(-) and the second input terminal Vin(+).

[0045] The output stage circuit 24 is configured to output a first output voltage Vout corresponding to the input current Iin and a source current corresponding to a first scale of the input current Iin in response to the pull-up signal UP and the pull-down signal DN. For this purpose, the output stage circuit 24 may include a first output stage circuit 24a and a second output stage circuit 24b.

[0046] The first output stage circuit 24a can output a first output voltage Vout corresponding to the input current Iin in response to the pull-up signal UP and the pull-down signal DN. For example, the first output stage circuit 24a may include a PMOS transistor P1 and an NMOS transistor N1 connected in series between a terminal of the first power supply voltage VDD and a terminal of the ground voltage. The node between the PMOS transistor P1 and the NMOS transistor N1 may be defined as a first output terminal OT1 that outputs the first output voltage Vout, and the first output terminal OT1 of the first output stage circuit 24a may be interconnected with the first input terminal Vin(-) of the input and load stage circuit 22.

[0047] The second output stage circuit 24b can respond to the pull-up signal UP and the pull-down signal DN to form a source current corresponding to the input current Iin and flowing through the current path Ipath. For example, the second output stage circuit 24b may include a PMOS transistor P2 and an NMOS transistor N2 connected in series between the terminal of the first power supply voltage VDD and the terminal of the ground voltage. The node between the PMOS transistor P2 and the NMOS transistor N2 may be defined as the node ND of the output source current.

[0048] The second output stage circuit 24b can be configured to have a 1:1 replication ratio with the first output stage circuit 24a. The replication ratio can be understood as the ratio between the amount of current flowing according to the channel ratio of the transistors included in the first output stage circuit 24a and the second output stage circuit 24b.

[0049] In other words, it can be understood that the second output stage circuit 24b outputs the source current by replicating the current corresponding to the input current Iin of the first output stage circuit 24a at a 1:1 replication ratio in response to the pull-up signal UP and the pull-down signal DN. Therefore, it can be understood that the input current Iin, the current of the first output stage circuit 24a, and the source current are defined as having current quantities within a first scale and having the same current quantity.

[0050] The current mirror circuit 26 is configured to replicate the source current flowing through the current path Ipath from node ND of the second output stage circuit 24b, and thereby output a second-scaled output current Iout, which has a smaller current magnitude than the first-scaled current. Through replication by the output stage circuit 24 and the current mirror circuit 26, the output current Iout can be output with linearity relative to the input current Iin. For example, the current mirror circuit 26 can replicate the output current Iout relative to the source current of the second output stage circuit 24b at a preset replication ratio of 1 / N (where N is a positive real number greater than 1).

[0051] The current mirror circuit 26 may include PMOS transistors P3 and PMOS transistor P4. PMOS transistor P3 is configured between the terminal of the second power supply voltage VCC and node ND, and PMOS transistor P4 is configured between the terminal of the second power supply voltage VCC and the second output terminal OT2. The gate terminals of PMOS transistors P3 and PMOS transistor P4 may be interconnected and connected to node ND.

[0052] In the current mirror circuit 26, PMOS transistors P3 and P4 can have an N:1 channel ratio. Therefore, the current mirror circuit 26 can have an N:1 current replication ratio. The second power supply voltage VCC of the current mirror circuit 26 can be set to a level lower than the first power supply voltage VDD of the output stage circuit 24.

[0053] With the above configuration, when the source current flows through the second output stage circuit 24b, the current mirror circuit 26 can output an output current Iout corresponding to 1 / N of the source current through the current of the PMOS transistor P3 of the current mirror circuit 26 via the PMOS transistor P4 and the second output terminal OT2.

[0054] Return to reference Figure 2 The sampling circuit 30 can sample the output current Iout output from the amplifier circuit 20 and can output the sampling voltage Vsam.

[0055] The sampling circuit 30 may include a first switch SWsam, a sampling capacitor Cs, a second switch SWcarry, and a third switch SWrst.

[0056] The first switch SWsam can transfer the output current Iout from amplifier circuit 20 to sampling capacitor Cs. For example, the first switches SWsam of multiple channels can be turned on simultaneously.

[0057] The sampling capacitor Cs can sample the output current Iout transmitted through the first switch SWsam.

[0058] The second switch SWcarry can output the sampled voltage Vsam, which is sampled through the sampling capacitor Cs, to the global amplifier GA. For example, multiple channels of the second switch SWcarry can be turned on sequentially at predetermined time intervals.

[0059] The third switch SWrst can initialize the sampling capacitor Cs with the second reference voltage Vref.

[0060] The second reference voltage Vref of the sampling circuit 30 can be set to be lower than the level of the first reference voltage Vpre input to the amplifier circuit 20 to be compared with the input current Iin.

[0061] Figure 4 This is a timing diagram of the sensing circuit 10 according to an embodiment. Figure 4 In the diagram, waveform SWrst represents the signal used to control the third switch SWrst, waveform SWsam represents the signal used to control the first switch SWsam, and ON and OFF represent the on and off states of the corresponding switches.

[0062] refer to Figure 2 and Figure 4 First, the sensing circuit 10 can initialize the sampling voltage Vsam of the sampling capacitor Cs to the second reference voltage Vref by turning on the first switch SWsam and the third switch SWrst.

[0063] Then, the sensing circuit 10 can sample the output current Iout from the amplifier circuit 20 through the sampling capacitor Cs by turning on the first switch SWsam and turning off the third switch SWrst.

[0064] The sensing circuit 10 can sample the output current Iout transmitted through the first switch SWsam for a preset time t1. The sampling capacitor Cs can be charged by the output current Iout, and thus, the sampling voltage Vsam can rise within the preset time t1.

[0065] Next, the sensing circuit 10 can maintain the sampling voltage Vsam by disconnecting the first switch SWsam.

[0066] The magnitude ΔV of the sampling voltage Vsam can be calculated using the following equation 1.

[0067] [Equation 1]

[0068]

[0069] The magnitude ΔV of the sampling voltage Vsam can be determined by a replication ratio of 1 / N with linearity relative to the input current Iin, the sampling time t1, and the capacitance of the sampling capacitor Cs.

[0070] Subsequently, the sensing circuit 10 can sequentially output the sampled voltage Vsam to the global amplifier GA by turning on the second switch SWcarry.

[0071] As can be seen from the above description, by including an amplifier circuit that converts the input current into the output current, the sensing circuit according to the embodiment and the source driver including the sensing circuit can reduce the impact of panel load on the performance of the integrator, and the chip area can be reduced by eliminating the feedback capacitor of the integrator.

[0072] Furthermore, in the sensing circuit according to the embodiment, the reference voltage of the amplifier circuit can be set to a lower level compared to conventional technology.

[0073] Furthermore, the sensing circuit and source driver according to the implementation can accurately sense the signal of the pixel, regardless of whether the number of multiple channels is increased.

[0074] Furthermore, in the sensing circuit and source driver according to the embodiment, the amplifier circuit is configured such that the output current is less than the input current. Therefore, the sampling capacitor used to sample the output current can be designed to have a small capacitance. Thus, a small-area sampling capacitor can be used to implement the sensing circuit and source driver, and the chip area can be reduced.

Claims

1. A sensing circuit, comprising: The amplifier circuit is configured to receive input current from the display panel. The amplifier circuit converts the input current into an output current, and the magnitude of the output current is less than the magnitude of the input current. The amplifier circuit includes: The input and load stage circuitry is configured to output pull-up and pull-down signals in response to the input current and a first reference voltage. The output stage circuit is configured to, in response to the pull-up signal and the pull-down signal, output a first output voltage corresponding to the input current and a source current corresponding to a first scale of the input current; and A current mirror circuit is configured to output an output current at a second scale that replicates the source current at a rate less than the first scale.

2. The sensing circuit according to claim 1, wherein, The output stage circuit includes: A first output stage circuit is configured to output a first output voltage corresponding to the input current in response to the pull-up signal and the pull-down signal; and The second output stage circuit is configured to respond to the pull-up signal and the pull-down signal by outputting the source current corresponding to the first scale by replicating the current of the first output stage circuit corresponding to the input current.

3. The sensing circuit according to claim 2, wherein, The output terminal of the first output stage circuit is interconnected with the input terminal of the input and load stage circuit. The first output voltage is output through the output terminal of the first output stage circuit, and the input current is input through the input terminal of the input and load stage circuit.

4. The sensing circuit according to claim 1, wherein, The output stage circuit outputs the first output voltage and the source current of the first scale using the first power supply voltage, and The current mirror circuit replicates and outputs the output current of the second scale using a second power supply voltage that is lower than the level of the first power supply voltage.

5. The sensing circuit according to claim 1, wherein, The current mirror circuit replicates the output current relative to the source current at a preset replication ratio of 1 / N (N is a positive real number greater than 1).

6. The sensing circuit according to claim 1, further comprising: The sampling circuit is configured to output a sampling voltage by sampling the output current.

7. The sensing circuit according to claim 6, wherein, The sampling circuit includes: A first switch is configured to transmit the output current; A sampling capacitor is configured to sample the output current transmitted through the first switch. The second switch is configured to output the sampling voltage sampled through the sampling capacitor; and A third switch is configured to initialize the sampling capacitor to have a second reference voltage.

8. The sensing circuit according to claim 7, wherein, The second reference voltage of the sampling circuit is set to be lower than the level of the first reference voltage input to the amplifier circuit to be compared with the input current.

9. The sensing circuit according to claim 1, wherein, The amplifier circuit converts the input current into an output current with linearity.

10. Source driver, including: The sensing circuit is configured to output a sampled voltage by sensing the input current received from the display panel; A global amplifier configured to output an amplified signal by amplifying the sampled voltage; as well as An analog-to-digital converter, configured to convert the amplified signal into digital data. The sensing circuit includes: An amplifier circuit configured to convert the input current into an output current, wherein the magnitude of the output current is less than the magnitude of the input current; and The sampling circuit is configured to output the sampled voltage by sampling the output current. The amplifier circuit includes: The input and load stage circuitry is configured to output pull-up and pull-down signals in response to the input current and a first reference voltage. The output stage circuit is configured to, in response to the pull-up signal and the pull-down signal, output a first output voltage corresponding to the input current and a source current corresponding to a first scale of the input current; and A current mirror circuit is configured to output an output current at a second scale that replicates the source current at a rate less than the first scale.

11. The source driver according to claim 10, wherein, The output stage circuit includes: A first output stage circuit is configured to output a first output voltage corresponding to the input current in response to the pull-up signal and the pull-down signal; and The second output stage circuit is configured to respond to the pull-up signal and the pull-down signal by outputting the source current corresponding to the first scale by replicating the current of the first output stage circuit corresponding to the input current.

12. The source driver according to claim 11, wherein, The output terminal of the first output stage circuit is interconnected with the input terminal of the input and load stage circuit. The first output voltage is output through the output terminal of the first output stage circuit, and the input current is input through the input terminal of the input and load stage circuit.

13. The source driver according to claim 10, wherein, The output stage circuit outputs the first output voltage and the source current of the first scale using the first power supply voltage, and The current mirror circuit replicates and outputs the output current of the second scale using a second power supply voltage that is lower than the level of the first power supply voltage.

14. The source driver according to claim 10, wherein, The current mirror circuit replicates the output current relative to the source current at a preset replication ratio of 1 / N (N is a positive real number greater than 1).

15. The source driver according to claim 10, wherein, The sampling circuit includes: A first switch is configured to transmit the output current; A sampling capacitor is configured to sample the output current transmitted through the first switch. The second switch is configured to output the sampling voltage sampled through the sampling capacitor; and A third switch is configured to initialize the sampling capacitor to have a second reference voltage.

16. The source driver according to claim 15, wherein, The second reference voltage of the sampling circuit is set to be lower than the level of the first reference voltage input to the amplifier circuit to be compared with the input current.

17. The source driver according to claim 10, wherein, The amplifier circuit converts the input current into an output current with linearity.

Images